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authorAddepalli, Siva <siva.addepalli@amd.com>2023-08-08 18:12:31 +0530
committerSiva Addepalli <siva.addepalli@amd.com>2023-08-08 21:17:10 +0530
commit115b169151dbe40381a2f115e6065b074322c277 (patch)
tree3b01bf45ff99714aeb2ca39d0f11f274b98b365d /meta-xilinx-standalone
parent9ca66ce008d991fd79acb418142b51d761d5bff8 (diff)
downloadmeta-xilinx-115b169151dbe40381a2f115e6065b074322c277.tar.gz
embeddedsw : Updated SRCREV for 2023.2_5327
ddrpsv: Add VersalNet support BSP: cortexr5: Enable LLPP for CortexR52 sw_services:xilsem: Add support for SDT flow SDITXSS: Mismatch between config parameter and TCL parameter mapping. sw_services: xilsecure: Remove duplicate code sw_services: xilmailbox: Fix MISRA-C violations xilpm: versal: server: Add clk_cpll in CPM clock list xilpm: server: GtyHouseClean loop counter made volatile Video Drivers: Modified drivers to remove version number SDIRX: Register Read size is updated to 35. lib: bsp: standalone: Remove PM_CLOCK_SET/GET_RATE APIs from versioning xilpm: versal_common: server: Remove PM_CLOCK_SET/GET_RATE APIs from Featurecheck xilpm: versal_common: client: remove PM_CLOCK_SET/GET_RATE APIs xilpm: zynqmp: client: remove PM_CLOCK_SET/GET_RATE APIs XilNvm: Remove gaps in NVM API IDs gpio: Use Canonical form for base address in gpio examples Deprecate video drivers lib: bsp: Update GPIO and I2C interrupt Id macros for Versal Net sw_services: xilsecure:Handling endianness in ECDSA examples sw_services:xilplmi:Added redundant error check during update sw_services:xilplmi:Added redundant check in Tamper Detect sw_services:xilplmi:Added Redundant call for Sldstate check sw_services:xilplmi:Added redundant write for SSS Config sw_services:xilloader:Remove Additional PPK Check sw_services:xilloader:Updated Image Store Error codes lib: sw_apps: lwip_*: platform.c: Setup seperate timer function for SDT Flow lib: sw_apps: lwip*: Add missing properties from mss lwip213: Rename config params to generic names xilpm:versal_net:server: XPm_Reqm save and restore dynamic fields plm: versal_net: Reinitialize PsmToPlmEvent Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
Diffstat (limited to 'meta-xilinx-standalone')
-rw-r--r--meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass2
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
index 5b849331..41d256f9 100644
--- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
+++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
@@ -8,7 +8,7 @@ ESW_BRANCH[2023.2] = "xlnx_rel_v2023.2-next"
8BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" 8BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}"
9 9
10ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" 10ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab"
11ESW_REV[2023.2] = "3296a4acd4b09942d03ced91147a1062b6e9b204" 11ESW_REV[2023.2] = "1a8892594deaa2df664344302c8d1285ab4f77ad"
12SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" 12SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}"
13 13
14EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" 14EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}"