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authorMark Hatle <mark.hatle@amd.com>2024-06-04 16:51:04 -0600
committerMark Hatle <mark.hatle@amd.com>2024-06-04 17:00:14 -0600
commit195e1fa9fb13b21bc41af4e0747d4646caeb65e5 (patch)
tree27e92386d23080a44149b7ef0678e1bbddff2a2e /meta-xilinx-core/lib
parent3ea2f6cddd54881585084e7cb6f948c398ed980a (diff)
downloadmeta-xilinx-195e1fa9fb13b21bc41af4e0747d4646caeb65e5.tar.gz
various: Remove SOC_VARIANT, split versal and versal-net, add machine_features
SOC_VARIANT has been remove, we are now only using the YP standard SOC_FAMILY configuration. The defined families are: zynq, zynqmp, versal and versal-net. Our decision of breaking up versal-net from versal, is based on the SoC CPU changes from cortexa72/r5 to cortexa78/r52, thus we're treating it as a different SoC family. In order to capture the individual capabilities that we used to handle via SOC_VARIANT, we have defined the following features (some may have been previously defined): - mali400 (zynqmp eg and ev) - vcu (zynqmp ev) - rfsoc (zynqmp dr RF capabiltiies) - aie - (versal ai & premium) - vdu - (versal ai) SOC_VARIANT_ARCH and SOC_FAMILY_ARCH are now obsolete and replaced by MACHINE_ARCH. This is based on the guideline that any recipes that use MACHINE_FEATURES should be MACHINE_ARCH specific. Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Diffstat (limited to 'meta-xilinx-core/lib')
-rw-r--r--meta-xilinx-core/lib/devtool/boot-jtag.py30
1 files changed, 17 insertions, 13 deletions
diff --git a/meta-xilinx-core/lib/devtool/boot-jtag.py b/meta-xilinx-core/lib/devtool/boot-jtag.py
index 53d70262..247851ec 100644
--- a/meta-xilinx-core/lib/devtool/boot-jtag.py
+++ b/meta-xilinx-core/lib/devtool/boot-jtag.py
@@ -32,7 +32,6 @@ def bootjtag(args, config, basepath, workspace):
32 machine = rd.getVar('MACHINE') 32 machine = rd.getVar('MACHINE')
33 arch = rd.getVar('TARGET_ARCH') 33 arch = rd.getVar('TARGET_ARCH')
34 soc = rd.getVar("SOC_FAMILY") 34 soc = rd.getVar("SOC_FAMILY")
35 soc_variant = rd.getVar("SOC_VARIANT")
36 ddr_base_addr = rd.getVar('DDR_BASEADDR') 35 ddr_base_addr = rd.getVar('DDR_BASEADDR')
37 kernel_img_name = rd.getVar('KERNEL_IMAGE') 36 kernel_img_name = rd.getVar('KERNEL_IMAGE')
38 kernel_load_addr = rd.getVar('KERNEL_LOAD_ADDRESS') 37 kernel_load_addr = rd.getVar('KERNEL_LOAD_ADDRESS')
@@ -59,7 +58,7 @@ def bootjtag(args, config, basepath, workspace):
59 # MB = (DDR base address + DDR Size) - 0xe00000 58 # MB = (DDR base address + DDR Size) - 0xe00000
60 # Zynq 7000 = DDR base address + 0x3000000 59 # Zynq 7000 = DDR base address + 0x3000000
61 # ZynqMP = DDR base address + 0x20000000 60 # ZynqMP = DDR base address + 0x20000000
62 # Versal = DDR base address + 0x20000000 61 # Versal & Versal-net = DDR base address + 0x20000000
63 if arch == 'microblazeel': 62 if arch == 'microblazeel':
64 # Assuming DDR size is 2GB 63 # Assuming DDR size is 2GB
65 bootscr_addr = hex(int(ddr_base_addr, 16) + 0x80000000 - 0xe00000) 64 bootscr_addr = hex(int(ddr_base_addr, 16) + 0x80000000 - 0xe00000)
@@ -93,7 +92,7 @@ def bootjtag(args, config, basepath, workspace):
93 data['atf'] = os.path.join(deploy_dir, 'arm-trusted-firmware.elf') 92 data['atf'] = os.path.join(deploy_dir, 'arm-trusted-firmware.elf')
94 data['pmufw'] = os.path.join(deploy_dir, 'pmu-firmware-' + machine + '.elf') 93 data['pmufw'] = os.path.join(deploy_dir, 'pmu-firmware-' + machine + '.elf')
95 94
96 if soc == 'versal': 95 if soc in ('versal', 'versal-net'):
97 data['bootbin'] = os.path.join(deploy_dir, 'boot.bin') 96 data['bootbin'] = os.path.join(deploy_dir, 'boot.bin')
98 97
99 data['bootscr'] = os.path.join(deploy_dir, 'boot.scr') 98 data['bootscr'] = os.path.join(deploy_dir, 'boot.scr')
@@ -165,12 +164,17 @@ def bootjtag(args, config, basepath, workspace):
165 lines.append('puts stderr "INFO: Downloading BOOT bin file: ' + data['bootbin'] + '"') 164 lines.append('puts stderr "INFO: Downloading BOOT bin file: ' + data['bootbin'] + '"')
166 lines.append('device program \"' + data['bootbin'] + '\"') 165 lines.append('device program \"' + data['bootbin'] + '\"')
167 lines.append('') 166 lines.append('')
168 167 lines.append('targets -set -nocase -filter {name =~ \"*A72*#0\"}')
169 if soc_variant == 'net': 168 lines.append('stop')
170 lines.append('targets -set -nocase -filter {name =~ \"*A78*#0\"}') 169 lines.append('')
171 else: 170 lines.append('targets -set -nocase -filter {name =~ \"*Versal*\"}')
172 lines.append('targets -set -nocase -filter {name =~ \"*A72*#0\"}') 171 elif soc == 'versal-net':
173 172 # Download boot.bin to versal device
173 lines.append('targets -set -nocase -filter {name =~ \"*PMC*\"}')
174 lines.append('puts stderr "INFO: Downloading BOOT bin file: ' + data['bootbin'] + '"')
175 lines.append('device program \"' + data['bootbin'] + '\"')
176 lines.append('')
177 lines.append('targets -set -nocase -filter {name =~ \"*A78*#0\"}')
174 lines.append('stop') 178 lines.append('stop')
175 lines.append('') 179 lines.append('')
176 lines.append('targets -set -nocase -filter {name =~ \"*Versal*\"}') 180 lines.append('targets -set -nocase -filter {name =~ \"*Versal*\"}')
@@ -235,10 +239,10 @@ def bootjtag(args, config, basepath, workspace):
235 239
236 # Select A72 Core 0 to load and run Versal images 240 # Select A72 Core 0 to load and run Versal images
237 if soc == 'versal': 241 if soc == 'versal':
238 if soc_variant == 'net': 242 lines.append('targets -set -nocase -filter {name =~ \"*A72*#0\"}')
239 lines.append('targets -set -nocase -filter {name =~ \"*A78*#0\"}') 243
240 else: 244 if soc == 'versal-net':
241 lines.append('targets -set -nocase -filter {name =~ \"*A72*#0\"}') 245 lines.append('targets -set -nocase -filter {name =~ \"*A78*#0\"}')
242 246
243 lines.append('con') 247 lines.append('con')
244 lines.append('exit\n') 248 lines.append('exit\n')