README.dfx.user.dts.md: Update bit or bin or pdi only usage

Update README file with bit or bin or pdi usage only. Also
add Versal Segmented Configuration usage.

Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>

1 files changed, 104 insertions, 3 deletions

diff --git a/docs/README.dfx.user.dts.md b/docs/README.dfx.user.dts.md
index 4294c5bb..7b6682f7 100644
--- a/docs/README.dfx.user.dts.md
+++ b/docs/README.dfx.user.dts.md
@@ -16,11 +16,12 @@ following use cases.
 > **Note:** Refer https://github.com/Xilinx/dfx-mgr/blob/master/README.md for
 > shell.json and accel.json file content.
 
-* **Zynq-7000 and ZynqMP**:
-  * Design: Vivado flat design.
-    * Input files to firmware recipes: .bit or .bin, .dtsi or dtbo and shell.json (optional)
+* **Zynq 7000, ZynqMP and Versal**:
+  * Design: Vivado flat or Segmented Configuration design.
+    * Input files to firmware recipes: .bit or .bin or _pld.pdi, .dtsi or dtbo and shell.json (optional)
     * Usage Examples:
 ```
+# Zynq 7000 or ZynqMP flat design
 SRC_URI = " \
     file://<flat_design_pl>.bit \
     file://<flat_design_pl>.dtsi \
@@ -29,13 +30,16 @@ SRC_URI = " \
 ```
 
 ```
+# Zynq 7000 or ZynqMP flat design
 SRC_URI = " \
     file://<flat_design_pl>.bit \
     file://<flat_design_pl>.dtbo \
     file://shell.json \
     "
 ```
+
 ```
+# Zynq 7000 or ZynqMP flat design
 SRC_URI = " \
     file://<flat_design_pl>.bin \
     file://<flat_design_pl>.dtsi \
@@ -44,6 +48,7 @@ SRC_URI = " \
 ```
 
 ```
+# Zynq 7000 or ZynqMP flat design
 SRC_URI = " \
     file://<flat_design_pl>.bin \
     file://<flat_design_pl>.dtbo \
@@ -51,6 +56,48 @@ SRC_URI = " \
     "
 ```
 
+```
+# Zynq 7000 or ZynqMP flat design
+SRC_URI = " \
+    file://<flat_design_pl>.bit \
+    file://shell.json \
+    "
+```
+
+```
+# Zynq 7000 or ZynqMP flat design
+SRC_URI = " \
+    file://<flat_design_pl>.bin \
+    file://shell.json \
+    "
+```
+
+```
+# Versal Segmented Configuration design
+SRC_URI = " \
+    file://<flat_design>_pld.pdi \
+    file://<flat_design>_pld.dtsi \
+    file://shell.json \
+    "
+```
+
+```
+# Versal Segmented Configuration design
+SRC_URI = " \
+    file://<flat_design>_pld.pdi \
+    file://<flat_design>_pld.dtbo \
+    file://shell.json \
+    "
+```
+
+```
+# Versal Segmented Configuration design
+SRC_URI = " \
+    file://<flat_design>_pld.pdi \
+    file://shell.json \
+    "
+```
+
 * **ZynqMP and Versal**:
   * Design: Vivado DFx design.
     * Input files to firmware recipes: .bit/bin(ZynqMP) or .pdi(Versal), .dtsi or dtbo
@@ -98,6 +145,24 @@ SRC_URI = " \
 ```
 
 ```
+# ZynqMP DFx Static
+SRC_URI = " \
+    file://<dfx_design_static_pl>.bit \
+    file://shell.json \
+    file://<dfx_design_static_pl>.xclbin \
+    "
+```
+
+```
+# ZynqMP DFx Static
+SRC_URI = " \
+    file://<dfx_design_static_pl>.bin \
+    file://shell.json \
+    file://<dfx_design_static_pl>.xclbin \
+    "
+```
+
+```
 # ZynqMP DFx RP
 SRC_URI = " \
     file://<dfx_design_rp_rm_pl>.bit \
@@ -138,6 +203,24 @@ SRC_URI = " \
 ```
 
 ```
+# ZynqMP DFx RP
+SRC_URI = " \
+    file://<dfx_design_rp_rm_pl>.bit \
+    file://accel.json \
+    file://<dfx_design_rp_rm_pl>.xclbin \
+    "
+```
+
+```
+# ZynqMP DFx RP
+SRC_URI = " \
+    file://<dfx_design_rp_rm_pl>.bin \
+    file://accel.json \
+    file://<dfx_design_rp_rm_pl>.xclbin \
+    "
+```
+
+```
 # Versal DFx Static
 SRC_URI = " \
     file://<dfx_design_static_pl>.pdi \
@@ -158,6 +241,15 @@ SRC_URI = " \
 ```
 
 ```
+# Versal DFx Static
+SRC_URI = " \
+    file://<dfx_design_static_pl>.pdi \
+    file://shell.json \
+    file://<dfx_design_static_pl>.xclbin \
+    "
+```
+
+```
 # Versal DFx RP
 SRC_URI = " \
     file://<dfx_design_rp_rm_pl>.pdi \
@@ -176,6 +268,15 @@ SRC_URI = " \
     file://<dfx_design_rp_rm_pl>.xclbin \
     "
 ```
+
+```
+# Versal DFx RP
+SRC_URI = " \
+    file://<dfx_design_rp_rm_pl>.pdi \
+    file://accel.json \
+    file://<dfx_design_rp_rm_pl>.xclbin \
+    "
+```
 ---
 
 ## How to create a firmware recipe app