summaryrefslogtreecommitdiffstats
path: root/conf
diff options
context:
space:
mode:
authorNathan Rossi <nathan@nathanrossi.com>2015-09-24 16:57:51 +1000
committerNathan Rossi <nathan@nathanrossi.com>2015-09-24 17:33:17 +1000
commit88f9267aa26d546e657fcea72880b55a4fd9aa5d (patch)
tree32d49505814b82ea0a4c01399bbad721b519e68e /conf
parentd9b25aa3bb7fe60a9f8577c64aa7e21fc0b513cc (diff)
downloadmeta-xilinx-88f9267aa26d546e657fcea72880b55a4fd9aa5d.tar.gz
qemumicroblaze: Remove device-tree usage
* Remove the qemumicroblaze device-tree as instead of using a in layer device tree the device tree that is provided as part of QEMU is used * Update device-tree recipe removing the need for the runqemu compatiblity for qemumicroblaze Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Diffstat (limited to 'conf')
-rw-r--r--conf/machine/boards/qemu/qemumicroblaze.dts405
-rw-r--r--conf/machine/qemumicroblaze.conf2
2 files changed, 0 insertions, 407 deletions
diff --git a/conf/machine/boards/qemu/qemumicroblaze.dts b/conf/machine/boards/qemu/qemumicroblaze.dts
deleted file mode 100644
index 3e22be92..00000000
--- a/conf/machine/boards/qemu/qemumicroblaze.dts
+++ /dev/null
@@ -1,405 +0,0 @@
1/dts-v1/;
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5 compatible = "xlnx,microblaze";
6 model = "petalogix-ml605";
7 ddr3_sdram: memory@50000000 {
8 device_type = "memory";
9 reg = < 0x50000000 0x4000000 >;
10 } ;
11 aliases {
12 ethernet0 = &ethernet;
13 serial0 = &rs232_uart_1;
14 } ;
15 chosen {
16 bootargs = "console=ttyS0,115200 root=/dev/ram rw udev.children-max=1";
17 linux,stdout-path = "/axi@1/serial@83e00000";
18 } ;
19 cpus {
20 #address-cells = <1>;
21 #cpus = <0x1>;
22 #size-cells = <0>;
23 microblaze_0: cpu@0 {
24 bus-handle = <&axi4_0>, <&axi4lite_0>;
25 clock-frequency = <100000000>;
26 clocks = <&clk_cpu>;
27 compatible = "xlnx,microblaze-8.40.a";
28 d-cache-baseaddr = <0x50000000>;
29 d-cache-highaddr = <0x53ffffff>;
30 d-cache-line-size = <0x10>;
31 d-cache-size = <0x8000>;
32 device_type = "cpu";
33 i-cache-baseaddr = <0x50000000>;
34 i-cache-highaddr = <0x53ffffff>;
35 i-cache-line-size = <0x10>;
36 i-cache-size = <0x8000>;
37 model = "microblaze,8.40.a";
38 reg = <0>;
39 timebase-frequency = <100000000>;
40 xlnx,addr-tag-bits = <0xb>;
41 xlnx,allow-dcache-wr = <0x1>;
42 xlnx,allow-icache-wr = <0x1>;
43 xlnx,area-optimized = <0x0>;
44 xlnx,avoid-primitives = <0x0>;
45 xlnx,branch-target-cache-size = <0x0>;
46 xlnx,cache-byte-size = <0x8000>;
47 xlnx,d-axi = <0x1>;
48 xlnx,d-lmb = <0x1>;
49 xlnx,d-plb = <0x0>;
50 xlnx,data-size = <0x20>;
51 xlnx,dcache-addr-tag = <0xb>;
52 xlnx,dcache-always-used = <0x1>;
53 xlnx,dcache-byte-size = <0x8000>;
54 xlnx,dcache-data-width = <0x0>;
55 xlnx,dcache-force-tag-lutram = <0x0>;
56 xlnx,dcache-interface = <0x0>;
57 xlnx,dcache-line-len = <0x4>;
58 xlnx,dcache-use-fsl = <0x0>;
59 xlnx,dcache-use-writeback = <0x0>;
60 xlnx,dcache-victims = <0x0>;
61 xlnx,debug-enabled = <0x0>;
62 xlnx,div-zero-exception = <0x1>;
63 xlnx,dynamic-bus-sizing = <0x1>;
64 xlnx,ecc-use-ce-exception = <0x0>;
65 xlnx,edge-is-positive = <0x1>;
66 xlnx,endianness = <0x1>;
67 xlnx,family = "virtex6";
68 xlnx,fault-tolerant = <0x0>;
69 xlnx,fpu-exception = <0x1>;
70 xlnx,freq = <0x5f5e100>;
71 xlnx,fsl-data-size = <0x20>;
72 xlnx,fsl-exception = <0x0>;
73 xlnx,fsl-links = <0x0>;
74 xlnx,i-axi = <0x1>;
75 xlnx,i-lmb = <0x1>;
76 xlnx,i-plb = <0x0>;
77 xlnx,icache-always-used = <0x1>;
78 xlnx,icache-data-width = <0x0>;
79 xlnx,icache-force-tag-lutram = <0x0>;
80 xlnx,icache-interface = <0x0>;
81 xlnx,icache-line-len = <0x4>;
82 xlnx,icache-streams = <0x0>;
83 xlnx,icache-use-fsl = <0x0>;
84 xlnx,icache-victims = <0x0>;
85 xlnx,ill-opcode-exception = <0x1>;
86 xlnx,instance = "microblaze_0";
87 xlnx,interconnect = <0x2>;
88 xlnx,interrupt-is-edge = <0x0>;
89 xlnx,lockstep-slave = <0x0>;
90 xlnx,mmu-dtlb-size = <0x2>;
91 xlnx,mmu-itlb-size = <0x4>;
92 xlnx,mmu-privileged-instr = <0x0>;
93 xlnx,mmu-tlb-access = <0x3>;
94 xlnx,mmu-zones = <0x2>;
95 xlnx,number-of-pc-brk = <0x1>;
96 xlnx,number-of-rd-addr-brk = <0x0>;
97 xlnx,number-of-wr-addr-brk = <0x0>;
98 xlnx,opcode-0x0-illegal = <0x0>;
99 xlnx,optimization = <0x0>;
100 xlnx,pc-width = <0x20>;
101 xlnx,pvr = <0x2>;
102 xlnx,pvr-user1 = <0x0>;
103 xlnx,pvr-user2 = <0x0>;
104 xlnx,reset-msr = <0x0>;
105 xlnx,sco = <0x0>;
106 xlnx,stream-interconnect = <0x0>;
107 xlnx,unaligned-exceptions = <0x0>;
108 xlnx,use-barrel = <0x1>;
109 xlnx,use-branch-target-cache = <0x0>;
110 xlnx,use-dcache = <0x1>;
111 xlnx,use-div = <0x1>;
112 xlnx,use-ext-brk = <0x1>;
113 xlnx,use-ext-nm-brk = <0x1>;
114 xlnx,use-extended-fsl-instr = <0x0>;
115 xlnx,use-fpu = <0x1>;
116 xlnx,use-hw-mul = <0x2>;
117 xlnx,use-icache = <0x1>;
118 xlnx,use-interrupt = <0x1>;
119 xlnx,use-mmu = <0x3>;
120 xlnx,use-msr-instr = <0x1>;
121 xlnx,use-pcmp-instr = <0x1>;
122 xlnx,use-reorder-instr = <0x1>;
123 xlnx,use-stack-protection = <0x0>;
124 } ;
125 } ;
126 clocks {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 clk_bus: bus {
130 #clock-cells = <0>;
131 clock-frequency = <100000000>;
132 clock-output-names = "bus";
133 compatible = "fixed-clock";
134 reg = <1>;
135 } ;
136 clk_cpu: cpu {
137 #clock-cells = <0>;
138 clock-frequency = <100000000>;
139 clock-output-names = "cpu";
140 compatible = "fixed-clock";
141 reg = <0>;
142 } ;
143 } ;
144 axi4_0: axi@0 {
145 #address-cells = <1>;
146 #size-cells = <1>;
147 compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
148 ranges ;
149 } ;
150 axi4lite_0: axi@1 {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
154 ranges ;
155 ethernet: axi-ethernet@82780000 {
156 axistream-connected = <&ethernet_dma>;
157 axistream-control-connected = <&ethernet_dma>;
158 clock-frequency = <100000000>;
159 clocks = <&clk_bus>;
160 compatible = "xlnx,axi-ethernet-3.01.a", "xlnx,axi-ethernet-1.00.a";
161 device_type = "network";
162 interrupt-parent = <&microblaze_0_intc>;
163 interrupts = < 3 2 >;
164 local-mac-address = [ 00 0a 35 00 00 00 ];
165 phy-handle = <&phy0>;
166 reg = < 0x82780000 0x40000 >;
167 xlnx,avb = <0x0>;
168 xlnx,halfdup = <0x0>;
169 xlnx,include-io = <0x1>;
170 xlnx,mcast-extend = <0x0>;
171 xlnx,phy-type = <0x1>;
172 xlnx,phyaddr = <0x1>;
173 xlnx,rxcsum = <0x0>;
174 xlnx,rxmem = <0x1000>;
175 xlnx,rxvlan-strp = <0x0>;
176 xlnx,rxvlan-tag = <0x0>;
177 xlnx,rxvlan-tran = <0x0>;
178 xlnx,stats = <0x0>;
179 xlnx,txcsum = <0x0>;
180 xlnx,txmem = <0x1000>;
181 xlnx,txvlan-strp = <0x0>;
182 xlnx,txvlan-tag = <0x0>;
183 xlnx,txvlan-tran = <0x0>;
184 xlnx,type = <0x2>;
185 mdio {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 phy0: phy@7 {
189 device_type = "ethernet-phy";
190 reg = <7>;
191 } ;
192 } ;
193 } ;
194 ethernet_dma: axi-dma@84600000 {
195 axistream-connected = <&ethernet>;
196 axistream-control-connected = <&ethernet>;
197 compatible = "xlnx,axi-dma-4.00.a", "xlnx,axi-dma-1.00.a";
198 interrupt-parent = <&microblaze_0_intc>;
199 interrupts = < 1 2 0 2 >;
200 reg = < 0x84600000 0x10000 >;
201 xlnx,dlytmr-resolution = <0x4e2>;
202 xlnx,family = "virtex6";
203 xlnx,include-mm2s = <0x1>;
204 xlnx,include-mm2s-dre = <0x1>;
205 xlnx,include-s2mm = <0x1>;
206 xlnx,include-s2mm-dre = <0x1>;
207 xlnx,include-sg = <0x1>;
208 xlnx,mm2s-burst-size = <0x10>;
209 xlnx,prmry-is-aclk-async = <0x0>;
210 xlnx,s2mm-burst-size = <0x10>;
211 xlnx,sg-include-desc-queue = <0x1>;
212 xlnx,sg-include-stscntrl-strm = <0x1>;
213 xlnx,sg-length-width = <0x10>;
214 xlnx,sg-use-stsapp-length = <0x1>;
215 } ;
216 rs232_uart_1: serial@83e00000 {
217 clock-frequency = <100000000>;
218 clocks = <&clk_bus>;
219 compatible = "xlnx,axi-uart16550-1.01.a", "xlnx,xps-uart16550-2.00.a", "ns16550a";
220 current-speed = <115200>;
221 device_type = "serial";
222 interrupt-parent = <&microblaze_0_intc>;
223 interrupts = < 5 2 >;
224 reg = < 0x83e00000 0x10000 >;
225 reg-offset = <0x1000>;
226 reg-shift = <2>;
227 xlnx,external-xin-clk-hz = <0x17d7840>;
228 xlnx,family = "virtex6";
229 xlnx,has-external-rclk = <0x0>;
230 xlnx,has-external-xin = <0x0>;
231 xlnx,instance = "RS232_Uart_1";
232 xlnx,is-a-16550 = <0x1>;
233 xlnx,use-modem-ports = <0x0>;
234 xlnx,use-user-ports = <0x0>;
235 } ;
236 axi_spi_0: spi@40a00000 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "xlnx,axi-spi-1.01.a", "xlnx,xps-spi-2.00.a";
240 interrupt-parent = <&microblaze_0_intc>;
241 interrupts = < 4 2 >;
242 reg = < 0x40a00000 0x10000 >;
243 xlnx,family = "virtex6";
244 xlnx,fifo-exist = <0x1>;
245 xlnx,num-ss-bits = <0x4>;
246 xlnx,num-transfer-bits = <0x8>;
247 xlnx,sck-ratio = <0x20>;
248 flash0: axi-spi@0 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 compatible = "st,m25p80";
252 reg = < 0x0 >;
253 spi-max-frequency = <3125000>;
254 partition0@0x00000000 {
255 label = "all0";
256 reg = <0x00000000 0x01000000>;
257 };
258 } ;
259 flash1: axi-spi@1 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 compatible = "st,m25p80";
263 reg = < 0x1 >;
264 spi-max-frequency = <3125000>;
265 partition1@0x00000000 {
266 label = "all1";
267 reg = <0x00000000 0x01000000>;
268 };
269 } ;
270 flash2: axi-spi@2 {
271 #address-cells = <1>;
272 #size-cells = <1>;
273 compatible = "st,m25p80";
274 reg = < 0x2 >;
275 spi-max-frequency = <3125000>;
276 partition2@0x00000000 {
277 label = "all2";
278 reg = <0x00000000 0x01000000>;
279 };
280 } ;
281 flash3: axi-spi@3 {
282 #address-cells = <1>;
283 #size-cells = <1>;
284 compatible = "st,m25p80";
285 reg = < 0x3 >;
286 spi-max-frequency = <3125000>;
287 partition3@0x00000000 {
288 label = "all3";
289 reg = <0x00000000 0x01000000>;
290 };
291 } ;
292 } ;
293 pflash: flash@86000000 {
294 #address-cells = <1>;
295 #size-cells = <1>;
296 compatible = "xlnx,axi-emc-1.03.a", "cfi-flash";
297 bank-width = <2>;
298 reg = < 0x86000000 0x2000000 >;
299 xlnx,axi-clk-period-ps = <0x2710>;
300 xlnx,family = "virtex6";
301 xlnx,include-datawidth-matching-0 = <0x1>;
302 xlnx,include-datawidth-matching-1 = <0x0>;
303 xlnx,include-datawidth-matching-2 = <0x0>;
304 xlnx,include-datawidth-matching-3 = <0x0>;
305 xlnx,include-negedge-ioregs = <0x0>;
306 xlnx,instance = "Linear_Flash";
307 xlnx,lflash-period-ps = <0x4e20>;
308 xlnx,linear-flash-sync-burst = <0x0>;
309 xlnx,max-mem-width = <0x10>;
310 xlnx,mem0-type = <0x2>;
311 xlnx,mem0-width = <0x10>;
312 xlnx,mem1-type = <0x0>;
313 xlnx,mem1-width = <0x20>;
314 xlnx,mem2-type = <0x0>;
315 xlnx,mem2-width = <0x20>;
316 xlnx,mem3-type = <0x0>;
317 xlnx,mem3-width = <0x20>;
318 xlnx,num-banks-mem = <0x1>;
319 xlnx,parity-type-mem-0 = <0x0>;
320 xlnx,parity-type-mem-1 = <0x0>;
321 xlnx,parity-type-mem-2 = <0x0>;
322 xlnx,parity-type-mem-3 = <0x0>;
323 xlnx,s-axi-en-reg = <0x0>;
324 xlnx,s-axi-mem-addr-width = <0x20>;
325 xlnx,s-axi-mem-data-width = <0x20>;
326 xlnx,s-axi-mem-id-width = <0x1>;
327 xlnx,s-axi-mem-protocol = "AXI4LITE";
328 xlnx,s-axi-reg-addr-width = <0x5>;
329 xlnx,s-axi-reg-data-width = <0x20>;
330 xlnx,s-axi-reg-protocol = "axi4";
331 xlnx,synch-pipedelay-0 = <0x2>;
332 xlnx,synch-pipedelay-1 = <0x2>;
333 xlnx,synch-pipedelay-2 = <0x2>;
334 xlnx,synch-pipedelay-3 = <0x2>;
335 xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
336 xlnx,tavdv-ps-mem-1 = <0x3a98>;
337 xlnx,tavdv-ps-mem-2 = <0x3a98>;
338 xlnx,tavdv-ps-mem-3 = <0x3a98>;
339 xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
340 xlnx,tcedv-ps-mem-1 = <0x3a98>;
341 xlnx,tcedv-ps-mem-2 = <0x3a98>;
342 xlnx,tcedv-ps-mem-3 = <0x3a98>;
343 xlnx,thzce-ps-mem-0 = <0x88b8>;
344 xlnx,thzce-ps-mem-1 = <0x1b58>;
345 xlnx,thzce-ps-mem-2 = <0x1b58>;
346 xlnx,thzce-ps-mem-3 = <0x1b58>;
347 xlnx,thzoe-ps-mem-0 = <0x1b58>;
348 xlnx,thzoe-ps-mem-1 = <0x1b58>;
349 xlnx,thzoe-ps-mem-2 = <0x1b58>;
350 xlnx,thzoe-ps-mem-3 = <0x1b58>;
351 xlnx,tlzwe-ps-mem-0 = <0x88b8>;
352 xlnx,tlzwe-ps-mem-1 = <0x0>;
353 xlnx,tlzwe-ps-mem-2 = <0x0>;
354 xlnx,tlzwe-ps-mem-3 = <0x0>;
355 xlnx,tpacc-ps-flash-0 = <0x61a8>;
356 xlnx,tpacc-ps-flash-1 = <0x61a8>;
357 xlnx,tpacc-ps-flash-2 = <0x61a8>;
358 xlnx,tpacc-ps-flash-3 = <0x61a8>;
359 xlnx,twc-ps-mem-0 = <0x11170>;
360 xlnx,twc-ps-mem-1 = <0x3a98>;
361 xlnx,twc-ps-mem-2 = <0x3a98>;
362 xlnx,twc-ps-mem-3 = <0x3a98>;
363 xlnx,twp-ps-mem-0 = <0x11170>;
364 xlnx,twp-ps-mem-1 = <0x2ee0>;
365 xlnx,twp-ps-mem-2 = <0x2ee0>;
366 xlnx,twp-ps-mem-3 = <0x2ee0>;
367 xlnx,twph-ps-mem-0 = <0x2ee0>;
368 xlnx,twph-ps-mem-1 = <0x2ee0>;
369 xlnx,twph-ps-mem-2 = <0x2ee0>;
370 xlnx,twph-ps-mem-3 = <0x2ee0>;
371 xlnx,wr-rec-time-mem-0 = <0x186a0>;
372 xlnx,wr-rec-time-mem-1 = <0x186a0>;
373 xlnx,wr-rec-time-mem-2 = <0x186a0>;
374 xlnx,wr-rec-time-mem-3 = <0x186a0>;
375 partition@0x00000000 {
376 label = "all";
377 reg = <0x00000000 0x01000000>;
378 };
379 } ;
380 microblaze_0_intc: interrupt-controller@81800000 {
381 #interrupt-cells = <0x2>;
382 compatible = "xlnx,axi-intc-1.02.a", "xlnx,xps-intc-1.00.a";
383 interrupt-controller ;
384 reg = < 0x81800000 0x10000 >;
385 xlnx,kind-of-intr = <0x0>;
386 xlnx,num-intr-inputs = <0x7>;
387 } ;
388 system_timer: system-timer@83c00000 {
389 clock-frequency = <100000000>;
390 clocks = <&clk_bus>;
391 compatible = "xlnx,axi-timer-1.03.a", "xlnx,xps-timer-1.00.a";
392 interrupt-parent = <&microblaze_0_intc>;
393 interrupts = < 2 2 >;
394 reg = < 0x83c00000 0x10000 >;
395 xlnx,count-width = <0x20>;
396 xlnx,family = "virtex6";
397 xlnx,gen0-assert = <0x1>;
398 xlnx,gen1-assert = <0x1>;
399 xlnx,instance = "system_timer";
400 xlnx,one-timer-only = <0x0>;
401 xlnx,trig0-assert = <0x1>;
402 xlnx,trig1-assert = <0x1>;
403 } ;
404 } ;
405} ;
diff --git a/conf/machine/qemumicroblaze.conf b/conf/machine/qemumicroblaze.conf
index 643823cf..9de93c8c 100644
--- a/conf/machine/qemumicroblaze.conf
+++ b/conf/machine/qemumicroblaze.conf
@@ -14,8 +14,6 @@ EXTRA_IMAGEDEPENDS += "qemu-native qemu-helper-native"
14USE_VT = "" 14USE_VT = ""
15SERIAL_CONSOLE = "115200 ttyS0" 15SERIAL_CONSOLE = "115200 ttyS0"
16 16
17MACHINE_DEVICETREE := "qemu/qemumicroblaze.dts"
18
19# Use the networking setup from qemuarm 17# Use the networking setup from qemuarm
20FILESOVERRIDES_append_pn-init-ifupdown = ":qemuarm" 18FILESOVERRIDES_append_pn-init-ifupdown = ":qemuarm"
21 19
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-04-22 16:06:21 +0000