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authorManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2018-02-26 17:54:53 -0800
committerManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2018-05-25 11:09:21 -0700
commitc1484bbce2c6b32fd77369a8bb1a8f238b10401b (patch)
tree96d0c010f83ce5b5fa7dd1a0c7c7e2e6c8081064
parentf4062d49ab6c10e1403745cc2932fff3abfeff61 (diff)
downloadmeta-xilinx-c1484bbce2c6b32fd77369a8bb1a8f238b10401b.tar.gz
Remove 2017.3 component recipes
Remove 2017.3 based component recipes Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
Diffstat
-rw-r--r--meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2017.3.bb5
-rw-r--r--meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2017.3/arm64-zynqmp-Setup-partid-for-QEMU-to-match-silicon.patch33
-rw-r--r--meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2017.3/microblaze-kc705-Convert-microblaze-generic-to-k.patch1181
-rw-r--r--meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2017.3.bb26
-rw-r--r--meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2017.3.bb4
-rw-r--r--meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2017.3.bb5
-rw-r--r--meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2017.3.bb6
-rw-r--r--meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2017.3/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch302
-rw-r--r--meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2017.3/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch607
-rw-r--r--meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2017.3/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch54
-rw-r--r--meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2017.3.bbappend8
11 files changed, 0 insertions, 2231 deletions
diff --git a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2017.3.bb b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2017.3.bb
deleted file mode 100644
index a9d46691..00000000
--- a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2017.3.bb
+++ /dev/null
@@ -1,5 +0,0 @@
1ATF_VERSION = "1.3"
2XILINX_RELEASE_VERSION = "v2017.3"
3SRCREV ?= "f9b244beaa7ac6a670b192192b6e92e5fd6044dc"
4
5include arm-trusted-firmware.inc
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2017.3/arm64-zynqmp-Setup-partid-for-QEMU-to-match-silicon.patch b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2017.3/arm64-zynqmp-Setup-partid-for-QEMU-to-match-silicon.patch
deleted file mode 100644
index d8261e62..00000000
--- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2017.3/arm64-zynqmp-Setup-partid-for-QEMU-to-match-silicon.patch
+++ /dev/null
@@ -1,33 +0,0 @@
1From 777ac896daaffeaa2fac2bdb424a96def7409a4b Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Wed, 18 Oct 2017 21:29:47 +1000
4Subject: [PATCH] arm64: zynqmp: Setup partid for QEMU to match silicon
5
6During board late init the environment is 'setup' to set the partid to 0
7for QEMU. Change this so that QEMU targets behave just like silicon and
8emulation targets such that partid is set to auto.
9
10Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
11Upstream-Status: Submitted [sent to git@xilinx.com]
12---
13 board/xilinx/zynqmp/zynqmp.c | 2 +-
14 1 file changed, 1 insertion(+), 1 deletion(-)
15
16diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
17index fd80844df6..2df66a4b75 100644
18--- a/board/xilinx/zynqmp/zynqmp.c
19+++ b/board/xilinx/zynqmp/zynqmp.c
20@@ -294,9 +294,9 @@ int board_late_init(void)
21 setenv("setup", "setenv baudrate 4800 && setenv bootcmd run veloce");
22 case ZYNQMP_CSU_VERSION_EP108:
23 case ZYNQMP_CSU_VERSION_SILICON:
24+ case ZYNQMP_CSU_VERSION_QEMU:
25 setenv("setup", "setenv partid auto");
26 break;
27- case ZYNQMP_CSU_VERSION_QEMU:
28 default:
29 setenv("setup", "setenv partid 0");
30 }
31--
322.15.0
33
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2017.3/microblaze-kc705-Convert-microblaze-generic-to-k.patch b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2017.3/microblaze-kc705-Convert-microblaze-generic-to-k.patch
deleted file mode 100644
index 99e2a648..00000000
--- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2017.3/microblaze-kc705-Convert-microblaze-generic-to-k.patch
+++ /dev/null
@@ -1,1181 +0,0 @@
1From cb4350d00089c0e133ef18d2b662e18ab82a14c6 Mon Sep 17 00:00:00 2001
2From: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
3Date: Tue, 8 Aug 2017 10:34:28 -0700
4Subject: [PATCH] kc705-microblazeel: Convert microblaze-generic to kc705-microblazeel
5
6This is an update to earlier kc705-trd patch done by Nathan Rossi. Starting
7from v2016.1, KC705 will no longer refer to deprecated KC705 TRD application.
8
9Change the microblaze-generic board to match the kc705-microblazeel. This patch
10is not intended for upstream and serves as an intermediate solution
11until OF support in upstream u-boot allows for easy support for custom
12microblaze boards.
13
14Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
15Upstream-Status: Not-Upstreamable [meta-xilinx/kc705 specific]
16---
17 arch/microblaze/dts/microblaze-generic.dts | 570 ++++++++++++++++++++++++++++-
18 board/xilinx/microblaze-generic/config.mk | 30 +-
19 configs/microblaze-generic_defconfig | 27 +-
20 include/configs/microblaze-generic.h | 470 +++++++++---------------
21 4 files changed, 754 insertions(+), 343 deletions(-)
22
23diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts
24index 08a1396..879bacd 100644
25--- a/arch/microblaze/dts/microblaze-generic.dts
26+++ b/arch/microblaze/dts/microblaze-generic.dts
27@@ -1,9 +1,567 @@
28 /dts-v1/;
29+
30 / {
31- #address-cells = <1>;
32- #size-cells = <1>;
33- aliases {
34- } ;
35+ #address-cells = <0x1>;
36+ #size-cells = <0x1>;
37+ compatible = "xlnx,microblaze";
38+ model = "Xilinx MicroBlaze";
39+ hard-reset-gpios = <0x1 0x0 0x1>;
40+
41+ cpus {
42+ #address-cells = <0x1>;
43+ #cpus = <0x1>;
44+ #size-cells = <0x0>;
45+
46+ cpu@0 {
47+ bus-handle = <0x2>;
48+ clock-frequency = <0xbebc200>;
49+ clocks = <0x3>;
50+ compatible = "xlnx,microblaze-10.0";
51+ d-cache-baseaddr = <0x80000000>;
52+ d-cache-highaddr = <0xbfffffff>;
53+ d-cache-line-size = <0x20>;
54+ d-cache-size = <0x4000>;
55+ device_type = "cpu";
56+ i-cache-baseaddr = <0x80000000>;
57+ i-cache-highaddr = <0xbfffffff>;
58+ i-cache-line-size = <0x10>;
59+ i-cache-size = <0x4000>;
60+ interrupt-handle = <0x4>;
61+ model = "microblaze,10.0";
62+ timebase-frequency = <0xbebc200>;
63+ xlnx,addr-size = <0x20>;
64+ xlnx,addr-tag-bits = <0x10>;
65+ xlnx,allow-dcache-wr = <0x1>;
66+ xlnx,allow-icache-wr = <0x1>;
67+ xlnx,area-optimized = <0x0>;
68+ xlnx,async-interrupt = <0x1>;
69+ xlnx,async-wakeup = <0x3>;
70+ xlnx,avoid-primitives = <0x0>;
71+ xlnx,base-vectors = <0x0>;
72+ xlnx,branch-target-cache-size = <0x0>;
73+ xlnx,cache-byte-size = <0x4000>;
74+ xlnx,d-axi = <0x1>;
75+ xlnx,d-lmb = <0x1>;
76+ xlnx,d-lmb-mon = <0x0>;
77+ xlnx,daddr-size = <0x20>;
78+ xlnx,data-size = <0x20>;
79+ xlnx,dc-axi-mon = <0x0>;
80+ xlnx,dcache-addr-tag = <0x10>;
81+ xlnx,dcache-always-used = <0x1>;
82+ xlnx,dcache-byte-size = <0x4000>;
83+ xlnx,dcache-data-width = <0x0>;
84+ xlnx,dcache-force-tag-lutram = <0x0>;
85+ xlnx,dcache-line-len = <0x8>;
86+ xlnx,dcache-use-writeback = <0x0>;
87+ xlnx,dcache-victims = <0x0>;
88+ xlnx,debug-counter-width = <0x20>;
89+ xlnx,debug-enabled = <0x1>;
90+ xlnx,debug-event-counters = <0x5>;
91+ xlnx,debug-external-trace = <0x0>;
92+ xlnx,debug-interface = <0x0>;
93+ xlnx,debug-latency-counters = <0x1>;
94+ xlnx,debug-profile-size = <0x0>;
95+ xlnx,debug-trace-async-reset = <0x0>;
96+ xlnx,debug-trace-size = <0x2000>;
97+ xlnx,div-zero-exception = <0x1>;
98+ xlnx,dp-axi-mon = <0x0>;
99+ xlnx,dynamic-bus-sizing = <0x0>;
100+ xlnx,ecc-use-ce-exception = <0x0>;
101+ xlnx,edge-is-positive = <0x1>;
102+ xlnx,enable-discrete-ports = <0x0>;
103+ xlnx,endianness = <0x1>;
104+ xlnx,fault-tolerant = <0x0>;
105+ xlnx,fpu-exception = <0x0>;
106+ xlnx,freq = <0xbebc200>;
107+ xlnx,fsl-exception = <0x0>;
108+ xlnx,fsl-links = <0x0>;
109+ xlnx,i-axi = <0x0>;
110+ xlnx,i-lmb = <0x1>;
111+ xlnx,i-lmb-mon = <0x0>;
112+ xlnx,iaddr-size = <0x20>;
113+ xlnx,ic-axi-mon = <0x0>;
114+ xlnx,icache-always-used = <0x1>;
115+ xlnx,icache-data-width = <0x0>;
116+ xlnx,icache-force-tag-lutram = <0x0>;
117+ xlnx,icache-line-len = <0x4>;
118+ xlnx,icache-streams = <0x1>;
119+ xlnx,icache-victims = <0x8>;
120+ xlnx,ill-opcode-exception = <0x1>;
121+ xlnx,imprecise-exceptions = <0x0>;
122+ xlnx,instr-size = <0x20>;
123+ xlnx,interconnect = <0x2>;
124+ xlnx,interrupt-is-edge = <0x0>;
125+ xlnx,interrupt-mon = <0x0>;
126+ xlnx,ip-axi-mon = <0x0>;
127+ xlnx,lockstep-master = <0x0>;
128+ xlnx,lockstep-select = <0x0>;
129+ xlnx,lockstep-slave = <0x0>;
130+ xlnx,mmu-dtlb-size = <0x4>;
131+ xlnx,mmu-itlb-size = <0x2>;
132+ xlnx,mmu-privileged-instr = <0x0>;
133+ xlnx,mmu-tlb-access = <0x3>;
134+ xlnx,mmu-zones = <0x2>;
135+ xlnx,num-sync-ff-clk = <0x2>;
136+ xlnx,num-sync-ff-clk-debug = <0x2>;
137+ xlnx,num-sync-ff-clk-irq = <0x1>;
138+ xlnx,num-sync-ff-dbg-clk = <0x1>;
139+ xlnx,num-sync-ff-dbg-trace-clk = <0x2>;
140+ xlnx,number-of-pc-brk = <0x1>;
141+ xlnx,number-of-rd-addr-brk = <0x0>;
142+ xlnx,number-of-wr-addr-brk = <0x0>;
143+ xlnx,opcode-0x0-illegal = <0x1>;
144+ xlnx,optimization = <0x0>;
145+ xlnx,pc-width = <0x20>;
146+ xlnx,piaddr-size = <0x20>;
147+ xlnx,pvr = <0x2>;
148+ xlnx,pvr-user1 = <0x0>;
149+ xlnx,pvr-user2 = <0x0>;
150+ xlnx,reset-msr = <0x0>;
151+ xlnx,reset-msr-bip = <0x0>;
152+ xlnx,reset-msr-dce = <0x0>;
153+ xlnx,reset-msr-ee = <0x0>;
154+ xlnx,reset-msr-eip = <0x0>;
155+ xlnx,reset-msr-ice = <0x0>;
156+ xlnx,reset-msr-ie = <0x0>;
157+ xlnx,sco = <0x0>;
158+ xlnx,trace = <0x0>;
159+ xlnx,unaligned-exceptions = <0x1>;
160+ xlnx,use-barrel = <0x1>;
161+ xlnx,use-branch-target-cache = <0x0>;
162+ xlnx,use-config-reset = <0x0>;
163+ xlnx,use-dcache = <0x1>;
164+ xlnx,use-div = <0x1>;
165+ xlnx,use-ext-brk = <0x0>;
166+ xlnx,use-ext-nm-brk = <0x0>;
167+ xlnx,use-extended-fsl-instr = <0x0>;
168+ xlnx,use-fpu = <0x0>;
169+ xlnx,use-hw-mul = <0x2>;
170+ xlnx,use-icache = <0x1>;
171+ xlnx,use-interrupt = <0x2>;
172+ xlnx,use-mmu = <0x3>;
173+ xlnx,use-msr-instr = <0x1>;
174+ xlnx,use-non-secure = <0x0>;
175+ xlnx,use-pcmp-instr = <0x1>;
176+ xlnx,use-reorder-instr = <0x1>;
177+ xlnx,use-stack-protection = <0x0>;
178+ };
179+ };
180+
181+ clocks {
182+ #address-cells = <0x1>;
183+ #size-cells = <0x0>;
184+
185+ clk_cpu@0 {
186+ #clock-cells = <0x0>;
187+ clock-frequency = <0xbebc200>;
188+ clock-output-names = "clk_cpu";
189+ compatible = "fixed-clock";
190+ reg = <0x0>;
191+ linux,phandle = <0x3>;
192+ phandle = <0x3>;
193+ };
194+
195+ clk_bus_0@1 {
196+ #clock-cells = <0x0>;
197+ clock-frequency = <0xbebc200>;
198+ clock-output-names = "clk_bus_0";
199+ compatible = "fixed-clock";
200+ reg = <0x1>;
201+ linux,phandle = <0x8>;
202+ phandle = <0x8>;
203+ };
204+ };
205+
206+ amba_pl {
207+ #address-cells = <0x1>;
208+ #size-cells = <0x1>;
209+ compatible = "simple-bus";
210+ ranges;
211+ linux,phandle = <0x2>;
212+ phandle = <0x2>;
213+
214+ ethernet@40c00000 {
215+ axistream-connected = <0x5>;
216+ axistream-control-connected = <0x5>;
217+ clock-frequency = <0x5f5e100>;
218+ compatible = "xlnx,axi-ethernet-1.00.a";
219+ device_type = "network";
220+ interrupt-parent = <0x4>;
221+ interrupts = <0x4 0x2>;
222+ phy-mode = "gmii";
223+ reg = <0x40c00000 0x40000>;
224+ xlnx = <0x0>;
225+ xlnx,axiliteclkrate = <0x0>;
226+ xlnx,axisclkrate = <0x0>;
227+ xlnx,clockselection = <0x0>;
228+ xlnx,enableasyncsgmii = <0x0>;
229+ xlnx,gt-type = <0x0>;
230+ xlnx,gtinex = <0x0>;
231+ xlnx,gtlocation = <0x0>;
232+ xlnx,gtrefclksrc = <0x0>;
233+ xlnx,include-dre;
234+ xlnx,instantiatebitslice0 = <0x0>;
235+ xlnx,phy-type = <0x1>;
236+ xlnx,phyaddr = <0x1>;
237+ xlnx,rable = <0x0>;
238+ xlnx,rxcsum = <0x0>;
239+ xlnx,rxlane0-placement = <0x0>;
240+ xlnx,rxlane1-placement = <0x0>;
241+ xlnx,rxmem = <0x1000>;
242+ xlnx,rxnibblebitslice0used = <0x0>;
243+ xlnx,tx-in-upper-nibble = <0x1>;
244+ xlnx,txcsum = <0x0>;
245+ xlnx,txlane0-placement = <0x0>;
246+ xlnx,txlane1-placement = <0x0>;
247+ phy-handle = <0x6>;
248+ local-mac-address = [00 0a 35 00 22 01];
249+ linux,phandle = <0x7>;
250+ phandle = <0x7>;
251+
252+ mdio {
253+ #address-cells = <0x1>;
254+ #size-cells = <0x0>;
255+
256+ phy@7 {
257+ device_type = "ethernet-phy";
258+ reg = <0x7>;
259+ linux,phandle = <0x6>;
260+ phandle = <0x6>;
261+ };
262+ };
263+ };
264+
265+ dma@41e00000 {
266+ #dma-cells = <0x1>;
267+ axistream-connected = <0x7>;
268+ axistream-control-connected = <0x7>;
269+ clock-frequency = <0xbebc200>;
270+ clock-names = "s_axi_lite_aclk";
271+ clocks = <0x8>;
272+ compatible = "xlnx,eth-dma";
273+ interrupt-parent = <0x4>;
274+ interrupts = <0x3 0x2 0x2 0x2>;
275+ reg = <0x41e00000 0x10000>;
276+ xlnx,include-dre;
277+ linux,phandle = <0x5>;
278+ phandle = <0x5>;
279+ };
280+
281+ timer@41c00000 {
282+ clock-frequency = <0xbebc200>;
283+ clocks = <0x8>;
284+ compatible = "xlnx,xps-timer-1.00.a";
285+ interrupt-parent = <0x4>;
286+ interrupts = <0x5 0x2>;
287+ reg = <0x41c00000 0x10000>;
288+ xlnx,count-width = <0x20>;
289+ xlnx,gen0-assert = <0x1>;
290+ xlnx,gen1-assert = <0x1>;
291+ xlnx,one-timer-only = <0x0>;
292+ xlnx,trig0-assert = <0x1>;
293+ xlnx,trig1-assert = <0x1>;
294+ };
295+
296+ gpio@40010000 {
297+ #gpio-cells = <0x2>;
298+ compatible = "xlnx,xps-gpio-1.00.a";
299+ gpio-controller;
300+ reg = <0x40010000 0x10000>;
301+ xlnx,all-inputs = <0x1>;
302+ xlnx,all-inputs-2 = <0x0>;
303+ xlnx,all-outputs = <0x0>;
304+ xlnx,all-outputs-2 = <0x0>;
305+ xlnx,dout-default = <0x0>;
306+ xlnx,dout-default-2 = <0x0>;
307+ xlnx,gpio-width = <0x1>;
308+ xlnx,gpio2-width = <0x20>;
309+ xlnx,interrupt-present = <0x0>;
310+ xlnx,is-dual = <0x0>;
311+ xlnx,tri-default = <0xffffffff>;
312+ xlnx,tri-default-2 = <0xffffffff>;
313+ };
314+
315+ gpio@40020000 {
316+ #gpio-cells = <0x2>;
317+ compatible = "xlnx,xps-gpio-1.00.a";
318+ gpio-controller;
319+ reg = <0x40020000 0x10000>;
320+ xlnx,all-inputs = <0x1>;
321+ xlnx,all-inputs-2 = <0x0>;
322+ xlnx,all-outputs = <0x0>;
323+ xlnx,all-outputs-2 = <0x0>;
324+ xlnx,dout-default = <0x0>;
325+ xlnx,dout-default-2 = <0x0>;
326+ xlnx,gpio-width = <0x4>;
327+ xlnx,gpio2-width = <0x20>;
328+ xlnx,interrupt-present = <0x0>;
329+ xlnx,is-dual = <0x0>;
330+ xlnx,tri-default = <0xffffffff>;
331+ xlnx,tri-default-2 = <0xffffffff>;
332+ };
333+
334+ i2c@40800000 {
335+ #address-cells = <0x1>;
336+ #size-cells = <0x0>;
337+ clock-frequency = <0xbebc200>;
338+ clocks = <0x8>;
339+ compatible = "xlnx,xps-iic-2.00.a";
340+ interrupt-parent = <0x4>;
341+ interrupts = <0x1 0x2>;
342+ reg = <0x40800000 0x10000>;
343+
344+ i2cswitch@74 {
345+ compatible = "nxp,pca9548";
346+ #address-cells = <0x1>;
347+ #size-cells = <0x0>;
348+ reg = <0x74>;
349+
350+ i2c@0 {
351+ #address-cells = <0x1>;
352+ #size-cells = <0x0>;
353+ reg = <0x0>;
354+
355+ clock-generator@5d {
356+ #clock-cells = <0x0>;
357+ compatible = "silabs,si570";
358+ temperature-stability = <0x32>;
359+ reg = <0x5d>;
360+ factory-fout = <0x9502f90>;
361+ clock-frequency = <0x8d9ee20>;
362+ };
363+ };
364+
365+ i2c@3 {
366+ #address-cells = <0x1>;
367+ #size-cells = <0x0>;
368+ reg = <0x3>;
369+
370+ eeprom@54 {
371+ compatible = "at,24c08";
372+ reg = <0x54>;
373+ };
374+ };
375+ };
376+ };
377+
378+ gpio@40030000 {
379+ #gpio-cells = <0x2>;
380+ compatible = "xlnx,xps-gpio-1.00.a";
381+ gpio-controller;
382+ reg = <0x40030000 0x10000>;
383+ xlnx,all-inputs = <0x0>;
384+ xlnx,all-inputs-2 = <0x0>;
385+ xlnx,all-outputs = <0x1>;
386+ xlnx,all-outputs-2 = <0x0>;
387+ xlnx,dout-default = <0x0>;
388+ xlnx,dout-default-2 = <0x0>;
389+ xlnx,gpio-width = <0x8>;
390+ xlnx,gpio2-width = <0x20>;
391+ xlnx,interrupt-present = <0x0>;
392+ xlnx,is-dual = <0x0>;
393+ xlnx,tri-default = <0xffffffff>;
394+ xlnx,tri-default-2 = <0xffffffff>;
395+ };
396+
397+ flash@60000000 {
398+ bank-width = <0x2>;
399+ compatible = "cfi-flash";
400+ reg = <0x60000000 0x8000000>;
401+ xlnx,axi-clk-period-ps = <0x1388>;
402+ xlnx,include-datawidth-matching-0 = <0x1>;
403+ xlnx,include-datawidth-matching-1 = <0x1>;
404+ xlnx,include-datawidth-matching-2 = <0x1>;
405+ xlnx,include-datawidth-matching-3 = <0x1>;
406+ xlnx,include-negedge-ioregs = <0x0>;
407+ xlnx,lflash-period-ps = <0x1388>;
408+ xlnx,linear-flash-sync-burst = <0x0>;
409+ xlnx,max-mem-width = <0x10>;
410+ xlnx,mem-a-lsb = <0x0>;
411+ xlnx,mem-a-msb = <0x1f>;
412+ xlnx,mem0-type = <0x2>;
413+ xlnx,mem0-width = <0x10>;
414+ xlnx,mem1-type = <0x0>;
415+ xlnx,mem1-width = <0x10>;
416+ xlnx,mem2-type = <0x0>;
417+ xlnx,mem2-width = <0x10>;
418+ xlnx,mem3-type = <0x0>;
419+ xlnx,mem3-width = <0x10>;
420+ xlnx,num-banks-mem = <0x1>;
421+ xlnx,page-size = <0x10>;
422+ xlnx,parity-type-mem-0 = <0x0>;
423+ xlnx,parity-type-mem-1 = <0x0>;
424+ xlnx,parity-type-mem-2 = <0x0>;
425+ xlnx,parity-type-mem-3 = <0x0>;
426+ xlnx,port-diff = <0x0>;
427+ xlnx,s-axi-en-reg = <0x0>;
428+ xlnx,s-axi-mem-addr-width = <0x20>;
429+ xlnx,s-axi-mem-data-width = <0x20>;
430+ xlnx,s-axi-mem-id-width = <0x1>;
431+ xlnx,s-axi-reg-addr-width = <0x5>;
432+ xlnx,s-axi-reg-data-width = <0x20>;
433+ xlnx,synch-pipedelay-0 = <0x1>;
434+ xlnx,synch-pipedelay-1 = <0x1>;
435+ xlnx,synch-pipedelay-2 = <0x1>;
436+ xlnx,synch-pipedelay-3 = <0x1>;
437+ xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
438+ xlnx,tavdv-ps-mem-1 = <0x3a98>;
439+ xlnx,tavdv-ps-mem-2 = <0x3a98>;
440+ xlnx,tavdv-ps-mem-3 = <0x3a98>;
441+ xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
442+ xlnx,tcedv-ps-mem-1 = <0x3a98>;
443+ xlnx,tcedv-ps-mem-2 = <0x3a98>;
444+ xlnx,tcedv-ps-mem-3 = <0x3a98>;
445+ xlnx,thzce-ps-mem-0 = <0x88b8>;
446+ xlnx,thzce-ps-mem-1 = <0x1b58>;
447+ xlnx,thzce-ps-mem-2 = <0x1b58>;
448+ xlnx,thzce-ps-mem-3 = <0x1b58>;
449+ xlnx,thzoe-ps-mem-0 = <0x1b58>;
450+ xlnx,thzoe-ps-mem-1 = <0x1b58>;
451+ xlnx,thzoe-ps-mem-2 = <0x1b58>;
452+ xlnx,thzoe-ps-mem-3 = <0x1b58>;
453+ xlnx,tlzwe-ps-mem-0 = <0xc350>;
454+ xlnx,tlzwe-ps-mem-1 = <0x0>;
455+ xlnx,tlzwe-ps-mem-2 = <0x0>;
456+ xlnx,tlzwe-ps-mem-3 = <0x0>;
457+ xlnx,tpacc-ps-flash-0 = <0x61a8>;
458+ xlnx,tpacc-ps-flash-1 = <0x61a8>;
459+ xlnx,tpacc-ps-flash-2 = <0x61a8>;
460+ xlnx,tpacc-ps-flash-3 = <0x61a8>;
461+ xlnx,twc-ps-mem-0 = <0x11170>;
462+ xlnx,twc-ps-mem-1 = <0x3a98>;
463+ xlnx,twc-ps-mem-2 = <0x3a98>;
464+ xlnx,twc-ps-mem-3 = <0x3a98>;
465+ xlnx,twp-ps-mem-0 = <0x13880>;
466+ xlnx,twp-ps-mem-1 = <0x2ee0>;
467+ xlnx,twp-ps-mem-2 = <0x2ee0>;
468+ xlnx,twp-ps-mem-3 = <0x2ee0>;
469+ xlnx,twph-ps-mem-0 = <0x13880>;
470+ xlnx,twph-ps-mem-1 = <0x2ee0>;
471+ xlnx,twph-ps-mem-2 = <0x2ee0>;
472+ xlnx,twph-ps-mem-3 = <0x2ee0>;
473+ xlnx,use-startup = <0x0>;
474+ xlnx,use-startup-int = <0x0>;
475+ xlnx,wr-rec-time-mem-0 = <0x186a0>;
476+ xlnx,wr-rec-time-mem-1 = <0x6978>;
477+ xlnx,wr-rec-time-mem-2 = <0x6978>;
478+ xlnx,wr-rec-time-mem-3 = <0x6978>;
479+ #address-cells = <0x1>;
480+ #size-cells = <0x1>;
481+
482+ partition@0x00000000 {
483+ label = "fpga";
484+ reg = <0x0 0xb00000>;
485+ };
486+
487+ partition@0x00b00000 {
488+ label = "boot";
489+ reg = <0xb00000 0x80000>;
490+ };
491+
492+ partition@0x00b80000 {
493+ label = "bootenv";
494+ reg = <0xb80000 0x20000>;
495+ };
496+
497+ partition@0x00ba0000 {
498+ label = "kernel";
499+ reg = <0xba0000 0xc00000>;
500+ };
501+
502+ partition@0x017a0000 {
503+ label = "spare";
504+ reg = <0x17a0000 0x0>;
505+ };
506+ };
507+
508+ interrupt-controller@41200000 {
509+ #interrupt-cells = <0x2>;
510+ compatible = "xlnx,xps-intc-1.00.a";
511+ interrupt-controller;
512+ reg = <0x41200000 0x10000>;
513+ xlnx,kind-of-intr = <0x0>;
514+ xlnx,num-intr-inputs = <0x6>;
515+ linux,phandle = <0x4>;
516+ phandle = <0x4>;
517+ };
518+
519+ gpio@40040000 {
520+ #gpio-cells = <0x2>;
521+ compatible = "xlnx,xps-gpio-1.00.a";
522+ gpio-controller;
523+ reg = <0x40040000 0x10000>;
524+ xlnx,all-inputs = <0x1>;
525+ xlnx,all-inputs-2 = <0x0>;
526+ xlnx,all-outputs = <0x0>;
527+ xlnx,all-outputs-2 = <0x0>;
528+ xlnx,dout-default = <0x0>;
529+ xlnx,dout-default-2 = <0x0>;
530+ xlnx,gpio-width = <0x5>;
531+ xlnx,gpio2-width = <0x20>;
532+ xlnx,interrupt-present = <0x0>;
533+ xlnx,is-dual = <0x0>;
534+ xlnx,tri-default = <0xffffffff>;
535+ xlnx,tri-default-2 = <0xffffffff>;
536+ };
537+
538+ gpio@40000000 {
539+ #gpio-cells = <0x2>;
540+ compatible = "xlnx,xps-gpio-1.00.a";
541+ gpio-controller;
542+ reg = <0x40000000 0x10000>;
543+ xlnx,all-inputs = <0x0>;
544+ xlnx,all-inputs-2 = <0x0>;
545+ xlnx,all-outputs = <0x1>;
546+ xlnx,all-outputs-2 = <0x0>;
547+ xlnx,dout-default = <0x0>;
548+ xlnx,dout-default-2 = <0x0>;
549+ xlnx,gpio-width = <0x1>;
550+ xlnx,gpio2-width = <0x20>;
551+ xlnx,interrupt-present = <0x0>;
552+ xlnx,is-dual = <0x0>;
553+ xlnx,tri-default = <0xffffffff>;
554+ xlnx,tri-default-2 = <0xffffffff>;
555+ linux,phandle = <0x1>;
556+ phandle = <0x1>;
557+ };
558+
559+ serial@44a00000 {
560+ clock-frequency = <0xbebc200>;
561+ clocks = <0x8>;
562+ compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
563+ current-speed = <0x1c200>;
564+ device_type = "serial";
565+ interrupt-parent = <0x4>;
566+ interrupts = <0x0 0x2>;
567+ port-number = <0x0>;
568+ reg = <0x44a00000 0x10000>;
569+ reg-offset = <0x1000>;
570+ reg-shift = <0x2>;
571+ xlnx,external-xin-clk-hz = <0x17d7840>;
572+ xlnx,external-xin-clk-hz-d = <0x19>;
573+ xlnx,has-external-rclk = <0x0>;
574+ xlnx,has-external-xin = <0x0>;
575+ xlnx,is-a-16550 = <0x1>;
576+ xlnx,s-axi-aclk-freq-hz-d = "200.0";
577+ xlnx,use-modem-ports = <0x1>;
578+ xlnx,use-user-ports = <0x1>;
579+ };
580+ };
581+
582 chosen {
583- } ;
584-} ;
585+ bootargs = "console=ttyS0,115200 earlyprintk";
586+ stdout-path = "serial0:115200n8";
587+ };
588+
589+ aliases {
590+ ethernet0 = "/amba_pl/ethernet@40c00000";
591+ i2c0 = "/amba_pl/i2c@40800000";
592+ serial0 = "/amba_pl/serial@44a00000";
593+ };
594+
595+ memory {
596+ device_type = "memory";
597+ reg = <0x80000000 0x40000000>;
598+ };
599+};
600+
601diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
602index 1dee2d6..cb75fde 100644
603--- a/board/xilinx/microblaze-generic/config.mk
604+++ b/board/xilinx/microblaze-generic/config.mk
605@@ -1,20 +1,10 @@
606-#
607-# (C) Copyright 2007 - 2016 Michal Simek
608-#
609-# Michal SIMEK <monstr@monstr.eu>
610-#
611-# SPDX-License-Identifier: GPL-2.0+
612-#
613-
614-CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
615-
616-# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
617-CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
618-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
619-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
620-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
621-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
622-
623-CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
624-
625-PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
626+TEXT_BASE = 0x80400000
627+CONFIG_SYS_TEXT_BASE = 0x80400000
628+
629+PLATFORM_CPPFLAGS += -mxl-barrel-shift
630+PLATFORM_CPPFLAGS += -mno-xl-soft-div
631+PLATFORM_CPPFLAGS += -mxl-pattern-compare
632+PLATFORM_CPPFLAGS += -mxl-multiply-high
633+PLATFORM_CPPFLAGS += -mno-xl-soft-mul
634+PLATFORM_CPPFLAGS += -mcpu=v10.0
635+PLATFORM_CPPFLAGS += -fgnu89-inline
636diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
637index 5d13d21..1458ce6 100644
638--- a/configs/microblaze-generic_defconfig
639+++ b/configs/microblaze-generic_defconfig
640@@ -7,32 +7,35 @@ CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
641 CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
642 CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
643 CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
644-CONFIG_SYS_TEXT_BASE=0x29000000
645+CONFIG_SYS_TEXT_BASE=0x80400000
646 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
647 CONFIG_FIT=y
648 CONFIG_FIT_VERBOSE=y
649-CONFIG_BOOTDELAY=-1
650+CONFIG_BOOTDELAY=4
651 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
652-CONFIG_SPL=y
653-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
654 CONFIG_SPL_NOR_SUPPORT=y
655 CONFIG_SPL_OS_BOOT=y
656 CONFIG_SYS_OS_BASE=0x2c060000
657 CONFIG_HUSH_PARSER=y
658-CONFIG_SYS_PROMPT="U-Boot-mONStR> "
659+CONFIG_SYS_PROMPT="U-Boot> "
660 CONFIG_CMD_ASKENV=y
661-CONFIG_CMD_GPIO=y
662 # CONFIG_CMD_SETEXPR is not set
663-CONFIG_CMD_TFTPPUT=y
664+CONFIG_SYS_ENET=y
665+CONFIG_NET=y
666+CONFIG_NETDEVICES=y
667+CONFIG_CMD_NET=y
668 CONFIG_CMD_DHCP=y
669+CONFIG_CMD_NFS=y
670 CONFIG_CMD_MII=y
671 CONFIG_CMD_PING=y
672-CONFIG_SPL_OF_CONTROL=y
673 CONFIG_OF_EMBED=y
674-CONFIG_NETCONSOLE=y
675-CONFIG_SPL_DM=y
676 CONFIG_DM_ETH=y
677+CONFIG_SYS_MALLOC_F=y
678+CONFIG_SYS_GENERIC_BOARD=y
679 CONFIG_XILINX_AXIEMAC=y
680-CONFIG_XILINX_EMACLITE=y
681 CONFIG_SYS_NS16550=y
682-CONFIG_XILINX_UARTLITE=y
683+CONFIG_CMD_FLASH=y
684+CONFIG_CMD_IMLS=y
685+CONFIG_CMD_GPIO=y
686+CONFIG_CMD_TFTPPUT=y
687+CONFIG_NETCONSOLE=y
688diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
689index 36b0a0e..1227c95 100644
690--- a/include/configs/microblaze-generic.h
691+++ b/include/configs/microblaze-generic.h
692@@ -1,319 +1,183 @@
693-/*
694- * (C) Copyright 2007-2010 Michal Simek
695- *
696- * Michal SIMEK <monstr@monstr.eu>
697- *
698- * SPDX-License-Identifier: GPL-2.0+
699- */
700-
701 #ifndef __CONFIG_H
702 #define __CONFIG_H
703
704-#include "../board/xilinx/microblaze-generic/xparameters.h"
705-
706-/* MicroBlaze CPU */
707-#define MICROBLAZE_V5 1
708-
709-/* linear and spi flash memory */
710-#ifdef XILINX_FLASH_START
711-#define FLASH
712-#undef SPIFLASH
713-#undef RAMENV /* hold environment in flash */
714-#else
715-#ifdef XILINX_SPI_FLASH_BASEADDR
716-#undef FLASH
717-#define SPIFLASH
718-#undef RAMENV /* hold environment in flash */
719-#else
720-#undef FLASH
721-#undef SPIFLASH
722-#define RAMENV /* hold environment in RAM */
723-#endif
724-#endif
725-
726-/* uart */
727-# define CONFIG_BAUDRATE 115200
728-/* The following table includes the supported baudrates */
729-# define CONFIG_SYS_BAUDRATE_TABLE \
730- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
731-
732-/* setting reset address */
733-/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
734+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
735
736-/* gpio */
737-#ifdef XILINX_GPIO_BASEADDR
738-# define CONFIG_XILINX_GPIO
739-# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
740-#endif
741-#define CONFIG_BOARD_LATE_INIT
742-
743-/* watchdog */
744-#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
745-# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
746-# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
747-# ifndef CONFIG_SPL_BUILD
748-# define CONFIG_HW_WATCHDOG
749-# define CONFIG_XILINX_TB_WATCHDOG
750-# endif
751-#endif
752-
753-#define CONFIG_SYS_MALLOC_LEN 0xC0000
754-
755-/* Stack location before relocation */
756-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
757- CONFIG_SYS_MALLOC_F_LEN)
758-
759-/*
760- * CFI flash memory layout - Example
761- * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
762- * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
763- *
764- * SECT_SIZE = 0x20000; 128kB is one sector
765- * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
766- *
767- * 0x2200_0000 CONFIG_SYS_FLASH_BASE
768- * FREE 256kB
769- * 0x2204_0000 CONFIG_ENV_ADDR
770- * ENV_AREA 128kB
771- * 0x2206_0000
772- * FREE
773- * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
774- *
775- */
776-
777-#ifdef FLASH
778-# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
779-# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
780-# define CONFIG_SYS_FLASH_CFI 1
781-# define CONFIG_FLASH_CFI_DRIVER 1
782-/* ?empty sector */
783-# define CONFIG_SYS_FLASH_EMPTY_INFO 1
784-/* max number of memory banks */
785-# define CONFIG_SYS_MAX_FLASH_BANKS 1
786-/* max number of sectors on one chip */
787-# define CONFIG_SYS_MAX_FLASH_SECT 512
788-/* hardware flash protection */
789-# define CONFIG_SYS_FLASH_PROTECTION
790-/* use buffered writes (20x faster) */
791-# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
792-# ifdef RAMENV
793-# define CONFIG_ENV_IS_NOWHERE 1
794-# define CONFIG_ENV_SIZE 0x1000
795-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
796-
797-# else /* FLASH && !RAMENV */
798-# define CONFIG_ENV_IS_IN_FLASH 1
799-/* 128K(one sector) for env */
800-# define CONFIG_ENV_SECT_SIZE 0x20000
801-# define CONFIG_ENV_ADDR \
802- (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
803-# define CONFIG_ENV_SIZE 0x20000
804-# endif /* FLASH && !RAMBOOT */
805-#else /* !FLASH */
806-
807-#ifdef SPIFLASH
808-# define CONFIG_SYS_NO_FLASH 1
809-# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
810-# define CONFIG_SPI 1
811-# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
812-# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
813-# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
814-
815-# ifdef RAMENV
816-# define CONFIG_ENV_IS_NOWHERE 1
817-# define CONFIG_ENV_SIZE 0x1000
818-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
819-
820-# else /* SPIFLASH && !RAMENV */
821-# define CONFIG_ENV_IS_IN_SPI_FLASH 1
822-# define CONFIG_ENV_SPI_MODE SPI_MODE_3
823-# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
824-# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
825-/* 128K(two sectors) for env */
826-# define CONFIG_ENV_SECT_SIZE 0x10000
827-# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
828-/* Warning: adjust the offset in respect of other flash content and size */
829-# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
830-# endif /* SPIFLASH && !RAMBOOT */
831-#else /* !SPIFLASH */
832-
833-/* ENV in RAM */
834-# define CONFIG_SYS_NO_FLASH 1
835-# define CONFIG_ENV_IS_NOWHERE 1
836-# define CONFIG_ENV_SIZE 0x1000
837-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
838-#endif /* !SPIFLASH */
839-#endif /* !FLASH */
840-
841-#if defined(XILINX_USE_ICACHE)
842-# define CONFIG_ICACHE
843-#else
844-# undef CONFIG_ICACHE
845-#endif
846-
847-#if defined(XILINX_USE_DCACHE)
848-# define CONFIG_DCACHE
849-#else
850-# undef CONFIG_DCACHE
851-#endif
852+/* use serial multi for all serial devices */
853+#define CONFIG_SERIAL_MULTI
854+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
855
856-#ifndef XILINX_DCACHE_BYTE_SIZE
857-#define XILINX_DCACHE_BYTE_SIZE 32768
858-#endif
859+/* Board name */
860
861-/*
862- * BOOTP options
863- */
864+/* processor - microblaze_0 */
865+#define XILINX_USE_MSR_INSTR 1
866+#define XILINX_USE_ICACHE 1
867+#define XILINX_USE_DCACHE 1
868+#define XILINX_DCACHE_BYTE_SIZE 16384
869+#define XILINX_PVR 2
870+#define MICROBLAZE_V5
871+#define CONFIG_CMD_IRQ
872+#define CONFIG_DCACHE
873+#define CONFIG_ICACHE
874+
875+/* main_memory - ddr3_sdram */
876+
877+
878+/* uart - rs232_uart */
879+#define CONFIG_CONS_INDEX 1
880+#define CONFIG_SYS_NS16550_COM1 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
881+#define CONFIG_SYS_NS16550_REG_SIZE -4
882+#define CONSOLE_ARG "console=console=ttyS0,115200\0"
883+#define CONFIG_SYS_NS16550_SERIAL
884+#define ESERIAL0 "eserial0=setenv stdout eserial0;setenv stdin eserial0\0"
885+#define SERIAL_MULTI "serial=setenv stdout serial;setenv stdin serial\0"
886+#define CONFIG_SYS_NS16550_CLK 200000000
887+#define CONFIG_BAUDRATE 115200
888+
889+/* ethernet - axi_ethernet */
890+#define CONFIG_PHY_XILINX
891+#define CONFIG_MII
892+#define CONFIG_PHY_GIGE
893+#define CONFIG_PHY_MARVELL
894+#define CONFIG_PHY_NATSEMI
895+#define CONFIG_NET_MULTI
896+#define CONFIG_NETCONSOLE 1
897+#define CONFIG_SERVERIP 172.25.229.115
898+#define CONFIG_IPADDR
899+
900+/* nor_flash - linear_flash */
901+#define CONFIG_SYS_FLASH_BASE 0x60000000
902+#define CONFIG_FLASH_END 0x68000000
903+#define CONFIG_SYS_MAX_FLASH_SECT 2048
904+#define CONFIG_SYS_FLASH_PROTECTION
905+#define CONFIG_SYS_FLASH_EMPTY_INFO
906+#define CONFIG_SYS_FLASH_CFI
907+#define CONFIG_FLASH_CFI_DRIVER
908+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
909+#define CONFIG_SYS_MAX_FLASH_BANKS 1
910+
911+/* timer - axi_timer_0 */
912+
913+/* gpio - reset_gpio */
914+#define XILINX_GPIO_BASEADDR 0x40000000
915+#define CONFIG_SYS_GPIO_0_ADDR 0x40000000
916+#define CONFIG_XILINX_GPIO
917+
918+/* intc - microblaze_0_axi_intc */
919+
920+/* Make the BOOTM LEN big enough for the compressed image */
921+#define CONFIG_SYS_BOOTM_LEN 0xF000000
922+
923+/* FPGA */
924+
925+/* Memory testing handling */
926+#define CONFIG_SYS_MEMTEST_START 0x80000000
927+#define CONFIG_SYS_MEMTEST_END (0x80000000 + 0x1000)
928+#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* default load address */
929+
930+/* global pointer options */
931+#define CONFIG_SYS_GBL_DATA_OFFSET (0x40000000 - GENERATED_GBL_DATA_SIZE)
932+
933+/* Size of malloc() pool */
934+#define SIZE 0x100000
935+#define CONFIG_SYS_MALLOC_LEN SIZE
936+#define CONFIG_SYS_MONITOR_LEN SIZE
937+#define CONFIG_SYS_MONITOR_BASE (0x80000000 + CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
938+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
939+
940+/* stack */
941+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_F_LEN)
942+
943+/* No of_control support yet*/
944+
945+/* BOOTP options */
946+#define CONFIG_BOOTP_SERVERIP
947 #define CONFIG_BOOTP_BOOTFILESIZE
948 #define CONFIG_BOOTP_BOOTPATH
949 #define CONFIG_BOOTP_GATEWAY
950 #define CONFIG_BOOTP_HOSTNAME
951+#define CONFIG_BOOTP_MAY_FAIL
952
953-/*
954- * Command line configuration.
955- */
956-#define CONFIG_CMD_IRQ
957-#define CONFIG_CMD_MFSL
958-
959-#if defined(FLASH)
960-# define CONFIG_CMD_JFFS2
961-# undef CONFIG_CMD_UBIFS
962-
963-# if !defined(RAMENV)
964-# define CONFIG_CMD_SAVES
965-# endif
966-
967-#else
968-#if defined(SPIFLASH)
969-
970-# if !defined(RAMENV)
971-# define CONFIG_CMD_SAVES
972-# endif
973-#else
974-# undef CONFIG_CMD_JFFS2
975-# undef CONFIG_CMD_UBIFS
976-#endif
977-#endif
978-
979-#if defined(CONFIG_CMD_JFFS2)
980-# define CONFIG_MTD_PARTITIONS
981-#endif
982-
983-#if defined(CONFIG_CMD_UBIFS)
984-# define CONFIG_LZO
985-#endif
986-
987-#if defined(CONFIG_CMD_UBI)
988-# define CONFIG_MTD_PARTITIONS
989-# define CONFIG_RBTREE
990-#endif
991-
992-#if defined(CONFIG_MTD_PARTITIONS)
993-/* MTD partitions */
994-#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
995-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
996-#define CONFIG_FLASH_CFI_MTD
997-#define MTDIDS_DEFAULT "nor0=flash-0"
998-
999-/* default mtd partition table */
1000-#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
1001- "256k(env),3m(kernel),1m(romfs),"\
1002- "1m(cramfs),-(jffs2)"
1003-#endif
1004-
1005-/* size of console buffer */
1006-#define CONFIG_SYS_CBSIZE 512
1007- /* print buffer size */
1008-#define CONFIG_SYS_PBSIZE \
1009- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
1010-/* max number of command args */
1011-#define CONFIG_SYS_MAXARGS 15
1012-#define CONFIG_SYS_LONGHELP
1013-/* default load address */
1014-#define CONFIG_SYS_LOAD_ADDR 0
1015-
1016-#define CONFIG_BOOTARGS "root=romfs"
1017-#define CONFIG_HOSTNAME XILINX_BOARD_NAME
1018-#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
1019-
1020-/* architecture dependent code */
1021-#define CONFIG_SYS_USR_EXCEP /* user exception */
1022-
1023-#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
1024-
1025-#ifndef CONFIG_EXTRA_ENV_SETTINGS
1026-#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
1027- "nor0=flash-0\0"\
1028- "mtdparts=mtdparts=flash-0:"\
1029- "256k(u-boot),256k(env),3m(kernel),"\
1030- "1m(romfs),1m(cramfs),-(jffs2)\0"\
1031- "nc=setenv stdout nc;"\
1032- "setenv stdin nc\0" \
1033- "serial=setenv stdout serial;"\
1034- "setenv stdin serial\0"
1035-#endif
1036-
1037+/*Command line configuration.*/
1038 #define CONFIG_CMDLINE_EDITING
1039+#define CONFIG_CMD_SAVES
1040
1041-/* Enable flat device tree support */
1042-#define CONFIG_LMB 1
1043-
1044-#if defined(CONFIG_XILINX_AXIEMAC)
1045-# define CONFIG_MII 1
1046-# define CONFIG_PHY_GIGE 1
1047-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
1048-# define CONFIG_PHY_ATHEROS 1
1049-# define CONFIG_PHY_BROADCOM 1
1050-# define CONFIG_PHY_DAVICOM 1
1051-# define CONFIG_PHY_LXT 1
1052-# define CONFIG_PHY_MARVELL 1
1053-# define CONFIG_PHY_MICREL 1
1054-# define CONFIG_PHY_MICREL_KSZ9021
1055-# define CONFIG_PHY_NATSEMI 1
1056-# define CONFIG_PHY_REALTEK 1
1057-# define CONFIG_PHY_VITESSE 1
1058-#else
1059-# undef CONFIG_MII
1060-#endif
1061-
1062-/* SPL part */
1063-#define CONFIG_CMD_SPL
1064-#define CONFIG_SPL_FRAMEWORK
1065-#define CONFIG_SPL_BOARD_INIT
1066+/* Miscellaneous configurable options */
1067+#define CONFIG_SYS_CBSIZE 2048/* Console I/O Buffer Size */
1068+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
1069
1070-#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
1071+/* Boot Argument Buffer Size */
1072+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
1073+#define CONFIG_SYS_LONGHELP
1074+/* architecture dependent code */
1075+#define CONFIG_SYS_USR_EXCEP /* user exception */
1076+#define CONFIG_SYS_HZ 1000
1077+
1078+/* Use the HUSH parser */
1079+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
1080+
1081+/* Don't define BOOTARGS, we get it from the DTB chosen fragment */
1082+#undef CONFIG_BOOTARGS
1083+
1084+#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */
1085+
1086+#define CONFIG_LMB
1087+
1088+/* Initial memory map for Linux */
1089+#define CONFIG_SYS_BOOTMAPSZ 0x8000000
1090+
1091+/* Environment settings*/
1092+#define CONFIG_ENV_IS_IN_FLASH
1093+#define CONFIG_ENV_ADDR 0x60b80000
1094+#define CONFIG_ENV_SIZE 0x20000
1095+#define CONFIG_ENV_SECT_SIZE 0x20000
1096+/* PREBOOT */
1097+#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot; echo; dhcp"
1098+
1099+/* Extra U-Boot Env settings */
1100+#define CONFIG_EXTRA_ENV_SETTINGS \
1101+ SERIAL_MULTI \
1102+ CONSOLE_ARG \
1103+ ESERIAL0 \
1104+ "nc=setenv stdout nc;setenv stdin nc;\0" \
1105+ "ethaddr=00:0a:35:00:22:01\0" \
1106+ "autoload=no\0" \
1107+ "clobstart=0x81000000\0" \
1108+ "netstart=0x81000000\0" \
1109+ "dtbnetstart=0x82800000\0" \
1110+ "loadaddr=0x81000000\0" \
1111+ "bootsize=0x80000\0" \
1112+ "bootstart=0x60b00000\0" \
1113+ "boot_img=u-boot-s.bin\0" \
1114+ "load_boot=tftpboot ${clobstart} ${boot_img}\0" \
1115+ "update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot test_img; setenv img; setenv psize; setenv installcmd\0" \
1116+ "install_boot=protect off ${bootstart} +${bootsize} && erase ${bootstart} +${bootsize} && " "cp.b ${clobstart} ${bootstart} ${filesize}\0" \
1117+ "bootenvsize=0x20000\0" \
1118+ "bootenvstart=0x60b80000\0" \
1119+ "eraseenv=protect off ${bootenvstart} +${bootenvsize} && erase ${bootenvstart} +${bootenvsize}\0" \
1120+ "kernelsize=0xc00000\0" \
1121+ "kernelstart=0x60ba0000\0" \
1122+ "kernel_img=image.ub\0" \
1123+ "load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \
1124+ "update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel test_crc; setenv img; setenv psize; setenv installcmd\0" \
1125+ "install_kernel=protect off ${kernelstart} +${kernelsize} && erase ${kernelstart} +${kernelsize} && " "cp.b ${clobstart} ${kernelstart} ${filesize}\0" \
1126+ "cp_kernel2ram=cp.b ${kernelstart} ${netstart} ${kernelsize}\0" \
1127+ "fpgasize=0xb00000\0" \
1128+ "fpgastart=0x60000000\0" \
1129+ "fpga_img=system.bit.bin\0" \
1130+ "load_fpga=tftpboot ${clobstart} ${fpga_img}\0" \
1131+ "update_fpga=setenv img fpga; setenv psize ${fpgasize}; setenv installcmd \"install_fpga\"; run load_fpga test_img; setenv img; setenv psize; setenv installcmd\0" \
1132+ "install_fpga=protect off ${fpgastart} +${fpgasize} && erase ${fpgastart} +${fpgasize} && " "cp.b ${clobstart} ${fpgastart} ${filesize}\0" \
1133+ "fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \
1134+ "test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \
1135+ "test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \
1136+ "netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \
1137+ "default_bootcmd=bootm ${kernelstart}\0" \
1138+""
1139+
1140+/* BOOTCOMMAND */
1141+#define CONFIG_BOOTCOMMAND "run default_bootcmd"
1142+
1143+#undef CONFIG_SPL_BUILD /* Disable SPL by default*/
1144
1145-#define CONFIG_SPL_RAM_DEVICE
1146-#ifdef CONFIG_SYS_FLASH_BASE
1147-# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
1148 #endif
1149-
1150-/* for booting directly linux */
1151-
1152-#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
1153- 0x40000)
1154-#define CONFIG_SYS_FDT_SIZE (16<<10)
1155-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
1156- 0x1000000)
1157-
1158-/* SP location before relocation, must use scratch RAM */
1159-/* BRAM start */
1160-#define CONFIG_SYS_INIT_RAM_ADDR 0x0
1161-/* BRAM size - will be generated */
1162-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
1163-
1164-# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
1165- CONFIG_SYS_INIT_RAM_SIZE - \
1166- CONFIG_SYS_MALLOC_F_LEN)
1167-
1168-/* Just for sure that there is a space for stack */
1169-#define CONFIG_SPL_STACK_SIZE 0x100
1170-
1171-#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
1172-
1173-#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
1174- CONFIG_SYS_INIT_RAM_ADDR - \
1175- CONFIG_SYS_MALLOC_F_LEN - \
1176- CONFIG_SPL_STACK_SIZE)
1177-
1178-#endif /* __CONFIG_H */
1179--
11802.7.4
1181
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2017.3.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2017.3.bb
deleted file mode 100644
index 016c0cee..00000000
--- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2017.3.bb
+++ /dev/null
@@ -1,26 +0,0 @@
1UBOOT_VERSION = "v2017.01"
2XILINX_RELEASE_VERSION = "v2017.3"
3SRCREV ?= "da811c4511ef9caeb95f9a22fe49d38bd8e56ded"
4
5include u-boot-xlnx.inc
6include u-boot-spl-zynq-init.inc
7
8SRC_URI_append = " \
9 file://arm64-zynqmp-Setup-partid-for-QEMU-to-match-silicon.patch \
10 "
11
12SRC_URI_append_kc705-microblazeel = " file://microblaze-kc705-Convert-microblaze-generic-to-k.patch"
13
14LICENSE = "GPLv2+"
15LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c"
16
17# u-boot-xlnx has support for these
18HAS_PLATFORM_INIT ?= " \
19 zynq_microzed_config \
20 zynq_zed_config \
21 zynq_zc702_config \
22 zynq_zc706_config \
23 zynq_zybo_config \
24 xilinx_zynqmp_zcu102_rev1_0_config \
25 "
26
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2017.3.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2017.3.bb
deleted file mode 100644
index ec6093b7..00000000
--- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2017.3.bb
+++ /dev/null
@@ -1,4 +0,0 @@
1require qemu-devicetrees.inc
2
3XILINX_RELEASE_VERSION = "v2017.3"
4SRCREV ?= "4b951c594078562e9dd828430075968dd91ac425"
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2017.3.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2017.3.bb
deleted file mode 100644
index f8a91d75..00000000
--- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2017.3.bb
+++ /dev/null
@@ -1,5 +0,0 @@
1require qemu-xilinx.inc
2
3XILINX_RELEASE_VERSION = "v2017.3"
4XILINX_QEMU_VERSION = "v2.8.1"
5SRCREV ?= "8f8c89b18f6e4523099e41d81769fc534064b8de"
diff --git a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2017.3.bb b/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2017.3.bb
deleted file mode 100644
index 7115947b..00000000
--- a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2017.3.bb
+++ /dev/null
@@ -1,6 +0,0 @@
1LINUX_VERSION = "4.9"
2XILINX_RELEASE_VERSION = "v2017.3"
3SRCREV ?= "f1b1e077d641fc83b54c1b8f168cbb58044fbd4e"
4
5include linux-xlnx.inc
6
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2017.3/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2017.3/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
deleted file mode 100644
index b8ba70ea..00000000
--- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2017.3/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
+++ /dev/null
@@ -1,302 +0,0 @@
1From c1bf9e8c50baa237b514715dcb9c8fd367694c93 Mon Sep 17 00:00:00 2001
2From: Jason Wu <jason.wu.misc@gmail.com>
3Date: Sun, 10 Apr 2016 13:14:13 +1000
4Subject: [PATCH 1/3] drm: xilinx: Add encoder for Digilent boards
5
6Add the dglnt_encoder driver that enables DRM support for the VGA and
7HDMI output ports found on many Digilent boards.
8
9Upstream-Status: Pending
10
11Signed-off-by: Sam Bobrowicz <sbobrowicz@digilentinc.com>
12Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
13---
14 .../bindings/drm/xilinx/dglnt_encoder.txt | 23 +++
15 drivers/gpu/drm/xilinx/Kconfig | 6 +
16 drivers/gpu/drm/xilinx/Makefile | 1 +
17 drivers/gpu/drm/xilinx/dglnt_encoder.c | 217 +++++++++++++++++++++
18 4 files changed, 247 insertions(+)
19 create mode 100644 Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
20 create mode 100644 drivers/gpu/drm/xilinx/dglnt_encoder.c
21
22diff --git a/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
23new file mode 100644
24index 0000000000..242b24e482
25--- /dev/null
26+++ b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
27@@ -0,0 +1,23 @@
28+Device-Tree bindings for Digilent DRM Encoder Slave
29+
30+This driver provides support for VGA and HDMI outputs on Digilent FPGA boards.
31+The VGA or HDMI port must be connected to a Xilinx display pipeline via an
32+axi2vid IP core.
33+
34+Required properties:
35+ - compatible: Should be "digilent,drm-encoder".
36+
37+Optional properties:
38+ - dglnt,edid-i2c: The I2C device connected to the DDC bus on the video
39+ connector. This is used to obtain the supported resolutions
40+ of an attached monitor. If not defined, then a default
41+ set of resolutions is used and the display will initialize
42+ to 720p. Note most VGA connectors on Digilent boards do
43+ not have the DDC bus routed out.
44+
45+Example:
46+
47+ encoder_0: digilent_encoder {
48+ compatible = "digilent,drm-encoder";
49+ dglnt,edid-i2c = <&i2c1>;
50+ };
51diff --git a/drivers/gpu/drm/xilinx/Kconfig b/drivers/gpu/drm/xilinx/Kconfig
52index 12b548c2a9..c3e2562e53 100644
53--- a/drivers/gpu/drm/xilinx/Kconfig
54+++ b/drivers/gpu/drm/xilinx/Kconfig
55@@ -57,3 +57,9 @@ config DRM_XILINX_SDI
56 depends on DRM_XILINX
57 help
58 DRM driver for Xilinx Display Port Subsystem.
59+
60+config DRM_DIGILENT_ENCODER
61+ tristate "Digilent VGA/HDMI DRM Encoder Driver"
62+ depends on DRM_XILINX
63+ help
64+ DRM slave encoder for Video-out on Digilent boards.
65diff --git a/drivers/gpu/drm/xilinx/Makefile b/drivers/gpu/drm/xilinx/Makefile
66index 19bc1541ca..c2717e40ea 100644
67--- a/drivers/gpu/drm/xilinx/Makefile
68+++ b/drivers/gpu/drm/xilinx/Makefile
69@@ -7,6 +7,7 @@ xilinx_drm-y := xilinx_drm_crtc.o xilinx_drm_connector.o xilinx_drm_drv.o \
70 xilinx_drm_plane.o
71 xilinx_drm-y += xilinx_cresample.o xilinx_osd.o xilinx_rgb2yuv.o xilinx_vtc.o
72
73+obj-$(CONFIG_DRM_DIGILENT_ENCODER) += dglnt_encoder.o
74 obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o
75 obj-$(CONFIG_DRM_XILINX_DP) += xilinx_drm_dp.o
76 obj-$(CONFIG_DRM_XILINX_DP_SUB) += xilinx_drm_dp_sub.o
77diff --git a/drivers/gpu/drm/xilinx/dglnt_encoder.c b/drivers/gpu/drm/xilinx/dglnt_encoder.c
78new file mode 100644
79index 0000000000..26a23986f9
80--- /dev/null
81+++ b/drivers/gpu/drm/xilinx/dglnt_encoder.c
82@@ -0,0 +1,217 @@
83+/*
84+ * dglnt_encoder.c - DRM slave encoder for Video-out on Digilent boards
85+ *
86+ * Copyright (C) 2015 Digilent
87+ * Author: Sam Bobrowicz <sbobrowicz@digilentinc.com>
88+ *
89+ * Based on udl_encoder.c and udl_connector.c, Copyright (C) 2012 Red Hat.
90+ * Also based on xilinx_drm_dp.c, Copyright (C) 2014 Xilinx, Inc.
91+ *
92+ * This software is licensed under the terms of the GNU General Public
93+ * License version 2, as published by the Free Software Foundation, and
94+ * may be copied, distributed, and modified under those terms.
95+ *
96+ * This program is distributed in the hope that it will be useful,
97+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
98+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
99+ * GNU General Public License for more details.
100+ */
101+
102+#include <drm/drmP.h>
103+#include <drm/drm_edid.h>
104+#include <drm/drm_encoder_slave.h>
105+
106+#include <linux/device.h>
107+#include <linux/module.h>
108+#include <linux/err.h>
109+#include <linux/i2c.h>
110+#include <linux/of.h>
111+#include <linux/of_platform.h>
112+#include <linux/platform_device.h>
113+
114+#define DGLNT_ENC_MAX_FREQ 150000
115+#define DGLNT_ENC_MAX_H 1920
116+#define DGLNT_ENC_MAX_V 1080
117+#define DGLNT_ENC_PREF_H 1280
118+#define DGLNT_ENC_PREF_V 720
119+
120+struct dglnt_encoder {
121+ struct drm_encoder *encoder;
122+ struct i2c_adapter *i2c_bus;
123+ bool i2c_present;
124+};
125+
126+static inline struct dglnt_encoder *to_dglnt_encoder(
127+ struct drm_encoder *encoder)
128+{
129+ return to_encoder_slave(encoder)->slave_priv;
130+}
131+
132+static bool dglnt_mode_fixup(struct drm_encoder *encoder,
133+ const struct drm_display_mode *mode,
134+ struct drm_display_mode *adjusted_mode)
135+{
136+ return true;
137+}
138+
139+static void dglnt_encoder_mode_set(struct drm_encoder *encoder,
140+ struct drm_display_mode *mode,
141+ struct drm_display_mode *adjusted_mode)
142+{
143+}
144+
145+static void
146+dglnt_encoder_dpms(struct drm_encoder *encoder, int mode)
147+{
148+}
149+
150+static void dglnt_encoder_save(struct drm_encoder *encoder)
151+{
152+}
153+
154+static void dglnt_encoder_restore(struct drm_encoder *encoder)
155+{
156+}
157+
158+static int dglnt_encoder_mode_valid(struct drm_encoder *encoder,
159+ struct drm_display_mode *mode)
160+{
161+ if (mode &&
162+ !(mode->flags & ((DRM_MODE_FLAG_INTERLACE |
163+ DRM_MODE_FLAG_DBLCLK) | DRM_MODE_FLAG_3D_MASK)) &&
164+ (mode->clock <= DGLNT_ENC_MAX_FREQ) &&
165+ (mode->hdisplay <= DGLNT_ENC_MAX_H) &&
166+ (mode->vdisplay <= DGLNT_ENC_MAX_V))
167+ return MODE_OK;
168+ return MODE_BAD;
169+}
170+
171+static int dglnt_encoder_get_modes(struct drm_encoder *encoder,
172+ struct drm_connector *connector)
173+{
174+ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder);
175+ struct edid *edid;
176+ int num_modes = 0;
177+
178+ if (dglnt->i2c_present) {
179+ edid = drm_get_edid(connector, dglnt->i2c_bus);
180+ drm_mode_connector_update_edid_property(connector, edid);
181+ if (edid) {
182+ num_modes = drm_add_edid_modes(connector, edid);
183+ kfree(edid);
184+ }
185+ } else {
186+ num_modes = drm_add_modes_noedid(connector, DGLNT_ENC_MAX_H,
187+ DGLNT_ENC_MAX_V);
188+ drm_set_preferred_mode(connector, DGLNT_ENC_PREF_H,
189+ DGLNT_ENC_PREF_V);
190+ }
191+ return num_modes;
192+}
193+
194+static enum drm_connector_status dglnt_encoder_detect(
195+ struct drm_encoder *encoder,
196+ struct drm_connector *connector)
197+{
198+ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder);
199+
200+ if (dglnt->i2c_present) {
201+ if (drm_probe_ddc(dglnt->i2c_bus))
202+ return connector_status_connected;
203+ return connector_status_disconnected;
204+ } else
205+ return connector_status_unknown;
206+}
207+
208+static struct drm_encoder_slave_funcs dglnt_encoder_slave_funcs = {
209+ .dpms = dglnt_encoder_dpms,
210+ .save = dglnt_encoder_save,
211+ .restore = dglnt_encoder_restore,
212+ .mode_fixup = dglnt_mode_fixup,
213+ .mode_valid = dglnt_encoder_mode_valid,
214+ .mode_set = dglnt_encoder_mode_set,
215+ .detect = dglnt_encoder_detect,
216+ .get_modes = dglnt_encoder_get_modes,
217+};
218+
219+static int dglnt_encoder_encoder_init(struct platform_device *pdev,
220+ struct drm_device *dev,
221+ struct drm_encoder_slave *encoder)
222+{
223+ struct dglnt_encoder *dglnt = platform_get_drvdata(pdev);
224+ struct device_node *sub_node;
225+
226+ encoder->slave_priv = dglnt;
227+ encoder->slave_funcs = &dglnt_encoder_slave_funcs;
228+
229+ dglnt->encoder = &encoder->base;
230+
231+ /* get i2c adapter for edid */
232+ dglnt->i2c_present = false;
233+ sub_node = of_parse_phandle(pdev->dev.of_node, "dglnt,edid-i2c", 0);
234+ if (sub_node) {
235+ dglnt->i2c_bus = of_find_i2c_adapter_by_node(sub_node);
236+ if (!dglnt->i2c_bus)
237+ DRM_INFO("failed to get the edid i2c adapter, using default modes\n");
238+ else
239+ dglnt->i2c_present = true;
240+ of_node_put(sub_node);
241+ }
242+
243+ return 0;
244+}
245+
246+static int dglnt_encoder_probe(struct platform_device *pdev)
247+{
248+ struct dglnt_encoder *dglnt;
249+
250+ dglnt = devm_kzalloc(&pdev->dev, sizeof(*dglnt), GFP_KERNEL);
251+ if (!dglnt)
252+ return -ENOMEM;
253+
254+ platform_set_drvdata(pdev, dglnt);
255+
256+ return 0;
257+}
258+
259+static int dglnt_encoder_remove(struct platform_device *pdev)
260+{
261+ return 0;
262+}
263+
264+static const struct of_device_id dglnt_encoder_of_match[] = {
265+ { .compatible = "digilent,drm-encoder", },
266+ { /* end of table */ },
267+};
268+MODULE_DEVICE_TABLE(of, dglnt_encoder_of_match);
269+
270+static struct drm_platform_encoder_driver dglnt_encoder_driver = {
271+ .platform_driver = {
272+ .probe = dglnt_encoder_probe,
273+ .remove = dglnt_encoder_remove,
274+ .driver = {
275+ .owner = THIS_MODULE,
276+ .name = "dglnt-drm-enc",
277+ .of_match_table = dglnt_encoder_of_match,
278+ },
279+ },
280+
281+ .encoder_init = dglnt_encoder_encoder_init,
282+};
283+
284+static int __init dglnt_encoder_init(void)
285+{
286+ return platform_driver_register(&dglnt_encoder_driver.platform_driver);
287+}
288+
289+static void __exit dglnt_encoder_exit(void)
290+{
291+ platform_driver_unregister(&dglnt_encoder_driver.platform_driver);
292+}
293+
294+module_init(dglnt_encoder_init);
295+module_exit(dglnt_encoder_exit);
296+
297+MODULE_AUTHOR("Digilent, Inc.");
298+MODULE_DESCRIPTION("DRM slave encoder for Video-out on Digilent boards");
299+MODULE_LICENSE("GPL v2");
300--
3012.14.2
302
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2017.3/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2017.3/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
deleted file mode 100644
index 9b6229db..00000000
--- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2017.3/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
+++ /dev/null
@@ -1,607 +0,0 @@
1From 217e3b6f4393926b8dcad841381527ef3fc808c2 Mon Sep 17 00:00:00 2001
2From: Jason Wu <jason.wu.misc@gmail.com>
3Date: Sun, 10 Apr 2016 13:16:06 +1000
4Subject: [PATCH 2/3] clk: Add driver for axi_dynclk IP Core
5
6Add support for the axi_dynclk IP Core available from Digilent. This IP
7core dynamically configures the clock resources inside a Xilinx FPGA to
8generate a clock with a software programmable frequency.
9
10Upstream-Status: Pending
11
12Signed-off-by: Sam Bobrowicz <sbobrowicz@digilentinc.com>
13Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
14---
15 drivers/clk/Kconfig | 8 +
16 drivers/clk/Makefile | 1 +
17 drivers/clk/clk-dglnt-dynclk.c | 547 +++++++++++++++++++++++++++++++++++++++++
18 3 files changed, 556 insertions(+)
19 create mode 100644 drivers/clk/clk-dglnt-dynclk.c
20
21diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
22index dccb111100..7fe65a702b 100644
23--- a/drivers/clk/Kconfig
24+++ b/drivers/clk/Kconfig
25@@ -148,6 +148,14 @@ config CLK_QORIQ
26 This adds the clock driver support for Freescale QorIQ platforms
27 using common clock framework.
28
29+config COMMON_CLK_DGLNT_DYNCLK
30+ tristate "Digilent axi_dynclk Driver"
31+ depends on ARCH_ZYNQ || MICROBLAZE
32+ help
33+ ---help---
34+ Support for the Digilent AXI Dynamic Clock core for Xilinx
35+ FPGAs.
36+
37 config COMMON_CLK_XGENE
38 bool "Clock driver for APM XGene SoC"
39 default y
40diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
41index 0760449dde..45ce97d053 100644
42--- a/drivers/clk/Makefile
43+++ b/drivers/clk/Makefile
44@@ -24,6 +24,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o
45 obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
46 obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
47 obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
48+obj-$(CONFIG_COMMON_CLK_DGLNT_DYNCLK) += clk-dglnt-dynclk.o
49 obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
50 obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
51 obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
52diff --git a/drivers/clk/clk-dglnt-dynclk.c b/drivers/clk/clk-dglnt-dynclk.c
53new file mode 100644
54index 0000000000..496ad5fc90
55--- /dev/null
56+++ b/drivers/clk/clk-dglnt-dynclk.c
57@@ -0,0 +1,547 @@
58+/*
59+ * clk-dglnt-dynclk.c - Digilent AXI Dynamic Clock (axi_dynclk) Driver
60+ *
61+ * Copyright (C) 2015 Digilent
62+ * Author: Sam Bobrowicz <sbobrowicz@digilentinc.com>
63+ *
64+ * Reused code from clk-axi-clkgen.c, Copyright (C) 2012-2013 Analog Devices Inc.
65+ *
66+ * This software is licensed under the terms of the GNU General Public
67+ * License version 2, as published by the Free Software Foundation, and
68+ * may be copied, distributed, and modified under those terms.
69+ *
70+ * This program is distributed in the hope that it will be useful,
71+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
72+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
73+ * GNU General Public License for more details.
74+ */
75+
76+#include <linux/platform_device.h>
77+#include <linux/clk-provider.h>
78+#include <linux/clk.h>
79+#include <linux/slab.h>
80+#include <linux/io.h>
81+#include <linux/of.h>
82+#include <linux/module.h>
83+#include <linux/err.h>
84+#include <linux/kernel.h>
85+
86+#define CLK_BIT_WEDGE 13
87+#define CLK_BIT_NOCOUNT 12
88+
89+/* This value is used to signal an error */
90+#define ERR_CLKCOUNTCALC 0xFFFFFFFF
91+#define ERR_CLKDIVIDER (1 << CLK_BIT_WEDGE | 1 << CLK_BIT_NOCOUNT)
92+
93+#define DYNCLK_DIV_1_REGMASK 0x1041
94+/* 25 MHz (125 KHz / 5) */
95+#define DYNCLK_DEFAULT_FREQ 125000
96+
97+#define MMCM_FREQ_VCOMIN 600000
98+#define MMCM_FREQ_VCOMAX 1200000
99+#define MMCM_FREQ_PFDMIN 10000
100+#define MMCM_FREQ_PFDMAX 450000
101+#define MMCM_FREQ_OUTMIN 4000
102+#define MMCM_FREQ_OUTMAX 800000
103+#define MMCM_DIV_MAX 106
104+#define MMCM_FB_MIN 2
105+#define MMCM_FB_MAX 64
106+#define MMCM_CLKDIV_MAX 128
107+#define MMCM_CLKDIV_MIN 1
108+
109+#define OFST_DISPLAY_CTRL 0x0
110+#define OFST_DISPLAY_STATUS 0x4
111+#define OFST_DISPLAY_CLK_L 0x8
112+#define OFST_DISPLAY_FB_L 0x0C
113+#define OFST_DISPLAY_FB_H_CLK_H 0x10
114+#define OFST_DISPLAY_DIV 0x14
115+#define OFST_DISPLAY_LOCK_L 0x18
116+#define OFST_DISPLAY_FLTR_LOCK_H 0x1C
117+
118+static const u64 lock_lookup[64] = {
119+ 0b0011000110111110100011111010010000000001,
120+ 0b0011000110111110100011111010010000000001,
121+ 0b0100001000111110100011111010010000000001,
122+ 0b0101101011111110100011111010010000000001,
123+ 0b0111001110111110100011111010010000000001,
124+ 0b1000110001111110100011111010010000000001,
125+ 0b1001110011111110100011111010010000000001,
126+ 0b1011010110111110100011111010010000000001,
127+ 0b1100111001111110100011111010010000000001,
128+ 0b1110011100111110100011111010010000000001,
129+ 0b1111111111111000010011111010010000000001,
130+ 0b1111111111110011100111111010010000000001,
131+ 0b1111111111101110111011111010010000000001,
132+ 0b1111111111101011110011111010010000000001,
133+ 0b1111111111101000101011111010010000000001,
134+ 0b1111111111100111000111111010010000000001,
135+ 0b1111111111100011111111111010010000000001,
136+ 0b1111111111100010011011111010010000000001,
137+ 0b1111111111100000110111111010010000000001,
138+ 0b1111111111011111010011111010010000000001,
139+ 0b1111111111011101101111111010010000000001,
140+ 0b1111111111011100001011111010010000000001,
141+ 0b1111111111011010100111111010010000000001,
142+ 0b1111111111011001000011111010010000000001,
143+ 0b1111111111011001000011111010010000000001,
144+ 0b1111111111010111011111111010010000000001,
145+ 0b1111111111010101111011111010010000000001,
146+ 0b1111111111010101111011111010010000000001,
147+ 0b1111111111010100010111111010010000000001,
148+ 0b1111111111010100010111111010010000000001,
149+ 0b1111111111010010110011111010010000000001,
150+ 0b1111111111010010110011111010010000000001,
151+ 0b1111111111010010110011111010010000000001,
152+ 0b1111111111010001001111111010010000000001,
153+ 0b1111111111010001001111111010010000000001,
154+ 0b1111111111010001001111111010010000000001,
155+ 0b1111111111001111101011111010010000000001,
156+ 0b1111111111001111101011111010010000000001,
157+ 0b1111111111001111101011111010010000000001,
158+ 0b1111111111001111101011111010010000000001,
159+ 0b1111111111001111101011111010010000000001,
160+ 0b1111111111001111101011111010010000000001,
161+ 0b1111111111001111101011111010010000000001,
162+ 0b1111111111001111101011111010010000000001,
163+ 0b1111111111001111101011111010010000000001,
164+ 0b1111111111001111101011111010010000000001,
165+ 0b1111111111001111101011111010010000000001,
166+ 0b1111111111001111101011111010010000000001,
167+ 0b1111111111001111101011111010010000000001,
168+ 0b1111111111001111101011111010010000000001,
169+ 0b1111111111001111101011111010010000000001,
170+ 0b1111111111001111101011111010010000000001,
171+ 0b1111111111001111101011111010010000000001,
172+ 0b1111111111001111101011111010010000000001,
173+ 0b1111111111001111101011111010010000000001,
174+ 0b1111111111001111101011111010010000000001,
175+ 0b1111111111001111101011111010010000000001,
176+ 0b1111111111001111101011111010010000000001,
177+ 0b1111111111001111101011111010010000000001,
178+ 0b1111111111001111101011111010010000000001,
179+ 0b1111111111001111101011111010010000000001,
180+ 0b1111111111001111101011111010010000000001,
181+ 0b1111111111001111101011111010010000000001,
182+ 0b1111111111001111101011111010010000000001
183+};
184+
185+static const u32 filter_lookup_low[64] = {
186+ 0b0001011111,
187+ 0b0001010111,
188+ 0b0001111011,
189+ 0b0001011011,
190+ 0b0001101011,
191+ 0b0001110011,
192+ 0b0001110011,
193+ 0b0001110011,
194+ 0b0001110011,
195+ 0b0001001011,
196+ 0b0001001011,
197+ 0b0001001011,
198+ 0b0010110011,
199+ 0b0001010011,
200+ 0b0001010011,
201+ 0b0001010011,
202+ 0b0001010011,
203+ 0b0001010011,
204+ 0b0001010011,
205+ 0b0001010011,
206+ 0b0001010011,
207+ 0b0001010011,
208+ 0b0001010011,
209+ 0b0001100011,
210+ 0b0001100011,
211+ 0b0001100011,
212+ 0b0001100011,
213+ 0b0001100011,
214+ 0b0001100011,
215+ 0b0001100011,
216+ 0b0001100011,
217+ 0b0001100011,
218+ 0b0001100011,
219+ 0b0001100011,
220+ 0b0001100011,
221+ 0b0001100011,
222+ 0b0001100011,
223+ 0b0010010011,
224+ 0b0010010011,
225+ 0b0010010011,
226+ 0b0010010011,
227+ 0b0010010011,
228+ 0b0010010011,
229+ 0b0010010011,
230+ 0b0010010011,
231+ 0b0010010011,
232+ 0b0010010011,
233+ 0b0010100011,
234+ 0b0010100011,
235+ 0b0010100011,
236+ 0b0010100011,
237+ 0b0010100011,
238+ 0b0010100011,
239+ 0b0010100011,
240+ 0b0010100011,
241+ 0b0010100011,
242+ 0b0010100011,
243+ 0b0010100011,
244+ 0b0010100011,
245+ 0b0010100011,
246+ 0b0010100011,
247+ 0b0010100011,
248+ 0b0010100011,
249+ 0b0010100011
250+};
251+
252+struct dglnt_dynclk_reg;
253+struct dglnt_dynclk_mode;
254+struct dglnt_dynclk;
255+
256+struct dglnt_dynclk_reg {
257+ u32 clk0L;
258+ u32 clkFBL;
259+ u32 clkFBH_clk0H;
260+ u32 divclk;
261+ u32 lockL;
262+ u32 fltr_lockH;
263+};
264+
265+struct dglnt_dynclk_mode {
266+ u32 freq;
267+ u32 fbmult;
268+ u32 clkdiv;
269+ u32 maindiv;
270+};
271+
272+struct dglnt_dynclk {
273+ void __iomem *base;
274+ struct clk_hw clk_hw;
275+ unsigned long freq;
276+};
277+
278+u32 dglnt_dynclk_divider(u32 divide)
279+{
280+ u32 output = 0;
281+ u32 highTime = 0;
282+ u32 lowTime = 0;
283+
284+ if ((divide < 1) || (divide > 128))
285+ return ERR_CLKDIVIDER;
286+
287+ if (divide == 1)
288+ return DYNCLK_DIV_1_REGMASK;
289+
290+ highTime = divide / 2;
291+ /* if divide is odd */
292+ if (divide & 0x1) {
293+ lowTime = highTime + 1;
294+ output = 1 << CLK_BIT_WEDGE;
295+ } else {
296+ lowTime = highTime;
297+ }
298+
299+ output |= 0x03F & lowTime;
300+ output |= 0xFC0 & (highTime << 6);
301+ return output;
302+}
303+
304+u32 dglnt_dynclk_count_calc(u32 divide)
305+{
306+ u32 output = 0;
307+ u32 divCalc = 0;
308+
309+ divCalc = dglnt_dynclk_divider(divide);
310+ if (divCalc == ERR_CLKDIVIDER)
311+ output = ERR_CLKCOUNTCALC;
312+ else
313+ output = (0xFFF & divCalc) | ((divCalc << 10) & 0x00C00000);
314+ return output;
315+}
316+
317+
318+int dglnt_dynclk_find_reg(struct dglnt_dynclk_reg *regValues,
319+ struct dglnt_dynclk_mode *clkParams)
320+{
321+ if ((clkParams->fbmult < 2) || clkParams->fbmult > 64)
322+ return -EINVAL;
323+
324+ regValues->clk0L = dglnt_dynclk_count_calc(clkParams->clkdiv);
325+ if (regValues->clk0L == ERR_CLKCOUNTCALC)
326+ return -EINVAL;
327+
328+ regValues->clkFBL = dglnt_dynclk_count_calc(clkParams->fbmult);
329+ if (regValues->clkFBL == ERR_CLKCOUNTCALC)
330+ return -EINVAL;
331+
332+ regValues->clkFBH_clk0H = 0;
333+
334+ regValues->divclk = dglnt_dynclk_divider(clkParams->maindiv);
335+ if (regValues->divclk == ERR_CLKDIVIDER)
336+ return -EINVAL;
337+
338+ regValues->lockL = (u32)(lock_lookup[clkParams->fbmult - 1] &
339+ 0xFFFFFFFF);
340+
341+ regValues->fltr_lockH = (u32)((lock_lookup[clkParams->fbmult - 1] >>
342+ 32) & 0x000000FF);
343+ regValues->fltr_lockH |= ((filter_lookup_low[clkParams->fbmult - 1] <<
344+ 16) & 0x03FF0000);
345+
346+ return 0;
347+}
348+
349+void dglnt_dynclk_write_reg(struct dglnt_dynclk_reg *regValues,
350+ void __iomem *baseaddr)
351+{
352+ writel(regValues->clk0L, baseaddr + OFST_DISPLAY_CLK_L);
353+ writel(regValues->clkFBL, baseaddr + OFST_DISPLAY_FB_L);
354+ writel(regValues->clkFBH_clk0H, baseaddr + OFST_DISPLAY_FB_H_CLK_H);
355+ writel(regValues->divclk, baseaddr + OFST_DISPLAY_DIV);
356+ writel(regValues->lockL, baseaddr + OFST_DISPLAY_LOCK_L);
357+ writel(regValues->fltr_lockH, baseaddr + OFST_DISPLAY_FLTR_LOCK_H);
358+}
359+
360+u32 dglnt_dynclk_find_mode(u32 freq, u32 parentFreq,
361+ struct dglnt_dynclk_mode *bestPick)
362+{
363+ u32 bestError = MMCM_FREQ_OUTMAX;
364+ u32 curError;
365+ u32 curClkMult;
366+ u32 curFreq;
367+ u32 divVal;
368+ u32 curFb, curClkDiv;
369+ u32 minFb = 0;
370+ u32 maxFb = 0;
371+ u32 curDiv = 1;
372+ u32 maxDiv;
373+ bool freq_found = false;
374+
375+ bestPick->freq = 0;
376+ if (parentFreq == 0)
377+ return 0;
378+
379+ /* minimum frequency is actually dictated by VCOmin */
380+ if (freq < MMCM_FREQ_OUTMIN)
381+ freq = MMCM_FREQ_OUTMIN;
382+ if (freq > MMCM_FREQ_OUTMAX)
383+ freq = MMCM_FREQ_OUTMAX;
384+
385+ if (parentFreq > MMCM_FREQ_PFDMAX)
386+ curDiv = 2;
387+ maxDiv = parentFreq / MMCM_FREQ_PFDMIN;
388+ if (maxDiv > MMCM_DIV_MAX)
389+ maxDiv = MMCM_DIV_MAX;
390+
391+ while (curDiv <= maxDiv && !freq_found) {
392+ minFb = curDiv * DIV_ROUND_UP(MMCM_FREQ_VCOMIN, parentFreq);
393+ maxFb = curDiv * (MMCM_FREQ_VCOMAX / parentFreq);
394+ if (maxFb > MMCM_FB_MAX)
395+ maxFb = MMCM_FB_MAX;
396+ if (minFb < MMCM_FB_MIN)
397+ minFb = MMCM_FB_MIN;
398+
399+ divVal = curDiv * freq;
400+ /*
401+ * This multiplier is used to find the best clkDiv value for
402+ * each FB value
403+ */
404+ curClkMult = ((parentFreq * 1000) + (divVal / 2)) / divVal;
405+
406+ curFb = minFb;
407+ while (curFb <= maxFb && !freq_found) {
408+ curClkDiv = ((curClkMult * curFb) + 500) / 1000;
409+ if (curClkDiv > MMCM_CLKDIV_MAX)
410+ curClkDiv = MMCM_CLKDIV_MAX;
411+ if (curClkDiv < MMCM_CLKDIV_MIN)
412+ curClkDiv = MMCM_CLKDIV_MIN;
413+ curFreq = (((parentFreq * curFb) / curDiv) / curClkDiv);
414+ if (curFreq >= freq)
415+ curError = curFreq - freq;
416+ else
417+ curError = freq - curFreq;
418+ if (curError < bestError) {
419+ bestError = curError;
420+ bestPick->clkdiv = curClkDiv;
421+ bestPick->fbmult = curFb;
422+ bestPick->maindiv = curDiv;
423+ bestPick->freq = curFreq;
424+ }
425+ if (!curError)
426+ freq_found = true;
427+ curFb++;
428+ }
429+ curDiv++;
430+ }
431+ return bestPick->freq;
432+}
433+
434+static struct dglnt_dynclk *clk_hw_to_dglnt_dynclk(struct clk_hw *clk_hw)
435+{
436+ return container_of(clk_hw, struct dglnt_dynclk, clk_hw);
437+}
438+
439+
440+static int dglnt_dynclk_enable(struct clk_hw *clk_hw)
441+{
442+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
443+ unsigned int clock_state;
444+
445+ if (dglnt_dynclk->freq) {
446+ writel(1, dglnt_dynclk->base + OFST_DISPLAY_CTRL);
447+ do {
448+ clock_state = readl(dglnt_dynclk->base +
449+ OFST_DISPLAY_STATUS);
450+ } while (!clock_state);
451+ }
452+ return 0;
453+}
454+
455+static void dglnt_dynclk_disable(struct clk_hw *clk_hw)
456+{
457+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
458+
459+ writel(0, dglnt_dynclk->base + OFST_DISPLAY_CTRL);
460+}
461+
462+static int dglnt_dynclk_set_rate(struct clk_hw *clk_hw,
463+ unsigned long rate, unsigned long parent_rate)
464+{
465+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
466+ struct dglnt_dynclk_reg clkReg;
467+ struct dglnt_dynclk_mode clkMode;
468+
469+ if (parent_rate == 0 || rate == 0)
470+ return -EINVAL;
471+ if (rate == dglnt_dynclk->freq)
472+ return 0;
473+
474+ /*
475+ * Convert from Hz to KHz, then multiply by five to account for
476+ * BUFR division
477+ */
478+ rate = (rate + 100) / 200;
479+ /* convert from Hz to KHz */
480+ parent_rate = (parent_rate + 500) / 1000;
481+ if (!dglnt_dynclk_find_mode(rate, parent_rate, &clkMode))
482+ return -EINVAL;
483+
484+ /*
485+ * Write to the PLL dynamic configuration registers to configure it
486+ * with the calculated parameters.
487+ */
488+ dglnt_dynclk_find_reg(&clkReg, &clkMode);
489+ dglnt_dynclk_write_reg(&clkReg, dglnt_dynclk->base);
490+ dglnt_dynclk->freq = clkMode.freq * 200;
491+ dglnt_dynclk_disable(clk_hw);
492+ dglnt_dynclk_enable(clk_hw);
493+
494+ return 0;
495+}
496+
497+static long dglnt_dynclk_round_rate(struct clk_hw *hw, unsigned long rate,
498+ unsigned long *parent_rate)
499+{
500+ struct dglnt_dynclk_mode clkMode;
501+
502+ dglnt_dynclk_find_mode(((rate + 100) / 200),
503+ ((*parent_rate) + 500) / 1000, &clkMode);
504+
505+ return (clkMode.freq * 200);
506+}
507+
508+static unsigned long dglnt_dynclk_recalc_rate(struct clk_hw *clk_hw,
509+ unsigned long parent_rate)
510+{
511+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
512+
513+ return dglnt_dynclk->freq;
514+}
515+
516+
517+static const struct clk_ops dglnt_dynclk_ops = {
518+ .recalc_rate = dglnt_dynclk_recalc_rate,
519+ .round_rate = dglnt_dynclk_round_rate,
520+ .set_rate = dglnt_dynclk_set_rate,
521+ .enable = dglnt_dynclk_enable,
522+ .disable = dglnt_dynclk_disable,
523+};
524+
525+static const struct of_device_id dglnt_dynclk_ids[] = {
526+ { .compatible = "digilent,axi-dynclk", },
527+ { },
528+};
529+MODULE_DEVICE_TABLE(of, dglnt_dynclk_ids);
530+
531+static int dglnt_dynclk_probe(struct platform_device *pdev)
532+{
533+ const struct of_device_id *id;
534+ struct dglnt_dynclk *dglnt_dynclk;
535+ struct clk_init_data init;
536+ const char *parent_name;
537+ const char *clk_name;
538+ struct resource *mem;
539+ struct clk *clk;
540+
541+ if (!pdev->dev.of_node)
542+ return -ENODEV;
543+
544+ id = of_match_node(dglnt_dynclk_ids, pdev->dev.of_node);
545+ if (!id)
546+ return -ENODEV;
547+
548+ dglnt_dynclk = devm_kzalloc(&pdev->dev, sizeof(*dglnt_dynclk),
549+ GFP_KERNEL);
550+ if (!dglnt_dynclk)
551+ return -ENOMEM;
552+
553+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
554+ dglnt_dynclk->base = devm_ioremap_resource(&pdev->dev, mem);
555+ if (IS_ERR(dglnt_dynclk->base))
556+ return PTR_ERR(dglnt_dynclk->base);
557+
558+ parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
559+ if (!parent_name)
560+ return -EINVAL;
561+
562+ clk_name = pdev->dev.of_node->name;
563+ of_property_read_string(pdev->dev.of_node, "clock-output-names",
564+ &clk_name);
565+
566+ init.name = clk_name;
567+ init.ops = &dglnt_dynclk_ops;
568+ init.flags = 0;
569+ init.parent_names = &parent_name;
570+ init.num_parents = 1;
571+
572+ dglnt_dynclk->freq = 0;
573+ dglnt_dynclk_disable(&dglnt_dynclk->clk_hw);
574+
575+ dglnt_dynclk->clk_hw.init = &init;
576+ clk = devm_clk_register(&pdev->dev, &dglnt_dynclk->clk_hw);
577+ if (IS_ERR(clk))
578+ return PTR_ERR(clk);
579+
580+ return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get,
581+ clk);
582+}
583+
584+static int dglnt_dynclk_remove(struct platform_device *pdev)
585+{
586+ of_clk_del_provider(pdev->dev.of_node);
587+
588+ return 0;
589+}
590+
591+static struct platform_driver dglnt_dynclk_driver = {
592+ .driver = {
593+ .name = "dglnt-dynclk",
594+ .owner = THIS_MODULE,
595+ .of_match_table = dglnt_dynclk_ids,
596+ },
597+ .probe = dglnt_dynclk_probe,
598+ .remove = dglnt_dynclk_remove,
599+};
600+module_platform_driver(dglnt_dynclk_driver);
601+
602+MODULE_LICENSE("GPL v2");
603+MODULE_AUTHOR("Sam Bobrowicz <sbobrowicz@digilentinc.com>");
604+MODULE_DESCRIPTION("CCF Driver for Digilent axi_dynclk IP Core");
605--
6062.14.2
607
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2017.3/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2017.3/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
deleted file mode 100644
index a98d84c5..00000000
--- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2017.3/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
+++ /dev/null
@@ -1,54 +0,0 @@
1From 1a18e2b514ae9e75145597ac509a87f656c976ba Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Mon, 2 May 2016 23:46:42 +1000
4Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on
5
6Fix the issues where the VTC is reset (losing its timing config).
7
8Also fix the issue where the plane destroys its DMA descriptors and
9marks the DMA channels as inactive but never recreates the descriptors
10and never updates the active state when turning DPMS back on.
11
12Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
13Upstream-Status: Pending [This is a workaround]
14---
15 drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | 1 -
16 drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 3 ++-
17 2 files changed, 2 insertions(+), 2 deletions(-)
18
19diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
20index 631d35b921..93dbd4b58a 100644
21--- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
22+++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
23@@ -88,7 +88,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms)
24 default:
25 if (crtc->vtc) {
26 xilinx_vtc_disable(crtc->vtc);
27- xilinx_vtc_reset(crtc->vtc);
28 }
29 if (crtc->cresample) {
30 xilinx_cresample_disable(crtc->cresample);
31diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
32index 6a248b72d4..d2518a4bdf 100644
33--- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
34+++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
35@@ -140,7 +140,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
36 for (i = 0; i < MAX_NUM_SUB_PLANES; i++) {
37 struct xilinx_drm_plane_dma *dma = &plane->dma[i];
38
39- if (dma->chan && dma->is_active) {
40+ if (dma->chan) {
41 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
42 desc = dmaengine_prep_interleaved_dma(dma->chan,
43 &dma->xt,
44@@ -153,6 +153,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
45 dmaengine_submit(desc);
46
47 dma_async_issue_pending(dma->chan);
48+ dma->is_active = true;
49 }
50 }
51 }
52--
532.14.2
54
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2017.3.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2017.3.bbappend
deleted file mode 100644
index 83b08f1b..00000000
--- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2017.3.bbappend
+++ /dev/null
@@ -1,8 +0,0 @@
1FILESEXTRAPATHS_prepend := "${THISDIR}/linux-xlnx:"
2
3SRC_URI_append_zybo-linux-bd-zynq7 = " \
4 file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \
5 file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \
6 file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \
7 "
8
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-04-22 05:03:40 +0000