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authorNathan Rossi <nathan@nathanrossi.com>2016-03-30 23:28:02 +1000
committerNathan Rossi <nathan@nathanrossi.com>2016-03-31 18:34:56 +1000
commit54b35fdfa0dd9b45c9b7fdaada6e9aafc278cb7a (patch)
treea2d63d905eaee278dc3c359b61402047b244e48a
parentff86e231ca1fa4f4dc0e8806b38965afb6a34faa (diff)
downloadmeta-xilinx-54b35fdfa0dd9b45c9b7fdaada6e9aafc278cb7a.tar.gz
u-boot-xlnx: Update to pre-release xilinx-v2016.1
Update the recipe to the current master of u-boot-xlnx vendor tree, in preparation for the xilinx-v2016.1 release. Update the KC705 configuration patch and remove upstreamed patches for MicroBlaze. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Diffstat
-rw-r--r--recipes-bsp/u-boot/u-boot-xlnx/0001-microblaze-Fix-style-issues-in-header-files.patch236
-rw-r--r--recipes-bsp/u-boot/u-boot-xlnx/0002-microblaze-Fix-C99-gnu99-compatiblity-for-inline-fun.patch239
-rw-r--r--recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-trd-Convert-microblaze-generic-to-k.patch707
-rw-r--r--recipes-bsp/u-boot/u-boot-xlnx_2016.01.bb (renamed from recipes-bsp/u-boot/u-boot-xlnx_2015.07.bb)13
4 files changed, 579 insertions, 616 deletions
diff --git a/recipes-bsp/u-boot/u-boot-xlnx/0001-microblaze-Fix-style-issues-in-header-files.patch b/recipes-bsp/u-boot/u-boot-xlnx/0001-microblaze-Fix-style-issues-in-header-files.patch
deleted file mode 100644
index f81aee4c..00000000
--- a/recipes-bsp/u-boot/u-boot-xlnx/0001-microblaze-Fix-style-issues-in-header-files.patch
+++ /dev/null
@@ -1,236 +0,0 @@
1From 4a4d9396b889686914101607417bc094e43060e4 Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Fri, 6 Nov 2015 19:25:05 +1000
4Subject: [PATCH 1/2] microblaze: Fix style issues in header files
5
6Fix various style issues in MicroBlaze header files. Specifically fixing
7style voilations including '__inline__', 'foo * bar' and 'void foo ('.
8
9Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
10Cc: Michal Simek <monstr@monstr.eu>
11Cc: Tom Rini <trini@konsulko.com>
12Signed-off-by: Michal Simek <michal.simek@xilinx.com>
13Upstream-Status: Backport
14---
15 arch/microblaze/include/asm/bitops.h | 66 ++++++++++++++++++------------------
16 arch/microblaze/include/asm/system.h | 2 +-
17 2 files changed, 34 insertions(+), 34 deletions(-)
18
19diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h
20index d24f2cf..178c94f 100644
21--- a/arch/microblaze/include/asm/bitops.h
22+++ b/arch/microblaze/include/asm/bitops.h
23@@ -21,31 +21,31 @@
24 * The __ functions are not atomic
25 */
26
27-extern void set_bit(int nr, volatile void * addr);
28-extern void __set_bit(int nr, volatile void * addr);
29+extern void set_bit(int nr, volatile void *addr);
30+extern void __set_bit(int nr, volatile void *addr);
31
32-extern void clear_bit(int nr, volatile void * addr);
33+extern void clear_bit(int nr, volatile void *addr);
34 #define __clear_bit(nr, addr) clear_bit(nr, addr)
35 #define PLATFORM__CLEAR_BIT
36
37-extern void change_bit(int nr, volatile void * addr);
38-extern void __change_bit(int nr, volatile void * addr);
39-extern int test_and_set_bit(int nr, volatile void * addr);
40-extern int __test_and_set_bit(int nr, volatile void * addr);
41-extern int test_and_clear_bit(int nr, volatile void * addr);
42-extern int __test_and_clear_bit(int nr, volatile void * addr);
43-extern int test_and_change_bit(int nr, volatile void * addr);
44-extern int __test_and_change_bit(int nr, volatile void * addr);
45-extern int __constant_test_bit(int nr, const volatile void * addr);
46-extern int __test_bit(int nr, volatile void * addr);
47-extern int find_first_zero_bit(void * addr, unsigned size);
48-extern int find_next_zero_bit (void * addr, int size, int offset);
49+extern void change_bit(int nr, volatile void *addr);
50+extern void __change_bit(int nr, volatile void *addr);
51+extern int test_and_set_bit(int nr, volatile void *addr);
52+extern int __test_and_set_bit(int nr, volatile void *addr);
53+extern int test_and_clear_bit(int nr, volatile void *addr);
54+extern int __test_and_clear_bit(int nr, volatile void *addr);
55+extern int test_and_change_bit(int nr, volatile void *addr);
56+extern int __test_and_change_bit(int nr, volatile void *addr);
57+extern int __constant_test_bit(int nr, const volatile void *addr);
58+extern int __test_bit(int nr, volatile void *addr);
59+extern int find_first_zero_bit(void *addr, unsigned size);
60+extern int find_next_zero_bit(void *addr, int size, int offset);
61
62 /*
63 * ffz = Find First Zero in word. Undefined if no zero exists,
64 * so code should check against ~0UL first..
65 */
66-extern __inline__ unsigned long ffz(unsigned long word)
67+extern inline unsigned long ffz(unsigned long word)
68 {
69 unsigned long result = 0;
70
71@@ -57,7 +57,7 @@ extern __inline__ unsigned long ffz(unsigned long word)
72 }
73
74
75-extern __inline__ void set_bit(int nr, volatile void * addr)
76+extern inline void set_bit(int nr, volatile void *addr)
77 {
78 int * a = (int *) addr;
79 int mask;
80@@ -70,7 +70,7 @@ extern __inline__ void set_bit(int nr, volatile void * addr)
81 restore_flags(flags);
82 }
83
84-extern __inline__ void __set_bit(int nr, volatile void * addr)
85+extern inline void __set_bit(int nr, volatile void *addr)
86 {
87 int * a = (int *) addr;
88 int mask;
89@@ -87,7 +87,7 @@ extern __inline__ void __set_bit(int nr, volatile void * addr)
90 #define smp_mb__before_clear_bit() barrier()
91 #define smp_mb__after_clear_bit() barrier()
92
93-extern __inline__ void clear_bit(int nr, volatile void * addr)
94+extern inline void clear_bit(int nr, volatile void *addr)
95 {
96 int * a = (int *) addr;
97 int mask;
98@@ -100,7 +100,7 @@ extern __inline__ void clear_bit(int nr, volatile void * addr)
99 restore_flags(flags);
100 }
101
102-extern __inline__ void change_bit(int nr, volatile void * addr)
103+extern inline void change_bit(int nr, volatile void *addr)
104 {
105 int mask;
106 unsigned long flags;
107@@ -113,7 +113,7 @@ extern __inline__ void change_bit(int nr, volatile void * addr)
108 restore_flags(flags);
109 }
110
111-extern __inline__ void __change_bit(int nr, volatile void * addr)
112+extern inline void __change_bit(int nr, volatile void *addr)
113 {
114 int mask;
115 unsigned long *ADDR = (unsigned long *) addr;
116@@ -123,7 +123,7 @@ extern __inline__ void __change_bit(int nr, volatile void * addr)
117 *ADDR ^= mask;
118 }
119
120-extern __inline__ int test_and_set_bit(int nr, volatile void * addr)
121+extern inline int test_and_set_bit(int nr, volatile void *addr)
122 {
123 int mask, retval;
124 volatile unsigned int *a = (volatile unsigned int *) addr;
125@@ -139,7 +139,7 @@ extern __inline__ int test_and_set_bit(int nr, volatile void * addr)
126 return retval;
127 }
128
129-extern __inline__ int __test_and_set_bit(int nr, volatile void * addr)
130+extern inline int __test_and_set_bit(int nr, volatile void *addr)
131 {
132 int mask, retval;
133 volatile unsigned int *a = (volatile unsigned int *) addr;
134@@ -151,7 +151,7 @@ extern __inline__ int __test_and_set_bit(int nr, volatile void * addr)
135 return retval;
136 }
137
138-extern __inline__ int test_and_clear_bit(int nr, volatile void * addr)
139+extern inline int test_and_clear_bit(int nr, volatile void *addr)
140 {
141 int mask, retval;
142 volatile unsigned int *a = (volatile unsigned int *) addr;
143@@ -167,7 +167,7 @@ extern __inline__ int test_and_clear_bit(int nr, volatile void * addr)
144 return retval;
145 }
146
147-extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
148+extern inline int __test_and_clear_bit(int nr, volatile void *addr)
149 {
150 int mask, retval;
151 volatile unsigned int *a = (volatile unsigned int *) addr;
152@@ -179,7 +179,7 @@ extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
153 return retval;
154 }
155
156-extern __inline__ int test_and_change_bit(int nr, volatile void * addr)
157+extern inline int test_and_change_bit(int nr, volatile void *addr)
158 {
159 int mask, retval;
160 volatile unsigned int *a = (volatile unsigned int *) addr;
161@@ -195,7 +195,7 @@ extern __inline__ int test_and_change_bit(int nr, volatile void * addr)
162 return retval;
163 }
164
165-extern __inline__ int __test_and_change_bit(int nr, volatile void * addr)
166+extern inline int __test_and_change_bit(int nr, volatile void *addr)
167 {
168 int mask, retval;
169 volatile unsigned int *a = (volatile unsigned int *) addr;
170@@ -210,12 +210,12 @@ extern __inline__ int __test_and_change_bit(int nr, volatile void * addr)
171 /*
172 * This routine doesn't need to be atomic.
173 */
174-extern __inline__ int __constant_test_bit(int nr, const volatile void * addr)
175+extern inline int __constant_test_bit(int nr, const volatile void *addr)
176 {
177 return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
178 }
179
180-extern __inline__ int __test_bit(int nr, volatile void * addr)
181+extern inline int __test_bit(int nr, volatile void *addr)
182 {
183 int * a = (int *) addr;
184 int mask;
185@@ -233,7 +233,7 @@ extern __inline__ int __test_bit(int nr, volatile void * addr)
186 #define find_first_zero_bit(addr, size) \
187 find_next_zero_bit((addr), (size), 0)
188
189-extern __inline__ int find_next_zero_bit (void * addr, int size, int offset)
190+extern inline int find_next_zero_bit(void *addr, int size, int offset)
191 {
192 unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
193 unsigned long result = offset & ~31UL;
194@@ -279,7 +279,7 @@ found_middle:
195 #define hweight8(x) generic_hweight8(x)
196
197
198-extern __inline__ int ext2_set_bit(int nr, volatile void * addr)
199+extern inline int ext2_set_bit(int nr, volatile void *addr)
200 {
201 int mask, retval;
202 unsigned long flags;
203@@ -294,7 +294,7 @@ extern __inline__ int ext2_set_bit(int nr, volatile void * addr)
204 return retval;
205 }
206
207-extern __inline__ int ext2_clear_bit(int nr, volatile void * addr)
208+extern inline int ext2_clear_bit(int nr, volatile void *addr)
209 {
210 int mask, retval;
211 unsigned long flags;
212@@ -309,7 +309,7 @@ extern __inline__ int ext2_clear_bit(int nr, volatile void * addr)
213 return retval;
214 }
215
216-extern __inline__ int ext2_test_bit(int nr, const volatile void * addr)
217+extern inline int ext2_test_bit(int nr, const volatile void *addr)
218 {
219 int mask;
220 const volatile unsigned char *ADDR = (const unsigned char *) addr;
221diff --git a/arch/microblaze/include/asm/system.h b/arch/microblaze/include/asm/system.h
222index 0297a11..3090835 100644
223--- a/arch/microblaze/include/asm/system.h
224+++ b/arch/microblaze/include/asm/system.h
225@@ -131,7 +131,7 @@ extern void *switch_thread (struct thread_struct *last,
226 ((__typeof__ (*(ptr)))__xchg ((unsigned long)(with), (ptr), sizeof (*(ptr))))
227 #define tas(ptr) (xchg ((ptr), 1))
228
229-extern inline unsigned long __xchg (unsigned long with,
230+extern inline unsigned long __xchg(unsigned long with,
231 __volatile__ void *ptr, int size)
232 {
233 unsigned long tmp, flags;
234--
2352.6.2
236
diff --git a/recipes-bsp/u-boot/u-boot-xlnx/0002-microblaze-Fix-C99-gnu99-compatiblity-for-inline-fun.patch b/recipes-bsp/u-boot/u-boot-xlnx/0002-microblaze-Fix-C99-gnu99-compatiblity-for-inline-fun.patch
deleted file mode 100644
index d334867b..00000000
--- a/recipes-bsp/u-boot/u-boot-xlnx/0002-microblaze-Fix-C99-gnu99-compatiblity-for-inline-fun.patch
+++ /dev/null
@@ -1,239 +0,0 @@
1From ccd0c906131053b11790a6be076e2cf4f71fed10 Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Fri, 6 Nov 2015 19:25:06 +1000
4Subject: [PATCH 2/2] microblaze: Fix C99/gnu99 compatiblity for inline
5 functions
6
7'extern inline' is not portable across various C standards. To ensure
8compatiblity with various standards/compilers change the functions to
9static inline. This is a portable construct and serves as a comparable
10definition to 'extern inline' from the gnu90 standard.
11
12Additionally remove the function prototypes as they are not required due
13to the functions being declared static and functions are correctly
14ordered based on dependence.
15
16Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
17Cc: Michal Simek <monstr@monstr.eu>
18Cc: Tom Rini <trini@konsulko.com>
19Acked-by: Mans Rullgard <mans@mansr.com>
20Signed-off-by: Michal Simek <michal.simek@xilinx.com>
21Upstream-Status: Backport
22---
23 arch/microblaze/include/asm/bitops.h | 63 ++++++++++++------------------------
24 arch/microblaze/include/asm/system.h | 2 +-
25 2 files changed, 22 insertions(+), 43 deletions(-)
26
27diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h
28index 178c94f..2cab2ac 100644
29--- a/arch/microblaze/include/asm/bitops.h
30+++ b/arch/microblaze/include/asm/bitops.h
31@@ -14,38 +14,14 @@
32
33 #ifdef __KERNEL__
34 /*
35- * Function prototypes to keep gcc -Wall happy
36- */
37-
38-/*
39 * The __ functions are not atomic
40 */
41
42-extern void set_bit(int nr, volatile void *addr);
43-extern void __set_bit(int nr, volatile void *addr);
44-
45-extern void clear_bit(int nr, volatile void *addr);
46-#define __clear_bit(nr, addr) clear_bit(nr, addr)
47-#define PLATFORM__CLEAR_BIT
48-
49-extern void change_bit(int nr, volatile void *addr);
50-extern void __change_bit(int nr, volatile void *addr);
51-extern int test_and_set_bit(int nr, volatile void *addr);
52-extern int __test_and_set_bit(int nr, volatile void *addr);
53-extern int test_and_clear_bit(int nr, volatile void *addr);
54-extern int __test_and_clear_bit(int nr, volatile void *addr);
55-extern int test_and_change_bit(int nr, volatile void *addr);
56-extern int __test_and_change_bit(int nr, volatile void *addr);
57-extern int __constant_test_bit(int nr, const volatile void *addr);
58-extern int __test_bit(int nr, volatile void *addr);
59-extern int find_first_zero_bit(void *addr, unsigned size);
60-extern int find_next_zero_bit(void *addr, int size, int offset);
61-
62 /*
63 * ffz = Find First Zero in word. Undefined if no zero exists,
64 * so code should check against ~0UL first..
65 */
66-extern inline unsigned long ffz(unsigned long word)
67+static inline unsigned long ffz(unsigned long word)
68 {
69 unsigned long result = 0;
70
71@@ -57,7 +33,7 @@ extern inline unsigned long ffz(unsigned long word)
72 }
73
74
75-extern inline void set_bit(int nr, volatile void *addr)
76+static inline void set_bit(int nr, volatile void *addr)
77 {
78 int * a = (int *) addr;
79 int mask;
80@@ -70,7 +46,7 @@ extern inline void set_bit(int nr, volatile void *addr)
81 restore_flags(flags);
82 }
83
84-extern inline void __set_bit(int nr, volatile void *addr)
85+static inline void __set_bit(int nr, volatile void *addr)
86 {
87 int * a = (int *) addr;
88 int mask;
89@@ -87,7 +63,7 @@ extern inline void __set_bit(int nr, volatile void *addr)
90 #define smp_mb__before_clear_bit() barrier()
91 #define smp_mb__after_clear_bit() barrier()
92
93-extern inline void clear_bit(int nr, volatile void *addr)
94+static inline void clear_bit(int nr, volatile void *addr)
95 {
96 int * a = (int *) addr;
97 int mask;
98@@ -100,7 +76,10 @@ extern inline void clear_bit(int nr, volatile void *addr)
99 restore_flags(flags);
100 }
101
102-extern inline void change_bit(int nr, volatile void *addr)
103+#define __clear_bit(nr, addr) clear_bit(nr, addr)
104+#define PLATFORM__CLEAR_BIT
105+
106+static inline void change_bit(int nr, volatile void *addr)
107 {
108 int mask;
109 unsigned long flags;
110@@ -113,7 +92,7 @@ extern inline void change_bit(int nr, volatile void *addr)
111 restore_flags(flags);
112 }
113
114-extern inline void __change_bit(int nr, volatile void *addr)
115+static inline void __change_bit(int nr, volatile void *addr)
116 {
117 int mask;
118 unsigned long *ADDR = (unsigned long *) addr;
119@@ -123,7 +102,7 @@ extern inline void __change_bit(int nr, volatile void *addr)
120 *ADDR ^= mask;
121 }
122
123-extern inline int test_and_set_bit(int nr, volatile void *addr)
124+static inline int test_and_set_bit(int nr, volatile void *addr)
125 {
126 int mask, retval;
127 volatile unsigned int *a = (volatile unsigned int *) addr;
128@@ -139,7 +118,7 @@ extern inline int test_and_set_bit(int nr, volatile void *addr)
129 return retval;
130 }
131
132-extern inline int __test_and_set_bit(int nr, volatile void *addr)
133+static inline int __test_and_set_bit(int nr, volatile void *addr)
134 {
135 int mask, retval;
136 volatile unsigned int *a = (volatile unsigned int *) addr;
137@@ -151,7 +130,7 @@ extern inline int __test_and_set_bit(int nr, volatile void *addr)
138 return retval;
139 }
140
141-extern inline int test_and_clear_bit(int nr, volatile void *addr)
142+static inline int test_and_clear_bit(int nr, volatile void *addr)
143 {
144 int mask, retval;
145 volatile unsigned int *a = (volatile unsigned int *) addr;
146@@ -167,7 +146,7 @@ extern inline int test_and_clear_bit(int nr, volatile void *addr)
147 return retval;
148 }
149
150-extern inline int __test_and_clear_bit(int nr, volatile void *addr)
151+static inline int __test_and_clear_bit(int nr, volatile void *addr)
152 {
153 int mask, retval;
154 volatile unsigned int *a = (volatile unsigned int *) addr;
155@@ -179,7 +158,7 @@ extern inline int __test_and_clear_bit(int nr, volatile void *addr)
156 return retval;
157 }
158
159-extern inline int test_and_change_bit(int nr, volatile void *addr)
160+static inline int test_and_change_bit(int nr, volatile void *addr)
161 {
162 int mask, retval;
163 volatile unsigned int *a = (volatile unsigned int *) addr;
164@@ -195,7 +174,7 @@ extern inline int test_and_change_bit(int nr, volatile void *addr)
165 return retval;
166 }
167
168-extern inline int __test_and_change_bit(int nr, volatile void *addr)
169+static inline int __test_and_change_bit(int nr, volatile void *addr)
170 {
171 int mask, retval;
172 volatile unsigned int *a = (volatile unsigned int *) addr;
173@@ -210,12 +189,12 @@ extern inline int __test_and_change_bit(int nr, volatile void *addr)
174 /*
175 * This routine doesn't need to be atomic.
176 */
177-extern inline int __constant_test_bit(int nr, const volatile void *addr)
178+static inline int __constant_test_bit(int nr, const volatile void *addr)
179 {
180 return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
181 }
182
183-extern inline int __test_bit(int nr, volatile void *addr)
184+static inline int __test_bit(int nr, volatile void *addr)
185 {
186 int * a = (int *) addr;
187 int mask;
188@@ -233,7 +212,7 @@ extern inline int __test_bit(int nr, volatile void *addr)
189 #define find_first_zero_bit(addr, size) \
190 find_next_zero_bit((addr), (size), 0)
191
192-extern inline int find_next_zero_bit(void *addr, int size, int offset)
193+static inline int find_next_zero_bit(void *addr, int size, int offset)
194 {
195 unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
196 unsigned long result = offset & ~31UL;
197@@ -279,7 +258,7 @@ found_middle:
198 #define hweight8(x) generic_hweight8(x)
199
200
201-extern inline int ext2_set_bit(int nr, volatile void *addr)
202+static inline int ext2_set_bit(int nr, volatile void *addr)
203 {
204 int mask, retval;
205 unsigned long flags;
206@@ -294,7 +273,7 @@ extern inline int ext2_set_bit(int nr, volatile void *addr)
207 return retval;
208 }
209
210-extern inline int ext2_clear_bit(int nr, volatile void *addr)
211+static inline int ext2_clear_bit(int nr, volatile void *addr)
212 {
213 int mask, retval;
214 unsigned long flags;
215@@ -309,7 +288,7 @@ extern inline int ext2_clear_bit(int nr, volatile void *addr)
216 return retval;
217 }
218
219-extern inline int ext2_test_bit(int nr, const volatile void *addr)
220+static inline int ext2_test_bit(int nr, const volatile void *addr)
221 {
222 int mask;
223 const volatile unsigned char *ADDR = (const unsigned char *) addr;
224diff --git a/arch/microblaze/include/asm/system.h b/arch/microblaze/include/asm/system.h
225index 3090835..3107748 100644
226--- a/arch/microblaze/include/asm/system.h
227+++ b/arch/microblaze/include/asm/system.h
228@@ -131,7 +131,7 @@ extern void *switch_thread (struct thread_struct *last,
229 ((__typeof__ (*(ptr)))__xchg ((unsigned long)(with), (ptr), sizeof (*(ptr))))
230 #define tas(ptr) (xchg ((ptr), 1))
231
232-extern inline unsigned long __xchg(unsigned long with,
233+static inline unsigned long __xchg(unsigned long with,
234 __volatile__ void *ptr, int size)
235 {
236 unsigned long tmp, flags;
237--
2382.6.2
239
diff --git a/recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-trd-Convert-microblaze-generic-to-k.patch b/recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-trd-Convert-microblaze-generic-to-k.patch
index e9974f4f..47601e7d 100644
--- a/recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-trd-Convert-microblaze-generic-to-k.patch
+++ b/recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-trd-Convert-microblaze-generic-to-k.patch
@@ -1,6 +1,6 @@
1From 0a6818050dcc711f36bd96decc7a2abba5871928 Mon Sep 17 00:00:00 2001 1From 36651e266a840e0767e8f1b6d0ff4944f96cbdcf Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com> 2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Wed, 6 Jan 2016 15:40:17 +1000 3Date: Thu, 31 Mar 2016 18:15:02 +1000
4Subject: [PATCH] microblaze: kc705-trd: Convert microblaze-generic to 4Subject: [PATCH] microblaze: kc705-trd: Convert microblaze-generic to
5 kc705-trd 5 kc705-trd
6 6
@@ -12,24 +12,543 @@ microblaze boards.
12Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> 12Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
13Upstream-Status: Not-Upstreamable [meta-xilinx/kc705 specific] 13Upstream-Status: Not-Upstreamable [meta-xilinx/kc705 specific]
14--- 14---
15 arch/microblaze/dts/microblaze-generic.dts | 4 ++ 15 arch/microblaze/dts/microblaze-generic.dts | 520 ++++++++++++++++++++++++++
16 board/xilinx/microblaze-generic/config.mk | 23 +++---- 16 board/xilinx/microblaze-generic/config.mk | 23 +-
17 board/xilinx/microblaze-generic/xparameters.h | 86 ++++++++++----------------- 17 board/xilinx/microblaze-generic/xparameters.h | 16 +-
18 include/configs/microblaze-generic.h | 11 ++-- 18 configs/microblaze-generic_defconfig | 5 +-
19 4 files changed, 52 insertions(+), 72 deletions(-) 19 include/configs/microblaze-generic.h | 4 +-
20 5 files changed, 540 insertions(+), 28 deletions(-)
20 21
21diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts 22diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts
22index 2033309..8c21cd3 100644 23index 2033309..7faf61d 100644
23--- a/arch/microblaze/dts/microblaze-generic.dts 24--- a/arch/microblaze/dts/microblaze-generic.dts
24+++ b/arch/microblaze/dts/microblaze-generic.dts 25+++ b/arch/microblaze/dts/microblaze-generic.dts
25@@ -4,4 +4,8 @@ 26@@ -2,6 +2,526 @@
27 / {
28 #address-cells = <1>;
26 #size-cells = <1>; 29 #size-cells = <1>;
27 aliases { 30+ compatible = "xlnx,microblaze";
28 } ; 31+ model = "Xilinx-KC705-TRD";
29+ memory: memory@80000000 { 32+ ddr3_sdram: memory@80000000 {
30+ device_type = "memory"; 33+ device_type = "memory";
31+ reg = <0x80000000 0x40000000>; 34+ reg = < 0x80000000 0x40000000 >;
35+ } ;
36 aliases {
37+ ethernet0 = &soft_ethernet_mac;
38+ serial0 = &rs232_uart_1;
39+ } ;
40+ chosen {
41+ bootargs = "";
42+ stdout-path = "serial0:115200";
32+ } ; 43+ } ;
44+ cpus {
45+ #address-cells = <1>;
46+ #cpus = <0x1>;
47+ #size-cells = <0>;
48+ microblaze_0: cpu@0 {
49+ bus-handle = <&axi_mm_mb>, <&axi4_0>, <&axi4lite_0>;
50+ clock-frequency = <150000000>;
51+ clocks = <&clk_cpu>;
52+ compatible = "xlnx,microblaze-8.50.a";
53+ d-cache-baseaddr = <0x80000000>;
54+ d-cache-highaddr = <0xffffffff>;
55+ d-cache-line-size = <0x20>;
56+ d-cache-size = <0x2000>;
57+ device_type = "cpu";
58+ i-cache-baseaddr = <0x80000000>;
59+ i-cache-highaddr = <0xffffffff>;
60+ i-cache-line-size = <0x20>;
61+ i-cache-size = <0x2000>;
62+ model = "microblaze,8.50.a";
63+ reg = <0>;
64+ timebase-frequency = <150000000>;
65+ xlnx,addr-tag-bits = <0x12>;
66+ xlnx,allow-dcache-wr = <0x1>;
67+ xlnx,allow-icache-wr = <0x1>;
68+ xlnx,area-optimized = <0x0>;
69+ xlnx,avoid-primitives = <0x0>;
70+ xlnx,base-vectors = <0x0>;
71+ xlnx,branch-target-cache-size = <0x0>;
72+ xlnx,cache-byte-size = <0x2000>;
73+ xlnx,d-axi = <0x1>;
74+ xlnx,d-lmb = <0x1>;
75+ xlnx,d-plb = <0x0>;
76+ xlnx,data-size = <0x20>;
77+ xlnx,dcache-addr-tag = <0x12>;
78+ xlnx,dcache-always-used = <0x1>;
79+ xlnx,dcache-byte-size = <0x2000>;
80+ xlnx,dcache-data-width = <0x0>;
81+ xlnx,dcache-force-tag-lutram = <0x1>;
82+ xlnx,dcache-interface = <0x0>;
83+ xlnx,dcache-line-len = <0x8>;
84+ xlnx,dcache-use-fsl = <0x0>;
85+ xlnx,dcache-use-writeback = <0x0>;
86+ xlnx,dcache-victims = <0x0>;
87+ xlnx,debug-enabled = <0x1>;
88+ xlnx,div-zero-exception = <0x0>;
89+ xlnx,dynamic-bus-sizing = <0x1>;
90+ xlnx,ecc-use-ce-exception = <0x0>;
91+ xlnx,edge-is-positive = <0x1>;
92+ xlnx,endianness = <0x1>;
93+ xlnx,family = "kintex7";
94+ xlnx,fault-tolerant = <0x0>;
95+ xlnx,fpu-exception = <0x0>;
96+ xlnx,freq = <0x8f0d180>;
97+ xlnx,fsl-data-size = <0x20>;
98+ xlnx,fsl-exception = <0x0>;
99+ xlnx,fsl-links = <0x0>;
100+ xlnx,i-axi = <0x0>;
101+ xlnx,i-lmb = <0x1>;
102+ xlnx,i-plb = <0x0>;
103+ xlnx,icache-always-used = <0x1>;
104+ xlnx,icache-data-width = <0x0>;
105+ xlnx,icache-force-tag-lutram = <0x1>;
106+ xlnx,icache-interface = <0x0>;
107+ xlnx,icache-line-len = <0x8>;
108+ xlnx,icache-streams = <0x0>;
109+ xlnx,icache-use-fsl = <0x0>;
110+ xlnx,icache-victims = <0x0>;
111+ xlnx,ill-opcode-exception = <0x1>;
112+ xlnx,instance = "microblaze_0";
113+ xlnx,interconnect = <0x2>;
114+ xlnx,interrupt-is-edge = <0x0>;
115+ xlnx,lockstep-slave = <0x0>;
116+ xlnx,mmu-dtlb-size = <0x2>;
117+ xlnx,mmu-itlb-size = <0x2>;
118+ xlnx,mmu-privileged-instr = <0x0>;
119+ xlnx,mmu-tlb-access = <0x3>;
120+ xlnx,mmu-zones = <0x2>;
121+ xlnx,number-of-pc-brk = <0x1>;
122+ xlnx,number-of-rd-addr-brk = <0x0>;
123+ xlnx,number-of-wr-addr-brk = <0x0>;
124+ xlnx,opcode-0x0-illegal = <0x1>;
125+ xlnx,optimization = <0x0>;
126+ xlnx,pc-width = <0x20>;
127+ xlnx,pvr = <0x2>;
128+ xlnx,pvr-user1 = <0x0>;
129+ xlnx,pvr-user2 = <0x0>;
130+ xlnx,reset-msr = <0x0>;
131+ xlnx,sco = <0x0>;
132+ xlnx,stream-interconnect = <0x0>;
133+ xlnx,unaligned-exceptions = <0x1>;
134+ xlnx,use-barrel = <0x1>;
135+ xlnx,use-branch-target-cache = <0x0>;
136+ xlnx,use-dcache = <0x1>;
137+ xlnx,use-div = <0x0>;
138+ xlnx,use-ext-brk = <0x1>;
139+ xlnx,use-ext-nm-brk = <0x1>;
140+ xlnx,use-extended-fsl-instr = <0x0>;
141+ xlnx,use-fpu = <0x0>;
142+ xlnx,use-hw-mul = <0x1>;
143+ xlnx,use-icache = <0x1>;
144+ xlnx,use-interrupt = <0x1>;
145+ xlnx,use-mmu = <0x3>;
146+ xlnx,use-msr-instr = <0x1>;
147+ xlnx,use-pcmp-instr = <0x1>;
148+ xlnx,use-reorder-instr = <0x1>;
149+ xlnx,use-stack-protection = <0x0>;
150+ } ;
151+ } ;
152+ clocks {
153+ #address-cells = <1>;
154+ #size-cells = <0>;
155+ clk_bus: bus {
156+ #clock-cells = <0>;
157+ clock-frequency = <100000000>;
158+ clock-output-names = "bus";
159+ compatible = "fixed-clock";
160+ reg = <1>;
161+ } ;
162+ clk_cpu: cpu {
163+ #clock-cells = <0>;
164+ clock-frequency = <150000000>;
165+ clock-output-names = "cpu";
166+ compatible = "fixed-clock";
167+ reg = <0>;
168+ } ;
169+ } ;
170+ axi4lite_0: axi@2 {
171+ #address-cells = <1>;
172+ #size-cells = <1>;
173+ compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
174+ ranges ;
175+ axi_dma_ethernet: axi-dma@50000000 {
176+ axistream-connected = <&soft_ethernet_mac>;
177+ axistream-control-connected = <&soft_ethernet_mac>;
178+ compatible = "xlnx,axi-dma-6.03.a", "xlnx,axi-dma-1.00.a";
179+ interrupt-parent = <&interrupt_cntlr>;
180+ interrupts = < 0 2 1 2 >;
181+ reg = < 0x50000000 0x10000 >;
182+ xlnx,dlytmr-resolution = <0x4e2>;
183+ xlnx,enable-multi-channel = <0x0>;
184+ xlnx,family = "kintex7";
185+ xlnx,generic = <0x0>;
186+ xlnx,include-mm2s = <0x1>;
187+ xlnx,include-mm2s-dre = <0x1>;
188+ xlnx,include-mm2s-sf = <0x1>;
189+ xlnx,include-s2mm = <0x1>;
190+ xlnx,include-s2mm-dre = <0x1>;
191+ xlnx,include-s2mm-sf = <0x1>;
192+ xlnx,include-sg = <0x1>;
193+ xlnx,instance = "AXI_DMA_Ethernet";
194+ xlnx,mm2s-burst-size = <0x10>;
195+ xlnx,num-mm2s-channels = <0x1>;
196+ xlnx,num-s2mm-channels = <0x1>;
197+ xlnx,prmry-is-aclk-async = <0x1>;
198+ xlnx,s2mm-burst-size = <0x10>;
199+ xlnx,sg-include-desc-queue = <0x1>;
200+ xlnx,sg-include-stscntrl-strm = <0x1>;
201+ xlnx,sg-length-width = <0x10>;
202+ xlnx,sg-use-stsapp-length = <0x1>;
203+ } ;
204+ axi_xadc_0: axi-xadc@40d00000 {
205+ clocks = <&clk_bus>;
206+ compatible = "xlnx,axi-xadc-1.00.a";
207+ interrupt-parent = <&interrupt_cntlr>;
208+ interrupts = < 7 2 >;
209+ reg = < 0x40d00000 0x10000 >;
210+ xlnx,family = "kintex7";
211+ xlnx,has-temp-bus = <0x1>;
212+ xlnx,include-intr = <0x1>;
213+ xlnx,instance = "axi_xadc_0";
214+ xlnx,sim-monitor-file = "Sysmon_Design.txt";
215+ } ;
216+ debug_module: serial@40200000 {
217+ compatible = "xlnx,mdm-2.10.a", "xlnx,xps-uartlite-1.00.a";
218+ reg = < 0x40200000 0x10000 >;
219+ xlnx,family = "kintex7";
220+ xlnx,interconnect = <0x2>;
221+ xlnx,jtag-chain = <0x2>;
222+ xlnx,mb-dbg-ports = <0x1>;
223+ xlnx,use-bscan = <0x0>;
224+ xlnx,use-uart = <0x1>;
225+ } ;
226+ dip_switches_4bits: gpio@40700000 {
227+ #gpio-cells = <2>;
228+ compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
229+ gpio-controller ;
230+ reg = < 0x40700000 0x10000 >;
231+ xlnx,all-inputs = <0x1>;
232+ xlnx,all-inputs-2 = <0x0>;
233+ xlnx,dout-default = <0x0>;
234+ xlnx,dout-default-2 = <0x0>;
235+ xlnx,family = "kintex7";
236+ xlnx,gpio-width = <0x4>;
237+ xlnx,gpio2-width = <0x20>;
238+ xlnx,instance = "DIP_Switches_4Bits";
239+ xlnx,interrupt-present = <0x1>;
240+ xlnx,is-dual = <0x0>;
241+ xlnx,tri-default = <0xffffffff>;
242+ xlnx,tri-default-2 = <0xffffffff>;
243+ } ;
244+ dual_timer_counter: system-timer@40300000 {
245+ clock-frequency = <100000000>;
246+ clocks = <&clk_bus>;
247+ compatible = "xlnx,axi-timer-1.03.a", "xlnx,xps-timer-1.00.a";
248+ interrupt-parent = <&interrupt_cntlr>;
249+ interrupts = < 3 2 >;
250+ reg = < 0x40300000 0x10000 >;
251+ xlnx,count-width = <0x20>;
252+ xlnx,family = "kintex7";
253+ xlnx,gen0-assert = <0x1>;
254+ xlnx,gen1-assert = <0x1>;
255+ xlnx,instance = "Dual_Timer_Counter";
256+ xlnx,one-timer-only = <0x0>;
257+ xlnx,trig0-assert = <0x1>;
258+ xlnx,trig1-assert = <0x1>;
259+ } ;
260+ iic_eeprom: i2c@40a00000 {
261+ compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
262+ interrupt-parent = <&interrupt_cntlr>;
263+ interrupts = < 4 2 >;
264+ reg = < 0x40a00000 0x10000 >;
265+ xlnx,family = "kintex7";
266+ xlnx,gpo-width = <0x1>;
267+ xlnx,iic-freq = <0x186a0>;
268+ xlnx,instance = "IIC_EEPROM";
269+ xlnx,scl-inertial-delay = <0x0>;
270+ xlnx,sda-inertial-delay = <0x0>;
271+ xlnx,sda-level = <0x1>;
272+ xlnx,ten-bit-adr = <0x0>;
273+ } ;
274+ interrupt_cntlr: interrupt-controller@40100000 {
275+ #interrupt-cells = <0x2>;
276+ compatible = "xlnx,axi-intc-1.03.a", "xlnx,xps-intc-1.00.a";
277+ interrupt-controller ;
278+ reg = < 0x40100000 0x10000 >;
279+ xlnx,kind-of-intr = <0x0>;
280+ xlnx,num-intr-inputs = <0x8>;
281+ } ;
282+ lcd_gpio: gpio@40800000 {
283+ #gpio-cells = <2>;
284+ compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
285+ gpio-controller ;
286+ reg = < 0x40800000 0x10000 >;
287+ xlnx,all-inputs = <0x0>;
288+ xlnx,all-inputs-2 = <0x0>;
289+ xlnx,dout-default = <0x0>;
290+ xlnx,dout-default-2 = <0x0>;
291+ xlnx,family = "kintex7";
292+ xlnx,gpio-width = <0x7>;
293+ xlnx,gpio2-width = <0x20>;
294+ xlnx,instance = "LCD_GPIO";
295+ xlnx,interrupt-present = <0x0>;
296+ xlnx,is-dual = <0x0>;
297+ xlnx,tri-default = <0xffffffff>;
298+ xlnx,tri-default-2 = <0xffffffff>;
299+ } ;
300+ leds_8bits: gpio@40600000 {
301+ #gpio-cells = <2>;
302+ compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
303+ gpio-controller ;
304+ reg = < 0x40600000 0x10000 >;
305+ xlnx,all-inputs = <0x0>;
306+ xlnx,all-inputs-2 = <0x0>;
307+ xlnx,dout-default = <0x0>;
308+ xlnx,dout-default-2 = <0x0>;
309+ xlnx,family = "kintex7";
310+ xlnx,gpio-width = <0x8>;
311+ xlnx,gpio2-width = <0x20>;
312+ xlnx,instance = "LEDs_8Bits";
313+ xlnx,interrupt-present = <0x1>;
314+ xlnx,is-dual = <0x0>;
315+ xlnx,tri-default = <0xffffffff>;
316+ xlnx,tri-default-2 = <0xffffffff>;
317+ } ;
318+ logisdhc_0: logisdhc@40b00000 {
319+ compatible = "xlnx,logisdhc-1.06.c";
320+ interrupt-parent = <&interrupt_cntlr>;
321+ interrupts = < 6 2 >;
322+ reg = < 0x40b00000 0x10000 >;
323+ xlnx,byte-per-pixel = <0x4>;
324+ xlnx,convert-endianess = <0x0>;
325+ xlnx,dma-type = <0x1>;
326+ xlnx,family = "kintex7";
327+ xlnx,ip-license-type = <0x1>;
328+ xlnx,ip-major-revision = <0x1>;
329+ xlnx,ip-minor-revision = <0x6>;
330+ xlnx,ip-patch-level = <0x2>;
331+ xlnx,mem-burst = <0x4>;
332+ xlnx,mem-data-bus-width = <0x20>;
333+ xlnx,mem-interface = <0x1>;
334+ xlnx,regs-interface = <0x2>;
335+ xlnx,row-stride = <0x400>;
336+ xlnx,sd-base-clock-freq = <0x64>;
337+ xlnx,use-dma = <0x0>;
338+ } ;
339+ primary_flash: flash@48000000 {
340+ #address-cells = <1>;
341+ #size-cells = <1>;
342+ bank-width = <2>;
343+ compatible = "xlnx,axi-emc-1.03.b", "cfi-flash";
344+ reg = < 0x48000000 0x8000000 >;
345+ xlnx,axi-clk-period-ps = <0x2710>;
346+ xlnx,family = "kintex7";
347+ xlnx,include-datawidth-matching-0 = <0x1>;
348+ xlnx,include-datawidth-matching-1 = <0x0>;
349+ xlnx,include-datawidth-matching-2 = <0x0>;
350+ xlnx,include-datawidth-matching-3 = <0x0>;
351+ xlnx,include-negedge-ioregs = <0x0>;
352+ xlnx,instance = "Linear_Flash";
353+ xlnx,lflash-period-ps = <0x4e20>;
354+ xlnx,linear-flash-sync-burst = <0x0>;
355+ xlnx,max-mem-width = <0x10>;
356+ xlnx,mem0-type = <0x2>;
357+ xlnx,mem0-width = <0x10>;
358+ xlnx,mem1-type = <0x0>;
359+ xlnx,mem1-width = <0x20>;
360+ xlnx,mem2-type = <0x0>;
361+ xlnx,mem2-width = <0x20>;
362+ xlnx,mem3-type = <0x0>;
363+ xlnx,mem3-width = <0x20>;
364+ xlnx,num-banks-mem = <0x1>;
365+ xlnx,parity-type-mem-0 = <0x0>;
366+ xlnx,parity-type-mem-1 = <0x0>;
367+ xlnx,parity-type-mem-2 = <0x0>;
368+ xlnx,parity-type-mem-3 = <0x0>;
369+ xlnx,s-axi-en-reg = <0x0>;
370+ xlnx,s-axi-mem-addr-width = <0x20>;
371+ xlnx,s-axi-mem-data-width = <0x20>;
372+ xlnx,s-axi-mem-id-width = <0x1>;
373+ xlnx,s-axi-mem-protocol = "AXI4LITE";
374+ xlnx,s-axi-reg-addr-width = <0x5>;
375+ xlnx,s-axi-reg-data-width = <0x20>;
376+ xlnx,s-axi-reg-protocol = "axi4";
377+ xlnx,synch-pipedelay-0 = <0x2>;
378+ xlnx,synch-pipedelay-1 = <0x2>;
379+ xlnx,synch-pipedelay-2 = <0x2>;
380+ xlnx,synch-pipedelay-3 = <0x2>;
381+ xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
382+ xlnx,tavdv-ps-mem-1 = <0x3a98>;
383+ xlnx,tavdv-ps-mem-2 = <0x3a98>;
384+ xlnx,tavdv-ps-mem-3 = <0x3a98>;
385+ xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
386+ xlnx,tcedv-ps-mem-1 = <0x3a98>;
387+ xlnx,tcedv-ps-mem-2 = <0x3a98>;
388+ xlnx,tcedv-ps-mem-3 = <0x3a98>;
389+ xlnx,thzce-ps-mem-0 = <0x88b8>;
390+ xlnx,thzce-ps-mem-1 = <0x1b58>;
391+ xlnx,thzce-ps-mem-2 = <0x1b58>;
392+ xlnx,thzce-ps-mem-3 = <0x1b58>;
393+ xlnx,thzoe-ps-mem-0 = <0x1b58>;
394+ xlnx,thzoe-ps-mem-1 = <0x1b58>;
395+ xlnx,thzoe-ps-mem-2 = <0x1b58>;
396+ xlnx,thzoe-ps-mem-3 = <0x1b58>;
397+ xlnx,tlzwe-ps-mem-0 = <0x88b8>;
398+ xlnx,tlzwe-ps-mem-1 = <0x0>;
399+ xlnx,tlzwe-ps-mem-2 = <0x0>;
400+ xlnx,tlzwe-ps-mem-3 = <0x0>;
401+ xlnx,tpacc-ps-flash-0 = <0x61a8>;
402+ xlnx,tpacc-ps-flash-1 = <0x61a8>;
403+ xlnx,tpacc-ps-flash-2 = <0x61a8>;
404+ xlnx,tpacc-ps-flash-3 = <0x61a8>;
405+ xlnx,twc-ps-mem-0 = <0x11170>;
406+ xlnx,twc-ps-mem-1 = <0x3a98>;
407+ xlnx,twc-ps-mem-2 = <0x3a98>;
408+ xlnx,twc-ps-mem-3 = <0x3a98>;
409+ xlnx,twp-ps-mem-0 = <0x11170>;
410+ xlnx,twp-ps-mem-1 = <0x2ee0>;
411+ xlnx,twp-ps-mem-2 = <0x2ee0>;
412+ xlnx,twp-ps-mem-3 = <0x2ee0>;
413+ xlnx,twph-ps-mem-0 = <0x2ee0>;
414+ xlnx,twph-ps-mem-1 = <0x2ee0>;
415+ xlnx,twph-ps-mem-2 = <0x2ee0>;
416+ xlnx,twph-ps-mem-3 = <0x2ee0>;
417+ xlnx,wr-rec-time-mem-0 = <0x186a0>;
418+ xlnx,wr-rec-time-mem-1 = <0x186a0>;
419+ xlnx,wr-rec-time-mem-2 = <0x186a0>;
420+ xlnx,wr-rec-time-mem-3 = <0x186a0>;
421+ partition@0x00000000 {
422+ label = "fpga";
423+ reg = <0x00000000 0x00200000>;
424+ };
425+ partition@0x00200000 {
426+ label = "boot";
427+ reg = <0x00200000 0x00040000>;
428+ };
429+ partition@0x00240000 {
430+ label = "bootenv";
431+ reg = <0x00240000 0x00020000>;
432+ };
433+ partition@0x00260000 {
434+ label = "image";
435+ reg = <0x00260000 0x00c00000>;
436+ };
437+ partition@0x00e60000 {
438+ label = "spare";
439+ reg = <0x00e60000 0x00000000>;
440+ };
441+ } ;
442+ push_buttons_5bits: gpio@40500000 {
443+ #gpio-cells = <2>;
444+ compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
445+ gpio-controller ;
446+ reg = < 0x40500000 0x10000 >;
447+ xlnx,all-inputs = <0x1>;
448+ xlnx,all-inputs-2 = <0x0>;
449+ xlnx,dout-default = <0x0>;
450+ xlnx,dout-default-2 = <0x0>;
451+ xlnx,family = "kintex7";
452+ xlnx,gpio-width = <0x5>;
453+ xlnx,gpio2-width = <0x20>;
454+ xlnx,instance = "Push_Buttons_5Bits";
455+ xlnx,interrupt-present = <0x1>;
456+ xlnx,is-dual = <0x0>;
457+ xlnx,tri-default = <0xffffffff>;
458+ xlnx,tri-default-2 = <0xffffffff>;
459+ } ;
460+ rotary_gpio: gpio@40900000 {
461+ #gpio-cells = <2>;
462+ compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
463+ gpio-controller ;
464+ reg = < 0x40900000 0x10000 >;
465+ xlnx,all-inputs = <0x1>;
466+ xlnx,all-inputs-2 = <0x0>;
467+ xlnx,dout-default = <0x0>;
468+ xlnx,dout-default-2 = <0x0>;
469+ xlnx,family = "kintex7";
470+ xlnx,gpio-width = <0x3>;
471+ xlnx,gpio2-width = <0x20>;
472+ xlnx,instance = "ROTARY_GPIO";
473+ xlnx,interrupt-present = <0x0>;
474+ xlnx,is-dual = <0x0>;
475+ xlnx,tri-default = <0xffffffff>;
476+ xlnx,tri-default-2 = <0xffffffff>;
477+ } ;
478+ rs232_uart_1: serial@40400000 {
479+ clock-frequency = <100000000>;
480+ clocks = <&clk_bus>;
481+ compatible = "xlnx,axi-uart16550-1.01.a", "xlnx,xps-uart16550-2.00.a", "ns16550a";
482+ current-speed = <115200>;
483+ device_type = "serial";
484+ interrupt-parent = <&interrupt_cntlr>;
485+ interrupts = < 5 2 >;
486+ reg = < 0x40400000 0x10000 >;
487+ reg-offset = <0x1000>;
488+ reg-shift = <2>;
489+ xlnx,external-xin-clk-hz = <0x17d7840>;
490+ xlnx,family = "kintex7";
491+ xlnx,has-external-rclk = <0x0>;
492+ xlnx,has-external-xin = <0x0>;
493+ xlnx,instance = "RS232_Uart_1";
494+ xlnx,is-a-16550 = <0x1>;
495+ xlnx,use-modem-ports = <0x0>;
496+ xlnx,use-user-ports = <0x0>;
497+ } ;
498+ soft_ethernet_mac: axi-ethernet@50100000 {
499+ axistream-connected = <&axi_dma_ethernet>;
500+ axistream-control-connected = <&axi_dma_ethernet>;
501+ clock-frequency = <100000000>;
502+ clocks = <&clk_bus>;
503+ compatible = "xlnx,axi-ethernet-3.01.a", "xlnx,axi-ethernet-1.00.a";
504+ device_type = "network";
505+ interrupt-parent = <&interrupt_cntlr>;
506+ interrupts = < 2 2 >;
507+ local-mac-address = [ 00 0a 35 00 d9 4e ];
508+ phy-mode = "gmii";
509+ phy-handle = <&phy0>;
510+ reg = < 0x50100000 0x40000 >;
511+ xlnx,avb = <0x0>;
512+ xlnx,halfdup = <0x0>;
513+ xlnx,include-io = <0x1>;
514+ xlnx,mcast-extend = <0x0>;
515+ xlnx,phy-type = <0x1>;
516+ xlnx,phyaddr = <0x1>;
517+ xlnx,rxcsum = <0x0>;
518+ xlnx,rxmem = <0x1000>;
519+ xlnx,rxvlan-strp = <0x0>;
520+ xlnx,rxvlan-tag = <0x0>;
521+ xlnx,rxvlan-tran = <0x0>;
522+ xlnx,stats = <0x0>;
523+ xlnx,txcsum = <0x0>;
524+ xlnx,txmem = <0x1000>;
525+ xlnx,txvlan-strp = <0x0>;
526+ xlnx,txvlan-tag = <0x0>;
527+ xlnx,txvlan-tran = <0x0>;
528+ xlnx,type = <0x1>;
529+ mdio {
530+ #address-cells = <1>;
531+ #size-cells = <0>;
532+ phy0: phy@7 {
533+ compatible = "marvell,88e1111";
534+ device_type = "ethernet-phy";
535+ reg = <7>;
536+ } ;
537+ } ;
538+ } ;
539+ } ;
540+ axi_mm_mb: axi@1 {
541+ #address-cells = <1>;
542+ #size-cells = <1>;
543+ compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
544+ ranges ;
545+ axi4_0: axi@0 {
546+ #address-cells = <1>;
547+ #size-cells = <1>;
548+ compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
549+ ranges = < 0x80000000 0x80000000 0x40000000 >;
550+ } ;
551 } ;
33 } ; 552 } ;
34diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk 553diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
35index 36bdd96..25e97de 100644 554index 36bdd96..25e97de 100644
@@ -63,115 +582,58 @@ index 36bdd96..25e97de 100644
63+PLATFORM_CCPFLAGS += -mxl-pattern-compare 582+PLATFORM_CCPFLAGS += -mxl-pattern-compare
64+PLATFORM_CCPFLAGS += -mxl-reorder 583+PLATFORM_CCPFLAGS += -mxl-reorder
65diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h 584diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
66index d6d0d67..f539044 100644 585index dc5645b..80b1ce3 100644
67--- a/board/xilinx/microblaze-generic/xparameters.h 586--- a/board/xilinx/microblaze-generic/xparameters.h
68+++ b/board/xilinx/microblaze-generic/xparameters.h 587+++ b/board/xilinx/microblaze-generic/xparameters.h
69@@ -1,67 +1,47 @@ 588@@ -15,15 +15,11 @@
70-/* 589
71- * (C) Copyright 2007 Michal Simek
72- *
73- * Michal SIMEK <monstr@monstr.eu>
74- *
75- * SPDX-License-Identifier: GPL-2.0+
76- *
77- * CAUTION: This file is a faked configuration !!!
78- * There is no real target for the microblaze-generic
79- * configuration. You have to replace this file with
80- * the generated file from your Xilinx design flow.
81- */
82-
83-#define XILINX_BOARD_NAME microblaze-generic
84-
85-/* System Clock Frequency */
86-#define XILINX_CLOCK_FREQ 100000000
87-
88 /* Microblaze is microblaze_0 */ 590 /* Microblaze is microblaze_0 */
89 #define XILINX_USE_MSR_INSTR 1 591 #define XILINX_USE_MSR_INSTR 1
90-#define XILINX_FSL_NUMBER 3 592-#define XILINX_FSL_NUMBER 3
91+#define XILINX_PVR 2 593-
594-/* GPIO is LEDs_4Bit*/
595-#define XILINX_GPIO_BASEADDR 0x40000000
92+#define XILINX_FSL_NUMBER 0 596+#define XILINX_FSL_NUMBER 0
93+#define XILINX_USE_ICACHE 1 597+#define XILINX_USE_ICACHE 1
94+#define XILINX_USE_DCACHE 1 598+#define XILINX_USE_DCACHE 1
95+#define XILINX_DCACHE_BYTE_SIZE 8192 599+#define XILINX_DCACHE_BYTE_SIZE 8192
96 600
97-/* Interrupt controller is opb_intc_0 */ 601 /* Flash Memory is FLASH_2Mx32 */
98-#define XILINX_INTC_BASEADDR 0x41200000
99-#define XILINX_INTC_NUM_INTR_INPUTS 6
100+/* Interrupt controller is interrupt_cntlr */
101+#define XILINX_INTC_BASEADDR 0x40100000
102+#define XILINX_INTC_NUM_INTR_INPUTS 8
103
104-/* Timer pheriphery is opb_timer_1 */
105-#define XILINX_TIMER_BASEADDR 0x41c00000
106-#define XILINX_TIMER_IRQ 0
107+/* Timer pheriphery is dual_timer_counter */
108+#define XILINX_TIMER_BASEADDR 0x40300000
109+#define XILINX_TIMER_IRQ 3
110
111-/* Uart pheriphery is RS232_Uart */
112-#define XILINX_UARTLITE_BASEADDR 0x40600000
113-#define XILINX_UARTLITE_BAUDRATE 115200
114+/* System Timer Clock Frequency */
115+#define XILINX_CLOCK_FREQ 100000000
116+
117+/* Uart console is rs232_uart_1 */
118+#define XILINX_UART16550
119+#define XILINX_UART16550_BASEADDR 0x40400000
120+#define XILINX_UART16550_CLOCK_HZ 100000000
121+#define CONFIG_CONS_INDEX 1
122
123-/* IIC pheriphery is IIC_EEPROM */
124-#define XILINX_IIC_0_BASEADDR 0x40800000
125+/* IIC pheriphery is iic_eeprom */
126+#define XILINX_IIC_0_BASEADDR 0x40a00000
127 #define XILINX_IIC_0_FREQ 100000
128 #define XILINX_IIC_0_BIT 0
129
130-/* GPIO is LEDs_4Bit*/
131-#define XILINX_GPIO_BASEADDR 0x40000000
132-
133-/* Flash Memory is FLASH_2Mx32 */
134-#define XILINX_FLASH_START 0x2c000000 602-#define XILINX_FLASH_START 0x2c000000
135-#define XILINX_FLASH_SIZE 0x00800000 603-#define XILINX_FLASH_SIZE 0x00800000
136+/* GPIO doesn't exist */ 604-
137
138-/* Main Memory is DDR_SDRAM_64Mx32 */
139-#define XILINX_RAM_START 0x28000000
140-#define XILINX_RAM_SIZE 0x04000000
141+/* SDIO doesn't exist */
142
143-/* Sysace Controller is SysACE_CompactFlash */
144-#define XILINX_SYSACE_BASEADDR 0x41800000
145-#define XILINX_SYSACE_HIGHADDR 0x4180ffff
146-#define XILINX_SYSACE_MEM_WIDTH 16
147+/* Main Memory is ddr3_sdram */
148+#define XILINX_RAM_START 0x80000000
149+#define XILINX_RAM_SIZE 0x40000000
150
151-/* Ethernet controller is Ethernet_MAC */
152-#define XILINX_EMACLITE_BASEADDR 0x40C00000
153+/* Flash Memory is linear_flash */
154+#define XILINX_FLASH_START 0x48000000
155+#define XILINX_FLASH_SIZE 0x08000000
156
157-/* LL_TEMAC Ethernet controller */
158-#define XILINX_LLTEMAC_BASEADDR 0x44000000
159-#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180
160-#define XILINX_LLTEMAC_BASEADDR1 0x44200000
161-#define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000
162+/* Sysace doesn't exist */
163
164-/* Watchdog IP is wxi_timebase_wdt_0 */ 605-/* Watchdog IP is wxi_timebase_wdt_0 */
165-#define XILINX_WATCHDOG_BASEADDR 0x50000000 606-#define XILINX_WATCHDOG_BASEADDR 0x50000000
166-#define XILINX_WATCHDOG_IRQ 1 607-#define XILINX_WATCHDOG_IRQ 1
167+/* Ethernet controller is soft_ethernet_mac */ 608+#define XILINX_FLASH_START 0x48000000
168+#define XILINX_AXIEMAC_BASEADDR 0x50100000 609+#define XILINX_FLASH_SIZE 0x08000000
169+#define XILINX_AXIDMA_BASEADDR 0x50000000 610diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
611index 21a7261..5f17daf 100644
612--- a/configs/microblaze-generic_defconfig
613+++ b/configs/microblaze-generic_defconfig
614@@ -7,8 +7,8 @@ CONFIG_SPL=y
615 CONFIG_FIT=y
616 CONFIG_FIT_VERBOSE=y
617 CONFIG_HUSH_PARSER=y
618-CONFIG_SYS_PROMPT="U-Boot-mONStR> "
619-CONFIG_CMD_GPIO=y
620+CONFIG_SYS_PROMPT="U-Boot> "
621+# CONFIG_CMD_GPIO is not set
622 # CONFIG_CMD_SETEXPR is not set
623 CONFIG_CMD_TFTPPUT=y
624 CONFIG_CMD_DHCP=y
625@@ -19,5 +19,6 @@ CONFIG_NETCONSOLE=y
626 CONFIG_DM_ETH=y
627 CONFIG_XILINX_AXIEMAC=y
628 CONFIG_XILINX_EMACLITE=y
629+CONFIG_NET_RANDOM_ETHADDR=y
630 CONFIG_SYS_NS16550=y
631 CONFIG_XILINX_UARTLITE=y
170diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h 632diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
171index e16965c..f463b83 100644 633index b424782..eb56f12 100644
172--- a/include/configs/microblaze-generic.h 634--- a/include/configs/microblaze-generic.h
173+++ b/include/configs/microblaze-generic.h 635+++ b/include/configs/microblaze-generic.h
174@@ -151,7 +151,7 @@ 636@@ -91,7 +91,7 @@
175 /* max number of memory banks */ 637 /* max number of memory banks */
176 # define CONFIG_SYS_MAX_FLASH_BANKS 1 638 # define CONFIG_SYS_MAX_FLASH_BANKS 1
177 /* max number of sectors on one chip */ 639 /* max number of sectors on one chip */
@@ -180,36 +642,15 @@ index e16965c..f463b83 100644
180 /* hardware flash protection */ 642 /* hardware flash protection */
181 # define CONFIG_SYS_FLASH_PROTECTION 643 # define CONFIG_SYS_FLASH_PROTECTION
182 /* use buffered writes (20x faster) */ 644 /* use buffered writes (20x faster) */
183@@ -247,7 +247,9 @@ 645@@ -161,6 +161,8 @@
184 #define CONFIG_CMD_ASKENV 646 #define XILINX_DCACHE_BYTE_SIZE 32768
185 #define CONFIG_CMD_IRQ
186 #define CONFIG_CMD_MFSL
187-#define CONFIG_CMD_GPIO
188+#ifdef CONFIG_XILINX_GPIO
189+# define CONFIG_CMD_GPIO
190+#endif
191
192 #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
193 # define CONFIG_CMD_CACHE
194@@ -317,7 +319,7 @@
195 #endif 647 #endif
196 648
197 /* Miscellaneous configurable options */ 649+#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
198-#define CONFIG_SYS_PROMPT "U-Boot-mONStR> " 650+
199+#define CONFIG_SYS_PROMPT "U-Boot> " 651 /*
200 /* size of console buffer */ 652 * BOOTP options
201 #define CONFIG_SYS_CBSIZE 512 653 */
202 /* print buffer size */
203@@ -350,7 +352,8 @@
204 "nc=setenv stdout nc;"\
205 "setenv stdin nc\0" \
206 "serial=setenv stdout serial;"\
207- "setenv stdin serial\0"
208+ "setenv stdin serial\0" \
209+ "ethaddr=00:0a:35:00:01:22\0"
210
211 #define CONFIG_CMDLINE_EDITING
212
213-- 654--
2142.6.4 6552.7.0
215 656
diff --git a/recipes-bsp/u-boot/u-boot-xlnx_2015.07.bb b/recipes-bsp/u-boot/u-boot-xlnx_2016.01.bb
index 25d50eb2..67c73da5 100644
--- a/recipes-bsp/u-boot/u-boot-xlnx_2015.07.bb
+++ b/recipes-bsp/u-boot/u-boot-xlnx_2016.01.bb
@@ -1,15 +1,11 @@
1include u-boot-xlnx.inc 1include u-boot-xlnx.inc
2include u-boot-spl-zynq-init.inc 2include u-boot-spl-zynq-init.inc
3 3
4# this matches u-boot-xlnx 'xilinx-v2015.4' release tag 4# this matches u-boot-xlnx 'xilinx-v2016.?' release tag
5SRCREV = "4942ae4d03ee4ef4b2dd750d441f730150ee9288" 5SRCREV = "68b454fbd9f7ce10e87e736888ea54c1655ce025"
6PV = "v2015.07${XILINX_EXTENSION}+git${SRCPV}" 6PV = "v2016.01${XILINX_EXTENSION}+git${SRCPV}"
7 7
8FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot-xlnx:" 8FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot-xlnx:"
9SRC_URI += " \
10 file://0001-microblaze-Fix-style-issues-in-header-files.patch \
11 file://0002-microblaze-Fix-C99-gnu99-compatiblity-for-inline-fun.patch \
12 "
13 9
14SRC_URI_append_kc705-trd-microblazeel = " file://microblaze-kc705-trd-Convert-microblaze-generic-to-k.patch" 10SRC_URI_append_kc705-trd-microblazeel = " file://microblaze-kc705-trd-Convert-microblaze-generic-to-k.patch"
15 11
@@ -21,11 +17,12 @@ UBOOT_ENV_zedboard-zynq7 = "uEnv"
21SRC_URI_append_zc702-zynq7 = " file://uEnv.txt" 17SRC_URI_append_zc702-zynq7 = " file://uEnv.txt"
22SRC_URI_append_zedboard-zynq7 = " file://uEnv.txt" 18SRC_URI_append_zedboard-zynq7 = " file://uEnv.txt"
23 19
24# u-boot 2015.07 has support for these 20# u-boot 2016.01 has support for these
25HAS_PS7INIT ?= " \ 21HAS_PS7INIT ?= " \
26 zynq_microzed_config \ 22 zynq_microzed_config \
27 zynq_zed_config \ 23 zynq_zed_config \
28 zynq_zc702_config \ 24 zynq_zc702_config \
29 zynq_zc706_config \ 25 zynq_zc706_config \
26 zynq_zybo_config \
30 " 27 "
31 28
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-10-01 23:11:03 +0000