Merge remote-tracking branch 'origin/rel-v2022.2' into honister

Signed-off-by: Mark Hatle <mark.hatle@amd.com>

13 files changed, 22 insertions, 17 deletions

diff --git a/meta-xilinx-core/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-core/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend
index a3dedd85..151bd0e0 100644
--- a/meta-xilinx-core/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend
+++ b/meta-xilinx-core/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend
@@ -14,5 +14,5 @@ YAML_DT_BOARD_FLAGS:zynqmp-generic ?= "{BOARD zcu102-rev1.0}"
 # versal-generic.conf file uses HDF_MACHINE = "vck190-versal", Hence set versal-vck190-reva-x-ebm-01-reva dtsi file.
 YAML_DT_BOARD_FLAGS:versal-generic ?= "{BOARD versal-vck190-reva-x-ebm-01-reva}"
 
-# versal-net-generic.conf uses HDF_MACHINE = "versal-net-generic", Hence set versal-net-ipp-rev1.5 dtsi file.
-YAML_DT_BOARD_FLAGS:versal-net-generic ?= "{BOARD versal-net-ipp-rev1.5}"
+# versal-net-generic.conf uses HDF_MACHINE = "versal-net-generic", Hence set versal-net-ipp-rev1.9 dtsi file.
+YAML_DT_BOARD_FLAGS:versal-net-generic ?= "{BOARD versal-net-ipp-rev1.9}"
diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc
index 4b076444..a45b5ce5 100644
--- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc
+++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc
@@ -36,6 +36,7 @@ PACKAGE_ARCH = "${MACHINE_ARCH}"
 
 PLATFORM:zynqmp = "zynqmp"
 PLATFORM:versal = "versal"
+PLATFORM:versal-net = "versal_net"
 
 # requires CROSS_COMPILE set by hand as there is no configure script
 export CROSS_COMPILE="${TARGET_PREFIX}"
@@ -55,6 +56,7 @@ DEBUG_ATF:versal ?= "1"
 
 EXTRA_OEMAKE:append:zynqmp = "${@' ZYNQMP_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}"
 EXTRA_OEMAKE:append:versal = "${@' VERSAL_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}"
+EXTRA_OEMAKE:append:versal-net = "${@' VERSAL_NET_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}"
 EXTRA_OEMAKE:append = " ${@bb.utils.contains('DEBUG_ATF', '1', ' DEBUG=${DEBUG_ATF}', '', d)}"
 
 OUTPUT_DIR = "${@bb.utils.contains('DEBUG_ATF', '1', '${B}/${PLATFORM}/debug', '${B}/${PLATFORM}/release', d)}"
@@ -68,6 +70,9 @@ EXTRA_OEMAKE:append:zynqmp = "${@' ZYNQMP_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.get
 EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}"
 EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}"
 
+EXTRA_OEMAKE:append:versal-net = "${@' VERSAL_NET_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}"
+EXTRA_OEMAKE:append:versal-net = "${@' VERSAL_NET_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}"
+
 ATF_PROVENCORE = "SPD=pncd SPD_PNCD_NS_IRQ=51 ZYNQMP_BL32_MEM_BASE=0x70000000 ZYNQMP_BL32_MEM_SIZE=0x0FF00000"
 EXTRA_OEMAKE:append = "${@bb.utils.contains('MACHINE_FEATURES', 'provencore', ' ${ATF_PROVENCORE}', '', d)}"
 
diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb
index 6e4b7d0f..7e423b9c 100644
--- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb
+++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb
@@ -1,5 +1,5 @@
 ATF_VERSION = "2.6"
-SRCREV = "7c85661015b70f6b9aa821e6ebeea0dd96a59287"
+SRCREV = "85544c0159e216935e40174dadfed1296b6042bd"
 BRANCH = "xlnx_rebase_v2.6"
 LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031"
 
diff --git a/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb b/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb
index 85880158..f80e1feb 100644
--- a/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb
+++ b/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb
@@ -11,7 +11,7 @@ RDEPENDS:${PN} += "openssl"
 
 REPO ?= "git://github.com/Xilinx/bootgen.git;protocol=https"
 BRANCH ?= "master"
-SRCREV = "4eac958eb6c831ffa5768a0e2cd4be23c5efe2e0"
+SRCREV = "d890ba298685b73307a01a9dbcc8702f9afcdbcc"
 
 BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
 SRC_URI = "${REPO};${BRANCHARG}"
diff --git a/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c b/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c
index e4fb1d2f..04777a91 100644
--- a/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c
+++ b/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c
@@ -1,6 +1,7 @@
 /******************************************************************************
  *
- * Copyright (C) 2019-2020 Xilinx, Inc.  All rights reserved.
+ * Copyright (C) 2019-2022 Xilinx, Inc.  All rights reserved.
+ * Copyright (C) 2022 Advanced Micro Devices, Inc.  All rights reserved.
  *
  *  Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -91,7 +92,7 @@ void print_usage(char *prg)
         fprintf(stderr, "                                Device Tree\n");
         if (iszynqmp)
         {
-                fprintf(stderr, "                               Default: <Full>\n");
+                fprintf(stderr, "                               Default: <full>\n");
                 fprintf(stderr, "         -s <secure flags>     Optional: <Secure flags>\n");
                 fprintf(stderr, "                                  s := <AuthDDR | AuthOCM | EnUsrKey | EnDevKey | AuthEnUsrKeyDDR | AuthEnUsrKeyOCM | AuthEnDevKeyDDR | AuthEnDevKeyOCM>\n");
                 fprintf(stderr, "         -k <AesKey>           Optional: <AES User Key>\n");
@@ -107,7 +108,7 @@ void print_usage(char *prg)
         fprintf(stderr, " \n");
         fprintf(stderr, "Examples:\n");
         fprintf(stderr, "(Load Full bitstream using Overlay)\n");
-        fprintf(stderr, "%s -b top.bit.bin -o can.dtbo -f Full -n Full \n", prg);
+        fprintf(stderr, "%s -b top.bit.bin -o can.dtbo -f Full -n full \n", prg);
         fprintf(stderr, "(Load Partial bitstream using Overlay)\n");
         fprintf(stderr, "%s -b rm0.bit.bin -o rm0.dtbo -f Partial -n PR0\n", prg);
         fprintf(stderr, "(Load Full bitstream using sysfs interface)\n");
@@ -127,7 +128,7 @@ void print_usage(char *prg)
         fprintf(stderr, "(Remove Partial Overlay)\n");
         fprintf(stderr, "%s -R -n PR0\n", prg);
         fprintf(stderr, "(Remove Full Overlay)\n");
-        fprintf(stderr, "%s -R -n Full\n", prg);
+        fprintf(stderr, "%s -R -n full\n", prg);
         fprintf(stderr, "Note: %s -R is responsible for only removing the dtbo file from the livetree. it will not remove the PL logic from the FPGA region.\n", prg);
         fprintf(stderr, " \n");
 }
diff --git a/meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb b/meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb
index 416edf17..d22c995c 100644
--- a/meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb
+++ b/meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb
@@ -1,7 +1,7 @@
 SUMMARY = "Install user script to support fpga-manager"
 DESCRIPTION = "Install user script that loads and unloads overlays using kernel fpga-manager"
 LICENSE = "Proprietary"
-LIC_FILES_CHKSUM = "file://${WORKDIR}/fpgautil.c;beginline=1;endline=24;md5=8010e59a286b1e3a73a9fdd93bd18778"
+LIC_FILES_CHKSUM = "file://${WORKDIR}/fpgautil.c;beginline=1;endline=24;md5=0c02eabf57dba52842c5df9b96bccfae"
 
 SRC_URI = "\
         file://fpgautil.c \
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb
index 9d1ff13a..46bfd5b9 100644
--- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb
@@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01"
 
 UBRANCH ?= "master"
 
-SRCREV = "f7c1e7084dcb5ed9653e2fa89081f266ba02dfb8"
+SRCREV = "f2402773e2d82aafc08ac39c03f3bc430c014703"
 
 include u-boot-xlnx.inc
 include u-boot-spl-zynq-init.inc
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb
index 43be5437..c7719866 100644
--- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb
@@ -2,5 +2,5 @@
 require qemu-devicetrees.inc
 
 BRANCH ?= "master"
-SRCREV ?= "aec07daf197f1853ee1a1d905e1eff4fe160f408"
+SRCREV ?= "42d0b7e24fbd1adc72fb2d0e70e06ff332278468"
 
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc
index 60bc2ff3..555f18f9 100644
--- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc
@@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native"
 
 XILINX_QEMU_VERSION ?= "v6.1.0"
 BRANCH ?= "master"
-SRCREV = "de92de0a3cef8affbf256d8930817bf8765cce21"
+SRCREV = "fbcb55665e9f5f91110ba2a44f62be9bc72752ee"
 
 FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
 
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc
index adefabea..08755b26 100644
--- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc
@@ -53,6 +53,7 @@ KBUILD_DEFCONFIG:zynqmp ?= "xilinx_defconfig"
 KBUILD_DEFCONFIG:zynq ?= "xilinx_zynq_defconfig"
 KBUILD_DEFCONFIG:microblaze ?= "mmu_defconfig"
 KBUILD_DEFCONFIG:versal ?= "xilinx_defconfig"
+KBUILD_DEFCONFIG:versal-net ?= "xilinx_versal_net_defconfig"
 
 KERNEL_FEATURES:append:zynqmp = "${@bb.utils.contains('DISTRO_FEATURES', 'xen', ' features/xen/xen.scc', '', d)}"
 
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb
index c41e5df2..3551fb8b 100644
--- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb
@@ -1,6 +1,6 @@
 LINUX_VERSION = "5.15.36"
 KBRANCH="xlnx_rebase_v5.15_LTS"
-SRCREV = "0666ebfb0c32e2af2e2e943ca1561a9a0f83ee9f"
+SRCREV = "2ddbacde6539be25b5717af5705a0d0009d6b2d3"
 
 KCONF_AUDIT_LEVEL="0"
 
diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
index 51455162..ba42fd5f 100644
--- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
+++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
@@ -3,8 +3,6 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '
 SRC_URI = "${REPO};${BRANCHARG}"
 
 BRANCH= "master"
-SRCREV= "6af05b317093d0c38184322585ac21617f4789c5"
+SRCREV= "910828b3abdbf66b10cb6efc952e75df64962340"
 PV = "202220.2.14.0"
 
-
-
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
index 7ae40871..5dc2cc18 100644
--- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
+++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
@@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c"
 ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7"
 ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03"
 ESW_REV[2022.1] = "0cfb554e841f0837cabbb40a2481f5f7e5f2ddc0"
-ESW_REV[2022.2] = "f9503dcf194083da984776e51dc9c07f8cb6d498"
+ESW_REV[2022.2] = "72f6e3d45fb4dd9d6cd4a7581b935b39cf8ce96d"
 ESW_REV[git]    = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770"
 SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}"