Mirror of git.yoctoproject.org/meta-xilinx.git https://git.enea.com/cgit/linux/meta-xilinx.git/atom?h=mickledore 2023-10-23T00:40:49+00:00 2023-10-23T00:40:49+00:00 Mark Hatle mark.hatle@amd.com 2023-10-23T00:31:29+00:00 urn:sha1:e08eacd3b7e25d9435c742dcfb54c1e31113c047 Signed-off-by: Mark Hatle <mark.hatle@amd.com> 2023-10-21T20:25:20+00:00 Mark Hatle mark.hatle@amd.com 2023-10-21T20:25:20+00:00 urn:sha1:45cfe51f85519cfaa3bc51b0532ab2c441b628de Signed-off-by: Mark Hatle <mark.hatle@amd.com> 2023-10-12T16:47:11+00:00 Sivaprasad Addepalli sivaprasad.addepalli@xilinx.com 2023-10-12T16:14:13+00:00 urn:sha1:05911e19d85fd98c42054238392afe95a5125265 xilpm: versal: server: Remove XRAM axi-lite clock selection Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> 2023-10-06T08:27:11+00:00 Sivaprasad Addepalli sivaprasad.addepalli@xilinx.com 2023-10-06T07:20:40+00:00 urn:sha1:5f3b406206690c18fa5dc77f3feed4c01ace8274 scripts: pyesw: open_amp: Extend cleanup support for Libmetal and OpenAMP scripts: pyesw: open_amp: Simplify openamp-lopper run scripts: pyesw: open_amp: Add support for Zynq for OpenAMP and Libmetal in BSP scripts: Enable OpenAMP and Libmetal demos to mimic convention of other ESW apps Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> 2023-10-04T14:04:52+00:00 Mark Hatle mark.hatle@amd.com 2023-10-03T20:36:42+00:00 urn:sha1:9711aa74554f1afed5358d36cb9ba661abeb8e30 Move to release branch, which is rebased from the dev branch Signed-off-by: Mark Hatle <mark.hatle@amd.com> 2023-10-04T11:27:12+00:00 Sivaprasad Addepalli sivaprasad.addepalli@xilinx.com 2023-10-04T09:30:51+00:00 urn:sha1:98ce3f1bca175168d24bf41a2b50f01a53af6dd0 scripts: pyesw: build_app: Add command line arg to specify .repo.yaml path Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> 2023-09-29T07:47:11+00:00 Sivaprasad Addepalli sivaprasad.addepalli@xilinx.com 2023-09-29T06:25:53+00:00 urn:sha1:1208ea87db4a5444514b72f98fdb8599ab861f51 update Embedded SW license 2023.2 release Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> 2023-09-27T12:47:17+00:00 Sivaprasad Addepalli sivaprasad.addepalli@xilinx.com 2023-09-27T09:03:17+00:00 urn:sha1:e091ac343fd937463f43ef20ee72442a5ff700fc scripts: pyesw: library_utils: Pull the xilflash library irrespective of the hardware dependency Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> 2023-09-26T08:57:20+00:00 Sivaprasad Addepalli sivaprasad.addepalli@xilinx.com 2023-09-26T07:40:42+00:00 urn:sha1:9108010f9eb4602a8c60ab57c000a3e061e00067 Revert "uartps: Fix xuartps_intr_example compilation errors in SDT flow" sw_services:xilsecure:Fixed MISRA-C Rule 12.2 violation sw_services:xilsecure:Fixed compilation warning for ecdsa example sw_services:xilsecure:Fixed MISRA-C Rule 10.3 and 10.4 violations sw_services:xilsecure:Fixed misra-c Rule 8.13 violation sw_services:xilsecure:Fixed coverity warnings updated for ddrcpsu changelog Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> 2023-09-25T08:17:11+00:00 Sivaprasad Addepalli sivaprasad.addepalli@xilinx.com 2023-09-25T07:21:31+00:00 urn:sha1:55e94b3042398422a2034b1c3ed4db6472eb48bb sw_services: xilcert: Replace XSecure_MemCpy64 with Xil_SMemCpy sw_services: xilcert: Fix the value of UEID extension scripts: pyesw: reconfig_bsp: Add support for older platforms/bsp axidma: Fix simple interrupt example for SDT flow Xilsecure: Add version header file for client mode VersalNet: Disable cache for xilpuf and xilnvm libraries xilplmi: fixed missing header inclusion lib: sw_apps: Update the User Compile and Link options for c++ sources lib: sw_apps: Fix linker script LINK_DEPENDS in system device-tree flow updated for changelog vtc uartps: Fix xuartps_intr_example compilation errors in SDT flow sw_services:xilpuf:Fixed doxygen warnings sw_services:xilsecure:Fixed doxygen warnings Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>