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<title>linux/meta-xilinx.git/meta-xilinx-core/lib, branch master</title>
<subtitle>Mirror of git.yoctoproject.org/meta-xilinx.git</subtitle>
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<updated>2024-08-16T14:54:55+00:00</updated>
<entry>
<title>boot-jtag.py: Add IMAGE_NAME_SUFFIX to tcl</title>
<updated>2024-08-16T14:54:55+00:00</updated>
<author>
<name>Sandeep Gundlupet Raju</name>
<email>sandeep.gundlupet-raju@amd.com</email>
</author>
<published>2024-08-14T22:08:34+00:00</published>
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<id>urn:sha1:e3de5e4e3078b06e1bb866990d4bca7645ca6ec4</id>
<content type='text'>
In scarthgap release, By default IMAGE_NAME_SUFFIX=".rootfs" set in
image-artifact-name.bbclass, Due to this boot-jtag script doesn't
include rootfs in .tcl script. Hence add IMAGE_NAME_SUFFIX to tcl
script.

Signed-off-by: Sandeep Gundlupet Raju &lt;sandeep.gundlupet-raju@amd.com&gt;
Signed-off-by: Mark Hatle &lt;mark.hatle@amd.com&gt;
</content>
</entry>
<entry>
<title>boot-jtag.py: Remove stale imports</title>
<updated>2024-06-20T20:59:17+00:00</updated>
<author>
<name>Alain Péteut</name>
<email>alain.peteut@spacetek.ch</email>
</author>
<published>2024-06-18T17:03:48+00:00</published>
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<id>urn:sha1:f42c4f668932781a21ddb80fc33e4b2ffc94311f</id>
<content type='text'>
Based on github Pull Request #61.

1. `yaml` is imported but not used. This may cause issues as `yaml`
  is not a standard library module.
2. Remove trailing newlines.

Signed-off-by: Alain Péteut &lt;alain.peteut@spacetek.ch&gt;

Update commit message and added PR number in commit message.

Also update import list order.

Signed-off-by: Sandeep Gundlupet Raju &lt;sandeep.gundlupet-raju@amd.com&gt;
Signed-off-by: Mark Hatle &lt;mark.hatle@amd.com&gt;
</content>
</entry>
<entry>
<title>various: Remove SOC_VARIANT, split versal and versal-net, add machine_features</title>
<updated>2024-06-04T23:00:14+00:00</updated>
<author>
<name>Mark Hatle</name>
<email>mark.hatle@amd.com</email>
</author>
<published>2024-06-04T22:51:04+00:00</published>
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<id>urn:sha1:195e1fa9fb13b21bc41af4e0747d4646caeb65e5</id>
<content type='text'>
SOC_VARIANT has been remove, we are now only using the YP standard SOC_FAMILY
configuration.  The defined families are: zynq, zynqmp, versal and versal-net.

Our decision of breaking up versal-net from versal, is based on the SoC CPU
changes from cortexa72/r5 to cortexa78/r52, thus we're treating it as a
different SoC family.

In order to capture the individual capabilities that we used to handle via
SOC_VARIANT, we have defined the following features (some may have been
previously defined):
 - mali400 (zynqmp eg and ev)
 - vcu (zynqmp ev)
 - rfsoc (zynqmp dr RF capabiltiies)
 - aie - (versal ai &amp; premium)
 - vdu - (versal ai)

SOC_VARIANT_ARCH and SOC_FAMILY_ARCH are now obsolete and replaced by
MACHINE_ARCH.  This is based on the guideline that any recipes that use
MACHINE_FEATURES should be MACHINE_ARCH specific.

Signed-off-by: Mark Hatle &lt;mark.hatle@amd.com&gt;
</content>
</entry>
<entry>
<title>boot-jtag.py: Add devtool script for jtag boot mode</title>
<updated>2024-03-15T18:08:07+00:00</updated>
<author>
<name>Sandeep Gundlupet Raju</name>
<email>sandeep.gundlupet-raju@amd.com</email>
</author>
<published>2024-03-13T01:20:24+00:00</published>
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<id>urn:sha1:3a9cd6df2cda6e502c2e4556303ef77006d8387a</id>
<content type='text'>
This script uses devtool and creates a boot-jtag.tcl script in
${DEPLOY_DIR_IMAGE} directory. This script is executed by xsdb tool to
boot yocto generated images on HW via jtag boot mode.

Signed-off-by: Sandeep Gundlupet Raju &lt;sandeep.gundlupet-raju@amd.com&gt;
Signed-off-by: Mark Hatle &lt;mark.hatle@amd.com&gt;
</content>
</entry>
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