linux/meta-xilinx.git/meta-xilinx-bsp/conf/machine/cortexr5-zynqmp.conf, branch masterMirror of git.yoctoproject.org/meta-xilinx.githttps://git.enea.com/cgit/linux/meta-xilinx.git/atom?h=master2021-07-14T21:48:56+00:00Reorganize the various layer components2021-07-14T21:48:56+00:00Mark Hatlemark.hatle@kernel.crashing.org2021-01-23T22:35:15+00:00urn:sha1:40d304b9534ce9912f9027c14bf97842daccb4ad
Machines: Move baremetal machines to meta-xilinx-standalone
Layers:
- Add new meta-xilinx-standalone-experimental
This layer may require components that may not yet be available to the
general public. It will contain various experiemntal integration work.
- meta-xilinx-standalone
This layer should be functional and contain the necessary items to build a
baremetal toolchain that can use libxil (replacement to libgloss) from
the Xilinx embeddedsw components. (Note, libxil is NOT built as part of
this work!)
The layer also contains the buildable components for the various firmware
components required to startup various Xilinx FPGAs.
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
meta-xilinx-bsp: Adjust soc to permit multiple CPU/TUNES2020-03-13T16:43:43+00:00Mark Hatlemark.hatle@xilinx.com2020-03-10T21:40:04+00:00urn:sha1:6d20c4c6829d8a0a324e3c3e6a92590ad39e5f14
The various Xilinx FPGAs may have more then one CPU type including
cortexr5, microblaze and regular ARM Cortex CPUs.
Adding a new soc-tune-include.inc will allow the machine to choose a
default tune, and then the correct matching tune will be loaded.
In a perfect world this wouldn't be required, but doing it this way
permits us to target specific optimizations or CPUs in the soc.
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
cortex-r5: Add cortexr5f configuration2020-02-27T16:33:25+00:00Mark Hatlemark.hatle@xilinx.com2020-02-19T23:52:40+00:00urn:sha1:4dcc7db95f05567c167d2f00c747fbed8e26063f
cortexr5f includes vfp3-d16 support. Enable this and hard float.
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
cortexr5-zynqmp.conf: Include the tune inc file from the correct path2020-02-13T22:42:32+00:00Alejandro Enedino Hernandez Samaniegoalejandr@xilinx.com2020-02-12T00:55:30+00:00urn:sha1:a5f9380f1cda1de78894d11c5fa9f7f5ef6f883a
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
Fix arm cortex r/m profiles2020-02-05T15:31:47+00:00Mark Hatlemark.hatle@xilinx.com2020-02-05T15:31:42+00:00urn:sha1:31d30af45d9ff86e557139a1123238524ddacf33
As part of the merge of the code bases, changes were introduced that
changed the way the cortexr5 was defined. To sync this between the
baremetal compilation and the baremetal toolchain compilation we
create a new armrm tune file, define a new tune feature of 'armrm',
define 'armrm' as a new machine override based on the feature 'armrm',
and move the cortexr5 tuning to a common file.
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
meta-xilinx-bsp: Unify machine confs2020-01-31T00:16:59+00:00Alejandro Enedino Hernandez Samaniegoalejandr@xilinx.com2020-01-31T00:16:59+00:00urn:sha1:7c6ee7c2e9c9e45bb7e9480b50cd61dc009d530d
Unify the meta-xilinx-bsp and meta-xilinx-standalone layers
by moving the machine confs to the BSP layer and keeping the
standalone layer as a DISTRO layer
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>