linux/meta-xilinx.git/meta-xilinx-bsp/conf/machine/cortexa72-versal.conf, branch masterMirror of git.yoctoproject.org/meta-xilinx.githttps://git.enea.com/cgit/linux/meta-xilinx.git/atom?h=master2021-07-14T21:48:56+00:00Reorganize the various layer components2021-07-14T21:48:56+00:00Mark Hatlemark.hatle@kernel.crashing.org2021-01-23T22:35:15+00:00urn:sha1:40d304b9534ce9912f9027c14bf97842daccb4ad
Machines: Move baremetal machines to meta-xilinx-standalone
Layers:
- Add new meta-xilinx-standalone-experimental
This layer may require components that may not yet be available to the
general public. It will contain various experiemntal integration work.
- meta-xilinx-standalone
This layer should be functional and contain the necessary items to build a
baremetal toolchain that can use libxil (replacement to libgloss) from
the Xilinx embeddedsw components. (Note, libxil is NOT built as part of
this work!)
The layer also contains the buildable components for the various firmware
components required to startup various Xilinx FPGAs.
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
meta-xilinx-bsp: Adjust soc to permit multiple CPU/TUNES2020-03-13T16:43:43+00:00Mark Hatlemark.hatle@xilinx.com2020-03-10T21:40:04+00:00urn:sha1:6d20c4c6829d8a0a324e3c3e6a92590ad39e5f14
The various Xilinx FPGAs may have more then one CPU type including
cortexr5, microblaze and regular ARM Cortex CPUs.
Adding a new soc-tune-include.inc will allow the machine to choose a
default tune, and then the correct matching tune will be loaded.
In a perfect world this wouldn't be required, but doing it this way
permits us to target specific optimizations or CPUs in the soc.
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
cortexa53-zynqmp/cortexa72-versal: Fix cortex based BSPs2020-03-09T20:13:10+00:00Mark Hatlemark.hatle@xilinx.com2020-03-07T03:37:28+00:00urn:sha1:bbdc313355338c1eae3e914eab74fe9cec6dc8f2
The BSPs had defined their own internal tunes. Instead use the yocto
project default tunes.
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
meta-xilinx-standalone: Add support for cortexa72 processor2020-02-27T16:33:25+00:00Appana Durga Kedareswara raoappana.durga.rao@xilinx.com2020-01-20T16:20:03+00:00urn:sha1:5add1de35e0cca572f746a3222d156932f0abf9b
This patch updates the COMPATIBLE_HOST and COMPATIBLE_MACHINE
and DTBFILE variables to compile esw use cases for cortexa72 processor.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
meta-xilinx-bsp: Unify machine confs2020-01-31T00:16:59+00:00Alejandro Enedino Hernandez Samaniegoalejandr@xilinx.com2020-01-31T00:16:59+00:00urn:sha1:7c6ee7c2e9c9e45bb7e9480b50cd61dc009d530d
Unify the meta-xilinx-bsp and meta-xilinx-standalone layers
by moving the machine confs to the BSP layer and keeping the
standalone layer as a DISTRO layer
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>