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<title>linux/meta-xilinx.git/conf, branch master</title>
<subtitle>Mirror of git.yoctoproject.org/meta-xilinx.git</subtitle>
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<updated>2017-12-14T00:11:14+00:00</updated>
<entry>
<title>meta-xilinx: Restructuring meta-xilinx to support multiple layers</title>
<updated>2017-12-14T00:11:14+00:00</updated>
<author>
<name>Manjukumar Matha</name>
<email>manjukumar.harthikote-matha@xilinx.com</email>
</author>
<published>2017-12-07T00:06:35+00:00</published>
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<id>urn:sha1:a18947c20dba2c0c38db8bde1ad4684995df4bbd</id>
<content type='text'>
As discussed previously on mailing list, we are proceeding with layer
restructuring. For rocko release we will have the following layers

meta-xilinx
        -&gt;meta-xilinx-bsp (current meta-xilinx)
        -&gt;meta-xilinx-contrib

In the subsequent releases we will add other layers from Xilinx
meta-xilinx
        -&gt;meta-xilinx-bsp (current meta-xilinx)
        -&gt;meta-petalinux
        -&gt;meta-xilinx-tools
        -&gt;meta-xilinx-contrib

This will provide one clone to get all the required meta layers from
Xilinx for a complete solution, and the users can blacklist any layer
which they don't want to use using bblayer.conf.
This will enables us to help our vendors/partners to add their reference
designs, board definitions etc.

Recipe changes :
 * Move reference design zybo-linux-bd.bb to meta-xilinx-contrib
 * Move kernel patches realted to zybo-linux-bd-zynq7 board to
   meta-xilinx-contrib
 * Update README

Signed-off-by: Manjukumar Matha &lt;manjukumar.harthikote-matha@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arch-microblaze.inc: Add 'frequency-optimized' tune</title>
<updated>2017-12-06T23:45:16+00:00</updated>
<author>
<name>Nathan Rossi</name>
<email>nathan@nathanrossi.com</email>
</author>
<published>2017-11-24T13:28:00+00:00</published>
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<id>urn:sha1:6ddc5873b0ede30e6542f0ab151a6236acc37944</id>
<content type='text'>
With MicroBlaze v10.0 an additional AREA_OPTIMIZED value of 2 was added
named Frequency. This optimization adds additional pipeline stages, and
code can be optimized differently to achieve better tuned performance
for these targets.

The '-mxl-frequency' flag has been added to GCC (not in mainline) to
enable specific tune optimizations for CPUs configured this way.

Whilst this tune does not change any ABI the addition of the 'fo'
package arch flag is added to allow for building both target optimized
and un-optimized without mixing packages.

Signed-off-by: Nathan Rossi &lt;nathan@nathanrossi.com&gt;
Signed-off-by: Manjukumar Matha &lt;manjukumar.harthikote-matha@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arch-microblaze.inc: Add v10.0 conflict for bigendian</title>
<updated>2017-12-06T23:45:16+00:00</updated>
<author>
<name>Nathan Rossi</name>
<email>nathan@nathanrossi.com</email>
</author>
<published>2017-11-24T13:28:00+00:00</published>
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<id>urn:sha1:f408be5a95881803fb9b84babf122b42a3d853a0</id>
<content type='text'>
As of v10.0 MicroBlaze is no longer configurable as a bigendian CPU.
This change prevents the ability to configure the tunes of a MicroBlaze
machine with v10.0 and bigendian.

Signed-off-by: Nathan Rossi &lt;nathan@nathanrossi.com&gt;
Signed-off-by: Manjukumar Matha &lt;manjukumar.harthikote-matha@xilinx.com&gt;
</content>
</entry>
<entry>
<title>feature-microblaze-versions.inc: Rework and expand version conflicts</title>
<updated>2017-12-06T23:45:16+00:00</updated>
<author>
<name>Nathan Rossi</name>
<email>nathan@nathanrossi.com</email>
</author>
<published>2017-11-24T13:28:00+00:00</published>
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<id>urn:sha1:0f891fdd02753e86bf02123b43043b12f7582569</id>
<content type='text'>
This change removes the use of the python function to expand the
TUNECONFLICTS definitions for version tunes. Instead this is replaced
with hardcoded definitions. This is preferred due to reduced complexity
of the python code as well as streamlining the include, this is also
done to make the includes align better with expectations of tune
includes in OE-Core.

This change also moves the version conflicts for the reorder tune into
arch-microblaze.

Additional documentation is added to cover details of MicroBlaze CPU
versions, and the change between different version formats.

Signed-off-by: Nathan Rossi &lt;nathan@nathanrossi.com&gt;
Signed-off-by: Manjukumar Matha &lt;manjukumar.harthikote-matha@xilinx.com&gt;
</content>
</entry>
<entry>
<title>kc705-microblazeel: Updates to match v2017.3 bitstream</title>
<updated>2017-12-06T23:45:16+00:00</updated>
<author>
<name>Nathan Rossi</name>
<email>nathan@nathanrossi.com</email>
</author>
<published>2017-11-24T13:28:00+00:00</published>
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<id>urn:sha1:b86a915ae0129ad699eaa9ce7e4929591e093bf6</id>
<content type='text'>
Update the device tree and machine configuration to match the updated
bitstream.

The bitstream was updated to v10.0 of the MicroBlaze core although
mainline GCC does not currently support v10.0+. Additionally the design
now enables divide-hard feature support. Memory and device addresses are
unchanged.

Signed-off-by: Nathan Rossi &lt;nathan@nathanrossi.com&gt;
Signed-off-by: Manjukumar Matha &lt;manjukumar.harthikote-matha@xilinx.com&gt;
</content>
</entry>
<entry>
<title>conf/machine: Add virtual/boot-bin dependency and set provider</title>
<updated>2017-12-04T22:24:31+00:00</updated>
<author>
<name>Nathan Rossi</name>
<email>nathan@nathanrossi.com</email>
</author>
<published>2017-12-03T09:03:12+00:00</published>
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<id>urn:sha1:d88df6fc0ef6be2ffc7edb65258060ac51bbee89</id>
<content type='text'>
Add virtual/boot-bin to EXTRA_IMAGEDEPENDS for all Zynq and ZynqMP
targets that use the deployed boot.bin from U-Boot.

Set the default provider for virtual/boot-bin to the current
virtual/bootloader provider. This handles the differing
u-boot/u-boot-xlnx defaults and also sets up the default provider for
consumers of machine-xilinx-default.inc.

Signed-off-by: Nathan Rossi &lt;nathan@nathanrossi.com&gt;
Signed-off-by: Manjukumar Matha &lt;manjukumar.harthikote-matha@xilinx.com&gt;
</content>
</entry>
<entry>
<title>pmu-firmware: Fix the pmu-firmware provider</title>
<updated>2017-11-29T13:02:49+00:00</updated>
<author>
<name>Manjukumar Matha</name>
<email>manjukumar.harthikote-matha@xilinx.com</email>
</author>
<published>2017-11-28T23:02:37+00:00</published>
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<id>urn:sha1:32f5af1f1d77c7be4dbd615bd589aedf6e79ca45</id>
<content type='text'>
Fix the issue while switching between different pmu-firmware providers

Signed-off-by: Manjukumar Matha &lt;manjukumar.harthikote-matha@xilinx.com&gt;
Signed-off-by: Nathan Rossi &lt;nathan@nathanrossi.com&gt;
</content>
</entry>
<entry>
<title>zc706-zynq7: Add runqemu support</title>
<updated>2017-11-29T13:02:30+00:00</updated>
<author>
<name>Alistair Francis</name>
<email>alistair.francis@xilinx.com</email>
</author>
<published>2017-11-21T19:10:54+00:00</published>
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<id>urn:sha1:1457dbfd4f47862ea6e60095a0be56e9dbb75a63</id>
<content type='text'>
Add support for both mainline and Xilinx's QEMU.

Signed-off-by: Alistair Francis &lt;alistair.francis@xilinx.com&gt;
Signed-off-by: Nathan Rossi &lt;nathan@nathanrossi.com&gt;
</content>
</entry>
<entry>
<title>zc702-zynq7: Add runqemu support</title>
<updated>2017-11-29T13:01:44+00:00</updated>
<author>
<name>Alistair Francis</name>
<email>alistair.francis@xilinx.com</email>
</author>
<published>2017-11-21T19:10:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-xilinx.git/commit/?id=008592e13e9af3195450d6216bbc6eb6170a2e48'/>
<id>urn:sha1:008592e13e9af3195450d6216bbc6eb6170a2e48</id>
<content type='text'>
Add support for both mainline and Xilinx's QEMU.

Signed-off-by: Alistair Francis &lt;alistair.francis@xilinx.com&gt;
Signed-off-by: Nathan Rossi &lt;nathan@nathanrossi.com&gt;
</content>
</entry>
<entry>
<title>zcu102-zynqmp: Setup runqemu to boot from an SD image</title>
<updated>2017-11-21T19:19:00+00:00</updated>
<author>
<name>Nathan Rossi</name>
<email>nathan@nathanrossi.com</email>
</author>
<published>2017-11-14T13:15:23+00:00</published>
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<id>urn:sha1:d6aaa8a9406e1b2b1545c804fd64807543fa6808</id>
<content type='text'>
This sets up the zcu102-zynqmp machine to by default generate a padded
SD card image for which runqemu can use to boot from. This image
includes all the components that are expected from to boot and mirrors
the same requirements that the real board has.

The QEMU args are changed to default to the SD boot mode and only U-Boot
SPL is passed in as a ROM image to boot the QEMU instance.

This setup mimics the boot flow of the physical target where the Boot
ROM loads U-Boot SPL and the PMU Firmware from the boot.bin.

Signed-off-by: Nathan Rossi &lt;nathan@nathanrossi.com&gt;
Signed-off-by: Manjukumar Matha &lt;manjukumar.harthikote-matha@xilinx.com&gt;
</content>
</entry>
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