From 3d2f6026b75fe6fdf6550342e91a24a93c9ebd1b Mon Sep 17 00:00:00 2001 From: Bruce Ashfield Date: Wed, 3 Jun 2026 02:21:37 +0000 Subject: lopper: update to v1.4.2-tip Bumping lopper to version v1.4.2-23-g0c3cfa9, which comprises the following commits: 0c3cfa9 lopper: assists: zephyr: Drop bootph-all property from generated domain DTS fdc4cea tests: regression coverage for domain-to-domain /axi node survival ee83fa1 tests: regression coverage for child_nodes deserialization in overlays 86fa315 tree: coerce comment prop values in resolve() to handle libfdt variants 3263e49 lopper: narrow is_overlay_file() to true /plugin/; overlays 180c06d overlay: store fixup refs as (label, rel_path) tuples, not abs_paths f484b0d overlay: defer phandle resolution to build time via _resolve_overlay_fixups cbbc26e lopper:assists:baremetal_xparameters_xlnx: Refactor DDRMC5 property extraction to use target node instead of axi_noc2 nodes 3dbcf83 base: phandle_safe_name: replace all invalid label characters 79b7c0e lopper:assist:baremetal_validate_comp_xlnx: Fix srec_spi_bootloader build failure on Spartan US+ OSPI-enabled design fe54df3 assists: xlnx_overlay_pl_dt: Move amba_pl to amba rename after overlay tree construction f3e0808 Add per-hart interrupts for RISCV b7c6fd6 overlay: fix child_nodes deserialization in multi-pass lopper invocations b2a5280 Revert "lopper:assists:baremetallinker_xlnx: Fix default DDR selection for Microblaze RISC-V to prefer BRAM" ae0f2da gen_domain_dts: Add riscv,timer node generation 59b00b5 lopper:assists:baremetallinker_xlnx: Fix default DDR selection for Microblaze RISC-V to prefer BRAM 612ebb1 lopper:assists:baremetal_xparameters_xlnx: Add DDRMC5_I2C_MASTER and DDRMC5_DEBUG_ELF defines 49a6270 baremetalconfig_xlnx: fix clocks single-cell offset; optional prop first int 0f0b55b baremetal: Add lpddrmc to valid memory IP list 375bcee lopper: assists: zephyr: Fix UFS clock-name and clocks assignment 008897f lopper: assists: xlnx_overlay_pl_dt: exclude address-map property from overlay 9fc81f9 lops/%.yaml.lop: register OpenAMP domain-to-domain phandle properties a046513 domain_access: fix step 2c to scan full subnode depth and mark parent chain Signed-off-by: Bruce Ashfield --- recipes-kernel/lopper/lopper_git.bb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/recipes-kernel/lopper/lopper_git.bb b/recipes-kernel/lopper/lopper_git.bb index 0099e3bd..afee3fbe 100644 --- a/recipes-kernel/lopper/lopper_git.bb +++ b/recipes-kernel/lopper/lopper_git.bb @@ -4,9 +4,9 @@ LICENSE = "BSD-3-Clause" SECTION = "bootloader" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "b3ef9742752d836f7930c9415e3a7bec2e711478" +SRCREV = "0c3cfa9f5fc739f3e429330521b4a3c5cdd66563" -BASEVERSION = "1.0.2" +BASEVERSION = "1.4.2" PV = "v${BASEVERSION}+git" PYPA_WHEEL = "${PIP_INSTALL_DIST_PATH}/${BPN}-${BASEVERSION}-*.whl" -- cgit v1.2.3-54-g00ecf