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<title>linux/meta-intel.git/recipes-core, branch honister</title>
<subtitle>[no description]</subtitle>
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<updated>2022-08-19T01:29:45+00:00</updated>
<entry>
<title>intel-microcode: upgrade 20220510 -&gt; 20220809</title>
<updated>2022-08-19T01:29:45+00:00</updated>
<author>
<name>Anuj Mittal</name>
<email>anuj.mittal@intel.com</email>
</author>
<published>2022-08-12T02:21:04+00:00</published>
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<id>urn:sha1:75db9e135d53b070366cd0beecefd72e4cf135fd</id>
<content type='text'>
Fixes CVE-2022-21233.

Release notes:
https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20220809

Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
(cherry picked from commit 0f6e10d5ba47c4695ebf5d92599a82e84f0cf3b0)
Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
</content>
</entry>
<entry>
<title>intel-microcode: update SRCREV for 20220510</title>
<updated>2022-08-19T01:28:41+00:00</updated>
<author>
<name>Yongxin Liu</name>
<email>yongxin.liu@windriver.com</email>
</author>
<published>2022-08-10T07:47:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=d12fead20e0d5e0199d81bd7991d7e335b04e554'/>
<id>urn:sha1:d12fead20e0d5e0199d81bd7991d7e335b04e554</id>
<content type='text'>
The commit 6c0c4691e5bb446e0e428ebca595164709c59586 is missing in upstream
https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.

Reference:
https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/62.

Use 925555515555 instead of 6c0c4691e5bb. The difference between those
two commits are just some "^M" fixes in releasenote.md.

Signed-off-by: Yongxin Liu &lt;yongxin.liu@windriver.com&gt;
Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
(cherry picked from commit a29a3b55d21b242aaaafaaa0ef096ab592bf9774)
Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
</content>
</entry>
<entry>
<title>intel-microcode: upgrade 20220419 -&gt; 20220510</title>
<updated>2022-05-19T04:19:23+00:00</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovidiu.panait@windriver.com</email>
</author>
<published>2022-05-17T10:51:05+00:00</published>
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<id>urn:sha1:3650830a91623c00365207f2413e006d2f47831c</id>
<content type='text'>
intel-microcode-20220510 includes fixes for CVE-2021-33117 and CVE-2022-21151.

CVE-2021-33117:
A potential security vulnerability in some 3rd Generation Intel® Xeon® Scalable
Processors may allow information disclosure. Intel is releasing firmware
updates to mitigate this potential vulnerability.

https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00586.html

CVE-2022-21151:
A potential security vulnerability in some Intel® Processors may allow
information disclosure. Intel is releasing firmware updates to mitigate this
potential vulnerability.

https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00617.html

Signed-off-by: Ovidiu Panait &lt;ovidiu.panait@windriver.com&gt;
Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
(cherry picked from commit e26d271f1161a9a7256a0eac6de26fdf4601066e)
Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
</content>
</entry>
<entry>
<title>intel-microcode: upgrade 20220207 -&gt; 20220419</title>
<updated>2022-05-19T04:19:23+00:00</updated>
<author>
<name>Naveen Saini</name>
<email>naveen.kumar.saini@gmail.com</email>
</author>
<published>2022-05-06T09:55:09+00:00</published>
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<id>urn:sha1:ddb9b4dcde5a6a5dff104b0197e2ad09306b66e9</id>
<content type='text'>
Signed-off-by: Naveen Saini &lt;naveen.kumar.saini@intel.com&gt;
Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
(cherry picked from commit 6c9d750d7defcbb250a16f530b45302bce72ec46)
Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
</content>
</entry>
<entry>
<title>zlib: fix CVE-2018-25032</title>
<updated>2022-04-05T05:53:26+00:00</updated>
<author>
<name>Chee Yang Lee</name>
<email>chee.yang.lee@intel.com</email>
</author>
<published>2022-04-01T10:00:12+00:00</published>
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<id>urn:sha1:daf5c125a744d45d8fa395b576147edd5a714f5c</id>
<content type='text'>
CVE-2018-25032 fixes at oe-core causing fuzz and build error,
backport the patch with fuzz fixed and another patch to fix build error.

Signed-off-by: Chee Yang Lee &lt;chee.yang.lee@intel.com&gt;
Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
</content>
</entry>
<entry>
<title>zlib: override SRC_URI</title>
<updated>2022-04-05T05:53:26+00:00</updated>
<author>
<name>Chee Yang Lee</name>
<email>chee.yang.lee@intel.com</email>
</author>
<published>2022-04-01T10:00:11+00:00</published>
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<id>urn:sha1:a9fa3b1c452a867c203a16ef98d15b5b496a4f6f</id>
<content type='text'>
Signed-off-by: Chee Yang Lee &lt;chee.yang.lee@intel.com&gt;
Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
</content>
</entry>
<entry>
<title>intel-microcode: upgrade 20210608 -&gt; 20220207</title>
<updated>2022-03-02T23:10:50+00:00</updated>
<author>
<name>Anuj Mittal</name>
<email>anuj.mittal@intel.com</email>
</author>
<published>2022-02-09T02:36:55+00:00</published>
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<id>urn:sha1:fb9e0633614dbf956da185d291333bcc1b137e5a</id>
<content type='text'>
Also fixes CVE-2021-0146, CVE-2021-0127. More details:

https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20220207

Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
</content>
</entry>
<entry>
<title>meta: add explicit branch and protocol to SRC_URI</title>
<updated>2021-11-08T01:07:23+00:00</updated>
<author>
<name>Anuj Mittal</name>
<email>anuj.mittal@intel.com</email>
</author>
<published>2021-11-02T23:23:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=6fa578ecfebe308eee5c12c37829593482892968'/>
<id>urn:sha1:6fa578ecfebe308eee5c12c37829593482892968</id>
<content type='text'>
Add branch name explicitly to SRC_URI where it's not defined and switch
to using https protocol for Github projects.

The change was made using convert_srcuri script for OE-Core.

Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
(cherry picked from commit e4d0c52cba29298b32f97651412a7b28130d8beb)
Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
</content>
</entry>
<entry>
<title>Manually move some overrides to new syntax</title>
<updated>2021-08-06T07:51:53+00:00</updated>
<author>
<name>Anuj Mittal</name>
<email>anuj.mittal@intel.com</email>
</author>
<published>2021-08-06T03:23:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=e67676976b73b004eb293615edeb687b05013a17'/>
<id>urn:sha1:e67676976b73b004eb293615edeb687b05013a17</id>
<content type='text'>
Some of these were missed when using the script and were noticed when
building intel-skylake-64 and tiny images  which had started failing.

Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
</content>
</entry>
<entry>
<title>Convert to new override syntax</title>
<updated>2021-07-31T09:47:03+00:00</updated>
<author>
<name>Anuj Mittal</name>
<email>anuj.mittal@intel.com</email>
</author>
<published>2021-07-31T09:47:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=0584f638797a816b29b909d4611d5a099df7bbc1'/>
<id>urn:sha1:0584f638797a816b29b909d4611d5a099df7bbc1</id>
<content type='text'>
Use the convert-overrides.py to convert to new syntax and manually
fix some additional changes.

Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
</content>
</entry>
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