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<title>linux/meta-intel.git/meta-sys940x/recipes-bsp, branch master</title>
<subtitle>[no description]</subtitle>
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<updated>2014-03-27T03:41:49+00:00</updated>
<entry>
<title>Remove chiefriver, sys940x &amp; n450 BSPs</title>
<updated>2014-03-27T03:41:49+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-03-12T19:12:32+00:00</published>
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<id>urn:sha1:8d79fb4e0cec07fe05ca440578414eaa6be80a3a</id>
<content type='text'>
Configuration for the chiefriver, sys940x, sys940x-noemgd, n450 BSPs are
deleted. The consolidated BSPs viz intel-corei7-64 and intel-core2-32
support these boards.

As part of the usual retirement process, a heads-up email was sent to the
meta-intel mailing list requesting any feedback regarding retirement of
these BSPs. The community did not had any concerning feedback to
reconsider the retirement decision.

The MAINTAINERS file and the layer version of the meta-intel layer are
updated to reflect removal of the BSPs.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
CC: Darren Hart &lt;dvhart@linux.intel.com&gt;
Reviewed-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>Update after toplevel LICENSE file checksum change</title>
<updated>2014-01-02T16:46:30+00:00</updated>
<author>
<name>Richard Purdie</name>
<email>richard.purdie@linuxfoundation.org</email>
</author>
<published>2014-01-02T16:46:27+00:00</published>
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<id>urn:sha1:2be655a691b3a5f698113ed77d3fac6b16ea5337</id>
<content type='text'>
The top level LICENSE file in OE-Core changed so we need to update the checksum
references that refer to this to match the new file.

Signed-off-by: Richard Purdie &lt;richard.purdie@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>meta-intel: Drop PRINC usage</title>
<updated>2013-06-24T13:55:59+00:00</updated>
<author>
<name>Richard Purdie</name>
<email>richard.purdie@linuxfoundation.org</email>
</author>
<published>2013-06-24T13:45:01+00:00</published>
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<id>urn:sha1:c5a0c81e49e74fc5ddccb43dd8d3d89312389c44</id>
<content type='text'>
With the switch to the PR server we don't need to use PRINC. This
patch matches a change to OE-Core to bump the PR values of the appropriate
core recipes so PR values don't go backwards.

Signed-off-by: Richard Purdie &lt;richard.purdie@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Fix use of PRINC in meta-intel BSPs</title>
<updated>2012-10-09T23:04:30+00:00</updated>
<author>
<name>Darren Hart</name>
<email>dvhart@linux.intel.com</email>
</author>
<published>2012-10-09T22:07:14+00:00</published>
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<id>urn:sha1:5d8a05811101f7d69994f4028ec620c4480f6da4</id>
<content type='text'>
Replaces all uses of PRINC with the form:

PRINC := "${@int(PRINC) + N}"

Where N is the previously assigned value plus one to ensure a
monotonically increasing PRINC value.

Signed-off-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
Acked-by: Tom Zanussi &lt;tom.zanussi@intel.com&gt;
CC: Saul Wold &lt;sgw@linux.intel.com&gt;
CC: Nitin Kamble &lt;nitin.a.kamble@intel.com&gt;
</content>
</entry>
<entry>
<title>genmac: Replace RANDOM_MAC in network/interfaces with a randomly generated MAC</title>
<updated>2012-02-03T17:25:18+00:00</updated>
<author>
<name>Darren Hart</name>
<email>dvhart@linux.intel.com</email>
</author>
<published>2012-01-26T18:39:01+00:00</published>
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<id>urn:sha1:c42364375acb28f0f23867e3a24c9ae25beced37</id>
<content type='text'>
For machines that do not have a MAC in hardware and with drivers that don't
generate a random one in the kernel, this init script will replace the string
RANDOM_MAC in the network/interfaces file with one generated with "ranpwd -m".
Care is taken to ensure multiple interfaces can use RANDOM_MAC and receive
unique addresses. ranpwd generates MACs with the locally administered bit set
and the multicast bit disabled.

Signed-off-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
Signed-off-by: Joshua Lock &lt;josh@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>meta-intel: Add Inforce SYS940x BSP</title>
<updated>2012-02-03T17:25:17+00:00</updated>
<author>
<name>Darren Hart</name>
<email>dvhart@linux.intel.com</email>
</author>
<published>2012-01-23T23:46:07+00:00</published>
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<id>urn:sha1:6aad7407464ec9cc807916b71068fdae323bfcd1</id>
<content type='text'>
The Inforce SYS940x-ECX Developer-Ready Reference Platform features:
o Intel Atom E6xx (0.6-1.6 GHz)
o Up to 1GB on-board DDR2
o Intel Platform Controller Hub EG20T
o VGA,LVDS
o HD Audio
o SD Card
o Dual SATA
o Mini-PCIe

http://www.inforcecomputing.com/SYS940X_ECX.html

Signed-off-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
</content>
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