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<title>linux/meta-intel.git/meta-emenlow, branch master-enea</title>
<subtitle>[no description]</subtitle>
<id>https://git.enea.com/cgit/linux/meta-intel.git/atom?h=master-enea</id>
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<updated>2015-08-28T21:25:29+00:00</updated>
<entry>
<title>Remove older platform specific BSPs</title>
<updated>2015-08-28T21:25:29+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2015-08-25T23:39:01+00:00</published>
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<id>urn:sha1:4172351baa285b83eb54d54368fe2f037c48159b</id>
<content type='text'>
The intel-core* BSPs supercede these older BSPs therefore it's time
to remove these older platform specific bsps.

Bump LAYERVERSION to 3 to allow the Autobuilder to know that these
BSPs have been removed.

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>bsps: update meta SRCREVs</title>
<updated>2015-07-28T20:43:13+00:00</updated>
<author>
<name>Bruce Ashfield</name>
<email>bruce.ashfield@windriver.com</email>
</author>
<published>2015-07-23T22:00:31+00:00</published>
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<id>urn:sha1:b88b9629f7c02a6bf27d96577cb725077c711c50</id>
<content type='text'>
Now that the BSP meta data comes from a separate git repository, we
need to update the meta SRCREVs to ones that are valid in that tree
(the previous REVs are only valid in a linux-yocto meta branch).

Signed-off-by: Bruce Ashfield &lt;bruce.ashfield@windriver.com&gt;
Signed-off-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>linux-yocto: Update BSP to latest meta and branch SRCREV</title>
<updated>2015-04-15T18:15:03+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2015-04-15T15:08:25+00:00</published>
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<id>urn:sha1:e5de92902200d7a60ba4b5531efcd8fc9535367f</id>
<content type='text'>
Do the SRCREV update to the latest versions of linux-yocto to match
the fido release, this removes warnings that where noted during the
first round of 3.19.

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
Signed-off-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>MAINTAINERS: Update Maintainer to show Saul replaces Nitin</title>
<updated>2015-03-13T21:54:08+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2015-03-02T15:43:37+00:00</published>
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<id>urn:sha1:e80db2307aeb055c93a22f64dbfc09cc9d2297fc</id>
<content type='text'>
Saul will be the point of contact for core Intel BSPs

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
Signed-off-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>meta-emenlow: remove kernel 3.10 bbappend</title>
<updated>2015-02-20T21:32:33+00:00</updated>
<author>
<name>Ross Burton</name>
<email>ross.burton@intel.com</email>
</author>
<published>2015-02-20T20:17:39+00:00</published>
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<id>urn:sha1:b0928a6af0a9668f7b3c97ee9138e238ce5913e6</id>
<content type='text'>
Kernel 3.10 has been removed from oe-core so remove our bbappend.

Signed-off-by: Ross Burton &lt;ross.burton@intel.com&gt;
Signed-off-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>Prefer linux-yocto 3.19 for all Intel common architecture BSPs</title>
<updated>2015-02-20T21:32:33+00:00</updated>
<author>
<name>Darren Hart</name>
<email>dvhart@linux.intel.com</email>
</author>
<published>2015-02-20T21:18:09+00:00</published>
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<id>urn:sha1:21dd5b97465e70b56c20710db32edb6042fc412b</id>
<content type='text'>
Update all the BSPs using the Intel common architecture that preferred
3.17 to prefer 3.19, now built by the intel-core* common BSPs.

Signed-off-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>meta-emenlow: Update linux-yocto_3.14 SRCREVs to v3.14.19</title>
<updated>2014-10-22T14:51:44+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-10-21T21:59:41+00:00</published>
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<id>urn:sha1:002bef4c2a59e95503a2bb7729e7749cd5a9f65b</id>
<content type='text'>
Use the latest HEADs of the git branches from the linux-yocto v3.14
kernel repository.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>emenlow-noemgd: Add intel-ucode to MACHINE_FEATURES</title>
<updated>2014-10-21T19:40:39+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-09-17T20:46:04+00:00</published>
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<id>urn:sha1:0acec3ec4212c0ebf60a2dc216be261cc8407756</id>
<content type='text'>
Enable the Intel microcode feature for this BSP.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Acked-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>meta-emenlow: Update linux-yocto_3.10 SRCREVs to v3.10.55</title>
<updated>2014-10-21T17:09:59+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-10-16T22:13:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=03f827a381de5e3755fdf6381e13c4f16d096667'/>
<id>urn:sha1:03f827a381de5e3755fdf6381e13c4f16d096667</id>
<content type='text'>
Use the latest HEADs of the git branches from the linux-yocto v3.10
kernel repository.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>meta-emenlow: Use the v3.17 kernel by default for emenlow-noemgd</title>
<updated>2014-09-30T15:01:44+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-09-23T18:10:44+00:00</published>
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<id>urn:sha1:e69a58bc00a666df0c37e2caaba97f1166816237</id>
<content type='text'>
The linux-yocto_3.17 recipe is available for this BSP.  Make it the
default kernel for this BSP.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
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