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<title>linux/meta-intel.git/lib/oeqa/runtime/cases/cyclictest.py, branch hardknott</title>
<subtitle>[no description]</subtitle>
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<updated>2020-04-01T16:18:46+00:00</updated>
<entry>
<title>runtime/cyclictest: Enable cyclictest for image with rt kernel</title>
<updated>2020-04-01T16:18:46+00:00</updated>
<author>
<name>Yeoh Ee Peng</name>
<email>ee.peng.yeoh@intel.com</email>
</author>
<published>2020-04-01T06:50:33+00:00</published>
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<id>urn:sha1:9756afd47aa87593e382b8843337889ec7c31408</id>
<content type='text'>
Enable cyclictest:
 - test execute cyclictest, retrieve the maximum latency captured inside log and compare it to the
   target latency
 - cyclictest arguments based on public cyclictest arguments used for intel corei7
   https://www.osadl.org/Latency-plot-of-system-in-rack-9-slot.qa-latencyplot-r9s5.0.html?shadow=1
 - set default target latency based on 24 us (captured from public cyclictest execution) multiple
   by 1.2 (buffer)
 - enable user defined target latency by configuring 'RTKERNEL_TARGET_LATENCY' as bitbake config
   example, inside local.conf: RTKERNEL_TARGET_LATENCY = "25"

Signed-off-by: Yeoh Ee Peng &lt;ee.peng.yeoh@intel.com&gt;
Signed-off-by: Anuj Mittal &lt;anuj.mittal@intel.com&gt;
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