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<title>linux/meta-intel.git/conf, branch dizzy</title>
<subtitle>[no description]</subtitle>
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<updated>2014-10-21T20:50:37+00:00</updated>
<entry>
<title>intel-microcode: Add ability to filter microcode</title>
<updated>2014-10-21T20:50:37+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-10-01T01:23:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=a3a380373b3f47df90f0c585ce9b071f80b216c9'/>
<id>urn:sha1:a3a380373b3f47df90f0c585ce9b071f80b216c9</id>
<content type='text'>
The microcode data file released by Intel has microcode for many Intel
processors, which by default all get installed onto the target image.
In some situations it may desirable to choose microcode for only a
selected processor or processors.  This change provides an easier way
to filter and select only the microcode of interest for BSPs from
recipe space.

A new variable, UCODE_FILTER_PARAMETERS, is introduced, which can be
defined to contain parameters to the iucode_tool which will filter the
microcode of interest for the BSP under consideration.  More
information on the iucode-tool parameters is available here:
http://manned.org/iucode-tool.

This filtering makes the generated microcode files very
machine-specific, hence making the recipe machine-specific. BSPs using
the common Intel kernel will not be using the filtered microcode, and
will be able to share the intel-microcode packages with the common
Intel package arch for the recipe.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Acked-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>intel-corei7-64: Add intel-ucode to MACHINE_FEATURES</title>
<updated>2014-10-21T19:40:10+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-09-17T20:44:22+00:00</published>
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<id>urn:sha1:e5427e8e7573abc51d8908517551705e072271ae</id>
<content type='text'>
Enable the Intel microcode feature for this BSP.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Acked-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>intel-core2-32: Add intel-ucode to MACHINE_FEATURES</title>
<updated>2014-10-21T19:39:49+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-09-17T20:43:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=dd922d7cb225fbd794491ec0ef9df3c57a986f18'/>
<id>urn:sha1:dd922d7cb225fbd794491ec0ef9df3c57a986f18</id>
<content type='text'>
Enable the Intel microcode feature for this BSP.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Acked-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>meta-intel: Add new intel-ucode MACHINE_FEATURE</title>
<updated>2014-10-21T19:34:20+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-09-17T16:45:24+00:00</published>
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<id>urn:sha1:c64ade471ab70860604db2ade19ec6cfe9504f50</id>
<content type='text'>
With this change, Intel microcode support can be enabled or disabled
for any BSP by controlling the MACHINE_FEATURES variable.

Any BSP from the meta-intel layer can enable Intel microcode loading
support by adding the following line in the machine configuration.

  MACHINE_FEATURES += "intel-ucode"

This change keeps the intel-microcode feature disabled by default; it
can however be enabled as an "opt-in" feature via the MACHINE_FEATURES
variable.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>meta-intel.inc: Use LTSI kernel for poky-lsb images</title>
<updated>2014-10-21T17:28:13+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-10-16T22:17:02+00:00</published>
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<id>urn:sha1:c32b5938039830875e931340492cfd7dc6f57a77</id>
<content type='text'>
v3.10 is now the latest LTSI kernel.  Use it for all the poky-lsb
images, so that it gets validation in the QA cycles.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>layer.conf: Avoid conflicts with sub-layers</title>
<updated>2014-10-01T19:04:12+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-09-27T00:04:57+00:00</published>
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<id>urn:sha1:6702f5a00c414c68f6f6ceae46552bce571cf93f</id>
<content type='text'>
The layer priority is getting ignored because the same set of files
are visible in the meta-intel layer as well as any of its sub layers.

The layer pattern for recipe files is changed from "^${LAYERDIR}/" to
"^${LAYERDIR}/common" to stop unintentionally including the sub-layer
recipe files in the meta-intel layer.

Fixes Bug:
[YOCTO #6552]

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>intel-corei7-64: Use the v3.17 kernel by default</title>
<updated>2014-09-30T15:01:01+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-09-23T18:09:27+00:00</published>
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<id>urn:sha1:2033f399aa120eeed924e30ad3896a1f205b9730</id>
<content type='text'>
The linux-yocto_3.17 recipe is available for this BSP.  Make it the
default kernel for this BSP.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>intel-core2-32: Use the v3.17 kernel by default</title>
<updated>2014-09-30T15:01:01+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-09-23T18:07:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=d49bf442eb567580e7426a579c6ca34c9f980b68'/>
<id>urn:sha1:d49bf442eb567580e7426a579c6ca34c9f980b68</id>
<content type='text'>
The linux-yocto_3.17 recipe is available for this BSP.  Make it the
default kernel for this BSP.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>layer.conf: Bumping LAYERVERSION</title>
<updated>2014-09-18T23:35:54+00:00</updated>
<author>
<name>Elizabeth Flanagan</name>
<email>elizabeth.flanagan@intel.com</email>
</author>
<published>2014-09-18T22:12:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=a369fa8f2d76528cb296ef9314e613e26585d54d'/>
<id>urn:sha1:a369fa8f2d76528cb296ef9314e613e26585d54d</id>
<content type='text'>
As we've retired some BSPs we'll need to bump LAYERVERSION so
that the autobuilder does not fail out on them.

Signed-off-by: Elizabeth Flanagan &lt;elizabeth.flanagan@intel.com&gt;
Signed-off-by: Tom Zanussi &lt;tom.zanussi@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>intel-corei7-64.conf: include the AMT daemon in the images</title>
<updated>2014-09-18T16:35:21+00:00</updated>
<author>
<name>Nitin A Kamble</name>
<email>nitin.a.kamble@intel.com</email>
</author>
<published>2014-09-10T19:00:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=1a887e54300c764fff45d1714ec8b6cd32343299'/>
<id>urn:sha1:1a887e54300c764fff45d1714ec8b6cd32343299</id>
<content type='text'>
Some of the platforms supported by the intel-corei7-64 BSP have AMT feature
on the platform. Enable it so that it can get utilized with this BSP.

Signed-off-by: Nitin A Kamble &lt;nitin.a.kamble@intel.com&gt;
Acked-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
</content>
</entry>
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