<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/meta-intel.git/conf/machine/include/intel-quark-common.inc, branch warrior</title>
<subtitle>[no description]</subtitle>
<id>https://git.enea.com/cgit/linux/meta-intel.git/atom?h=warrior</id>
<link rel='self' href='https://git.enea.com/cgit/linux/meta-intel.git/atom?h=warrior'/>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/'/>
<updated>2017-12-08T23:04:46+00:00</updated>
<entry>
<title>intel-quark: Remove MACHINE configuration for Quark</title>
<updated>2017-12-08T23:04:46+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2017-12-08T14:54:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=5dbc69e339588834317b632119717996584b0d6c'/>
<id>urn:sha1:5dbc69e339588834317b632119717996584b0d6c</id>
<content type='text'>
As the Quark machine has been EOL'ed at the end of 2017, remove this
machine type from the 2018 planned release of meta-intel

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
Signed-off-by: California Sullivan &lt;california.l.sullivan@intel.com&gt;
</content>
</entry>
<entry>
<title>intel-quark-common: Add no-asm config to openssl</title>
<updated>2015-10-02T15:14:48+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2015-10-01T15:06:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=0d73402b4f350b8a11458c8b1e22ab927e0a015f'/>
<id>urn:sha1:0d73402b4f350b8a11458c8b1e22ab927e0a015f</id>
<content type='text'>
This causes the build to not use Assembly code which contains invalid
CMOV instructions.

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>intel-quark-common: disable padlock code</title>
<updated>2015-09-16T17:33:37+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2015-09-16T17:33:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=94890cec951bbf922326162823d2664cd0056ea0'/>
<id>urn:sha1:94890cec951bbf922326162823d2664cd0056ea0</id>
<content type='text'>
The padlock code is a subset of x86 hardware acceleration code. It uses
the cmov instruction which is invalid on Quark based hardware, so we
disable this code.

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>intel-quark: Introduce new BSP for Quark/X1000 SOC</title>
<updated>2015-07-08T17:26:08+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2015-07-08T17:26:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=2ff587659537dbdc31829739bcbb72731fab5ef9'/>
<id>urn:sha1:2ff587659537dbdc31829739bcbb72731fab5ef9</id>
<content type='text'>
This new BSP is for the Quark/X1000 and related series that need
the limited no-lock-prefix.

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
</content>
</entry>
</feed>
