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<title>linux/meta-intel.git/common, branch fido</title>
<subtitle>[no description]</subtitle>
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<updated>2016-02-12T22:53:32+00:00</updated>
<entry>
<title>linux-yocto: update SRCREVs to latest stable</title>
<updated>2016-02-12T22:53:32+00:00</updated>
<author>
<name>California Sullivan</name>
<email>california.l.sullivan@intel.com</email>
</author>
<published>2016-02-12T22:10:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=29a1746ea844e1d99571cbf5533f0ff581191b16'/>
<id>urn:sha1:29a1746ea844e1d99571cbf5533f0ff581191b16</id>
<content type='text'>
This also includes the fix to keyring leak CVE-2016-0728.

Signed-off-by: California Sullivan &lt;california.l.sullivan@intel.com&gt;
Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>linux-yocto_3.19: Update SRCREV to include driver update</title>
<updated>2015-06-12T21:56:50+00:00</updated>
<author>
<name>Chang Rebecca Swee Fun</name>
<email>rebecca.swee.fun.chang@intel.com</email>
</author>
<published>2015-06-11T08:57:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=28e8017ab8ba4f4d9e3fe5a5346bf31b3334bbbb'/>
<id>urn:sha1:28e8017ab8ba4f4d9e3fe5a5346bf31b3334bbbb</id>
<content type='text'>
Update SRCREV for linux-yocto-3.19 to include the following commits:

e152349 drm/i915: Reset CSB read pointer in ring init
a87a6ff drm/i915/bdw: Enable execlists by default where supported
6c21811 fs: aufs: fix a build error for archs which doesn't support MUTEX_SPIN_
f7e6e36 fs: yaffs2: kill f_dentry uses
2a5e3b1 intel_idle: Add support for the Airmont Core in the Cherrytrail and Bra
28c0578 intel_idle: Update support for Silvermont Core in Baytrail SOC
77bec57 intel_idle: Add -&gt;enter_freeze callbacks
ae682f3 intel_idle: support additional Broadwell model
3c88608 PM / sleep: Make it possible to quiesce timers during suspend-to-idle
cd240b6 PM / sleep: Re-implement suspend-to-idle handling
d3c0b95 drm/i915: New offset for reading frequencies on CHV.
dac6bab drm/i915/chv: Populate total EU count on Cherryview
a3f6f39 arm64: psci: move psci firmware calls out of line
374b5d0 drm/i915: Only wait for required lanes in vlv_wait_port_ready()
fca99e8 Revert "drm/i915: Hack to tie both common lanes together on chv"
00682f3 drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
654b1a4 drm/i915: Implement chv display PHY lane stagger setup

Signed-off-by: Chang Rebecca Swee Fun &lt;rebecca.swee.fun.chang@intel.com&gt;
Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>lttng-modules: add bbappend to address 3.19.5 update</title>
<updated>2015-05-12T20:12:10+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2015-05-11T20:46:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=f9738ec19d3b2864c0bd71b9bb3418d16e922a12'/>
<id>urn:sha1:f9738ec19d3b2864c0bd71b9bb3418d16e922a12</id>
<content type='text'>
The 3.19.5 kernel update included an incompatible change that caused lttng-modules
to fail to build, the patch needed to be rebased due to changes in the associated
Makefile.

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>linux-yocto_3.19: Update to the Intel i915 driver</title>
<updated>2015-05-11T18:18:41+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2015-05-11T18:18:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=afbba3222cb66c92d43e458330055f06380e29f0'/>
<id>urn:sha1:afbba3222cb66c92d43e458330055f06380e29f0</id>
<content type='text'>
0befa35 drm/i915/chv: Remove DPIO force latency causing interpair skew issue
184e037 drm/i915: Fix chv cdclk support
e2a99b9 drm/i915: Increase the range of sideband address.
9d5d55e drm/i915: Disable DDR DVFS on CHV
96cce94 drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV
b5005319 drm/i915: Program PFI credits for VLV
c7aa33e drm/i915: Rewrite VLV/CHV watermark code
a421d8b drm/i915: Make sure PND deadline mode is enabled on VLV/CHV
631afc9 drm/i915: Read out display FIFO size on VLV/CHV
e0dcdc0 drm/i915: Pass plane to vlv_compute_drain_latency()
a6a5562 drm/i915: Reorganize VLV DDL setup
bb662a4 drm/i915: Hide VLV DDL precision handling
3d2d932 drm/i915: Simplify VLV drain latency computation
f686147 drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines
86c658c drm/i915: Reduce CHV DDL multiplier to 16/8
8c4cdd9 drm/i915: Allow pixel clock up to 95% of cdclk on CHV
d9d4fb8 drm/i915: Reduce CHV DPLL min vco frequency to 4.8 GHz

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>linux-yocto: Update meta SRCREV for 3.14</title>
<updated>2015-05-08T18:24:43+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2015-05-08T18:24:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=1c807bdf9fc3e7ad323a4e244d0149559e6b5103'/>
<id>urn:sha1:1c807bdf9fc3e7ad323a4e244d0149559e6b5103</id>
<content type='text'>
This backports the various fixes for kernel configuration warning from
the 3.19 meta area

[YOCTO #7478]

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>xf86-video-mga: Upgrade 1.6.2 -&gt; 1.6.4</title>
<updated>2015-05-07T20:12:20+00:00</updated>
<author>
<name>Jussi Kukkonen</name>
<email>jussi.kukkonen@intel.com</email>
</author>
<published>2015-05-07T08:48:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=cac76011f9fae6bbf965758784199e6297db4db7'/>
<id>urn:sha1:cac76011f9fae6bbf965758784199e6297db4db7</id>
<content type='text'>
This update allows successfully building with xserver-xorg 1.17.

Signed-off-by: Jussi Kukkonen &lt;jussi.kukkonen@intel.com&gt;
Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>linux-yocto: Update v3.14 to 3.14.39</title>
<updated>2015-05-07T19:55:06+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2015-05-07T18:16:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=56471abb269f4fd8792aac4a299521324c8a05da'/>
<id>urn:sha1:56471abb269f4fd8792aac4a299521324c8a05da</id>
<content type='text'>
Update the 3.14 kernel to the lastest version available 3.14.39
in the linux-yocto repository.

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>linux-yocto: Update linux-yocto v3.19.2 SRCREV to v3.19.5</title>
<updated>2015-05-07T19:54:36+00:00</updated>
<author>
<name>Ng Wei Tee</name>
<email>wei.tee.ng@intel.com</email>
</author>
<published>2015-05-06T02:51:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=09f27d003293611900c421c3016f484ffc4cb856'/>
<id>urn:sha1:09f27d003293611900c421c3016f484ffc4cb856</id>
<content type='text'>
Use the latest HEADs of the git branches from the linux-yocto
v3.19 kernel repository.

Signed-off-by: Ng Wei Tee &lt;wei.tee.ng@intel.com&gt;
[sgw - tweaked summary commit info]
Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>lms7: re-write do_unpack to fix warning</title>
<updated>2015-04-15T22:07:52+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2015-04-15T19:17:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=4739f47e9358ec8cb82a72f3e185003c5ce40b2c'/>
<id>urn:sha1:4739f47e9358ec8cb82a72f3e185003c5ce40b2c</id>
<content type='text'>
Since the primary tarball unpacks into a non-standard directory create
a do_unpack that sets and resets  to first unpack the primary tarball
and then unpacks the actual src tarball into the correct directory.

This is similar to lsof which has a dual tarball also.

Fixes this WARNING:
WARNING: /srv/hdd/intel/test/tmp/work/corei7-64-poky-linux/lms7/7.1.20-r0/lms-7.1.20 ('S') doesn't exist, please set 'S' to a proper value

[YOCTO #7551]

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
Signed-off-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>linux-yocto: Add initial support for Braswell</title>
<updated>2015-04-15T18:15:03+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2015-04-15T15:08:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/meta-intel.git/commit/?id=8a76aa82e7dc32b64d5f47929a0f0af7c84f9f79'/>
<id>urn:sha1:8a76aa82e7dc32b64d5f47929a0f0af7c84f9f79</id>
<content type='text'>
This meta SRCREV update adds support for the initial support for the Braswell SOC
to the core BSPs. This enables CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT for the graphics
driver.

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
Signed-off-by: Darren Hart &lt;dvhart@linux.intel.com&gt;
</content>
</entry>
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