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authorZhenhua Luo <b19537@freescale.com>2012-03-09 10:57:35 +0000
committerMatthew McClintock <msm@freescale.com>2012-03-13 12:41:42 -0500
commit122c5bfdad95930de96e191aafb0304fded007b2 (patch)
treeea66cb9147fed9ceacd9eacd5913b10bb64734a1 /recipes-devtools/binutils
parent4f2d99fbb0afd19376e404583700ee31428f7c2e (diff)
downloadmeta-fsl-ppc-122c5bfdad95930de96e191aafb0304fded007b2.tar.gz
integrate fsl toolchain patches
binutils: bin.e500mc_nop.patch bin.e5500.patch bin.e6500-2.patch eglibc: generate-supported.mk glibc.e500mc_subspecies_of_powerpc_is_not_supported.patch glibc.fixgcc4.6.patch glibc.fix_prof.patch glibc.fix_sqrt.patch glibc.readv_proto.patch glibc.undefined_static.patch gcc: gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch gcc.fix_longversionstring.patch gcc.rm_slow_tests.patch gcc.fix_mingw32.patch gcc.fix_cloogstatic2.patch gcc.fix_build-with-cxx.patch gcc.e6500-FSF46.patch gcc.ld_unaligned-460.patch gcc.local_unaligned_altivec.patch gcc.soft_float-460.patch gcc.case_values.patch gcc.builtin_isel.patch gcc.experimental_move.patch gcc.widen_types-46.patch gcc.extelim-v3.patch gcc.e5500_mfocr.patch gcc.opt-array-offset.patch gcc.load_on_store_bypass-462.patch gcc.fix_constvector.patch gcc.fix_MTWX51204-dwarf-vector-reg.patch gcc.fix_ira-loop-pressure.patch optional_libstdc.patch gcc.remove_CCUNSmode_reference.patch gcc.check_path_validity.patch gcc.fix_header_issue.patch gcc.fix_SSIZE_MAX_undefine_issue.patch gettext: gettext.fix_testcase.patch Signed-off-by: Zhenhua Luo <b19537@freescale.com>
Diffstat (limited to 'recipes-devtools/binutils')
-rw-r--r--recipes-devtools/binutils/binutils-cross-canadian_2.21.1a.bbappend1
-rw-r--r--recipes-devtools/binutils/binutils-cross_2.21.1a.bbappend1
-rw-r--r--recipes-devtools/binutils/binutils-crosssdk_2.21.1a.bbappend1
-rw-r--r--recipes-devtools/binutils/binutils-fsl.inc10
-rw-r--r--recipes-devtools/binutils/binutils_2.21.1a.bbappend1
-rw-r--r--recipes-devtools/binutils/files/bin.e500mc_nop.patch114
-rw-r--r--recipes-devtools/binutils/files/bin.e5500.patch102
-rw-r--r--recipes-devtools/binutils/files/bin.e6500-2.patch674
8 files changed, 904 insertions, 0 deletions
diff --git a/recipes-devtools/binutils/binutils-cross-canadian_2.21.1a.bbappend b/recipes-devtools/binutils/binutils-cross-canadian_2.21.1a.bbappend
new file mode 100644
index 0000000..d46b87a
--- /dev/null
+++ b/recipes-devtools/binutils/binutils-cross-canadian_2.21.1a.bbappend
@@ -0,0 +1 @@
require binutils-fsl.inc
diff --git a/recipes-devtools/binutils/binutils-cross_2.21.1a.bbappend b/recipes-devtools/binutils/binutils-cross_2.21.1a.bbappend
new file mode 100644
index 0000000..d46b87a
--- /dev/null
+++ b/recipes-devtools/binutils/binutils-cross_2.21.1a.bbappend
@@ -0,0 +1 @@
require binutils-fsl.inc
diff --git a/recipes-devtools/binutils/binutils-crosssdk_2.21.1a.bbappend b/recipes-devtools/binutils/binutils-crosssdk_2.21.1a.bbappend
new file mode 100644
index 0000000..d46b87a
--- /dev/null
+++ b/recipes-devtools/binutils/binutils-crosssdk_2.21.1a.bbappend
@@ -0,0 +1 @@
require binutils-fsl.inc
diff --git a/recipes-devtools/binutils/binutils-fsl.inc b/recipes-devtools/binutils/binutils-fsl.inc
new file mode 100644
index 0000000..e425d42
--- /dev/null
+++ b/recipes-devtools/binutils/binutils-fsl.inc
@@ -0,0 +1,10 @@
1SRC_URI = "\
2 ${GNU_MIRROR}/binutils/binutils-${PV}.tar.bz2 \
3 file://bin.e5500.patch \
4 file://bin.e6500-2.patch \
5 file://bin.e500mc_nop.patch \
6 "
7
8FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
9
10PR .= "+${DISTRO}.0"
diff --git a/recipes-devtools/binutils/binutils_2.21.1a.bbappend b/recipes-devtools/binutils/binutils_2.21.1a.bbappend
new file mode 100644
index 0000000..d46b87a
--- /dev/null
+++ b/recipes-devtools/binutils/binutils_2.21.1a.bbappend
@@ -0,0 +1 @@
require binutils-fsl.inc
diff --git a/recipes-devtools/binutils/files/bin.e500mc_nop.patch b/recipes-devtools/binutils/files/bin.e500mc_nop.patch
new file mode 100644
index 0000000..9c9d52c
--- /dev/null
+++ b/recipes-devtools/binutils/files/bin.e500mc_nop.patch
@@ -0,0 +1,114 @@
1Generate the preferred NOP: ori r0, r0, 0 in the place of ori r2, r2, 0
2and add the nop test cases in gas for e500mc64, e5500 and e6500.
3
4diff -ruN binutils-4.6.0-orig/gas/config/tc-ppc.c binutils-4.6.0-new/gas/config/tc-ppc.c
5--- binutils-4.6.0-orig/gas/config/tc-ppc.c 2011-08-18 16:02:21.847979825 -0500
6+++ binutils-4.6.0-new/gas/config/tc-ppc.c 2011-08-19 10:09:19.888849978 -0500
7@@ -5815,8 +5817,14 @@
8 }
9
10 if ((ppc_cpu & PPC_OPCODE_POWER7) != 0)
11- /* power7 group terminating nop: "ori 2,2,0". */
12- md_number_to_chars (dest, 0x60420000, 4);
13+ {
14+ if (ppc_cpu & PPC_OPCODE_E500MC)
15+ /* e500mc group terminating nop: "ori 0,0,0". */
16+ md_number_to_chars (dest, 0x60000000, 4);
17+ else
18+ /* power7 group terminating nop: "ori 2,2,0". */
19+ md_number_to_chars (dest, 0x60420000, 4);
20+ }
21 else
22 /* power6 group terminating nop: "ori 1,1,0". */
23 md_number_to_chars (dest, 0x60210000, 4);
24diff -ruN binutils-4.6.0-orig/gas/testsuite/gas/ppc/e500mc64_nop.d binutils-4.6.0-new/gas/testsuite/gas/ppc/e500mc64_nop.d
25--- binutils-4.6.0-orig/gas/testsuite/gas/ppc/e500mc64_nop.d 1969-12-31 18:00:00.000000000 -0600
26+++ binutils-4.6.0-new/gas/testsuite/gas/ppc/e500mc64_nop.d 2011-08-19 10:16:29.561849966 -0500
27@@ -0,0 +1,13 @@
28+#as: -mppc -me500mc64
29+#objdump: -dr -Me500mc64
30+#name: Power E500MC64 nop tests
31+
32+.*: +file format elf(32)?(64)?-powerpc.*
33+
34+Disassembly of section \.text:
35+
36+0+00 <start>:
37+ 0: 60 00 00 00 nop
38+ 4: 60 00 00 00 nop
39+ 8: 60 00 00 00 nop
40+ c: 60 00 00 00 nop
41diff -ruN binutils-4.6.0-orig/gas/testsuite/gas/ppc/e500mc64_nop.s binutils-4.6.0-new/gas/testsuite/gas/ppc/e500mc64_nop.s
42--- binutils-4.6.0-orig/gas/testsuite/gas/ppc/e500mc64_nop.s 1969-12-31 18:00:00.000000000 -0600
43+++ binutils-4.6.0-new/gas/testsuite/gas/ppc/e500mc64_nop.s 2011-08-19 10:16:29.561849966 -0500
44@@ -0,0 +1,5 @@
45+# Power E500MC64 nop tests
46+ .section ".text"
47+start:
48+ nop
49+ .p2align 4,,15
50diff -ruN binutils-4.6.0-orig/gas/testsuite/gas/ppc/e5500_nop.d binutils-4.6.0-new/gas/testsuite/gas/ppc/e5500_nop.d
51--- binutils-4.6.0-orig/gas/testsuite/gas/ppc/e5500_nop.d 1969-12-31 18:00:00.000000000 -0600
52+++ binutils-4.6.0-new/gas/testsuite/gas/ppc/e5500_nop.d 2011-08-19 10:16:29.561849966 -0500
53@@ -0,0 +1,13 @@
54+#as: -mppc -me5500
55+#objdump: -dr -Me5500
56+#name: Power E5500 nop tests
57+
58+.*: +file format elf(32)?(64)?-powerpc.*
59+
60+Disassembly of section \.text:
61+
62+0+00 <start>:
63+ 0: 60 00 00 00 nop
64+ 4: 60 00 00 00 nop
65+ 8: 60 00 00 00 nop
66+ c: 60 00 00 00 nop
67diff -ruN binutils-4.6.0-orig/gas/testsuite/gas/ppc/e5500_nop.s binutils-4.6.0-new/gas/testsuite/gas/ppc/e5500_nop.s
68--- binutils-4.6.0-orig/gas/testsuite/gas/ppc/e5500_nop.s 1969-12-31 18:00:00.000000000 -0600
69+++ binutils-4.6.0-new/gas/testsuite/gas/ppc/e5500_nop.s 2011-08-19 10:16:29.561849966 -0500
70@@ -0,0 +1,5 @@
71+# Power E5500 nop tests
72+ .section ".text"
73+start:
74+ nop
75+ .p2align 4,,15
76diff -ruN binutils-4.6.0-orig/gas/testsuite/gas/ppc/e6500_nop.d binutils-4.6.0-new/gas/testsuite/gas/ppc/e6500_nop.d
77--- binutils-4.6.0-orig/gas/testsuite/gas/ppc/e6500_nop.d 1969-12-31 18:00:00.000000000 -0600
78+++ binutils-4.6.0-new/gas/testsuite/gas/ppc/e6500_nop.d 2011-08-19 10:16:29.561849966 -0500
79@@ -0,0 +1,13 @@
80+#as: -mppc -me6500
81+#objdump: -dr -Me6500
82+#name: Power E6500 nop tests
83+
84+.*: +file format elf(32)?(64)?-powerpc.*
85+
86+Disassembly of section \.text:
87+
88+0+00 <start>:
89+ 0: 60 00 00 00 nop
90+ 4: 60 00 00 00 nop
91+ 8: 60 00 00 00 nop
92+ c: 60 00 00 00 nop
93diff -ruN binutils-4.6.0-orig/gas/testsuite/gas/ppc/e6500_nop.s binutils-4.6.0-new/gas/testsuite/gas/ppc/e6500_nop.s
94--- binutils-4.6.0-orig/gas/testsuite/gas/ppc/e6500_nop.s 1969-12-31 18:00:00.000000000 -0600
95+++ binutils-4.6.0-new/gas/testsuite/gas/ppc/e6500_nop.s 2011-08-19 10:16:29.562849956 -0500
96@@ -0,0 +1,5 @@
97+# Power E6500 nop tests
98+ .section ".text"
99+start:
100+ nop
101+ .p2align 4,,15
102diff -ruN binutils-4.6.0-orig/gas/testsuite/gas/ppc/ppc.exp binutils-4.6.0-new/gas/testsuite/gas/ppc/ppc.exp
103--- binutils-4.6.0-orig/gas/testsuite/gas/ppc/ppc.exp 2011-08-19 10:15:29.445978575 -0500
104+++ binutils-4.6.0-new/gas/testsuite/gas/ppc/ppc.exp 2011-08-19 10:16:17.827852501 -0500
105@@ -43,6 +43,9 @@
106 run_dump_test "ppc750ps"
107 run_dump_test "e500mc"
108 run_dump_test "e6500"
109+ run_dump_test "e500mc64_nop"
110+ run_dump_test "e5500_nop"
111+ run_dump_test "e6500_nop"
112 run_dump_test "a2"
113 run_dump_test "cell"
114 run_dump_test "common"
diff --git a/recipes-devtools/binutils/files/bin.e5500.patch b/recipes-devtools/binutils/files/bin.e5500.patch
new file mode 100644
index 0000000..800590c
--- /dev/null
+++ b/recipes-devtools/binutils/files/bin.e5500.patch
@@ -0,0 +1,102 @@
1bin.e5500
2
3Implements target e5500 and -me5500, etc..
4
5diff -r -u binutils-2.21-20110211-orig/bfd/archures.c binutils-2.21-20110211/bfd/archures.c
6--- binutils-2.21-20110211-orig/bfd/archures.c 2010-12-30 18:33:31.000000000 -0600
7+++ binutils-2.21-20110211/bfd/archures.c 2011-02-14 13:17:00.528340236 -0600
8@@ -234,6 +234,7 @@
9 .#define bfd_mach_ppc_e500 500
10 .#define bfd_mach_ppc_e500mc 5001
11 .#define bfd_mach_ppc_e500mc64 5005
12+.#define bfd_mach_ppc_e5500 5006
13 .#define bfd_mach_ppc_titan 83
14 . bfd_arch_rs6000, {* IBM RS/6000 *}
15 .#define bfd_mach_rs6k 6000
16diff -r -u binutils-2.21-20110211-orig/bfd/bfd-in2.h binutils-2.21-20110211/bfd/bfd-in2.h
17--- binutils-2.21-20110211-orig/bfd/bfd-in2.h 2011-02-11 10:57:58.000000000 -0600
18+++ binutils-2.21-20110211/bfd/bfd-in2.h 2011-02-14 13:19:57.365092179 -0600
19@@ -1921,6 +1921,7 @@
20 #define bfd_mach_ppc_e500 500
21 #define bfd_mach_ppc_e500mc 5001
22 #define bfd_mach_ppc_e500mc64 5005
23+#define bfd_mach_ppc_e5500 5006
24 #define bfd_mach_ppc_titan 83
25 bfd_arch_rs6000, /* IBM RS/6000 */
26 #define bfd_mach_rs6k 6000
27diff -r -u binutils-2.21-20110211-orig/bfd/cpu-powerpc.c binutils-2.21-20110211/bfd/cpu-powerpc.c
28--- binutils-2.21-20110211-orig/bfd/cpu-powerpc.c 2010-02-07 19:59:34.000000000 -0600
29+++ binutils-2.21-20110211/bfd/cpu-powerpc.c 2011-02-14 13:21:48.802403135 -0600
30@@ -352,6 +352,20 @@
31 FALSE, /* not the default */
32 powerpc_compatible,
33 bfd_default_scan,
34+ &bfd_powerpc_archs[19]
35+ },
36+ {
37+ 64, /* 64 bits in a word */
38+ 64, /* 64 bits in an address */
39+ 8, /* 8 bits in a byte */
40+ bfd_arch_powerpc,
41+ bfd_mach_ppc_e5500,
42+ "powerpc",
43+ "powerpc:e5500",
44+ 3,
45+ FALSE, /* not the default */
46+ powerpc_compatible,
47+ bfd_default_scan,
48 0
49 }
50 };
51diff -r -u binutils-2.21-20110211-orig/gas/config/tc-ppc.c binutils-2.21-20110211/gas/config/tc-ppc.c
52--- binutils-2.21-20110211-orig/gas/config/tc-ppc.c 2011-02-11 10:58:01.000000000 -0600
53+++ binutils-2.21-20110211/gas/config/tc-ppc.c 2011-02-14 13:23:39.478340515 -0600
54@@ -1235,6 +1235,7 @@
55 -me500, -me500x2 generate code for Motorola e500 core complex\n\
56 -me500mc, generate code for Freescale e500mc core complex\n\
57 -me500mc64, generate code for Freescale e500mc64 core complex\n\
58+-me5500, generate code for Freescale e5500 core complex\n\
59 -mspe generate code for Motorola SPE instructions\n\
60 -mtitan generate code for AppliedMicro Titan core complex\n\
61 -mregnames Allow symbolic names for registers\n\
62diff -r -u binutils-2.21-20110211-orig/gas/doc/as.texinfo binutils-2.21-20110211/gas/doc/as.texinfo
63--- binutils-2.21-20110211-orig/gas/doc/as.texinfo 2011-02-11 10:58:01.000000000 -0600
64+++ binutils-2.21-20110211/gas/doc/as.texinfo 2011-02-14 13:26:01.383403323 -0600
65@@ -431,7 +431,7 @@
66 [@b{-a32}|@b{-a64}]
67 [@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}|@b{-m403}|@b{-m405}|
68 @b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mppc64}|
69- @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-mppc64bridge}|@b{-mbooke}|
70+ @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-mppc64bridge}|@b{-mbooke}|
71 @b{-mpower4}|@b{-mpr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}|
72 @b{-mpower7}|@b{-mpw7}|@b{-ma2}|@b{-mcell}|@b{-mspe}|@b{-mtitan}|@b{-me300}|@b{-mcom}]
73 [@b{-many}] [@b{-maltivec}|@b{-mvsx}]
74diff -r -u binutils-2.21-20110211-orig/gas/doc/c-ppc.texi binutils-2.21-20110211/gas/doc/c-ppc.texi
75--- binutils-2.21-20110211-orig/gas/doc/c-ppc.texi 2011-02-11 10:58:04.000000000 -0600
76+++ binutils-2.21-20110211/gas/doc/c-ppc.texi 2011-02-14 13:26:31.140090956 -0600
77@@ -88,6 +88,9 @@
78 @item -me500mc64
79 Generate code for Freescale e500mc64 core complex.
80
81+@item -me5500
82+Generate code for Freescale e5500 core complex.
83+
84 @item -mspe
85 Generate code for Motorola SPE instructions.
86
87diff -r -u binutils-2.21-20110211-orig/opcodes/ppc-dis.c binutils-2.21-20110211/opcodes/ppc-dis.c
88--- binutils-2.21-20110211-orig/opcodes/ppc-dis.c 2010-07-03 03:27:23.000000000 -0500
89+++ binutils-2.21-20110211/opcodes/ppc-dis.c 2011-02-14 13:28:54.384090879 -0600
90@@ -114,6 +114,12 @@
91 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
92 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
93 0 },
94+ { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
95+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
96+ | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
97+ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
98+ | PPC_OPCODE_POWER7),
99+ 0 },
100 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
101 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
102 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
diff --git a/recipes-devtools/binutils/files/bin.e6500-2.patch b/recipes-devtools/binutils/files/bin.e6500-2.patch
new file mode 100644
index 0000000..e863323
--- /dev/null
+++ b/recipes-devtools/binutils/files/bin.e6500-2.patch
@@ -0,0 +1,674 @@
1bin.e6500-2
2Implements target e6500 and -me6500, etc..
3
4Also enables some cell instructions but using different opcodes. (This
5should be temporary until new mnemonics are chosen. Likely to be
6defined only when ISA 2.07 comes out)
7
8Also implements new altivec instructions, and a few other e6500
9instructions like miso, and sync with two arguments.
10
11diff -ruN binutils-2.21-20110211-e5500/bfd/archures.c binutils-2.21-20110211-e6500/bfd/archures.c
12--- binutils-2.21-20110211-e5500/bfd/archures.c 2011-05-03 16:04:03.828069461 -0500
13+++ binutils-2.21-20110211-e6500/bfd/archures.c 2011-05-03 16:04:15.253938636 -0500
14@@ -235,6 +235,7 @@
15 .#define bfd_mach_ppc_e500mc 5001
16 .#define bfd_mach_ppc_e500mc64 5005
17 .#define bfd_mach_ppc_e5500 5006
18+.#define bfd_mach_ppc_e6500 5007
19 .#define bfd_mach_ppc_titan 83
20 . bfd_arch_rs6000, {* IBM RS/6000 *}
21 .#define bfd_mach_rs6k 6000
22diff -ruN binutils-2.21-20110211-e5500/bfd/bfd-in2.h binutils-2.21-20110211-e6500/bfd/bfd-in2.h
23--- binutils-2.21-20110211-e5500/bfd/bfd-in2.h 2011-05-03 16:04:03.836064584 -0500
24+++ binutils-2.21-20110211-e6500/bfd/bfd-in2.h 2011-05-03 16:04:15.260938268 -0500
25@@ -1922,6 +1922,7 @@
26 #define bfd_mach_ppc_e500mc 5001
27 #define bfd_mach_ppc_e500mc64 5005
28 #define bfd_mach_ppc_e5500 5006
29+#define bfd_mach_ppc_e6500 5007
30 #define bfd_mach_ppc_titan 83
31 bfd_arch_rs6000, /* IBM RS/6000 */
32 #define bfd_mach_rs6k 6000
33diff -ruN binutils-2.21-20110211-e5500/bfd/cpu-powerpc.c binutils-2.21-20110211-e6500/bfd/cpu-powerpc.c
34--- binutils-2.21-20110211-e5500/bfd/cpu-powerpc.c 2011-05-03 16:04:03.839066505 -0500
35+++ binutils-2.21-20110211-e6500/bfd/cpu-powerpc.c 2011-05-03 16:04:15.272066052 -0500
36@@ -366,6 +366,20 @@
37 FALSE, /* not the default */
38 powerpc_compatible,
39 bfd_default_scan,
40+ &bfd_powerpc_archs[20]
41+ },
42+ {
43+ 64, /* 64 bits in a word */
44+ 64, /* 64 bits in an address */
45+ 8, /* 8 bits in a byte */
46+ bfd_arch_powerpc,
47+ bfd_mach_ppc_e6500,
48+ "powerpc",
49+ "powerpc:e6500",
50+ 3,
51+ FALSE, /* not the default */
52+ powerpc_compatible,
53+ bfd_default_scan,
54 0
55 }
56 };
57diff -ruN binutils-2.21-20110211-e5500/gas/config/tc-ppc.c binutils-2.21-20110211-e6500/gas/config/tc-ppc.c
58--- binutils-2.21-20110211-e5500/gas/config/tc-ppc.c 2011-05-03 16:04:03.847063157 -0500
59+++ binutils-2.21-20110211-e6500/gas/config/tc-ppc.c 2011-05-03 16:04:15.279062744 -0500
60@@ -1236,6 +1236,7 @@
61 -me500mc, generate code for Freescale e500mc core complex\n\
62 -me500mc64, generate code for Freescale e500mc64 core complex\n\
63 -me5500, generate code for Freescale e5500 core complex\n\
64+-me6500, generate code for Freescale e6500 core complex\n\
65 -mspe generate code for Motorola SPE instructions\n\
66 -mtitan generate code for AppliedMicro Titan core complex\n\
67 -mregnames Allow symbolic names for registers\n\
68diff -ruN binutils-2.21-20110211-e5500/gas/doc/as.texinfo binutils-2.21-20110211-e6500/gas/doc/as.texinfo
69--- binutils-2.21-20110211-e5500/gas/doc/as.texinfo 2011-05-03 16:04:03.857062970 -0500
70+++ binutils-2.21-20110211-e6500/gas/doc/as.texinfo 2011-05-03 16:04:15.289062767 -0500
71@@ -431,8 +431,8 @@
72 [@b{-a32}|@b{-a64}]
73 [@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}|@b{-m403}|@b{-m405}|
74 @b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mppc64}|
75- @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-mppc64bridge}|@b{-mbooke}|
76- @b{-mpower4}|@b{-mpr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}|
77+ @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-me6500}|@b{-mppc64bridge}|
78+ @b{-mbooke}|@b{-mpower4}|@b{-mpr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}|
79 @b{-mpower7}|@b{-mpw7}|@b{-ma2}|@b{-mcell}|@b{-mspe}|@b{-mtitan}|@b{-me300}|@b{-mcom}]
80 [@b{-many}] [@b{-maltivec}|@b{-mvsx}]
81 [@b{-mregnames}|@b{-mno-regnames}]
82diff -ruN binutils-2.21-20110211-e5500/gas/doc/c-ppc.texi binutils-2.21-20110211-e6500/gas/doc/c-ppc.texi
83--- binutils-2.21-20110211-e5500/gas/doc/c-ppc.texi 2011-05-03 16:04:03.859065711 -0500
84+++ binutils-2.21-20110211-e6500/gas/doc/c-ppc.texi 2011-05-03 16:04:15.291064458 -0500
85@@ -91,6 +91,9 @@
86 @item -me5500
87 Generate code for Freescale e5500 core complex.
88
89+@item -me6500
90+Generate code for Freescale e6500 core complex.
91+
92 @item -mspe
93 Generate code for Motorola SPE instructions.
94
95diff -ruN binutils-2.21-20110211-e5500/gas/testsuite/gas/ppc/e6500.d binutils-2.21-20110211-e6500/gas/testsuite/gas/ppc/e6500.d
96--- binutils-2.21-20110211-e5500/gas/testsuite/gas/ppc/e6500.d 1969-12-31 18:00:00.000000000 -0600
97+++ binutils-2.21-20110211-e6500/gas/testsuite/gas/ppc/e6500.d 2011-05-03 17:04:13.611815418 -0500
98@@ -0,0 +1,75 @@
99+#as: -mppc -me6500
100+#objdump: -dr -Me6500
101+#name: Power E6500 tests
102+
103+.*: +file format elf(32)?(64)?-powerpc.*
104+
105+Disassembly of section \.text:
106+
107+0+00 <start>:
108+ 0: 10 01 10 c0 vabsdub v0,v1,v2
109+ 4: 10 01 11 00 vabsduh v0,v1,v2
110+ 8: 10 01 11 40 vabsduw v0,v1,v2
111+ c: 7c 01 10 dc mvidsplt v0,r1,r2
112+ 10: 7c 01 11 1c mviwsplt v0,r1,r2
113+ 14: 7c 00 12 0a lvexbx v0,0,r2
114+ 18: 7c 01 12 0a lvexbx v0,r1,r2
115+ 1c: 7c 00 12 4a lvexhx v0,0,r2
116+ 20: 7c 01 12 4a lvexhx v0,r1,r2
117+ 24: 7c 00 12 8a lvexwx v0,0,r2
118+ 28: 7c 01 12 8a lvexwx v0,r1,r2
119+ 2c: 7c 00 13 0a stvexbx v0,0,r2
120+ 30: 7c 01 13 0a stvexbx v0,r1,r2
121+ 34: 7c 00 13 4a stvexhx v0,0,r2
122+ 38: 7c 01 13 4a stvexhx v0,r1,r2
123+ 3c: 7c 00 13 8a stvexwx v0,0,r2
124+ 40: 7c 01 13 8a stvexwx v0,r1,r2
125+ 44: 7c 00 12 4e lvepx v0,0,r2
126+ 48: 7c 01 12 4e lvepx v0,r1,r2
127+ 4c: 7c 00 12 0e lvepxl v0,0,r2
128+ 50: 7c 01 12 0e lvepxl v0,r1,r2
129+ 54: 7c 00 16 4e stvepx v0,0,r2
130+ 58: 7c 01 16 4e stvepx v0,r1,r2
131+ 5c: 7c 00 16 0e stvepxl v0,0,r2
132+ 60: 7c 01 16 0e stvepxl v0,r1,r2
133+ 64: 7c 00 14 8a lvlx v0,0,r2
134+ 68: 7c 01 14 8a lvlx v0,r1,r2
135+ 6c: 7c 00 16 8a lvlxl v0,0,r2
136+ 70: 7c 01 16 8a lvlxl v0,r1,r2
137+ 74: 7c 00 14 4a lvrx v0,0,r2
138+ 78: 7c 01 14 4a lvrx v0,r1,r2
139+ 7c: 7c 00 16 4a lvrxl v0,0,r2
140+ 80: 7c 01 16 4a lvrxl v0,r1,r2
141+ 84: 7c 00 15 8a stvlx v0,0,r2
142+ 88: 7c 01 15 8a stvlx v0,r1,r2
143+ 8c: 7c 00 17 8a stvlxl v0,0,r2
144+ 90: 7c 01 17 8a stvlxl v0,r1,r2
145+ 94: 7c 00 15 4a stvrx v0,0,r2
146+ 98: 7c 01 15 4a stvrx v0,r1,r2
147+ 9c: 7c 00 17 4a stvrxl v0,0,r2
148+ a0: 7c 01 17 4a stvrxl v0,r1,r2
149+ a4: 7c 00 14 ca lvswx v0,0,r2
150+ a8: 7c 01 14 ca lvswx v0,r1,r2
151+ ac: 7c 00 16 ca lvswxl v0,0,r2
152+ b0: 7c 01 16 ca lvswxl v0,r1,r2
153+ b4: 7c 00 15 ca stvswx v0,0,r2
154+ b8: 7c 01 15 ca stvswx v0,r1,r2
155+ bc: 7c 00 17 ca stvswxl v0,0,r2
156+ c0: 7c 01 17 ca stvswxl v0,r1,r2
157+ c4: 7c 00 16 0a lvsm v0,0,r2
158+ c8: 7c 01 16 0a lvsm v0,r1,r2
159+ cc: 7f 5a d3 78 miso
160+ d0: 7c 00 04 ac sync
161+ d4: 7c 00 04 ac sync
162+ d8: 7c 20 04 ac lwsync
163+ dc: 7c 00 04 ac sync
164+ e0: 7c 07 04 ac sync 0,7
165+ e4: 7c 28 04 ac sync 1,8
166+ e8: 7c 00 00 c3 dni 0,0
167+ ec: 7f ff 00 c3 dni 31,31
168+ f0: 7c 40 0b 4d dcblq. 2,0,r1
169+ f4: 7c 43 0b 4d dcblq. 2,r3,r1
170+ f8: 7c 40 09 8d icblq. 2,0,r1
171+ fc: 7c 43 09 8d icblq. 2,r3,r1
172+ 100: 7c 10 02 dc mftmr r0,16
173+ 104: 7c 10 03 dc mttmr 16,r0
174diff -ruN binutils-2.21-20110211-e5500/gas/testsuite/gas/ppc/e6500.s binutils-2.21-20110211-e6500/gas/testsuite/gas/ppc/e6500.s
175--- binutils-2.21-20110211-e5500/gas/testsuite/gas/ppc/e6500.s 1969-12-31 18:00:00.000000000 -0600
176+++ binutils-2.21-20110211-e6500/gas/testsuite/gas/ppc/e6500.s 2011-05-03 16:35:30.724819687 -0500
177@@ -0,0 +1,69 @@
178+# Power E6500 tests
179+ .section ".text"
180+start:
181+ vabsdub 0, 1, 2
182+ vabsduh 0, 1, 2
183+ vabsduw 0, 1, 2
184+ mvidsplt 0, 1, 2
185+ mviwsplt 0, 1, 2
186+ lvexbx 0, 0, 2
187+ lvexbx 0, 1, 2
188+ lvexhx 0, 0, 2
189+ lvexhx 0, 1, 2
190+ lvexwx 0, 0, 2
191+ lvexwx 0, 1, 2
192+ stvexbx 0, 0, 2
193+ stvexbx 0, 1, 2
194+ stvexhx 0, 0, 2
195+ stvexhx 0, 1, 2
196+ stvexwx 0, 0, 2
197+ stvexwx 0, 1, 2
198+ lvepx 0, 0, 2
199+ lvepx 0, 1, 2
200+ lvepxl 0, 0, 2
201+ lvepxl 0, 1, 2
202+ stvepx 0, 0, 2
203+ stvepx 0, 1, 2
204+ stvepxl 0, 0, 2
205+ stvepxl 0, 1, 2
206+ lvlx 0, 0, 2
207+ lvlx 0, 1, 2
208+ lvlxl 0, 0, 2
209+ lvlxl 0, 1, 2
210+ lvrx 0, 0, 2
211+ lvrx 0, 1, 2
212+ lvrxl 0, 0, 2
213+ lvrxl 0, 1, 2
214+ stvlx 0, 0, 2
215+ stvlx 0, 1, 2
216+ stvlxl 0, 0, 2
217+ stvlxl 0, 1, 2
218+ stvrx 0, 0, 2
219+ stvrx 0, 1, 2
220+ stvrxl 0, 0, 2
221+ stvrxl 0, 1, 2
222+ lvswx 0, 0, 2
223+ lvswx 0, 1, 2
224+ lvswxl 0, 0, 2
225+ lvswxl 0, 1, 2
226+ stvswx 0, 0, 2
227+ stvswx 0, 1, 2
228+ stvswxl 0, 0, 2
229+ stvswxl 0, 1, 2
230+ lvsm 0, 0, 2
231+ lvsm 0, 1, 2
232+ miso
233+ sync
234+ sync 0,0
235+ sync 1,0
236+ sync 2,0
237+ sync 3,7
238+ sync 3,8
239+ dni 0,0
240+ dni 31,31
241+ dcblq. 2,0,1
242+ dcblq. 2,3,1
243+ icblq. 2,0,1
244+ icblq. 2,3,1
245+ mftmr 0,16
246+ mttmr 16,0
247diff -ruN binutils-2.21-20110211-e5500/gas/testsuite/gas/ppc/ppc.exp binutils-2.21-20110211-e6500/gas/testsuite/gas/ppc/ppc.exp
248--- binutils-2.21-20110211-e5500/gas/testsuite/gas/ppc/ppc.exp 2010-02-07 19:59:38.000000000 -0600
249+++ binutils-2.21-20110211-e6500/gas/testsuite/gas/ppc/ppc.exp 2011-05-03 16:04:15.297067070 -0500
250@@ -42,6 +42,7 @@
251 run_list_test "range" "-a32"
252 run_dump_test "ppc750ps"
253 run_dump_test "e500mc"
254+ run_dump_test "e6500"
255 run_dump_test "a2"
256 run_dump_test "cell"
257 run_dump_test "common"
258diff -ruN binutils-2.21-20110211-e5500/include/opcode/ppc.h binutils-2.21-20110211-e6500/include/opcode/ppc.h
259--- binutils-2.21-20110211-e5500/include/opcode/ppc.h 2010-07-03 01:51:53.000000000 -0500
260+++ binutils-2.21-20110211-e6500/include/opcode/ppc.h 2011-05-03 16:04:15.298069340 -0500
261@@ -174,6 +174,15 @@
262 /* Opcode which is supported by the e500 family */
263 #define PPC_OPCODE_E500 0x100000000ull
264
265+/* Opcode is supported by Extended Altivec Vector Unit */
266+#define PPC_OPCODE_ALTIVEC2 0x200000000ull
267+
268+/* Opcode is supported by Power E6500 */
269+#define PPC_OPCODE_E6500 0x400000000ull
270+
271+/* Opcode is supported by Thread management APU */
272+#define PPC_OPCODE_TMR 0x800000000ull
273+
274 /* A macro to extract the major opcode from an instruction. */
275 #define PPC_OP(i) (((i) >> 26) & 0x3f)
276
277diff -ruN binutils-2.21-20110211-e5500/opcodes/ppc-dis.c binutils-2.21-20110211-e6500/opcodes/ppc-dis.c
278--- binutils-2.21-20110211-e5500/opcodes/ppc-dis.c 2011-05-03 16:04:03.862065832 -0500
279+++ binutils-2.21-20110211-e6500/opcodes/ppc-dis.c 2011-05-03 16:04:15.300067851 -0500
280@@ -120,6 +120,12 @@
281 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
282 | PPC_OPCODE_POWER7),
283 0 },
284+ { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
285+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
286+ | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
287+ | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
288+ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
289+ 0 },
290 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
291 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
292 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
293diff -ruN binutils-2.21-20110211-e5500/opcodes/ppc-opc.c binutils-2.21-20110211-e6500/opcodes/ppc-opc.c
294--- binutils-2.21-20110211-e5500/opcodes/ppc-opc.c 2011-02-11 10:58:12.000000000 -0600
295+++ binutils-2.21-20110211-e6500/opcodes/ppc-opc.c 2011-05-03 17:22:20.260813917 -0500
296@@ -53,6 +53,7 @@
297 static long extract_boe (unsigned long, ppc_cpu_t, int *);
298 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
299 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
300+static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
301 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
302 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
303 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
304@@ -450,6 +451,7 @@
305 lower 5 bits are stored in the upper 5 and vice- versa. */
306 #define SPR SISIGNOPT + 1
307 #define PMR SPR
308+#define TMR SPR
309 #define SPR_MASK (0x3ff << 11)
310 { 0x3ff, 11, insert_spr, extract_spr, 0 },
311
312@@ -472,8 +474,12 @@
313 #define T STRM
314 { 0x3, 21, NULL, NULL, 0 },
315
316+ /* The ESYNC field in an X (sync) form instruction. */
317+#define ESYNC STRM + 1
318+ { 0xf, 16, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
319+
320 /* The SV field in a POWER SC form instruction. */
321-#define SV STRM + 1
322+#define SV ESYNC + 1
323 { 0x3fff, 2, NULL, NULL, 0 },
324
325 /* The TBR field in an XFX form instruction. This is like the SPR
326@@ -515,6 +521,7 @@
327
328 /* The UIMM field in a VX form instruction. */
329 #define UIMM SIMM + 1
330+#define DCTL UIMM
331 { 0x1f, 16, NULL, NULL, 0 },
332
333 /* The SHB field in a VA form instruction. */
334@@ -996,6 +1003,32 @@
335 return mask;
336 }
337
338+/* The LS field in a sync instruction that accepts 2 operands
339+ Values 2 and 3 are reserved,
340+ must be treated as 0 for future compatibility
341+ Values 0 and 1 can be accepted, if field ESYNC is zero
342+ Otherwise L = complement of ESYNC-bit2 (1<<18) */
343+
344+static unsigned long
345+insert_ls (unsigned long insn,
346+ long value,
347+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
348+ const char **errmsg ATTRIBUTE_UNUSED)
349+{
350+ unsigned long ls;
351+
352+ ls = (insn >> 21) & 0x03;
353+ if (value == 0)
354+ {
355+ if (ls > 1)
356+ return insn & ~(0x3 << 21);
357+ return insn;
358+ }
359+ if ((value & 0x2) != 0)
360+ return (insn & ~(0x3 << 21)) | ((value & 0xf) << 16);
361+ return (insn & ~(0x3 << 21)) | (0x1 << 21) | ((value & 0xf) << 16);
362+}
363+
364 /* The MB and ME fields in an M form instruction expressed as a single
365 operand which is itself a bitmask. The extraction function always
366 marks it as invalid, since we never want to recognize an
367@@ -1728,6 +1761,9 @@
368 /* An X form sync instruction with everything filled in except the LS field. */
369 #define XSYNC_MASK (0xff9fffff)
370
371+/* An X form sync instruction with everything filled in except the L and E fields. */
372+#define XSYNCLE_MASK (0xff90ffff)
373+
374 /* An X_MASK, but with the EH bit clear. */
375 #define XEH_MASK (X_MASK & ~((unsigned long )1))
376
377@@ -1922,6 +1958,7 @@
378 #define PPC860 PPC
379 #define PPCPS PPC_OPCODE_PPCPS
380 #define PPCVEC PPC_OPCODE_ALTIVEC
381+#define PPCVEC2 PPC_OPCODE_ALTIVEC2
382 #define PPCVSX PPC_OPCODE_VSX
383 #define POWER PPC_OPCODE_POWER
384 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
385@@ -1940,6 +1977,7 @@
386 #define PPCEFS PPC_OPCODE_EFS
387 #define PPCBRLK PPC_OPCODE_BRLOCK
388 #define PPCPMR PPC_OPCODE_PMR
389+#define PPCTMR PPC_OPCODE_TMR
390 #define PPCCHLK PPC_OPCODE_CACHELCK
391 #define PPCRFMCI PPC_OPCODE_RFMCI
392 #define E500MC PPC_OPCODE_E500MC
393@@ -1947,6 +1985,7 @@
394 #define TITAN PPC_OPCODE_TITAN
395 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
396 #define E500 PPC_OPCODE_E500
397+#define E6500 PPC_OPCODE_E6500
398
399 /* The opcode table.
400
401@@ -2112,12 +2151,14 @@
402 {"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
403 {"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
404 {"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
405+{"vabsdub", VX (4, 192), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
406 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
407 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
408 {"machhws", XO (4, 108,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
409 {"machhws.", XO (4, 108,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
410 {"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
411 {"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
412+{"vabsduh", VX (4, 256), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
413 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
414 {"vslb", VX (4, 260), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
415 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
416@@ -2130,6 +2171,7 @@
417 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
418 {"macchwu", XO (4, 140,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
419 {"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
420+{"vabsduw", VX (4, 320), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
421 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
422 {"vslh", VX (4, 324), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
423 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
424@@ -3613,6 +3655,8 @@
425
426 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
427
428+{"dni", XRC(31,97,1), XRB_MASK, E6500, PPCNONE, {DUI, DCTL}},
429+
430 {"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
431 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
432
433@@ -3622,6 +3666,8 @@
434 {"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
435 {"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
436
437+{"mvidsplt", X(31,110), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}},
438+
439 {"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
440
441 {"lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
442@@ -3656,6 +3702,8 @@
443 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
444 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
445
446+{"mviwsplt", X(31,142), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}},
447+
448 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
449
450 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}},
451@@ -3711,6 +3759,8 @@
452
453 {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}},
454
455+{"icblq.", XRC(31,198,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}},
456+
457 {"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
458 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
459
460@@ -3788,8 +3838,12 @@
461 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
462 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}},
463
464+{"lvexbx", X(31,261), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
465+
466 {"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}},
467
468+{"lvepxl", X(31,263), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
469+
470 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
471 {"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
472 {"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
473@@ -3823,6 +3877,9 @@
474
475 {"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}},
476
477+{"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
478+{"lvepx", X(31,295), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
479+
480 {"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}},
481 {"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
482
483@@ -3874,6 +3931,8 @@
484 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {RT, SPR}},
485 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}},
486
487+{"lvexwx", X(31,325), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
488+
489 {"dcread", X(31,326), X_MASK, PPC476|TITAN, PPCNONE, {RT, RA, RB}},
490
491 {"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
492@@ -3882,6 +3941,7 @@
493 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
494
495 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}},
496+{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, PPCNONE, {RT, TMR}},
497
498 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}},
499 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}},
500@@ -4112,6 +4172,8 @@
501 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
502 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}},
503
504+{"stvexbx", X(31,389), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
505+
506 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
507 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
508
509@@ -4136,6 +4198,10 @@
510
511 {"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}},
512
513+{"stvexhx", X(31,421), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
514+
515+{"dcblq.", XRC(31,422,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}},
516+
517 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
518 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
519 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
520@@ -4149,6 +4215,8 @@
521
522 {"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}},
523
524+{"miso", 0x7f5ad378, 0xffffffff, E6500, PPCNONE, {0}},
525+
526 {"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
527 {"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
528 {"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
529@@ -4191,6 +4259,8 @@
530 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {SPR, RS}},
531 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}},
532
533+{"stvexwx", X(31,453), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
534+
535 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
536 {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}},
537
538@@ -4201,6 +4271,7 @@
539 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
540
541 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}},
542+{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, PPCNONE, {TMR, RS}},
543
544 {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}},
545 {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}},
546@@ -4445,6 +4516,8 @@
547
548 {"lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
549
550+{"lvrx", X(31,549), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
551+
552 {"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}},
553
554 {"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
555@@ -4461,6 +4534,8 @@
556
557 {"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
558
559+{"lvlx", X(31,581), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
560+
561 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
562
563 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
564@@ -4472,9 +4547,10 @@
565
566 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
567 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
568+{"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}},
569 {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
570 {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
571-{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, PPCNONE, {0}},
572+{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
573 {"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}},
574 {"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}},
575
576@@ -4485,6 +4561,8 @@
577
578 {"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
579
580+{"lvswx", X(31,613), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
581+
582 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
583
584 {"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
585@@ -4534,6 +4612,8 @@
586
587 {"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
588
589+{"stvrx", X(31,677), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
590+
591 {"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
592 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
593
594@@ -4546,6 +4626,8 @@
595
596 {"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
597
598+{"stvlx", X(31,709), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
599+
600 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
601
602 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
603@@ -4578,6 +4660,8 @@
604
605 {"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
606
607+{"stvswx", X(31,741), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
608+
609 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
610
611 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
612@@ -4606,6 +4690,8 @@
613 {"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
614 {"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
615
616+{"lvsm", X(31,773), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
617+{"stvepxl", X(31,775), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
618 {"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
619 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
620
621@@ -4638,6 +4724,8 @@
622
623 {"lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}},
624
625+{"lvrxl", X(31,805), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
626+{"stvepx", X(31,807), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
627 {"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
628
629 {"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}},
630@@ -4658,6 +4746,8 @@
631 {"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
632 {"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
633
634+{"lvlxl", X(31,837), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
635+
636 {"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
637 {"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
638
639@@ -4676,6 +4766,8 @@
640
641 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, RA0, RB}},
642
643+{"lvswxl", X(31,869), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
644+
645 {"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
646 {"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
647
648@@ -4721,6 +4813,8 @@
649
650 {"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
651
652+{"stvrxl", X(31,933), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
653+
654 {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, PPCNONE, {RA0, RB}},
655 {"wclrall", X(31,934), XRARB_MASK, PPCA2, PPCNONE, {L}},
656 {"wclr", X(31,934), X_MASK, PPCA2, PPCNONE, {L, RA0, RB}},
657@@ -4749,6 +4843,8 @@
658 {"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}},
659 {"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}},
660
661+{"stvlxl", X(31,965), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
662+
663 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
664 {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}},
665
666@@ -4776,6 +4872,8 @@
667
668 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
669
670+{"stvswxl", X(31,997), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
671+
672 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}},
673
674 {"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-04-22 12:44:16 +0000