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-rw-r--r--meta-fsl-arm/classes/image_types_fsl.bbclass2
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1130-ENGR00157473-MX5X-UART-disable-UART2-DMA-to-make-G.patch41
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1131-ENGR00158480-IPUv3-Set-IDMAC-LOCK-for-SDC-display-ch.patch41
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1132-ENGR00155891-mx53_loco-enable-mc34708-s-WDI-functio.patch48
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1133-ENGR00159010-IPUv3-Restore-IDMAC_CH_LOCK_EN_1-for-re.patch32
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1134-ENGR00159738-v4l2-correct-wrong-parameter-when-V4l2.patch29
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1135-ENGR00160566-IPUv3-Improve-IDMAC_LOCK_EN-setting.patch70
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1136-ENGR00161215-1-arch-arm-Add-two-new-IOCTLs-in-mxc_v.patch33
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1137-ENGR00161215-2-vpu-Add-ioctls-for-querying-and-sett.patch49
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1138-ENGR00162195-IPUv3M-Clear-IDMAC_LOCK_EN_1-for-tough.patch43
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1139-ENGR00162464-update-pm4-microcode-pm4_microcode_r18.patch820
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1140-ENGR00162711-DA9053-Add-dummy-write-for-DA9053-I2C.patch434
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1141-ENGR00162708-MX5-Add-I2C-dummy-write-and-mask-nONKE.patch86
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1142-ENGR00163698-MX53-ARD-fix-typo-error-for-pwm1-pad-d.patch33
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1143-ENGR00162578-DMA-mx5-increase-DMA-Zone-size-to-112.patch109
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1144-ENGR00169603-MX53-ARD-FlexCAN-Set-lp_apm-as-clock.patch37
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1145-ENGR00170342-PWM-fix-pwm-output-can-t-be-set-to-100.patch35
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1146-ENGR00170244-1-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch80
-rwxr-xr-xmeta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1147-ENGR00170244-2-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch53
-rw-r--r--meta-fsl-arm/recipes-kernel/linux/linux-imx_2.6.35.3.bb29
20 files changed, 4 insertions, 2100 deletions
diff --git a/meta-fsl-arm/classes/image_types_fsl.bbclass b/meta-fsl-arm/classes/image_types_fsl.bbclass
index 94ec49338..1f4e6d4a7 100644
--- a/meta-fsl-arm/classes/image_types_fsl.bbclass
+++ b/meta-fsl-arm/classes/image_types_fsl.bbclass
@@ -101,7 +101,7 @@ generate_imx_sdcard () {
101 esac 101 esac
102 102
103 BOOT_BLOCKS=$(LC_ALL=C parted -s ${SDCARD} unit b print \ 103 BOOT_BLOCKS=$(LC_ALL=C parted -s ${SDCARD} unit b print \
104 | awk '/ 2 / { print substr($4, 1, length($4 -1)) / 1024 }') 104 | awk '/ 1 / { print substr($4, 1, length($4 -1)) / 1024 }')
105 mkfs.vfat -n "${BOOTDD_VOLUME_ID}" -S 512 -C ${WORKDIR}/boot.img $BOOT_BLOCKS 105 mkfs.vfat -n "${BOOTDD_VOLUME_ID}" -S 512 -C ${WORKDIR}/boot.img $BOOT_BLOCKS
106 mcopy -i ${WORKDIR}/boot.img -s ${DEPLOY_DIR_IMAGE}/uImage-${MACHINE}.bin ::/uImage 106 mcopy -i ${WORKDIR}/boot.img -s ${DEPLOY_DIR_IMAGE}/uImage-${MACHINE}.bin ::/uImage
107 if [ -e "${KERNEL_IMAGETYPE}-${MACHINE}.dtb" ]; then 107 if [ -e "${KERNEL_IMAGETYPE}-${MACHINE}.dtb" ]; then
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1130-ENGR00157473-MX5X-UART-disable-UART2-DMA-to-make-G.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1130-ENGR00157473-MX5X-UART-disable-UART2-DMA-to-make-G.patch
deleted file mode 100755
index aa897705b..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1130-ENGR00157473-MX5X-UART-disable-UART2-DMA-to-make-G.patch
+++ /dev/null
@@ -1,41 +0,0 @@
1From f7702086585465f6ccaa33ae815535e8ff10f025 Mon Sep 17 00:00:00 2001
2From: Zhang Jiejing <jiejing.zhang@freescale.com>
3Date: Fri, 23 Sep 2011 11:05:04 +0800
4Subject: [PATCH] ENGR00157473 MX5X: UART: disable UART2 DMA to make GPS work.
5
6After enable DMA, GPS will keep report these DMA error:
7
8 UART: DMA_ERROR: sr1:2010 sr2:508b
9 UART: DMA_ERROR: sr1:2050 sr2:508a
10 UART: DMA_ERROR: sr1:2050 sr2:508b
11 UART: DMA_ERROR: sr1:10 sr2:1083
12 UART: DMA_ERROR: sr1:50 sr2:1082
13 UART: DMA_ERROR: sr1:2010 sr2:508b
14 UART: DMA_ERROR: sr1:2050 sr2:508a
15 UART: DMA_ERROR: sr1:2010 sr2:508b
16 UART: DMA_ERROR: sr1:2010 sr2:508b
17 UART: DMA_ERROR: sr1:2010 sr2:508b
18 UART: DMA_ERROR: sr1:50 sr2:1083
19
20Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
21(cherry picked from commit ddaf091fd3f5fae56b3c83f5cf59ee4f189f0a40)
22---
23 arch/arm/mach-mx5/serial.h | 2 +-
24 1 files changed, 1 insertions(+), 1 deletions(-)
25
26diff --git a/arch/arm/mach-mx5/serial.h b/arch/arm/mach-mx5/serial.h
27index 6ed55da..b142fdb 100644
28--- a/arch/arm/mach-mx5/serial.h
29+++ b/arch/arm/mach-mx5/serial.h
30@@ -45,7 +45,7 @@
31 #define UART1_DMA_ENABLE 0
32 /* UART 2 configuration */
33 #define UART2_UCR4_CTSTL -1
34-#define UART2_DMA_ENABLE 1
35+#define UART2_DMA_ENABLE 0
36 #define UART2_DMA_RXBUFSIZE 512
37 #define UART2_UFCR_RXTL 16
38 #define UART2_UFCR_TXTL 16
39--
401.5.4.4
41
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1131-ENGR00158480-IPUv3-Set-IDMAC-LOCK-for-SDC-display-ch.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1131-ENGR00158480-IPUv3-Set-IDMAC-LOCK-for-SDC-display-ch.patch
deleted file mode 100755
index d06530027..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1131-ENGR00158480-IPUv3-Set-IDMAC-LOCK-for-SDC-display-ch.patch
+++ /dev/null
@@ -1,41 +0,0 @@
1From b33793cbdf0b24f61398dfb98718ac9377e2b046 Mon Sep 17 00:00:00 2001
2From: Liu Ying <Ying.Liu@freescale.com>
3Date: Fri, 30 Sep 2011 16:00:09 +0800
4Subject: [PATCH] ENGR00158480 IPUv3:Set IDMAC LOCK for SDC display channels
5
6Set IDMAC_LOCK_EN_1 to make SDC display channels to generate
7eight AXI bursts upon the assertion of the DMA request.
8This change fixes the random garbage lines when showing
9NV12 frames decoded by VPU with V4L2 output on
10XGA@60 display's overlay framebuffer. V4L2 output uses
11MEM_PP_MEM to do 180 degree rotation.
12
13The issue can be reproduced by the following VPU unit test
14on MX53 SMD platform:
15/unit_tests/mxc_vpu_test.out -D
16'-i /1920x1080_H264_AAC5.1ch.2.1ch_track1.h264 -f 2 -w 1024
17-h 768 -r 180 -u 1 -t 1'
18
19Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
20(cherry picked from commit 50f969030c25bc33cf0f05a6a5cad98c52afd858)
21---
22 drivers/mxc/ipu3/ipu_common.c | 3 +++
23 1 files changed, 3 insertions(+), 0 deletions(-)
24
25diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
26index 8dfa54f..4b12905 100644
27--- a/drivers/mxc/ipu3/ipu_common.c
28+++ b/drivers/mxc/ipu3/ipu_common.c
29@@ -385,6 +385,9 @@ static int ipu_probe(struct platform_device *pdev)
30 /* Set sync refresh channels and CSI->mem channel as high priority */
31 __raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
32
33+ /* AXI burst setting for sync refresh channels */
34+ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
35+
36 /* Set MCU_T to divide MCU access window into 2 */
37 __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
38
39--
401.5.4.4
41
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1132-ENGR00155891-mx53_loco-enable-mc34708-s-WDI-functio.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1132-ENGR00155891-mx53_loco-enable-mc34708-s-WDI-functio.patch
deleted file mode 100755
index 8ebcf840d..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1132-ENGR00155891-mx53_loco-enable-mc34708-s-WDI-functio.patch
+++ /dev/null
@@ -1,48 +0,0 @@
1From 8cece584b73434c1eb76a553424ff5b875fd1022 Mon Sep 17 00:00:00 2001
2From: Robin Gong <B38343@freescale.com>
3Date: Sat, 8 Oct 2011 11:17:42 +0800
4Subject: [PATCH] ENGR00155891 mx53_loco: enable mc34708's WDI function and pin configuration
5
6Because of reboot failure, we add mc34708's WDI reset function and the pin's
7mux function when system reboot. So mc34708 will be reset when AP reboot.
8Signed-off-by: Robin Gong <B38343@freescale.com>
9(cherry picked from commit 8e03278824625e8d528e129ad49e094e4d533f87)
10---
11 arch/arm/mach-mx5/mx53_loco_pmic_mc34708.c | 5 +++++
12 arch/arm/plat-mxc/system.c | 4 ++++
13 2 files changed, 9 insertions(+), 0 deletions(-)
14
15diff --git a/arch/arm/mach-mx5/mx53_loco_pmic_mc34708.c b/arch/arm/mach-mx5/mx53_loco_pmic_mc34708.c
16index ca5a052..3ad0206 100644
17--- a/arch/arm/mach-mx5/mx53_loco_pmic_mc34708.c
18+++ b/arch/arm/mach-mx5/mx53_loco_pmic_mc34708.c
19@@ -285,6 +285,11 @@ static int mc34708_regulator_init(struct mc34708 *mc34708)
20 value &= ~SWHOLD_MASK;
21 pmic_write_reg(REG_MC34708_USB_CONTROL, value, 0xffffff);
22
23+ /* enable WDI reset*/
24+ pmic_read_reg(REG_MC34708_POWER_CTL2, &value, 0xffffff);
25+ value |= 0x1000;
26+ pmic_write_reg(REG_MC34708_POWER_CTL2, value, 0xffffff);
27+
28 mc34708_register_regulator(mc34708, MC34708_SW1A, &sw1a_init);
29 mc34708_register_regulator(mc34708, MC34708_SW1B, &sw1b_init);
30 mc34708_register_regulator(mc34708, MC34708_SW2, &sw2_init);
31diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
32index e4665a2..4f21d5c 100644
33--- a/arch/arm/plat-mxc/system.c
34+++ b/arch/arm/plat-mxc/system.c
35@@ -78,6 +78,10 @@ void arch_reset(char mode, const char *cmd)
36 }
37
38 /* Assert SRS signal */
39+#ifdef CONFIG_ARCH_MX5
40+ if (board_is_mx53_loco_mc34708()) /*only for mx53_loco_mc34708*/
41+ mxc_iomux_v3_setup_pad(MX53_PAD_GPIO_9__WDOG1_WDOG_B);
42+#endif
43 __raw_writew(wcr_enable, wdog_base);
44
45 /* wait for reset to assert... */
46--
471.5.4.4
48
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1133-ENGR00159010-IPUv3-Restore-IDMAC_CH_LOCK_EN_1-for-re.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1133-ENGR00159010-IPUv3-Restore-IDMAC_CH_LOCK_EN_1-for-re.patch
deleted file mode 100755
index 0fc04f6c9..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1133-ENGR00159010-IPUv3-Restore-IDMAC_CH_LOCK_EN_1-for-re.patch
+++ /dev/null
@@ -1,32 +0,0 @@
1From 3d739cd79c28ea5d633a3f64758570b16260df69 Mon Sep 17 00:00:00 2001
2From: Liu Ying <Ying.Liu@freescale.com>
3Date: Sat, 8 Oct 2011 13:30:15 +0800
4Subject: [PATCH] ENGR00159010 IPUv3:Restore IDMAC_CH_LOCK_EN_1 for resume
5
6This patch restores IDMAC_CH_LOCK_EN_1 register when IPUv3
7driver resumes. This avoid the relative issue if setting
8IDMAC_CH_LOCK_EN_1 to be zero.
9
10Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
11(cherry picked from commit fce84cf35dcb338886df8e58f66a7ad1048d2abe)
12---
13 drivers/mxc/ipu3/ipu_common.c | 3 +++
14 1 files changed, 3 insertions(+), 0 deletions(-)
15
16diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
17index 4b12905..1f5ed8b 100644
18--- a/drivers/mxc/ipu3/ipu_common.c
19+++ b/drivers/mxc/ipu3/ipu_common.c
20@@ -2780,6 +2780,9 @@ static int ipu_resume(struct platform_device *pdev)
21
22 /* Set sync refresh channels as high priority */
23 __raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
24+
25+ /* AXI burst setting for sync refresh channels */
26+ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
27 clk_disable(g_ipu_clk);
28 }
29 mutex_unlock(&ipu_clk_lock);
30--
311.5.4.4
32
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1134-ENGR00159738-v4l2-correct-wrong-parameter-when-V4l2.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1134-ENGR00159738-v4l2-correct-wrong-parameter-when-V4l2.patch
deleted file mode 100755
index 66711688f..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1134-ENGR00159738-v4l2-correct-wrong-parameter-when-V4l2.patch
+++ /dev/null
@@ -1,29 +0,0 @@
1From 0fd61785f56c2785b471e1d2dd1071a480380c3f Mon Sep 17 00:00:00 2001
2From: Yuxi Sun <b36102@freescale.com>
3Date: Wed, 12 Oct 2011 12:17:02 +0800
4Subject: [PATCH] ENGR00159738 v4l2: correct wrong parameter when V4l2 set window size
5
6Correct wrong parameter when call ipu_csi_set_window_size function
7
8Signed-off-by: Yuxi Sun <b36102@freescale.com>
9(cherry picked from commit c1cb33e5cbebb979967f74eecf55efe6a83884ab)
10---
11 drivers/media/video/mxc/capture/mxc_v4l2_capture.c | 2 +-
12 1 files changed, 1 insertions(+), 1 deletions(-)
13
14diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
15index ded1839..c030a39 100644
16--- a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
17+++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
18@@ -1594,7 +1594,7 @@ static int mxc_v4l_open(struct file *file)
19 pr_debug("On Open: Input to ipu size is %d x %d\n",
20 cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height);
21 ipu_csi_set_window_size(cam->crop_current.width,
22- cam->crop_current.width,
23+ cam->crop_current.height,
24 cam->csi);
25 ipu_csi_set_window_pos(cam->crop_current.left,
26 cam->crop_current.top,
27--
281.5.4.4
29
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1135-ENGR00160566-IPUv3-Improve-IDMAC_LOCK_EN-setting.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1135-ENGR00160566-IPUv3-Improve-IDMAC_LOCK_EN-setting.patch
deleted file mode 100755
index 4debc1a56..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1135-ENGR00160566-IPUv3-Improve-IDMAC_LOCK_EN-setting.patch
+++ /dev/null
@@ -1,70 +0,0 @@
1From 8deffb95c405d2dde68da4d2570e57b6f2ec8ae5 Mon Sep 17 00:00:00 2001
2From: Liu Ying <Ying.Liu@freescale.com>
3Date: Tue, 25 Oct 2011 14:16:30 +0800
4Subject: [PATCH] ENGR00160566 IPUv3:Improve IDMAC_LOCK_EN setting
5
61) Clear IDMAC_LOCK_EN when dual display is enabled
7 to workaround black flash issue when playing video
8 on DP-FG.
92) Only set IDMAC_LOCK_EN for IPUv3M.
10
11Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
12(cherry picked from commit 7c22da39601cfc6551292cbd2c5c1d9ee3b4fbfa)
13---
14 drivers/mxc/ipu3/ipu_common.c | 19 +++++++++++++++++--
15 1 files changed, 17 insertions(+), 2 deletions(-)
16
17diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
18index 1f5ed8b..baf22dd 100644
19--- a/drivers/mxc/ipu3/ipu_common.c
20+++ b/drivers/mxc/ipu3/ipu_common.c
21@@ -386,7 +386,8 @@ static int ipu_probe(struct platform_device *pdev)
22 __raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
23
24 /* AXI burst setting for sync refresh channels */
25- __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
26+ if (g_ipu_hw_rev == 3)
27+ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
28
29 /* Set MCU_T to divide MCU access window into 2 */
30 __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
31@@ -989,6 +990,11 @@ void ipu_uninit_channel(ipu_channel_t channel)
32
33 __raw_writel(ipu_conf, IPU_CONF);
34
35+ /* Restore IDMAC_LOCK_EN when we don't use dual display */
36+ if (!(ipu_di_use_count[0] && ipu_di_use_count[1]) &&
37+ _ipu_is_dmfc_chan(in_dma) && g_ipu_hw_rev == 3)
38+ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
39+
40 spin_unlock_irqrestore(&ipu_lock, lock_flags);
41
42 ipu_put_clk();
43@@ -1800,6 +1806,14 @@ int32_t ipu_enable_channel(ipu_channel_t channel)
44 ipu_conf |= IPU_CONF_SMFC_EN;
45 __raw_writel(ipu_conf, IPU_CONF);
46
47+ /* Clear IDMAC_LOCK_EN to workaround black flash for dual display */
48+ if (g_ipu_hw_rev == 3 && _ipu_is_dmfc_chan(in_dma)) {
49+ if (ipu_di_use_count[1] && ipu_di_use_count[0])
50+ __raw_writel(0x0, IDMAC_CH_LOCK_EN_1);
51+ else
52+ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
53+ }
54+
55 if (idma_is_valid(in_dma)) {
56 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
57 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
58@@ -2782,7 +2796,8 @@ static int ipu_resume(struct platform_device *pdev)
59 __raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
60
61 /* AXI burst setting for sync refresh channels */
62- __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
63+ if (g_ipu_hw_rev == 3)
64+ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
65 clk_disable(g_ipu_clk);
66 }
67 mutex_unlock(&ipu_clk_lock);
68--
691.5.4.4
70
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1136-ENGR00161215-1-arch-arm-Add-two-new-IOCTLs-in-mxc_v.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1136-ENGR00161215-1-arch-arm-Add-two-new-IOCTLs-in-mxc_v.patch
deleted file mode 100755
index dbe92f4a1..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1136-ENGR00161215-1-arch-arm-Add-two-new-IOCTLs-in-mxc_v.patch
+++ /dev/null
@@ -1,33 +0,0 @@
1From 3083ae11d58fb7a083663865020c0a763540532b Mon Sep 17 00:00:00 2001
2From: Sammy He <r62914@freescale.com>
3Date: Wed, 2 Nov 2011 20:02:35 +0800
4Subject: [PATCH] ENGR00161215-1 arch/arm: Add two new IOCTLs in mxc_vpu.h
5
6Add IOCTL VPU_IOC_QUERY_BITWORK_MEM and VPU_IOC_SET_BITWORK_MEM
7for vpu driver.
8The two ioctls can be used when user allocates working buffer
9from user space, for exmaple, allocating it from pmem interface
10on android, then register it to vpu driver.
11
12Signed-off-by: Sammy He <r62914@freescale.com>
13(cherry picked from commit ad29cb1c2ad8ca4bbb30ff2ff55a4e8888b08373)
14---
15 arch/arm/plat-mxc/include/mach/mxc_vpu.h | 2 ++
16 1 files changed, 2 insertions(+), 0 deletions(-)
17
18diff --git a/arch/arm/plat-mxc/include/mach/mxc_vpu.h b/arch/arm/plat-mxc/include/mach/mxc_vpu.h
19index 355a9ef..32865e5 100644
20--- a/arch/arm/plat-mxc/include/mach/mxc_vpu.h
21+++ b/arch/arm/plat-mxc/include/mach/mxc_vpu.h
22@@ -48,6 +48,8 @@ struct vpu_mem_desc {
23 #define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 9)
24 #define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11)
25 #define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12)
26+#define VPU_IOC_QUERY_BITWORK_MEM _IO(VPU_IOC_MAGIC, 13)
27+#define VPU_IOC_SET_BITWORK_MEM _IO(VPU_IOC_MAGIC, 14)
28
29 #define BIT_CODE_RUN 0x000
30 #define BIT_CODE_DOWN 0x004
31--
321.5.4.4
33
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1137-ENGR00161215-2-vpu-Add-ioctls-for-querying-and-sett.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1137-ENGR00161215-2-vpu-Add-ioctls-for-querying-and-sett.patch
deleted file mode 100755
index b26260ac4..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1137-ENGR00161215-2-vpu-Add-ioctls-for-querying-and-sett.patch
+++ /dev/null
@@ -1,49 +0,0 @@
1From 9ca7a0b9b98e41c543bd328469e213b89251d470 Mon Sep 17 00:00:00 2001
2From: Sammy He <r62914@freescale.com>
3Date: Wed, 2 Nov 2011 20:08:42 +0800
4Subject: [PATCH] ENGR00161215-2 vpu: Add ioctls for querying and setting bitwork memory
5
6Add VPU_IOC_QUERY_BITWORK_MEM and VPU_IOC_SET_BITWORK_MEM ioctls
7implementation for registerring bitwork memory allocated from user
8space to vpu driver.
9
10Signed-off-by: Sammy He <r62914@freescale.com>
11(cherry picked from commit 98d71e85dbd05df9c866d153a4ead9526a26422e)
12---
13 drivers/mxc/vpu/mxc_vpu.c | 20 ++++++++++++++++++++
14 1 files changed, 20 insertions(+), 0 deletions(-)
15
16diff --git a/drivers/mxc/vpu/mxc_vpu.c b/drivers/mxc/vpu/mxc_vpu.c
17index 41bd188..00f164a 100644
18--- a/drivers/mxc/vpu/mxc_vpu.c
19+++ b/drivers/mxc/vpu/mxc_vpu.c
20@@ -446,6 +446,26 @@ static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd,
21 }
22 break;
23 }
24+ /*
25+ * The following two ioctl is used when user allocates working buffer
26+ * and register it to vpu driver.
27+ */
28+ case VPU_IOC_QUERY_BITWORK_MEM:
29+ {
30+ if (copy_to_user((void __user *)arg,
31+ &bitwork_mem,
32+ sizeof(struct vpu_mem_desc)))
33+ ret = -EFAULT;
34+ break;
35+ }
36+ case VPU_IOC_SET_BITWORK_MEM:
37+ {
38+ if (copy_from_user(&bitwork_mem,
39+ (struct vpu_mem_desc *)arg,
40+ sizeof(struct vpu_mem_desc)))
41+ ret = -EFAULT;
42+ break;
43+ }
44 case VPU_IOC_SYS_SW_RESET:
45 {
46 if (vpu_plat->reset)
47--
481.5.4.4
49
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1138-ENGR00162195-IPUv3M-Clear-IDMAC_LOCK_EN_1-for-tough.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1138-ENGR00162195-IPUv3M-Clear-IDMAC_LOCK_EN_1-for-tough.patch
deleted file mode 100755
index 27bac664a..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1138-ENGR00162195-IPUv3M-Clear-IDMAC_LOCK_EN_1-for-tough.patch
+++ /dev/null
@@ -1,43 +0,0 @@
1From f19b8f13079c5593c31a5eb381ba5ac734779f84 Mon Sep 17 00:00:00 2001
2From: Liu Ying <Ying.Liu@freescale.com>
3Date: Tue, 15 Nov 2011 16:21:25 +0800
4Subject: [PATCH] ENGR00162195 IPUv3M:Clear IDMAC_LOCK_EN_1 for tough single display
5
6This patch clears IDMAC_LOCK_EN_1 for tough single display(dmfc=3).
7For example, 1080P50/1080P60 with 32bpp fb.
8
9Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
10(cherry picked from commit 204a5fb6af1426c499332224dff00f52bdbef39b)
11---
12 drivers/mxc/ipu3/ipu_common.c | 6 +++++-
13 1 files changed, 5 insertions(+), 1 deletions(-)
14
15diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
16index baf22dd..18d46b3 100644
17--- a/drivers/mxc/ipu3/ipu_common.c
18+++ b/drivers/mxc/ipu3/ipu_common.c
19@@ -991,7 +991,9 @@ void ipu_uninit_channel(ipu_channel_t channel)
20 __raw_writel(ipu_conf, IPU_CONF);
21
22 /* Restore IDMAC_LOCK_EN when we don't use dual display */
23+ /* and the video mode for single display is not tough */
24 if (!(ipu_di_use_count[0] && ipu_di_use_count[1]) &&
25+ dmfc_type_setup != DMFC_HIGH_RESOLUTION_ONLY_DP &&
26 _ipu_is_dmfc_chan(in_dma) && g_ipu_hw_rev == 3)
27 __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
28
29@@ -1807,8 +1809,10 @@ int32_t ipu_enable_channel(ipu_channel_t channel)
30 __raw_writel(ipu_conf, IPU_CONF);
31
32 /* Clear IDMAC_LOCK_EN to workaround black flash for dual display */
33+ /* and for tough video mode of single display */
34 if (g_ipu_hw_rev == 3 && _ipu_is_dmfc_chan(in_dma)) {
35- if (ipu_di_use_count[1] && ipu_di_use_count[0])
36+ if ((ipu_di_use_count[1] && ipu_di_use_count[0]) ||
37+ (dmfc_type_setup == DMFC_HIGH_RESOLUTION_ONLY_DP))
38 __raw_writel(0x0, IDMAC_CH_LOCK_EN_1);
39 else
40 __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
41--
421.5.4.4
43
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1139-ENGR00162464-update-pm4-microcode-pm4_microcode_r18.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1139-ENGR00162464-update-pm4-microcode-pm4_microcode_r18.patch
deleted file mode 100755
index b880c2b5f..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1139-ENGR00162464-update-pm4-microcode-pm4_microcode_r18.patch
+++ /dev/null
@@ -1,820 +0,0 @@
1From 10841bda9560f6a5b5581f9a2df3760cf6ee8c17 Mon Sep 17 00:00:00 2001
2From: Richard Zhao <richard.zhao@freescale.com>
3Date: Fri, 18 Nov 2011 10:33:10 +0800
4Subject: [PATCH] ENGR00162464 update pm4 microcode: pm4_microcode_r18_20111020.a.inl.rel
5
6It fix gpu hang.
7
8Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
9(cherry picked from commit acc00a6f1847bf8cdde1802b4375dc89d5160dfe)
10---
11 drivers/mxc/amd-gpu/common/pm4_microcode.inl | 371 +++++++++++++-------------
12 1 files changed, 186 insertions(+), 185 deletions(-)
13
14diff --git a/drivers/mxc/amd-gpu/common/pm4_microcode.inl b/drivers/mxc/amd-gpu/common/pm4_microcode.inl
15index aa7c9fc..058548b 100644
16--- a/drivers/mxc/amd-gpu/common/pm4_microcode.inl
17+++ b/drivers/mxc/amd-gpu/common/pm4_microcode.inl
18@@ -1,4 +1,4 @@
19-/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved.
20+/* Copyright (c) 2008-2011, QUALCOMM Incorporated. All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24@@ -26,12 +26,14 @@
25 *
26 */
27
28+// Microcode Source Version 20111020.a
29+
30 #ifndef PM4_MICROCODE_H
31 #define PM4_MICROCODE_H
32
33-#define PM4_MICROCODE_VERSION 322696
34+#define PM4_MICROCODE_VERSION 422468
35
36-#define PM4_MICROCODE_SIZE 768
37+#define PM4_MICROCODE_SIZE 768 // Size of PM4 microcode in QWORD
38
39
40 #ifdef _PRIMLIB_INCLUDE
41@@ -47,20 +49,20 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
42 { 0x00000000, 0xd9004800, 0x000 },
43 { 0x00000000, 0x00400000, 0x000 },
44 { 0x00000000, 0x34e00000, 0x000 },
45- { 0x00000000, 0x00600000, 0x28c },
46+ { 0x00000000, 0x00600000, 0x287 },
47 { 0x0000ffff, 0xc0280a20, 0x000 },
48 { 0x00000000, 0x00294582, 0x000 },
49 { 0x00000000, 0xd9004800, 0x000 },
50 { 0x00000000, 0x00400000, 0x000 },
51- { 0x00000000, 0x00600000, 0x28c },
52+ { 0x00000000, 0x00600000, 0x287 },
53 { 0x0000ffff, 0xc0284620, 0x000 },
54 { 0x00000000, 0xd9004800, 0x000 },
55 { 0x00000000, 0x00400000, 0x000 },
56- { 0x00000000, 0x00600000, 0x2b0 },
57+ { 0x00000000, 0x00600000, 0x2ac },
58 { 0x00000000, 0xc0200c00, 0x000 },
59 { 0x000021fc, 0x0029462c, 0x000 },
60 { 0x00000000, 0x00404803, 0x021 },
61- { 0x00000000, 0x00600000, 0x2b0 },
62+ { 0x00000000, 0x00600000, 0x2ac },
63 { 0x00000000, 0xc0200000, 0x000 },
64 { 0x00000000, 0xc0200c00, 0x000 },
65 { 0x000021fc, 0x0029462c, 0x000 },
66@@ -78,7 +80,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
67 { 0x0000000e, 0x00404811, 0x000 },
68 { 0x00000394, 0x00204411, 0x000 },
69 { 0x00000001, 0xc0404811, 0x000 },
70- { 0x00000000, 0x00600000, 0x2b0 },
71+ { 0x00000000, 0x00600000, 0x2ac },
72 { 0x000021f9, 0x0029462c, 0x000 },
73 { 0x00000008, 0xc0210a20, 0x000 },
74 { 0x00000000, 0x14e00000, 0x02d },
75@@ -88,53 +90,48 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
76 { 0x0000001b, 0x002f0222, 0x000 },
77 { 0x00000000, 0x0ce00000, 0x043 },
78 { 0x00000002, 0x002f0222, 0x000 },
79- { 0x00000000, 0x0ce00000, 0x04a },
80+ { 0x00000000, 0x0ce00000, 0x045 },
81 { 0x00000003, 0x002f0222, 0x000 },
82- { 0x00000000, 0x0ce00000, 0x051 },
83+ { 0x00000000, 0x0ce00000, 0x047 },
84 { 0x00000004, 0x002f0222, 0x000 },
85- { 0x00000000, 0x0ce00000, 0x058 },
86+ { 0x00000000, 0x0ce00000, 0x049 },
87 { 0x00000014, 0x002f0222, 0x000 },
88- { 0x00000000, 0x0ce00000, 0x058 },
89+ { 0x00000000, 0x0ce00000, 0x049 },
90 { 0x00000015, 0x002f0222, 0x000 },
91- { 0x00000000, 0x0ce00000, 0x060 },
92+ { 0x00000000, 0x0ce00000, 0x05b },
93 { 0x000021f9, 0x0029462c, 0x000 },
94 { 0x00000000, 0xc0404802, 0x000 },
95 { 0x0000001f, 0x40280a20, 0x000 },
96 { 0x0000001b, 0x002f0222, 0x000 },
97 { 0x00000000, 0x0ce00000, 0x043 },
98 { 0x00000002, 0x002f0222, 0x000 },
99- { 0x00000000, 0x0ce00000, 0x04a },
100- { 0x00000000, 0x00400000, 0x051 },
101+ { 0x00000000, 0x0ce00000, 0x045 },
102+ { 0x00000000, 0x00400000, 0x047 },
103 { 0x0000001f, 0xc0210e20, 0x000 },
104- { 0x00000612, 0x00204411, 0x000 },
105- { 0x00000000, 0x00204803, 0x000 },
106- { 0x00000000, 0xc0204800, 0x000 },
107- { 0x00000000, 0xc0204800, 0x000 },
108- { 0x000021f9, 0x0029462c, 0x000 },
109- { 0x00000000, 0x00404802, 0x000 },
110+ { 0x00000612, 0x00404411, 0x04c },
111 { 0x0000001e, 0xc0210e20, 0x000 },
112- { 0x00000600, 0x00204411, 0x000 },
113- { 0x00000000, 0x00204803, 0x000 },
114- { 0x00000000, 0xc0204800, 0x000 },
115- { 0x00000000, 0xc0204800, 0x000 },
116- { 0x000021f9, 0x0029462c, 0x000 },
117- { 0x00000000, 0x00404802, 0x000 },
118+ { 0x00000600, 0x00404411, 0x04c },
119 { 0x0000001e, 0xc0210e20, 0x000 },
120- { 0x00000605, 0x00204411, 0x000 },
121- { 0x00000000, 0x00204803, 0x000 },
122- { 0x00000000, 0xc0204800, 0x000 },
123- { 0x00000000, 0xc0204800, 0x000 },
124- { 0x000021f9, 0x0029462c, 0x000 },
125- { 0x00000000, 0x00404802, 0x000 },
126+ { 0x00000605, 0x00404411, 0x04c },
127 { 0x0000001f, 0x40280a20, 0x000 },
128 { 0x0000001f, 0xc0210e20, 0x000 },
129 { 0x0000060a, 0x00204411, 0x000 },
130 { 0x00000000, 0x00204803, 0x000 },
131- { 0x00000000, 0xc0204800, 0x000 },
132- { 0x00000000, 0xc0204800, 0x000 },
133+ { 0x00000000, 0xc0201000, 0x000 },
134+ { 0x00000000, 0x00204804, 0x000 },
135+ { 0x00000000, 0xc0200c00, 0x000 },
136+ { 0x00000000, 0x00204803, 0x000 },
137+ { 0x00000080, 0x00201c11, 0x000 },
138 { 0x000021f9, 0x0029462c, 0x000 },
139- { 0x00000000, 0x00404802, 0x000 },
140- { 0x0000001f, 0xc0680a20, 0x2b0 },
141+ { 0x00000000, 0x00204802, 0x000 },
142+ { 0x00000000, 0x00600000, 0x130 },
143+ { 0x00000000, 0x002f0070, 0x000 },
144+ { 0x00000000, 0x0ce00000, 0x000 },
145+ { 0x00000001, 0x00331e27, 0x000 },
146+ { 0x00000000, 0x002f0227, 0x000 },
147+ { 0x00000000, 0x0ae00000, 0x054 },
148+ { 0x00000000, 0x00400000, 0x051 },
149+ { 0x0000001f, 0xc0680a20, 0x2ac },
150 { 0x000021f9, 0x0029462c, 0x000 },
151 { 0x00000000, 0x00404802, 0x000 },
152 { 0x8100ffff, 0x00204411, 0x000 },
153@@ -142,24 +139,24 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
154 { 0x00001fff, 0x40280a20, 0x000 },
155 { 0x80000000, 0x40280e20, 0x000 },
156 { 0x40000000, 0xc0281220, 0x000 },
157- { 0x00040000, 0x00694622, 0x2ba },
158+ { 0x00040000, 0x00694622, 0x2b4 },
159 { 0x00000000, 0x00201410, 0x000 },
160 { 0x00000000, 0x002f0223, 0x000 },
161- { 0x00000000, 0x0ae00000, 0x06d },
162- { 0x00000000, 0xc0401800, 0x070 },
163+ { 0x00000000, 0x0ae00000, 0x068 },
164+ { 0x00000000, 0xc0401800, 0x06b },
165 { 0x00001fff, 0xc0281a20, 0x000 },
166- { 0x00040000, 0x00694626, 0x2ba },
167+ { 0x00040000, 0x00694626, 0x2b4 },
168 { 0x00000000, 0x00201810, 0x000 },
169 { 0x00000000, 0x002f0224, 0x000 },
170- { 0x00000000, 0x0ae00000, 0x073 },
171- { 0x00000000, 0xc0401c00, 0x076 },
172+ { 0x00000000, 0x0ae00000, 0x06e },
173+ { 0x00000000, 0xc0401c00, 0x071 },
174 { 0x00001fff, 0xc0281e20, 0x000 },
175- { 0x00040000, 0x00694627, 0x2ba },
176+ { 0x00040000, 0x00694627, 0x2b4 },
177 { 0x00000000, 0x00201c10, 0x000 },
178 { 0x00000000, 0x00204402, 0x000 },
179 { 0x00000000, 0x002820c5, 0x000 },
180 { 0x00000000, 0x004948e8, 0x000 },
181- { 0x00000000, 0x00600000, 0x28c },
182+ { 0x00000000, 0x00600000, 0x287 },
183 { 0x00000010, 0x40210a20, 0x000 },
184 { 0x000000ff, 0x00280a22, 0x000 },
185 { 0x000007ff, 0x40280e20, 0x000 },
186@@ -167,25 +164,25 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
187 { 0x00000005, 0xc0211220, 0x000 },
188 { 0x00080000, 0x00281224, 0x000 },
189 { 0x00000013, 0x00210224, 0x000 },
190- { 0x00000000, 0x14c00000, 0x084 },
191+ { 0x00000000, 0x14c00000, 0x07f },
192 { 0xa100ffff, 0x00204411, 0x000 },
193 { 0x00000000, 0x00204811, 0x000 },
194 { 0x00000000, 0x002f0222, 0x000 },
195- { 0x00000000, 0x0ae00000, 0x088 },
196+ { 0x00000000, 0x0ae00000, 0x083 },
197 { 0x00000000, 0x0020162d, 0x000 },
198- { 0x00004000, 0x00500e23, 0x097 },
199+ { 0x00004000, 0x00500e23, 0x092 },
200 { 0x00000001, 0x002f0222, 0x000 },
201- { 0x00000000, 0x0ae00000, 0x08c },
202+ { 0x00000000, 0x0ae00000, 0x087 },
203 { 0x00000001, 0x0020162d, 0x000 },
204- { 0x00004800, 0x00500e23, 0x097 },
205+ { 0x00004800, 0x00500e23, 0x092 },
206 { 0x00000002, 0x002f0222, 0x000 },
207- { 0x00000000, 0x0ae00000, 0x090 },
208+ { 0x00000000, 0x0ae00000, 0x08b },
209 { 0x00000003, 0x0020162d, 0x000 },
210- { 0x00004900, 0x00500e23, 0x097 },
211+ { 0x00004900, 0x00500e23, 0x092 },
212 { 0x00000003, 0x002f0222, 0x000 },
213- { 0x00000000, 0x0ae00000, 0x094 },
214+ { 0x00000000, 0x0ae00000, 0x08f },
215 { 0x00000002, 0x0020162d, 0x000 },
216- { 0x00004908, 0x00500e23, 0x097 },
217+ { 0x00004908, 0x00500e23, 0x092 },
218 { 0x00000012, 0x0020162d, 0x000 },
219 { 0x00002000, 0x00300e23, 0x000 },
220 { 0x00000000, 0x00290d83, 0x000 },
221@@ -200,7 +197,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
222 { 0x00000000, 0x002948e5, 0x000 },
223 { 0x9300ffff, 0x00204411, 0x000 },
224 { 0x00000000, 0x00404806, 0x000 },
225- { 0x00000000, 0x00600000, 0x28c },
226+ { 0x00000000, 0x00600000, 0x287 },
227 { 0x00000000, 0xc0200800, 0x000 },
228 { 0x00000000, 0xc0201400, 0x000 },
229 { 0x0000001f, 0x00211a25, 0x000 },
230@@ -209,31 +206,31 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
231 { 0x00000010, 0x00211225, 0x000 },
232 { 0x8300ffff, 0x00204411, 0x000 },
233 { 0x00000000, 0x002f0224, 0x000 },
234- { 0x00000000, 0x0ae00000, 0x0ae },
235+ { 0x00000000, 0x0ae00000, 0x0a9 },
236 { 0x00000000, 0x00203622, 0x000 },
237- { 0x00004000, 0x00504a23, 0x0bd },
238+ { 0x00004000, 0x00504a23, 0x0b8 },
239 { 0x00000001, 0x002f0224, 0x000 },
240- { 0x00000000, 0x0ae00000, 0x0b2 },
241+ { 0x00000000, 0x0ae00000, 0x0ad },
242 { 0x00000001, 0x00203622, 0x000 },
243- { 0x00004800, 0x00504a23, 0x0bd },
244+ { 0x00004800, 0x00504a23, 0x0b8 },
245 { 0x00000002, 0x002f0224, 0x000 },
246- { 0x00000000, 0x0ae00000, 0x0b6 },
247+ { 0x00000000, 0x0ae00000, 0x0b1 },
248 { 0x00000003, 0x00203622, 0x000 },
249- { 0x00004900, 0x00504a23, 0x0bd },
250+ { 0x00004900, 0x00504a23, 0x0b8 },
251 { 0x00000003, 0x002f0224, 0x000 },
252- { 0x00000000, 0x0ae00000, 0x0ba },
253+ { 0x00000000, 0x0ae00000, 0x0b5 },
254 { 0x00000002, 0x00203622, 0x000 },
255- { 0x00004908, 0x00504a23, 0x0bd },
256+ { 0x00004908, 0x00504a23, 0x0b8 },
257 { 0x00000012, 0x00203622, 0x000 },
258 { 0x00000000, 0x00290d83, 0x000 },
259 { 0x00002000, 0x00304a23, 0x000 },
260 { 0x8400ffff, 0x00204411, 0x000 },
261 { 0x00000000, 0xc0204800, 0x000 },
262 { 0x00000000, 0x21000000, 0x000 },
263- { 0x00000000, 0x00400000, 0x0a4 },
264+ { 0x00000000, 0x00400000, 0x09f },
265 { 0x8100ffff, 0x00204411, 0x000 },
266 { 0x00000001, 0x00204811, 0x000 },
267- { 0x00040578, 0x00604411, 0x2ba },
268+ { 0x00040578, 0x00604411, 0x2b4 },
269 { 0x00000000, 0xc0400000, 0x000 },
270 { 0x00000000, 0xc0200c00, 0x000 },
271 { 0x00000000, 0xc0201000, 0x000 },
272@@ -241,62 +238,62 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
273 { 0x00000000, 0xc0201800, 0x000 },
274 { 0x00007f00, 0x00280a21, 0x000 },
275 { 0x00004500, 0x002f0222, 0x000 },
276- { 0x00000000, 0x0ce00000, 0x0cd },
277+ { 0x00000000, 0x0ce00000, 0x0c8 },
278 { 0x00000000, 0xc0201c00, 0x000 },
279 { 0x00000000, 0x17000000, 0x000 },
280 { 0x00000010, 0x00280a23, 0x000 },
281 { 0x00000010, 0x002f0222, 0x000 },
282- { 0x00000000, 0x0ce00000, 0x0d5 },
283+ { 0x00000000, 0x0ce00000, 0x0d0 },
284 { 0x8100ffff, 0x00204411, 0x000 },
285 { 0x00000001, 0x00204811, 0x000 },
286- { 0x00040000, 0x00694624, 0x2ba },
287- { 0x00000000, 0x00400000, 0x0d6 },
288- { 0x00000000, 0x00600000, 0x135 },
289+ { 0x00040000, 0x00694624, 0x2b4 },
290+ { 0x00000000, 0x00400000, 0x0d1 },
291+ { 0x00000000, 0x00600000, 0x130 },
292 { 0x00000000, 0x002820d0, 0x000 },
293 { 0x00000007, 0x00280a23, 0x000 },
294 { 0x00000001, 0x002f0222, 0x000 },
295- { 0x00000000, 0x0ae00000, 0x0dd },
296+ { 0x00000000, 0x0ae00000, 0x0d8 },
297 { 0x00000000, 0x002f00a8, 0x000 },
298- { 0x00000000, 0x04e00000, 0x0f6 },
299- { 0x00000000, 0x00400000, 0x0fd },
300+ { 0x00000000, 0x04e00000, 0x0f1 },
301+ { 0x00000000, 0x00400000, 0x0f8 },
302 { 0x00000002, 0x002f0222, 0x000 },
303- { 0x00000000, 0x0ae00000, 0x0e2 },
304+ { 0x00000000, 0x0ae00000, 0x0dd },
305 { 0x00000000, 0x002f00a8, 0x000 },
306- { 0x00000000, 0x02e00000, 0x0f6 },
307- { 0x00000000, 0x00400000, 0x0fd },
308+ { 0x00000000, 0x02e00000, 0x0f1 },
309+ { 0x00000000, 0x00400000, 0x0f8 },
310 { 0x00000003, 0x002f0222, 0x000 },
311- { 0x00000000, 0x0ae00000, 0x0e7 },
312+ { 0x00000000, 0x0ae00000, 0x0e2 },
313 { 0x00000000, 0x002f00a8, 0x000 },
314- { 0x00000000, 0x0ce00000, 0x0f6 },
315- { 0x00000000, 0x00400000, 0x0fd },
316+ { 0x00000000, 0x0ce00000, 0x0f1 },
317+ { 0x00000000, 0x00400000, 0x0f8 },
318 { 0x00000004, 0x002f0222, 0x000 },
319- { 0x00000000, 0x0ae00000, 0x0ec },
320+ { 0x00000000, 0x0ae00000, 0x0e7 },
321 { 0x00000000, 0x002f00a8, 0x000 },
322- { 0x00000000, 0x0ae00000, 0x0f6 },
323- { 0x00000000, 0x00400000, 0x0fd },
324- { 0x00000005, 0x002f0222, 0x000 },
325 { 0x00000000, 0x0ae00000, 0x0f1 },
326+ { 0x00000000, 0x00400000, 0x0f8 },
327+ { 0x00000005, 0x002f0222, 0x000 },
328+ { 0x00000000, 0x0ae00000, 0x0ec },
329 { 0x00000000, 0x002f00a8, 0x000 },
330- { 0x00000000, 0x06e00000, 0x0f6 },
331- { 0x00000000, 0x00400000, 0x0fd },
332+ { 0x00000000, 0x06e00000, 0x0f1 },
333+ { 0x00000000, 0x00400000, 0x0f8 },
334 { 0x00000006, 0x002f0222, 0x000 },
335- { 0x00000000, 0x0ae00000, 0x0f6 },
336+ { 0x00000000, 0x0ae00000, 0x0f1 },
337 { 0x00000000, 0x002f00a8, 0x000 },
338- { 0x00000000, 0x08e00000, 0x0f6 },
339- { 0x00000000, 0x00400000, 0x0fd },
340+ { 0x00000000, 0x08e00000, 0x0f1 },
341+ { 0x00000000, 0x00400000, 0x0f8 },
342 { 0x00007f00, 0x00280a21, 0x000 },
343 { 0x00004500, 0x002f0222, 0x000 },
344 { 0x00000000, 0x0ae00000, 0x000 },
345 { 0x00000008, 0x00210a23, 0x000 },
346- { 0x00000000, 0x14e00000, 0x11b },
347+ { 0x00000000, 0x14e00000, 0x116 },
348 { 0x00000000, 0xc0204400, 0x000 },
349 { 0x00000000, 0xc0404800, 0x000 },
350 { 0x00007f00, 0x00280a21, 0x000 },
351 { 0x00004500, 0x002f0222, 0x000 },
352- { 0x00000000, 0x0ae00000, 0x102 },
353+ { 0x00000000, 0x0ae00000, 0x0fd },
354 { 0x00000000, 0xc0200000, 0x000 },
355 { 0x00000000, 0xc0400000, 0x000 },
356- { 0x00000000, 0x00404c07, 0x0cd },
357+ { 0x00000000, 0x00404c07, 0x0c8 },
358 { 0x00000000, 0xc0201000, 0x000 },
359 { 0x00000000, 0xc0201400, 0x000 },
360 { 0x00000000, 0xc0201800, 0x000 },
361@@ -304,11 +301,11 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
362 { 0x00000000, 0x17000000, 0x000 },
363 { 0x8100ffff, 0x00204411, 0x000 },
364 { 0x00000001, 0x00204811, 0x000 },
365- { 0x00040000, 0x00694624, 0x2ba },
366+ { 0x00040000, 0x00694624, 0x2b4 },
367 { 0x00000000, 0x002820d0, 0x000 },
368 { 0x00000000, 0x002f00a8, 0x000 },
369 { 0x00000000, 0x0ce00000, 0x000 },
370- { 0x00000000, 0x00404c07, 0x107 },
371+ { 0x00000000, 0x00404c07, 0x102 },
372 { 0x00000000, 0xc0201000, 0x000 },
373 { 0x00000000, 0xc0201400, 0x000 },
374 { 0x00000000, 0xc0201800, 0x000 },
375@@ -316,11 +313,11 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
376 { 0x00000000, 0x17000000, 0x000 },
377 { 0x8100ffff, 0x00204411, 0x000 },
378 { 0x00000001, 0x00204811, 0x000 },
379- { 0x00040000, 0x00694624, 0x2ba },
380+ { 0x00040000, 0x00694624, 0x2b4 },
381 { 0x00000000, 0x002820d0, 0x000 },
382 { 0x00000000, 0x002f00a8, 0x000 },
383 { 0x00000000, 0x06e00000, 0x000 },
384- { 0x00000000, 0x00404c07, 0x113 },
385+ { 0x00000000, 0x00404c07, 0x10e },
386 { 0x0000060d, 0x00204411, 0x000 },
387 { 0x00000000, 0xc0204800, 0x000 },
388 { 0x0000860e, 0x00204411, 0x000 },
389@@ -335,13 +332,13 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
390 { 0x00000001, 0x00204811, 0x000 },
391 { 0x00000000, 0xc0200800, 0x000 },
392 { 0x00007fff, 0x00281a22, 0x000 },
393- { 0x00040000, 0x00694626, 0x2ba },
394+ { 0x00040000, 0x00694626, 0x2b4 },
395 { 0x00000000, 0x00200c10, 0x000 },
396 { 0x00000000, 0xc0201000, 0x000 },
397 { 0x80000000, 0x00281a22, 0x000 },
398 { 0x00000000, 0x002f0226, 0x000 },
399- { 0x00000000, 0x0ce00000, 0x132 },
400- { 0x00000000, 0x00600000, 0x135 },
401+ { 0x00000000, 0x0ce00000, 0x12d },
402+ { 0x00000000, 0x00600000, 0x130 },
403 { 0x00000000, 0x00201c10, 0x000 },
404 { 0x00000000, 0x00300c67, 0x000 },
405 { 0x0000060d, 0x00204411, 0x000 },
406@@ -353,10 +350,10 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
407 { 0x00000000, 0x00204811, 0x000 },
408 { 0x000001ea, 0x00204411, 0x000 },
409 { 0x00000000, 0x00204804, 0x000 },
410- { 0x00000000, 0x1ac00000, 0x13b },
411+ { 0x00000000, 0x1ac00000, 0x136 },
412 { 0x9e00ffff, 0x00204411, 0x000 },
413 { 0xdeadbeef, 0x00204811, 0x000 },
414- { 0x00000000, 0x1ae00000, 0x13e },
415+ { 0x00000000, 0x1ae00000, 0x139 },
416 { 0xa400ffff, 0x00204411, 0x000 },
417 { 0x00000000, 0x0080480b, 0x000 },
418 { 0x000001f3, 0x00204411, 0x000 },
419@@ -405,28 +402,28 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
420 { 0x00000001, 0x00303e2f, 0x000 },
421 { 0x00000000, 0xc0200800, 0x000 },
422 { 0x00000000, 0x002f0222, 0x000 },
423- { 0x00000000, 0x0ce00000, 0x172 },
424+ { 0x00000000, 0x0ce00000, 0x16d },
425 { 0x00000000, 0xd9000000, 0x000 },
426 { 0x00000000, 0x00400000, 0x000 },
427- { 0x00000000, 0x00600000, 0x28c },
428+ { 0x00000000, 0x00600000, 0x287 },
429 { 0x8100ffff, 0x00204411, 0x000 },
430 { 0x00000002, 0x00204811, 0x000 },
431 { 0x00000000, 0x002f0230, 0x000 },
432- { 0x00000000, 0x0ae00000, 0x175 },
433+ { 0x00000000, 0x0ae00000, 0x170 },
434 { 0x00000000, 0xc0200800, 0x000 },
435 { 0x00000009, 0x00210222, 0x000 },
436- { 0x00000000, 0x14c00000, 0x17d },
437- { 0x00000000, 0x00600000, 0x2b7 },
438+ { 0x00000000, 0x14c00000, 0x178 },
439+ { 0x00000000, 0x00600000, 0x2aa },
440 { 0x00000000, 0x00200c11, 0x000 },
441 { 0x00000016, 0x00203623, 0x000 },
442 { 0x00000000, 0x00210222, 0x000 },
443- { 0x00000000, 0x14c00000, 0x180 },
444+ { 0x00000000, 0x14c00000, 0x17b },
445 { 0x00000000, 0xc0200000, 0x000 },
446 { 0x00000001, 0x00210222, 0x000 },
447- { 0x00000000, 0x14c00000, 0x183 },
448+ { 0x00000000, 0x14c00000, 0x17e },
449 { 0x00000000, 0xc0200000, 0x000 },
450 { 0x00000002, 0x00210222, 0x000 },
451- { 0x00000000, 0x14c00000, 0x18d },
452+ { 0x00000000, 0x14c00000, 0x188 },
453 { 0x00000004, 0xc0203620, 0x000 },
454 { 0x00000005, 0xc0203620, 0x000 },
455 { 0x00000006, 0xc0203620, 0x000 },
456@@ -436,7 +433,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
457 { 0x0000000a, 0xc0203620, 0x000 },
458 { 0x0000000b, 0xc0203620, 0x000 },
459 { 0x00000003, 0x00210222, 0x000 },
460- { 0x00000000, 0x14c00000, 0x1b5 },
461+ { 0x00000000, 0x14c00000, 0x1b0 },
462 { 0x00000000, 0xc0200c00, 0x000 },
463 { 0x8c00ffff, 0x00204411, 0x000 },
464 { 0x00000000, 0x00204803, 0x000 },
465@@ -476,24 +473,24 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
466 { 0x00000003, 0x00384a27, 0x000 },
467 { 0x00300000, 0x00293a2e, 0x000 },
468 { 0x00000004, 0x00210222, 0x000 },
469- { 0x00000000, 0x14c00000, 0x1bd },
470+ { 0x00000000, 0x14c00000, 0x1b8 },
471 { 0xa300ffff, 0x00204411, 0x000 },
472 { 0x00000000, 0x40204800, 0x000 },
473 { 0x0000000a, 0xc0220e20, 0x000 },
474 { 0x00000011, 0x00203623, 0x000 },
475 { 0x000021f4, 0x00204411, 0x000 },
476- { 0x0000000a, 0x00614a2c, 0x2b7 },
477+ { 0x0000000a, 0x00614a2c, 0x2aa },
478 { 0x00000005, 0x00210222, 0x000 },
479- { 0x00000000, 0x14c00000, 0x1c0 },
480+ { 0x00000000, 0x14c00000, 0x1bb },
481 { 0x00000000, 0xc0200000, 0x000 },
482 { 0x00000006, 0x00210222, 0x000 },
483- { 0x00000000, 0x14c00000, 0x1c6 },
484+ { 0x00000000, 0x14c00000, 0x1c1 },
485 { 0x9c00ffff, 0x00204411, 0x000 },
486 { 0x0000001f, 0x40214a20, 0x000 },
487 { 0x9600ffff, 0x00204411, 0x000 },
488 { 0x00000000, 0xc0204800, 0x000 },
489 { 0x00000007, 0x00210222, 0x000 },
490- { 0x00000000, 0x14c00000, 0x1d0 },
491+ { 0x00000000, 0x14c00000, 0x1cb },
492 { 0x3fffffff, 0x00283a2e, 0x000 },
493 { 0xc0000000, 0x40280e20, 0x000 },
494 { 0x00000000, 0x0029386e, 0x000 },
495@@ -503,7 +500,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
496 { 0x00000000, 0xc0202c00, 0x000 },
497 { 0x00000000, 0x0020480b, 0x000 },
498 { 0x00000008, 0x00210222, 0x000 },
499- { 0x00000000, 0x14c00000, 0x1dc },
500+ { 0x00000000, 0x14c00000, 0x1d7 },
501 { 0x00000000, 0xc0200c00, 0x000 },
502 { 0x00000013, 0x00203623, 0x000 },
503 { 0x00000015, 0x00203623, 0x000 },
504@@ -515,7 +512,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
505 { 0xefffffff, 0x00283a2e, 0x000 },
506 { 0x00000000, 0x0029386e, 0x000 },
507 { 0x00000000, 0x00400000, 0x000 },
508- { 0x00000000, 0x00600000, 0x28c },
509+ { 0x00000000, 0x00600000, 0x287 },
510 { 0x00000000, 0xc0200800, 0x000 },
511 { 0x0000001f, 0x00210e22, 0x000 },
512 { 0x00000000, 0x14e00000, 0x000 },
513@@ -529,46 +526,46 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
514 { 0x8400ffff, 0x00204411, 0x000 },
515 { 0x00000000, 0x00204803, 0x000 },
516 { 0x00000000, 0x21000000, 0x000 },
517- { 0x00000000, 0x00400000, 0x1de },
518+ { 0x00000000, 0x00400000, 0x1d9 },
519 { 0x8200ffff, 0x00204411, 0x000 },
520 { 0x00000001, 0x00204811, 0x000 },
521 { 0x00000000, 0xc0200800, 0x000 },
522 { 0x00003fff, 0x40280e20, 0x000 },
523 { 0x00000010, 0xc0211220, 0x000 },
524 { 0x00000000, 0x002f0222, 0x000 },
525- { 0x00000000, 0x0ae00000, 0x1fb },
526- { 0x00000000, 0x2ae00000, 0x205 },
527+ { 0x00000000, 0x0ae00000, 0x1f6 },
528+ { 0x00000000, 0x2ae00000, 0x200 },
529 { 0x20000080, 0x00281e2e, 0x000 },
530 { 0x00000080, 0x002f0227, 0x000 },
531- { 0x00000000, 0x0ce00000, 0x1f8 },
532- { 0x00000000, 0x00401c0c, 0x1f9 },
533+ { 0x00000000, 0x0ce00000, 0x1f3 },
534+ { 0x00000000, 0x00401c0c, 0x1f4 },
535 { 0x00000010, 0x00201e2d, 0x000 },
536 { 0x000021f9, 0x00294627, 0x000 },
537- { 0x00000000, 0x00404811, 0x205 },
538+ { 0x00000000, 0x00404811, 0x200 },
539 { 0x00000001, 0x002f0222, 0x000 },
540- { 0x00000000, 0x0ae00000, 0x23a },
541- { 0x00000000, 0x28e00000, 0x205 },
542+ { 0x00000000, 0x0ae00000, 0x235 },
543+ { 0x00000000, 0x28e00000, 0x200 },
544 { 0x00800080, 0x00281e2e, 0x000 },
545 { 0x00000080, 0x002f0227, 0x000 },
546- { 0x00000000, 0x0ce00000, 0x202 },
547- { 0x00000000, 0x00401c0c, 0x203 },
548+ { 0x00000000, 0x0ce00000, 0x1fd },
549+ { 0x00000000, 0x00401c0c, 0x1fe },
550 { 0x00000010, 0x00201e2d, 0x000 },
551 { 0x000021f9, 0x00294627, 0x000 },
552 { 0x00000001, 0x00204811, 0x000 },
553 { 0x8100ffff, 0x00204411, 0x000 },
554 { 0x00000000, 0x002f0222, 0x000 },
555- { 0x00000000, 0x0ae00000, 0x20c },
556+ { 0x00000000, 0x0ae00000, 0x207 },
557 { 0x00000003, 0x00204811, 0x000 },
558 { 0x0000000c, 0x0020162d, 0x000 },
559 { 0x0000000d, 0x00201a2d, 0x000 },
560- { 0xffdfffff, 0x00483a2e, 0x210 },
561+ { 0xffdfffff, 0x00483a2e, 0x20b },
562 { 0x00000004, 0x00204811, 0x000 },
563 { 0x0000000e, 0x0020162d, 0x000 },
564 { 0x0000000f, 0x00201a2d, 0x000 },
565 { 0xffefffff, 0x00283a2e, 0x000 },
566 { 0x00000000, 0x00201c10, 0x000 },
567 { 0x00000000, 0x002f0067, 0x000 },
568- { 0x00000000, 0x04e00000, 0x205 },
569+ { 0x00000000, 0x04e00000, 0x200 },
570 { 0x8100ffff, 0x00204411, 0x000 },
571 { 0x00000006, 0x00204811, 0x000 },
572 { 0x8300ffff, 0x00204411, 0x000 },
573@@ -578,10 +575,10 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
574 { 0x8400ffff, 0x00204411, 0x000 },
575 { 0x00000000, 0x00204803, 0x000 },
576 { 0x00000000, 0x21000000, 0x000 },
577- { 0x00000000, 0x00601010, 0x28c },
578+ { 0x00000000, 0x00601010, 0x287 },
579 { 0x0000000c, 0x00221e24, 0x000 },
580 { 0x00000000, 0x002f0222, 0x000 },
581- { 0x00000000, 0x0ae00000, 0x22d },
582+ { 0x00000000, 0x0ae00000, 0x228 },
583 { 0x20000000, 0x00293a2e, 0x000 },
584 { 0x000021f7, 0x0029462c, 0x000 },
585 { 0x00000000, 0x002948c7, 0x000 },
586@@ -594,7 +591,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
587 { 0x00000000, 0x00204803, 0x000 },
588 { 0x00000000, 0x23000000, 0x000 },
589 { 0x8d00ffff, 0x00204411, 0x000 },
590- { 0x00000000, 0x00404803, 0x240 },
591+ { 0x00000000, 0x00404803, 0x23b },
592 { 0x00800000, 0x00293a2e, 0x000 },
593 { 0x000021f6, 0x0029462c, 0x000 },
594 { 0x00000000, 0x002948c7, 0x000 },
595@@ -607,7 +604,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
596 { 0x00000000, 0x00204803, 0x000 },
597 { 0x00000000, 0x25000000, 0x000 },
598 { 0x8e00ffff, 0x00204411, 0x000 },
599- { 0x00000000, 0x00404803, 0x240 },
600+ { 0x00000000, 0x00404803, 0x23b },
601 { 0x8300ffff, 0x00204411, 0x000 },
602 { 0x00000003, 0x00381224, 0x000 },
603 { 0x00005000, 0x00304a24, 0x000 },
604@@ -621,37 +618,37 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
605 { 0x8100ffff, 0x00204411, 0x000 },
606 { 0x00000001, 0x00204811, 0x000 },
607 { 0x00000001, 0x002f0222, 0x000 },
608- { 0x00000000, 0x0ae00000, 0x24a },
609+ { 0x00000000, 0x0ae00000, 0x245 },
610 { 0x000021f6, 0x0029122c, 0x000 },
611- { 0x00040000, 0x00494624, 0x24c },
612+ { 0x00040000, 0x00494624, 0x247 },
613 { 0x000021f7, 0x0029122c, 0x000 },
614 { 0x00040000, 0x00294624, 0x000 },
615- { 0x00000000, 0x00600000, 0x2ba },
616+ { 0x00000000, 0x00600000, 0x2b4 },
617 { 0x00000000, 0x002f0222, 0x000 },
618- { 0x00000000, 0x0ce00000, 0x252 },
619+ { 0x00000000, 0x0ce00000, 0x24d },
620 { 0x00000001, 0x002f0222, 0x000 },
621- { 0x00000000, 0x0ce00000, 0x252 },
622- { 0x00000000, 0x00481630, 0x258 },
623+ { 0x00000000, 0x0ce00000, 0x24d },
624+ { 0x00000000, 0x00481630, 0x253 },
625 { 0x00000fff, 0x00281630, 0x000 },
626 { 0x0000000c, 0x00211a30, 0x000 },
627 { 0x00000fff, 0x00281a26, 0x000 },
628 { 0x00000000, 0x002f0226, 0x000 },
629- { 0x00000000, 0x0ae00000, 0x258 },
630+ { 0x00000000, 0x0ae00000, 0x253 },
631 { 0x00000000, 0xc0400000, 0x000 },
632- { 0x00040d02, 0x00604411, 0x2ba },
633+ { 0x00040d02, 0x00604411, 0x2b4 },
634 { 0x00000000, 0x002f0222, 0x000 },
635- { 0x00000000, 0x0ae00000, 0x25d },
636+ { 0x00000000, 0x0ae00000, 0x258 },
637 { 0x00000010, 0x00211e30, 0x000 },
638- { 0x00000fff, 0x00482630, 0x267 },
639+ { 0x00000fff, 0x00482630, 0x262 },
640 { 0x00000001, 0x002f0222, 0x000 },
641- { 0x00000000, 0x0ae00000, 0x261 },
642+ { 0x00000000, 0x0ae00000, 0x25c },
643 { 0x00000fff, 0x00281e30, 0x000 },
644- { 0x00000200, 0x00402411, 0x267 },
645+ { 0x00000200, 0x00402411, 0x262 },
646 { 0x00000000, 0x00281e30, 0x000 },
647 { 0x00000010, 0x00212630, 0x000 },
648 { 0x00000010, 0x00211a30, 0x000 },
649 { 0x00000000, 0x002f0226, 0x000 },
650- { 0x00000000, 0x0ae00000, 0x258 },
651+ { 0x00000000, 0x0ae00000, 0x253 },
652 { 0x00000000, 0xc0400000, 0x000 },
653 { 0x00000003, 0x00381625, 0x000 },
654 { 0x00000003, 0x00381a26, 0x000 },
655@@ -662,13 +659,13 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
656 { 0x00000000, 0xc0204800, 0x000 },
657 { 0x00000000, 0x00204806, 0x000 },
658 { 0x00005000, 0x00302225, 0x000 },
659- { 0x00040000, 0x00694628, 0x2ba },
660+ { 0x00040000, 0x00694628, 0x2b4 },
661 { 0x00000001, 0x00302228, 0x000 },
662 { 0x00000000, 0x00202810, 0x000 },
663- { 0x00040000, 0x00694628, 0x2ba },
664+ { 0x00040000, 0x00694628, 0x2b4 },
665 { 0x00000001, 0x00302228, 0x000 },
666 { 0x00000000, 0x00200810, 0x000 },
667- { 0x00040000, 0x00694628, 0x2ba },
668+ { 0x00040000, 0x00694628, 0x2b4 },
669 { 0x00000001, 0x00302228, 0x000 },
670 { 0x00000000, 0x00201410, 0x000 },
671 { 0x0000060d, 0x00204411, 0x000 },
672@@ -678,39 +675,42 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
673 { 0x00000000, 0x00204802, 0x000 },
674 { 0x00000000, 0x00204805, 0x000 },
675 { 0x00000000, 0x002f0128, 0x000 },
676- { 0x00000000, 0x0ae00000, 0x282 },
677+ { 0x00000000, 0x0ae00000, 0x27d },
678 { 0x00005000, 0x00302227, 0x000 },
679 { 0x0000000c, 0x00300e23, 0x000 },
680 { 0x00000003, 0x00331a26, 0x000 },
681 { 0x00000000, 0x002f0226, 0x000 },
682- { 0x00000000, 0x0ae00000, 0x270 },
683+ { 0x00000000, 0x0ae00000, 0x26b },
684 { 0x00000000, 0x00400000, 0x000 },
685 { 0x000001f3, 0x00204411, 0x000 },
686 { 0x04000000, 0x00204811, 0x000 },
687- { 0x00000000, 0x00400000, 0x289 },
688- { 0x00000000, 0xc0600000, 0x28c },
689+ { 0x00000000, 0x00400000, 0x284 },
690+ { 0x00000000, 0xc0600000, 0x287 },
691 { 0x00000000, 0x00400000, 0x000 },
692- { 0x00000000, 0x0ec00000, 0x28e },
693+ { 0x00000000, 0x0ec00000, 0x289 },
694 { 0x00000000, 0x00800000, 0x000 },
695 { 0x000021f9, 0x0029462c, 0x000 },
696 { 0x00000005, 0x00204811, 0x000 },
697+ { 0x8100ffff, 0x00204411, 0x000 },
698+ { 0x00000002, 0x00204811, 0x000 },
699+ { 0x0000000a, 0x0021262c, 0x000 },
700+ { 0x00000000, 0x00210130, 0x000 },
701+ { 0x00000000, 0x14c00000, 0x292 },
702+ { 0xa500ffff, 0x00204411, 0x000 },
703+ { 0x00000001, 0x00404811, 0x28e },
704 { 0x00000000, 0x0020280c, 0x000 },
705 { 0x00000011, 0x0020262d, 0x000 },
706 { 0x00000000, 0x002f012c, 0x000 },
707- { 0x00000000, 0x0ae00000, 0x295 },
708- { 0x00000000, 0x00403011, 0x296 },
709+ { 0x00000000, 0x0ae00000, 0x297 },
710+ { 0x00000000, 0x00403011, 0x298 },
711 { 0x00000400, 0x0030322c, 0x000 },
712 { 0x8100ffff, 0x00204411, 0x000 },
713 { 0x00000002, 0x00204811, 0x000 },
714 { 0x0000000a, 0x0021262c, 0x000 },
715 { 0x00000000, 0x00210130, 0x000 },
716- { 0x00000000, 0x14c00000, 0x29d },
717+ { 0x00000000, 0x14c00000, 0x29f },
718 { 0xa500ffff, 0x00204411, 0x000 },
719- { 0x00000001, 0x00404811, 0x299 },
720- { 0x8100ffff, 0x00204411, 0x000 },
721- { 0x00000001, 0x00204811, 0x000 },
722- { 0x00042294, 0x00604411, 0x2ba },
723- { 0x00000000, 0x00200010, 0x000 },
724+ { 0x00000001, 0x00404811, 0x29b },
725 { 0xa500ffff, 0x00204411, 0x000 },
726 { 0x00000000, 0x00204811, 0x000 },
727 { 0x000021f4, 0x0029462c, 0x000 },
728@@ -721,11 +721,9 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
729 { 0x00000002, 0x00204811, 0x000 },
730 { 0x00000000, 0x00210130, 0x000 },
731 { 0xdf7fffff, 0x00283a2e, 0x000 },
732- { 0x8100ffff, 0x00204411, 0x000 },
733- { 0x00000001, 0x00204811, 0x000 },
734- { 0x00042294, 0x00604411, 0x2ba },
735- { 0x00000000, 0x00200010, 0x000 },
736 { 0x00000010, 0x0080362a, 0x000 },
737+ { 0x00000000, 0x00203011, 0x000 },
738+ { 0x00000010, 0x0080362c, 0x000 },
739 { 0x9700ffff, 0x00204411, 0x000 },
740 { 0x00000000, 0x0020480c, 0x000 },
741 { 0xa200ffff, 0x00204411, 0x000 },
742@@ -733,13 +731,11 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
743 { 0x8100ffff, 0x00204411, 0x000 },
744 { 0x00000002, 0x00204811, 0x000 },
745 { 0x00000000, 0x00810130, 0x000 },
746- { 0x00000000, 0x00203011, 0x000 },
747- { 0x00000010, 0x0080362c, 0x000 },
748 { 0x00000000, 0xc0400000, 0x000 },
749- { 0x00000000, 0x1ac00000, 0x2ba },
750+ { 0x00000000, 0x1ac00000, 0x2b4 },
751 { 0x9f00ffff, 0x00204411, 0x000 },
752 { 0xdeadbeef, 0x00204811, 0x000 },
753- { 0x00000000, 0x1ae00000, 0x2bd },
754+ { 0x00000000, 0x1ae00000, 0x2b7 },
755 { 0x00000000, 0x00800000, 0x000 },
756 { 0x00000000, 0x00000000, 0x000 },
757 { 0x00000000, 0x00000000, 0x000 },
758@@ -778,26 +774,32 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
759 { 0x00000000, 0x00000000, 0x000 },
760 { 0x00000000, 0x00000000, 0x000 },
761 { 0x00000000, 0x00000000, 0x000 },
762- { 0x00020143, 0x00020002, 0x000 },
763+ { 0x00000000, 0x00000000, 0x000 },
764+ { 0x00000000, 0x00000000, 0x000 },
765+ { 0x00000000, 0x00000000, 0x000 },
766+ { 0x00000000, 0x00000000, 0x000 },
767+ { 0x00000000, 0x00000000, 0x000 },
768+ { 0x00000000, 0x00000000, 0x000 },
769+ { 0x0002013e, 0x00020002, 0x000 },
770 { 0x00020002, 0x00020002, 0x000 },
771 { 0x00020002, 0x00020002, 0x000 },
772- { 0x00020002, 0x01dd0002, 0x000 },
773- { 0x006301ee, 0x00280012, 0x000 },
774+ { 0x00020002, 0x01d80002, 0x000 },
775+ { 0x005e01e9, 0x00280012, 0x000 },
776 { 0x00020002, 0x00020026, 0x000 },
777- { 0x00020002, 0x01ec0002, 0x000 },
778- { 0x00790242, 0x00020002, 0x000 },
779+ { 0x00020002, 0x01e70002, 0x000 },
780+ { 0x0074023d, 0x00020002, 0x000 },
781 { 0x00020002, 0x00020002, 0x000 },
782 { 0x00200012, 0x00020016, 0x000 },
783 { 0x00020002, 0x00020002, 0x000 },
784- { 0x011b00c5, 0x00020125, 0x000 },
785- { 0x00020141, 0x00020002, 0x000 },
786- { 0x00c50002, 0x0143002e, 0x000 },
787- { 0x00a2016b, 0x00020145, 0x000 },
788- { 0x00020002, 0x01200002, 0x000 },
789- { 0x00020002, 0x010f0103, 0x000 },
790+ { 0x011600c0, 0x00020120, 0x000 },
791+ { 0x0002013c, 0x00020002, 0x000 },
792+ { 0x00c00002, 0x013e002e, 0x000 },
793+ { 0x009d0166, 0x00020140, 0x000 },
794+ { 0x00020002, 0x011b0002, 0x000 },
795+ { 0x00020002, 0x010a00fe, 0x000 },
796 { 0x00090002, 0x000e000e, 0x000 },
797- { 0x0058003d, 0x00600002, 0x000 },
798- { 0x000200c1, 0x0002028a, 0x000 },
799+ { 0x0049003d, 0x005b0002, 0x000 },
800+ { 0x000200bc, 0x00020285, 0x000 },
801 { 0x00020002, 0x00020002, 0x000 },
802 { 0x00020002, 0x00020002, 0x000 },
803 { 0x00020002, 0x00020002, 0x000 },
804@@ -805,7 +807,7 @@ uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
805 { 0x00020002, 0x00020002, 0x000 },
806 { 0x00020002, 0x00020002, 0x000 },
807 { 0x00020002, 0x00020002, 0x000 },
808- { 0x000502b9, 0x00020008, 0x000 },
809+ { 0x000502b3, 0x00020008, 0x000 },
810 };
811
812 #endif
813@@ -813,4 +815,3 @@ static const uint32 ME_JUMP_TABLE_START = 740;
814 static const uint32 ME_JUMP_TABLE_END = 768;
815
816 #endif
817-
818--
8191.5.4.4
820
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1140-ENGR00162711-DA9053-Add-dummy-write-for-DA9053-I2C.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1140-ENGR00162711-DA9053-Add-dummy-write-for-DA9053-I2C.patch
deleted file mode 100755
index 908a36087..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1140-ENGR00162711-DA9053-Add-dummy-write-for-DA9053-I2C.patch
+++ /dev/null
@@ -1,434 +0,0 @@
1From 7c0c7fc3189f456f1899bf4aa0a27e3f71f6a808 Mon Sep 17 00:00:00 2001
2From: Wayne Zou <b36644@freescale.com>
3Date: Mon, 21 Nov 2011 14:44:33 +0800
4Subject: [PATCH] ENGR00162711 DA9053: Add dummy write for DA9053 I2C register access
5
6DA9053 i2c issue: Rarely the i2c interface of DA9053 hang and it can
7not be recovered if not power off totally. The Dialog suggests adding
8dummy write for DA9053 I2C register access, in order to decrease the failure
9of DA9053 register access and possibility of i2c failure.
10
11Signed-off-by: Wayne Zou <b36644@freescale.com>
12(cherry picked from commit bfd7cba1eeb46977b18a3c5fa65d812817a8294d)
13---
14 drivers/mfd/da9052-i2c.c | 317 ++++++++++++++++++++++++----------------------
15 1 files changed, 166 insertions(+), 151 deletions(-)
16
17diff --git a/drivers/mfd/da9052-i2c.c b/drivers/mfd/da9052-i2c.c
18index 6209e97..457523f 100644
19--- a/drivers/mfd/da9052-i2c.c
20+++ b/drivers/mfd/da9052-i2c.c
21@@ -19,6 +19,8 @@ static struct da9052 *da9052_i2c;
22
23 #define I2C_CONNECTED 0
24
25+#define DA9052_I2C_BUG_WORKAROUND
26+
27 static int da9052_i2c_is_connected(void)
28 {
29 struct da9052_ssc_msg msg;
30@@ -76,6 +78,15 @@ static int __devinit da9052_i2c_probe(struct i2c_client *client,
31
32 /* Validate I2C connectivity */
33 if ( I2C_CONNECTED == da9052_i2c_is_connected()) {
34+ /* Enable Repeated Write Mode permanently */
35+ struct da9052_ssc_msg ctrl_msg = {
36+ DA9052_CONTROLB_REG, DA9052_CONTROLB_WRITEMODE};
37+ if (da9052_i2c_write(da9052_i2c, &ctrl_msg) < 0) {
38+ dev_info(&da9052_i2c->i2c_client->dev,
39+ "%s: repeated mode not set!!\n", __func__);
40+ return -ENODEV;
41+ }
42+
43 /* I2C is connected */
44 da9052_i2c->connecting_device = I2C;
45 if( 0!= da9052_ssc_init(da9052_i2c) )
46@@ -100,27 +111,59 @@ static int da9052_i2c_remove(struct i2c_client *client)
47 return 0;
48 }
49
50+#ifdef DA9052_I2C_BUG_WORKAROUND
51+const unsigned char i2c_flush_data[] = {0xFF, 0xFF};
52+static const char safe_table[256] = {
53+ [DA9052_STATUSA_REG] = 1,
54+ [DA9052_STATUSB_REG] = 1,
55+ [DA9052_STATUSC_REG] = 1,
56+ [DA9052_STATUSD_REG] = 1,
57+ [DA9052_ADCRESL_REG] = 1,
58+ [DA9052_ADCRESH_REG] = 1,
59+ [DA9052_VDDRES_REG] = 1,
60+ [DA9052_ICHGAV_REG] = 1,
61+ [DA9052_TBATRES_REG] = 1,
62+ [DA9052_ADCIN4RES_REG] = 1,
63+ [DA9052_ADCIN5RES_REG] = 1,
64+ [DA9052_ADCIN6RES_REG] = 1,
65+ [DA9052_TJUNCRES_REG] = 1,
66+ [DA9052_TSIXMSB_REG] = 1,
67+ [DA9052_TSIYMSB_REG] = 1,
68+ [DA9052_TSILSB_REG] = 1,
69+ [DA9052_TSIZMSB_REG] = 1,
70+};
71+/* Enable safe register addresses */
72+static inline int da9052_is_i2c_reg_safe(unsigned char reg)
73+{
74+ return safe_table[reg];
75+}
76+#endif
77+
78 int da9052_i2c_write(struct da9052 *da9052, struct da9052_ssc_msg *msg)
79 {
80 struct i2c_msg i2cmsg;
81- unsigned char buf[2] = {0};
82+ unsigned char buf[4] = {0};
83 int ret = 0;
84
85- /* Copy the ssc msg to local character buffer */
86- buf[0] = msg->addr;
87- buf[1] = msg->data;
88-
89 /*Construct a i2c msg for a da9052 driver ssc message request */
90 i2cmsg.addr = da9052->slave_addr;
91- i2cmsg.len = 2;
92 i2cmsg.buf = buf;
93-
94- /* To write the data on I2C set flag to zero */
95 i2cmsg.flags = 0;
96+ i2cmsg.len = 2;
97+
98+ /* Copy the ssc msg and additional data to flush chip I2C registers */
99+ buf[0] = msg->addr;
100+ buf[1] = msg->data;
101
102+#ifdef DA9052_I2C_BUG_WORKAROUND
103+ if (!da9052_is_i2c_reg_safe(msg->addr)) {
104+ i2cmsg.len = 4;
105+ buf[2] = i2c_flush_data[0];
106+ buf[3] = i2c_flush_data[1];
107+ }
108+#endif
109 /* Start the i2c transfer by calling host i2c driver function */
110 ret = i2c_transfer(da9052->adapter, &i2cmsg, 1);
111-
112 if (ret < 0) {
113 dev_info(&da9052->i2c_client->dev,\
114 "_%s:master_xfer Failed!!\n", __func__);
115@@ -132,10 +175,8 @@ int da9052_i2c_write(struct da9052 *da9052, struct da9052_ssc_msg *msg)
116
117 int da9052_i2c_read(struct da9052 *da9052, struct da9052_ssc_msg *msg)
118 {
119-
120- /*Get the da9052_i2c client details*/
121 unsigned char buf[2] = {0, 0};
122- struct i2c_msg i2cmsg[2];
123+ struct i2c_msg i2cmsg[3];
124 int ret = 0;
125
126 /* Copy SSC Msg to local character buffer */
127@@ -145,107 +186,82 @@ int da9052_i2c_read(struct da9052 *da9052, struct da9052_ssc_msg *msg)
128 i2cmsg[0].addr = da9052->slave_addr ;
129 i2cmsg[0].len = 1;
130 i2cmsg[0].buf = &buf[0];
131-
132- /*To write the data on I2C set flag to zero */
133 i2cmsg[0].flags = 0;
134
135- /* Read the data from da9052*/
136 /*Construct a i2c msg for a da9052 driver ssc message request */
137 i2cmsg[1].addr = da9052->slave_addr ;
138 i2cmsg[1].len = 1;
139 i2cmsg[1].buf = &buf[1];
140-
141- /*To read the data on I2C set flag to I2C_M_RD */
142 i2cmsg[1].flags = I2C_M_RD;
143
144- /* Start the i2c transfer by calling host i2c driver function */
145+ /* Standard read transfer */
146 ret = i2c_transfer(da9052->adapter, i2cmsg, 2);
147+
148+#ifdef DA9052_I2C_BUG_WORKAROUND
149+ if (!da9052_is_i2c_reg_safe(msg->addr)) {
150+ /* Prepare additional message to flush chip I2C registers */
151+ i2cmsg[2].addr = da9052->slave_addr;
152+ i2cmsg[2].len = 2;
153+ i2cmsg[2].flags = 0; /* Write operation */
154+ i2cmsg[2].buf = (unsigned char *)i2c_flush_data;
155+
156+ /* Read transfer with additional flush write */
157+ ret = i2c_transfer(da9052->adapter, &i2cmsg[2], 1);
158+ }
159+#endif
160+
161 if (ret < 0) {
162- dev_info(&da9052->i2c_client->dev,\
163- "2 - %s:master_xfer Failed!!\n", __func__);
164+ dev_info(&da9052->i2c_client->dev,
165+ "2 - %s:master_xfer Failed!!\n", __func__);
166 return ret;
167 }
168
169- msg->data = *i2cmsg[1].buf;
170-
171+ msg->data = buf[1];
172 return 0;
173 }
174
175 int da9052_i2c_write_many(struct da9052 *da9052,
176 struct da9052_ssc_msg *sscmsg, int msg_no)
177 {
178-
179 struct i2c_msg i2cmsg;
180- unsigned char data_buf[MAX_READ_WRITE_CNT+1];
181- struct da9052_ssc_msg ctrlb_msg;
182- struct da9052_ssc_msg *msg_queue = sscmsg;
183 int ret = 0;
184- /* Flag to check if requested registers are contiguous */
185- unsigned char cont_data = 1;
186- unsigned char cnt = 0;
187-
188- /* Check if requested registers are contiguous */
189- for (cnt = 1; cnt < msg_no; cnt++) {
190- if ((msg_queue[cnt].addr - msg_queue[cnt-1].addr) != 1) {
191- /* Difference is not 1, i.e. non-contiguous registers */
192- cont_data = 0;
193- break;
194- }
195- }
196-
197- if (cont_data == 0) {
198- /* Requested registers are non-contiguous */
199- for (cnt = 0; cnt < msg_no; cnt++) {
200- ret = da9052->write(da9052, &msg_queue[cnt]);
201- if (ret != 0)
202- return ret;
203- }
204- return 0;
205- }
206- /*
207- * Requested registers are contiguous
208- * or PAGE WRITE sequence of I2C transactions is as below
209- * (slave_addr + reg_addr + data_1 + data_2 + ...)
210- * First read current WRITE MODE via CONTROL_B register of DA9052
211- */
212- ctrlb_msg.addr = DA9052_CONTROLB_REG;
213- ctrlb_msg.data = 0x0;
214- ret = da9052->read(da9052, &ctrlb_msg);
215-
216- if (ret != 0)
217- return ret;
218-
219- /* Check if PAGE WRITE mode is set */
220- if (ctrlb_msg.data & DA9052_CONTROLB_WRITEMODE) {
221- /* REPEAT WRITE mode is configured */
222- /* Now set DA9052 into PAGE WRITE mode */
223- ctrlb_msg.data &= ~DA9052_CONTROLB_WRITEMODE;
224- ret = da9052->write(da9052, &ctrlb_msg);
225-
226- if (ret != 0)
227- return ret;
228- }
229-
230- /* Put first register address */
231- data_buf[0] = msg_queue[0].addr;
232-
233- for (cnt = 0; cnt < msg_no; cnt++)
234- data_buf[cnt+1] = msg_queue[cnt].data;
235-
236- /* Construct a i2c msg for PAGE WRITE */
237+ int safe = 1;
238+ unsigned char *data_ptr;
239+#ifdef DA9052_I2C_BUG_WORKAROUND
240+ unsigned char data_buf[2 * MAX_READ_WRITE_CNT + 2];
241+#else
242+ unsigned char data_buf[2 * MAX_READ_WRITE_CNT];
243+#endif
244+
245+ BUG_ON(msg_no < 0);
246+ BUG_ON(msg_no >= MAX_READ_WRITE_CNT);
247+
248+ /* Construct a i2c msg for REPEATED WRITE */
249 i2cmsg.addr = da9052->slave_addr ;
250- /* First register address + all data*/
251- i2cmsg.len = (msg_no + 1);
252+ i2cmsg.len = 2*msg_no;
253 i2cmsg.buf = data_buf;
254-
255- /*To write the data on I2C set flag to zero */
256 i2cmsg.flags = 0;
257
258+ for (data_ptr = data_buf; msg_no; msg_no--) {
259+ safe &= da9052_is_i2c_reg_safe(sscmsg->addr);
260+ *(data_ptr++) = sscmsg->addr;
261+ *(data_ptr++) = sscmsg->data;
262+ sscmsg++;
263+ }
264+#ifdef DA9052_I2C_BUG_WORKAROUND
265+ if (!safe) {
266+ i2cmsg.len += 2;
267+ *(data_ptr++) = i2c_flush_data[0];
268+ *data_ptr = i2c_flush_data[1];
269+ }
270+#endif
271+
272 /* Start the i2c transfer by calling host i2c driver function */
273 ret = i2c_transfer(da9052->adapter, &i2cmsg, 1);
274 if (ret < 0) {
275- dev_info(&da9052->i2c_client->dev,\
276- "1 - i2c_transfer function falied in [%s]!!!\n", __func__);
277+ dev_info(&da9052->i2c_client->dev,
278+ "1 - i2c_transfer function falied in [%s]!!!\n",
279+ __func__);
280 return ret;
281 }
282
283@@ -255,83 +271,82 @@ int da9052_i2c_write_many(struct da9052 *da9052,
284 int da9052_i2c_read_many(struct da9052 *da9052,
285 struct da9052_ssc_msg *sscmsg, int msg_no)
286 {
287-
288- struct i2c_msg i2cmsg;
289+#ifdef DA9052_I2C_BUG_WORKAROUND
290+ struct i2c_msg i2cmsg[2 * MAX_READ_WRITE_CNT];
291+#else
292+ struct i2c_msg i2cmsg[2 * MAX_READ_WRITE_CNT + 1];
293+#endif
294 unsigned char data_buf[MAX_READ_WRITE_CNT];
295- struct da9052_ssc_msg *msg_queue = sscmsg;
296+ struct i2c_msg *msg_ptr = i2cmsg;
297 int ret = 0;
298- /* Flag to check if requested registers are contiguous */
299- unsigned char cont_data = 1;
300- unsigned char cnt = 0;
301-
302- /* Check if requested registers are contiguous */
303- for (cnt = 1; cnt < msg_no; cnt++) {
304- if ((msg_queue[cnt].addr - msg_queue[cnt-1].addr) != 1) {
305- /* Difference is not 1, i.e. non-contiguous registers */
306- cont_data = 0;
307- break;
308+ int safe = 1;
309+ int last_reg_read = -2;
310+ int cnt;
311+
312+ BUG_ON(msg_no < 0);
313+ BUG_ON(msg_no >= MAX_READ_WRITE_CNT);
314+
315+ /* Construct a i2c msgs for a da9052 driver ssc message request */
316+ for (cnt = 0; cnt < msg_no; cnt++) {
317+ if ((int)sscmsg[cnt].addr != last_reg_read + 1) {
318+ safe &= da9052_is_i2c_reg_safe(sscmsg[cnt].addr);
319+
320+ /* Build messages for first register, read in a row */
321+ msg_ptr->addr = da9052->slave_addr;
322+ msg_ptr->len = 1;
323+ msg_ptr->buf = &sscmsg[cnt].addr;
324+ msg_ptr->flags = 0;
325+ msg_ptr++;
326+
327+ msg_ptr->addr = da9052->slave_addr;
328+ msg_ptr->len = 1;
329+ msg_ptr->buf = &data_buf[cnt];
330+ msg_ptr->flags = I2C_M_RD;
331+ msg_ptr++;
332+
333+ last_reg_read = sscmsg[cnt].addr;
334+ } else {
335+ /* Increase read counter for consecutive reads */
336+ (msg_ptr - 1)->len++;
337 }
338 }
339
340- if (cont_data == 0) {
341- /* Requested registers are non-contiguous */
342- for (cnt = 0; cnt < msg_no; cnt++) {
343- ret = da9052->read(da9052, &msg_queue[cnt]);
344- if (ret != 0) {
345- dev_info(&da9052->i2c_client->dev,\
346- "Error in %s", __func__);
347- return ret;
348- }
349- }
350- return 0;
351+#ifdef DA9052_I2C_BUG_WORKAROUND
352+ if (!safe) {
353+ /* Prepare additional message to flush chip I2C registers */
354+ msg_ptr->addr = da9052->slave_addr;
355+ msg_ptr->len = 2;
356+ msg_ptr->flags = 0; /* Write operation */
357+ msg_ptr->buf = (unsigned char *)i2c_flush_data;
358+ msg_ptr++;
359 }
360-
361- /*
362- * We want to perform PAGE READ via I2C
363- * For PAGE READ sequence of I2C transactions is as below
364- * (slave_addr + reg_addr) + (slave_addr + data_1 + data_2 + ...)
365- */
366- /* Copy address of first register */
367- data_buf[0] = msg_queue[0].addr;
368-
369- /* Construct a i2c msg for first transaction of PAGE READ i.e. write */
370- i2cmsg.addr = da9052->slave_addr ;
371- i2cmsg.len = 1;
372- i2cmsg.buf = data_buf;
373-
374- /*To write the data on I2C set flag to zero */
375- i2cmsg.flags = 0;
376-
377- /* Start the i2c transfer by calling host i2c driver function */
378- ret = i2c_transfer(da9052->adapter, &i2cmsg, 1);
379- if (ret < 0) {
380- dev_info(&da9052->i2c_client->dev,\
381- "1 - i2c_transfer function falied in [%s]!!!\n", __func__);
382- return ret;
383+#endif
384+
385+ /* Using one transfer seems not to work well with D9052.
386+ * Read transfer with additional flush write
387+ * Performing many transfers is stable on D9052
388+ */
389+ for (cnt = 0; cnt < (msg_ptr - i2cmsg) - 1; cnt += 2) {
390+ ret = i2c_transfer(da9052->adapter, &i2cmsg[cnt], 2);
391+ if (ret < 0) {
392+ dev_info(&da9052->i2c_client->dev,
393+ "2 - %s:master_xfer Failed on msg[%d]!!\n",
394+ __func__, cnt);
395+ return ret;
396+ }
397 }
398-
399- /* Now Read the data from da9052 */
400- /* Construct a i2c msg for second transaction of PAGE READ i.e. read */
401- i2cmsg.addr = da9052->slave_addr ;
402- i2cmsg.len = msg_no;
403- i2cmsg.buf = data_buf;
404-
405- /*To read the data on I2C set flag to I2C_M_RD */
406- i2cmsg.flags = I2C_M_RD;
407-
408- /* Start the i2c transfer by calling host i2c driver function */
409- ret = i2c_transfer(da9052->adapter,
410- &i2cmsg, 1);
411- if (ret < 0) {
412- dev_info(&da9052->i2c_client->dev,\
413- "2 - i2c_transfer function falied in [%s]!!!\n", __func__);
414- return ret;
415+ if (cnt < (msg_ptr - i2cmsg)) {
416+ ret = i2c_transfer(da9052->adapter, &i2cmsg[cnt], 1);
417+ if (ret < 0) {
418+ dev_info(&da9052->i2c_client->dev,
419+ "2 - %s:master_xfer Failed on msg[%d]!!\n",
420+ __func__, cnt);
421+ return ret;
422+ }
423 }
424
425- /* Gather READ data */
426 for (cnt = 0; cnt < msg_no; cnt++)
427 sscmsg[cnt].data = data_buf[cnt];
428-
429 return 0;
430 }
431
432--
4331.5.4.4
434
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1141-ENGR00162708-MX5-Add-I2C-dummy-write-and-mask-nONKE.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1141-ENGR00162708-MX5-Add-I2C-dummy-write-and-mask-nONKE.patch
deleted file mode 100755
index 9244dbffe..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1141-ENGR00162708-MX5-Add-I2C-dummy-write-and-mask-nONKE.patch
+++ /dev/null
@@ -1,86 +0,0 @@
1From 3bc50cddbc5bc8c20c3bac50794a7ec80602ab16 Mon Sep 17 00:00:00 2001
2From: Wayne Zou <b36644@freescale.com>
3Date: Mon, 21 Nov 2011 15:06:54 +0800
4Subject: [PATCH] ENGR00162708 MX5: Add I2C dummy write and mask nONKEY event for i2c operation
5
6MX5: Add I2C dummy write when acessing DA9053 registers and mask nONKEY event
7for i2c operation before suspend
8
9Signed-off-by: Wayne Zou <b36644@freescale.com>
10(cherry picked from commit 0cc56da7dc91bbd5b6e9a51c1576daedce36093c)
11---
12 arch/arm/mach-mx5/pm_da9053.c | 22 +++++++++++++++++++---
13 1 files changed, 19 insertions(+), 3 deletions(-)
14
15diff --git a/arch/arm/mach-mx5/pm_da9053.c b/arch/arm/mach-mx5/pm_da9053.c
16index 63eda3a..7bb8915 100644
17--- a/arch/arm/mach-mx5/pm_da9053.c
18+++ b/arch/arm/mach-mx5/pm_da9053.c
19@@ -60,6 +60,7 @@ as the normal setting on Da9053 */
20 #define DA9052_GPIO0809_SMD_SET 0x18
21 #define DA9052_ID1415_SMD_SET 0x1
22 #define DA9052_GPI9_IRQ_MASK 0x2
23+#define DA9052_IRQ_MASKB_ONKEY 0x1
24
25 static u8 volt_settings[DA9052_LDO10_REG - DA9052_BUCKCORE_REG + 1];
26 extern int pm_i2c_imx_xfer(struct i2c_msg *msgs, int num);
27@@ -67,7 +68,8 @@ extern int pm_i2c_imx_xfer(struct i2c_msg *msgs, int num);
28 static void pm_da9053_read_reg(u8 reg, u8 *value)
29 {
30 unsigned char buf[2] = {0, 0};
31- struct i2c_msg i2cmsg[2];
32+ unsigned char dummy[2] = {0xff, 0xff};
33+ struct i2c_msg i2cmsg[3];
34 buf[0] = reg;
35 i2cmsg[0].addr = 0x48 ;
36 i2cmsg[0].len = 1;
37@@ -83,16 +85,22 @@ static void pm_da9053_read_reg(u8 reg, u8 *value)
38
39 pm_i2c_imx_xfer(i2cmsg, 2);
40 *value = buf[1];
41+
42+ i2cmsg[2].addr = 0x48 ;
43+ i2cmsg[2].len = 2;
44+ i2cmsg[2].buf = &dummy[0];
45+ i2cmsg[2].flags = 0;
46+ pm_i2c_imx_xfer(i2cmsg, 1);
47 }
48
49 static void pm_da9053_write_reg(u8 reg, u8 value)
50 {
51- unsigned char buf[2] = {0, 0};
52+ unsigned char buf[4] = {0, 0, 0xff, 0xff};
53 struct i2c_msg i2cmsg[2];
54 buf[0] = reg;
55 buf[1] = value;
56 i2cmsg[0].addr = 0x48 ;
57- i2cmsg[0].len = 2;
58+ i2cmsg[0].len = 4;
59 i2cmsg[0].buf = &buf[0];
60 i2cmsg[0].flags = 0;
61 pm_i2c_imx_xfer(i2cmsg, 1);
62@@ -172,6 +180,10 @@ int da9053_suspend_cmd_hw(void)
63 }
64 clk_enable(i2c_clk);
65
66+ pm_da9053_read_reg(DA9052_IRQMASKB_REG, &data);
67+ data |= DA9052_IRQ_MASKB_ONKEY;
68+ pm_da9053_write_reg(DA9052_IRQMASKB_REG, data);
69+
70 pm_da9053_preset_voltage();
71 pm_da9053_write_reg(DA9052_CONTROLC_REG,
72 DA9052_CONTROLC_SMD_SET);
73@@ -194,6 +206,10 @@ int da9053_suspend_cmd_hw(void)
74 pm_da9053_write_reg(DA9052_SEQTIMER_REG, 0);
75 /* pm_da9053_write_reg(DA9052_SEQB_REG, 0x1f); */
76
77+ pm_da9053_read_reg(DA9052_IRQMASKB_REG, &data);
78+ data &= ~DA9052_IRQ_MASKB_ONKEY;
79+ pm_da9053_write_reg(DA9052_IRQMASKB_REG, data);
80+
81 clk_disable(i2c_clk);
82 clk_put(i2c_clk);
83 return 0;
84--
851.5.4.4
86
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1142-ENGR00163698-MX53-ARD-fix-typo-error-for-pwm1-pad-d.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1142-ENGR00163698-MX53-ARD-fix-typo-error-for-pwm1-pad-d.patch
deleted file mode 100755
index 5b17895f2..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1142-ENGR00163698-MX53-ARD-fix-typo-error-for-pwm1-pad-d.patch
+++ /dev/null
@@ -1,33 +0,0 @@
1From bad1d7edba0addd5cb925d237242edbfbbf2f108 Mon Sep 17 00:00:00 2001
2From: Yuxi Sun <b36102@freescale.com>
3Date: Fri, 2 Dec 2011 11:12:28 +0800
4Subject: [PATCH] ENGR00163698 MX53 ARD: fix typo error for pwm1 pad disable function
5
6Fix typo error for pwm1 pad disable function.
7
8Signed-off-by: Yuxi Sun <b36102@freescale.com>
9(cherry picked from commit d04b2646528b586baeecc1f128508b5363e7ed63)
10---
11 arch/arm/mach-mx5/mx53_ard.c | 6 +++---
12 1 files changed, 3 insertions(+), 3 deletions(-)
13
14diff --git a/arch/arm/mach-mx5/mx53_ard.c b/arch/arm/mach-mx5/mx53_ard.c
15index 6550ca9..378e1c1 100644
16--- a/arch/arm/mach-mx5/mx53_ard.c
17+++ b/arch/arm/mach-mx5/mx53_ard.c
18@@ -393,9 +393,9 @@ static void disable_pwm1_pad(void)
19 {
20 mxc_iomux_v3_setup_pad(mx53_ard_pwm_pads[2]);
21
22- gpio_request(ARD_PWM2_OFF, "pwm2-off");
23- gpio_direction_output(ARD_PWM2_OFF, 1);
24- gpio_free(ARD_PWM2_OFF);
25+ gpio_request(ARD_PWM1_OFF, "pwm1-off");
26+ gpio_direction_output(ARD_PWM1_OFF, 1);
27+ gpio_free(ARD_PWM1_OFF);
28 }
29
30 static struct mxc_pwm_platform_data mxc_pwm1_platform_data = {
31--
321.5.4.4
33
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1143-ENGR00162578-DMA-mx5-increase-DMA-Zone-size-to-112.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1143-ENGR00162578-DMA-mx5-increase-DMA-Zone-size-to-112.patch
deleted file mode 100755
index cdbb0061a..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1143-ENGR00162578-DMA-mx5-increase-DMA-Zone-size-to-112.patch
+++ /dev/null
@@ -1,109 +0,0 @@
1From 690f2f35563a1f7a89b796f9b0e7996627dbda21 Mon Sep 17 00:00:00 2001
2From: Robin Gong <B38343@freescale.com>
3Date: Fri, 18 Nov 2011 10:52:32 +0800
4Subject: [PATCH] ENGR00162578 DMA mx5: increase DMA Zone size to 112
5
6Increase DMA zone size from 96 to 112 size, and default size is 112,
7change imx5_defconfig, change SPBA0_BASE_ADDR_VIRT from 0xFB100000 to
80xF7C00000 , so that it can't overlap with DMA zone
9Signed-off-by: Robin Gong <B38343@freescale.com>
10(cherry picked from commit 2d04dcb9b717a7c46358987f41a03141eccc42b0)
11---
12 arch/arm/configs/imx5_defconfig | 7 ++++---
13 arch/arm/plat-mxc/Kconfig | 4 ++--
14 arch/arm/plat-mxc/include/mach/memory.h | 4 ++--
15 arch/arm/plat-mxc/include/mach/mx5x.h | 2 +-
16 4 files changed, 9 insertions(+), 8 deletions(-)
17
18diff --git a/arch/arm/configs/imx5_defconfig b/arch/arm/configs/imx5_defconfig
19index 419adde..3a0cc96 100644
20--- a/arch/arm/configs/imx5_defconfig
21+++ b/arch/arm/configs/imx5_defconfig
22@@ -1,7 +1,7 @@
23 #
24 # Automatically generated make config: don't edit
25 # Linux kernel version: 2.6.35.3
26-# Wed Jun 1 20:11:44 2011
27+# Fri Nov 18 10:24:37 2011
28 #
29 CONFIG_ARM=y
30 CONFIG_HAVE_PWM=y
31@@ -266,7 +266,7 @@ CONFIG_ARCH_MXC_HAS_NFC_V3=y
32 CONFIG_ARCH_MXC_HAS_NFC_V3_2=y
33 CONFIG_MXC_BLUETOOTH_RFKILL=y
34 CONFIG_IRAM_ALLOC=y
35-CONFIG_DMA_ZONE_SIZE=96
36+CONFIG_DMA_ZONE_SIZE=112
37 CONFIG_ISP1504_MXC=y
38 CONFIG_UTMI_MXC=y
39 # CONFIG_MXC_IRQ_PRIOR is not set
40@@ -1230,9 +1230,9 @@ CONFIG_SENSORS_MAX17135=y
41 # CONFIG_SENSORS_W83627EHF is not set
42 # CONFIG_SENSORS_LIS3_SPI is not set
43 # CONFIG_SENSORS_LIS3_I2C is not set
44+CONFIG_SENSORS_IMX_AHCI=y
45 CONFIG_SENSORS_MAG3110=y
46 CONFIG_SENSORS_ISL29003=y
47-CONFIG_SENSORS_IMX_AHCI=y
48 CONFIG_MXC_MMA8450=y
49 CONFIG_MXC_MMA8451=y
50 # CONFIG_THERMAL is not set
51@@ -2112,6 +2112,7 @@ CONFIG_MXC_MC13892_POWER=y
52 CONFIG_MXC_MC34708_ADC=y
53 CONFIG_MXC_MC34708_RTC=y
54 CONFIG_MXC_MC34708_BATTERY=m
55+# CONFIG_MXC_MC34708_PWM is not set
56 # CONFIG_MXC_PMIC_MC9S08DZ60 is not set
57
58 #
59diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
60index 926379f..7a4412a 100644
61--- a/arch/arm/plat-mxc/Kconfig
62+++ b/arch/arm/plat-mxc/Kconfig
63@@ -87,8 +87,8 @@ config MXC_FB_IRAM
64
65 config DMA_ZONE_SIZE
66 int "DMA memory zone size"
67- range 0 96
68- default 24
69+ range 0 112
70+ default 112
71 help
72 This is the size in MB for the DMA zone. The DMA zone is used for
73 dedicated memory for large contiguous video buffers
74diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
75index 83532f6..2e66516 100644
76--- a/arch/arm/plat-mxc/include/mach/memory.h
77+++ b/arch/arm/plat-mxc/include/mach/memory.h
78@@ -1,5 +1,5 @@
79 /*
80- * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
81+ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
82 */
83
84 /*
85@@ -63,7 +63,7 @@
86 #else
87
88 #ifdef CONFIG_ARCH_MX5
89-#define CONSISTENT_DMA_SIZE (96 * SZ_1M)
90+#define CONSISTENT_DMA_SIZE (112 * SZ_1M)
91 #else
92 #define CONSISTENT_DMA_SIZE (32 * SZ_1M)
93 #endif
94diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h
95index 5c16710..96f6686 100644
96--- a/arch/arm/plat-mxc/include/mach/mx5x.h
97+++ b/arch/arm/plat-mxc/include/mach/mx5x.h
98@@ -194,7 +194,7 @@
99 * SPBA global module enabled #0
100 */
101 #define SPBA0_BASE_ADDR 0x70000000
102-#define SPBA0_BASE_ADDR_VIRT 0xFB100000
103+#define SPBA0_BASE_ADDR_VIRT 0xF7C00000
104 #define SPBA0_SIZE SZ_1M
105
106 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
107--
1081.5.4.4
109
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1144-ENGR00169603-MX53-ARD-FlexCAN-Set-lp_apm-as-clock.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1144-ENGR00169603-MX53-ARD-FlexCAN-Set-lp_apm-as-clock.patch
deleted file mode 100755
index 360902c71..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1144-ENGR00169603-MX53-ARD-FlexCAN-Set-lp_apm-as-clock.patch
+++ /dev/null
@@ -1,37 +0,0 @@
1From a5baaf44b75b0bd6d3411fc87531ddfd411e34fb Mon Sep 17 00:00:00 2001
2From: Rogerio Pimentel <rogerio.pimentel@freescale.com>
3Date: Thu, 8 Dec 2011 16:33:41 -0200
4Subject: [PATCH] ENGR00169603 MX53 ARD: FlexCAN: Set lp_apm as clock source
5
6The FlexCAN clock source must be lp_apm (24MHZ) instead
7ipg_clock_root (60MHZ) to meet automotive clock requirements.
8
9Signed-off-by: Rogerio Pimentel <rogerio.pimentel@freescale.com>
10(cherry picked from commit b7456a4f5f6fa12235effbffe4e4d1b62159b948)
11---
12 arch/arm/mach-mx5/mx53_ard.c | 2 ++
13 1 files changed, 2 insertions(+), 0 deletions(-)
14
15diff --git a/arch/arm/mach-mx5/mx53_ard.c b/arch/arm/mach-mx5/mx53_ard.c
16index 378e1c1..b1252fb 100644
17--- a/arch/arm/mach-mx5/mx53_ard.c
18+++ b/arch/arm/mach-mx5/mx53_ard.c
19@@ -455,6 +455,7 @@ static void flexcan_xcvr_enable(int id, int en)
20 static struct flexcan_platform_data flexcan0_data = {
21 .core_reg = NULL,
22 .io_reg = NULL,
23+ .root_clk_id = "lp_apm",
24 .xcvr_enable = flexcan_xcvr_enable,
25 .br_clksrc = 1,
26 .br_rjw = 2,
27@@ -472,6 +473,7 @@ static struct flexcan_platform_data flexcan0_data = {
28 static struct flexcan_platform_data flexcan1_data = {
29 .core_reg = NULL,
30 .io_reg = NULL,
31+ .root_clk_id = "lp_apm",
32 .xcvr_enable = flexcan_xcvr_enable,
33 .br_clksrc = 1,
34 .br_rjw = 2,
35--
361.5.4.4
37
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1145-ENGR00170342-PWM-fix-pwm-output-can-t-be-set-to-100.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1145-ENGR00170342-PWM-fix-pwm-output-can-t-be-set-to-100.patch
deleted file mode 100755
index 095ab148f..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1145-ENGR00170342-PWM-fix-pwm-output-can-t-be-set-to-100.patch
+++ /dev/null
@@ -1,35 +0,0 @@
1From d1eff01309855f850d82e4ce9abe42ad76aa7f9f Mon Sep 17 00:00:00 2001
2From: Yuxi Sun <b36102@freescale.com>
3Date: Thu, 15 Dec 2011 10:12:53 +0800
4Subject: [PATCH] ENGR00170342 PWM: fix pwm output can't be set to 100% full duty
5
6The chip document says the counter counts up to period_cycles + 1
7and then is reset to 0, so the actual period of the PWM wave is
8period_cycles + 2
9
10Signed-off-by: Yuxi Sun <b36102@freescale.com>
11(cherry picked from commit e1465447502c77b2951af7ace43d8f76fa5039fb)
12---
13 arch/arm/plat-mxc/pwm.c | 6 +++++-
14 1 files changed, 5 insertions(+), 1 deletions(-)
15
16diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
17index 2f8a35e..ccba298 100644
18--- a/arch/arm/plat-mxc/pwm.c
19+++ b/arch/arm/plat-mxc/pwm.c
20@@ -83,7 +83,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
21 prescale = period_cycles / 0x10000 + 1;
22
23 period_cycles /= prescale;
24- c = (unsigned long long)period_cycles * duty_ns;
25+ /* the chip document says the counter counts up to
26+ * period_cycles + 1 and then is reset to 0, so the
27+ * actual period of the PWM wave is period_cycles + 2
28+ */
29+ c = (unsigned long long)(period_cycles + 2) * duty_ns;
30 do_div(c, period_ns);
31 duty_cycles = c;
32
33--
341.5.4.4
35
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1146-ENGR00170244-1-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1146-ENGR00170244-1-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch
deleted file mode 100755
index 9a6def323..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1146-ENGR00170244-1-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch
+++ /dev/null
@@ -1,80 +0,0 @@
1From 10df11bb736c8166e53b41f96688b2e6bd53773b Mon Sep 17 00:00:00 2001
2From: Richard Zhu <r65037@freescale.com>
3Date: Fri, 16 Dec 2011 10:08:04 +0800
4Subject: [PATCH] ENGR00170244-1 ARM: AHCI: Enable PDDQ mode when no disk is attached
5
6In order to save the power consumption, enable the
7PDDQ mode of AHCI PHY when there is no sata disk
8on the port
9
10Signed-off-by: Richard Zhu <r65037@freescale.com>
11(cherry picked from commit a53c29d7e484a3562e3a4f24d952485fbeb4c933)
12---
13 arch/arm/plat-mxc/ahci_sata.c | 30 ++++++++++++++++++++-------
14 arch/arm/plat-mxc/include/mach/ahci_sata.h | 1 +
15 2 files changed, 23 insertions(+), 8 deletions(-)
16
17diff --git a/arch/arm/plat-mxc/ahci_sata.c b/arch/arm/plat-mxc/ahci_sata.c
18index 466636b..76a2747 100644
19--- a/arch/arm/plat-mxc/ahci_sata.c
20+++ b/arch/arm/plat-mxc/ahci_sata.c
21@@ -156,7 +156,7 @@ static int sata_init(struct device *dev)
22 {
23 void __iomem *mmio;
24 u32 tmpdata;
25- int ret = 0;
26+ int ret = 0, iterations = 20;
27 struct clk *clk;
28
29 sata_clk = clk_get(dev, "imx_sata_clk");
30@@ -281,14 +281,28 @@ static int sata_init(struct device *dev)
31
32 if (AHCI_SAVE_PWR_WITHOUT_HOTPLUG) {
33 /* Release resources when there is no device on the port */
34- if ((readl(mmio + PORT_SATA_SR) & 0xF) == 0) {
35- ret = -ENODEV;
36- if (machine_is_mx53_smd() || machine_is_mx53_loco()
37- || board_is_mx53_ard_b())
38- goto no_device;
39+ do {
40+ if ((readl(mmio + PORT_SATA_SR) & 0xF) == 0)
41+ msleep(25);
42 else
43- goto release_mem;
44- }
45+ break;
46+
47+ if (iterations == 0) {
48+ pr_info("No sata disk.\n");
49+ ret = -ENODEV;
50+ /* Enter into PDDQ mode, save power */
51+ tmpdata = readl(mmio + PORT_PHY_CTL);
52+ writel(tmpdata | PORT_PHY_CTL_PDDQ_LOC,
53+ mmio + PORT_PHY_CTL);
54+
55+ if (machine_is_mx53_smd()
56+ || machine_is_mx53_loco()
57+ || board_is_mx53_ard_b())
58+ goto no_device;
59+ else
60+ goto release_mem;
61+ }
62+ } while (iterations-- > 0);
63 }
64
65 iounmap(mmio);
66diff --git a/arch/arm/plat-mxc/include/mach/ahci_sata.h b/arch/arm/plat-mxc/include/mach/ahci_sata.h
67index ea68a19..e31797b 100644
68--- a/arch/arm/plat-mxc/include/mach/ahci_sata.h
69+++ b/arch/arm/plat-mxc/include/mach/ahci_sata.h
70@@ -37,6 +37,7 @@ enum {
71 PORT_PHY_CTL_CAP_DAT_LOC = 0x20000,
72 PORT_PHY_CTL_WRITE_LOC = 0x40000,
73 PORT_PHY_CTL_READ_LOC = 0x80000,
74+ PORT_PHY_CTL_PDDQ_LOC = 0x100000,
75 /* Port0 PHY Status */
76 PORT_PHY_SR = 0x17c,
77 /* PORT_PHY_SR */
78--
791.5.4.4
80
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1147-ENGR00170244-2-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch b/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1147-ENGR00170244-2-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch
deleted file mode 100755
index 3b14b8de6..000000000
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx-2.6.35.3/1147-ENGR00170244-2-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch
+++ /dev/null
@@ -1,53 +0,0 @@
1From 3cb5c41657a793fd442766d076eddde06af9c9ce Mon Sep 17 00:00:00 2001
2From: Richard Zhu <r65037@freescale.com>
3Date: Fri, 16 Dec 2011 10:08:42 +0800
4Subject: [PATCH] ENGR00170244-2 ARM: AHCI: Enable PDDQ mode when no disk is attached
5
6In order to save the power consumption, enable the
7PDDQ mode of AHCI PHY when there is no sata disk
8on the port
9
10Signed-off-by: Richard Zhu <r65037@freescale.com>
11(cherry picked from commit f97994abf50e9917a959ae62eabd08908a75a222)
12---
13 drivers/hwmon/imx_ahci_hwmon.c | 10 ++++++++++
14 1 files changed, 10 insertions(+), 0 deletions(-)
15
16diff --git a/drivers/hwmon/imx_ahci_hwmon.c b/drivers/hwmon/imx_ahci_hwmon.c
17index 62048f7..7688d92 100644
18--- a/drivers/hwmon/imx_ahci_hwmon.c
19+++ b/drivers/hwmon/imx_ahci_hwmon.c
20@@ -90,6 +90,11 @@ static ssize_t imx_ahci_hwmon_temp_show(struct device *dev,
21 return -1;
22 }
23
24+ /* Disable PDDQ mode when this mode is enabled */
25+ read_sum = readl(mmio + PORT_PHY_CTL);
26+ if (read_sum & PORT_PHY_CTL_PDDQ_LOC)
27+ writel(read_sum & ~PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
28+
29 /* check rd-wr to reg */
30 read_sum = 0;
31 sata_phy_cr_addr(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio);
32@@ -230,6 +235,10 @@ static ssize_t imx_ahci_hwmon_temp_show(struct device *dev,
33 a = (m2 - m1) / (m2 / 1000);
34 temp = ((((-559) * a) / 1000) * a) / 1000 + (1379) * a / 1000 + (-458);
35
36+ /* Enable PDDQ mode to save power */
37+ read_sum = readl(mmio + PORT_PHY_CTL);
38+ writel(read_sum | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
39+
40 iounmap(mmio);
41
42 /* Release the clocks */
43@@ -237,6 +246,7 @@ static ssize_t imx_ahci_hwmon_temp_show(struct device *dev,
44 clk_put(sata_ref_clk);
45 clk_disable(sata_clk);
46 clk_put(sata_clk);
47+
48 mutex_unlock(&hwmon->lock);
49
50 return sprintf(buf, "%d\n", temp * 1000);
51--
521.5.4.4
53
diff --git a/meta-fsl-arm/recipes-kernel/linux/linux-imx_2.6.35.3.bb b/meta-fsl-arm/recipes-kernel/linux/linux-imx_2.6.35.3.bb
index f54e2b969..b541ee1e0 100644
--- a/meta-fsl-arm/recipes-kernel/linux/linux-imx_2.6.35.3.bb
+++ b/meta-fsl-arm/recipes-kernel/linux/linux-imx_2.6.35.3.bb
@@ -4,33 +4,19 @@
4DESCRIPTION = "Linux kernel for imx platforms" 4DESCRIPTION = "Linux kernel for imx platforms"
5LICENSE = "GPLv2" 5LICENSE = "GPLv2"
6LIC_FILES_CHKSUM = "file://COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7" 6LIC_FILES_CHKSUM = "file://COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7"
7PR = "r29" 7PR = "r30"
8 8
9inherit kernel 9inherit kernel
10COMPATIBLE_MACHINE = "(mxs|mx5)" 10COMPATIBLE_MACHINE = "(mxs|mx5)"
11 11
12# Revision of 'rel_imx_2.6.35_11.09.01' tag 12# Revision of imx_2.6.35_11.09.01 branch
13SRCREV = "691c08adeed64d5153937a0e31aaf4c251924471" 13SRCREV = "3e2396eddb362ff70ee6eac43fb1f27f217dc0d1"
14 14
15SRC_URI = "git://git.freescale.com/imx/linux-2.6-imx.git \ 15SRC_URI = "git://git.freescale.com/imx/linux-2.6-imx.git \
16 file://0002-cgroupfs-create-sys-fs-cgroup-to-mount-cgroupfs-on.patch \ 16 file://0002-cgroupfs-create-sys-fs-cgroup-to-mount-cgroupfs-on.patch \
17 file://egalax_ts-enable-single-event-support.patch \ 17 file://egalax_ts-enable-single-event-support.patch \
18 file://NFS-Fix-nfsroot-support.patch \ 18 file://NFS-Fix-nfsroot-support.patch \
19 file://NFS-allow-nfs-root-mount-to-use-alternate-rpc-ports.patch \ 19 file://NFS-allow-nfs-root-mount-to-use-alternate-rpc-ports.patch \
20 file://1130-ENGR00157473-MX5X-UART-disable-UART2-DMA-to-make-G.patch \
21 file://1132-ENGR00155891-mx53_loco-enable-mc34708-s-WDI-functio.patch \
22 file://1134-ENGR00159738-v4l2-correct-wrong-parameter-when-V4l2.patch \
23 file://1136-ENGR00161215-1-arch-arm-Add-two-new-IOCTLs-in-mxc_v.patch \
24 file://1137-ENGR00161215-2-vpu-Add-ioctls-for-querying-and-sett.patch \
25 file://1139-ENGR00162464-update-pm4-microcode-pm4_microcode_r18.patch \
26 file://1140-ENGR00162711-DA9053-Add-dummy-write-for-DA9053-I2C.patch \
27 file://1141-ENGR00162708-MX5-Add-I2C-dummy-write-and-mask-nONKE.patch \
28 file://1142-ENGR00163698-MX53-ARD-fix-typo-error-for-pwm1-pad-d.patch \
29 file://1143-ENGR00162578-DMA-mx5-increase-DMA-Zone-size-to-112.patch \
30 file://1144-ENGR00169603-MX53-ARD-FlexCAN-Set-lp_apm-as-clock.patch \
31 file://1145-ENGR00170342-PWM-fix-pwm-output-can-t-be-set-to-100.patch \
32 file://1146-ENGR00170244-1-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch \
33 file://1147-ENGR00170244-2-ARM-AHCI-Enable-PDDQ-mode-when-no-d.patch \
34 file://no-unaligned-access.patch \ 20 file://no-unaligned-access.patch \
35 file://mx28-removecpufreq.patch \ 21 file://mx28-removecpufreq.patch \
36 file://mxs-duart-use-ttyAMA-for-device-name.patch \ 22 file://mxs-duart-use-ttyAMA-for-device-name.patch \
@@ -44,15 +30,6 @@ SRC_URI = "git://git.freescale.com/imx/linux-2.6-imx.git \
44 file://defconfig \ 30 file://defconfig \
45 " 31 "
46 32
47# TODO: Work in progress to follow Freescale. The following patches are
48# causing black screens when using VPU video playout.
49# -- Leon Woestenberg <leon@sidebranch.com>
50#
51# file://1131-ENGR00158480-IPUv3-Set-IDMAC-LOCK-for-SDC-display-ch.patch \
52# file://1133-ENGR00159010-IPUv3-Restore-IDMAC_CH_LOCK_EN_1-for-re.patch \
53# file://1138-ENGR00162195-IPUv3M-Clear-IDMAC_LOCK_EN_1-for-tough.patch \
54# file://1135-ENGR00160566-IPUv3-Improve-IDMAC_LOCK_EN-setting.patch \
55# file://devtmpfs-init-options-alignment.patch \
56#EXTRA_OEMAKE += "V=1" 33#EXTRA_OEMAKE += "V=1"
57 34
58S = "${WORKDIR}/git" 35S = "${WORKDIR}/git"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-12-18 15:11:37 +0000