57 files changed, 9222 insertions, 1 deletions
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0001-MX5-Add-definitions-for-SATA-controller.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0001-MX5-Add-definitions-for-SATA-controller.patch
new file mode 100644
index 000000000..a4da34585
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0001-MX5-Add-definitions-for-SATA-controller.patch
@@ -0,0 +1,57 @@
+From 4a7ee25e3f89d77a8ced081b73aebfb7a882302c Mon Sep 17 00:00:00 2001
+From: Stefano Babic <sbabic@denx.de>
+Date: Wed, 22 Feb 2012 00:24:36 +0000
+Subject: [PATCH 01/56] MX5: Add definitions for SATA controller
+Add base address and MXC_SATA_CLK to return
+the clock used for the SATA controller.
+Signed-off-by: Stefano Babic <sbabic@denx.de>
+CC: Fabio Estevam <fabio.estevam@freescale.com>
+CC: Dirk Behme <dirk.behme@de.bosch.com>
+---
+ arch/arm/cpu/armv7/mx5/clock.c           |    2 ++
+ arch/arm/include/asm/arch-mx5/clock.h    |    1 +
+ arch/arm/include/asm/arch-mx5/imx-regs.h |    1 +
+ 3 files changed, 4 insertions(+)
+diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
+index e92f106..8f8d01c 100644
+--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
+@@ -380,6 +380,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
+        case MXC_FEC_CLK:
+                return decode_pll(mxc_plls[PLL1_CLOCK],
+                                    CONFIG_SYS_MX5_HCLK);
+       case MXC_SATA_CLK:
+               return get_ahb_clk();
+        default:
+                break;
+        }
+diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
+index ea972a3..f9f82f3 100644
+--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
+@@ -32,6 +32,7 @@ enum mxc_clock {
+        MXC_UART_CLK,
+        MXC_CSPI_CLK,
+        MXC_FEC_CLK,
+       MXC_SATA_CLK,
+ };
+ 
+ unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
+diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
+index 4fa6658..262517e 100644
+--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
+@@ -43,6 +43,7 @@
+ #define NFC_BASE_ADDR_AXI       0xF7FF0000
+ #define IRAM_BASE_ADDR          0xF8000000
+ #define CS1_BASE_ADDR           0xF4000000
+#define SATA_BASE_ADDR         0x10000000
+ #else
+ #error "CPU_TYPE not defined"
+ #endif
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0002-SATA-check-for-return-value-from-sata-functions.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0002-SATA-check-for-return-value-from-sata-functions.patch
new file mode 100644
index 000000000..98135d7ba
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0002-SATA-check-for-return-value-from-sata-functions.patch
@@ -0,0 +1,38 @@
+From 5b37d183ef45f83c23f7a85d3bc87708fb07598a Mon Sep 17 00:00:00 2001
+From: Stefano Babic <sbabic@denx.de>
+Date: Wed, 22 Feb 2012 00:24:37 +0000
+Subject: [PATCH 02/56] SATA: check for return value from sata functions
+sata functions are called even if previous functions failed
+because return value is not checked.
+Signed-off-by: Stefano Babic <sbabic@denx.de>
+CC: Dirk Behme <dirk.behme@de.bosch.com>
+CC: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ common/cmd_sata.c |    9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+diff --git a/common/cmd_sata.c b/common/cmd_sata.c
+index 7b1703f..3f98235 100644
+--- a/common/cmd_sata.c
+++ b/common/cmd_sata.c
+@@ -48,9 +48,12 @@ int __sata_initialize(void)
+                sata_dev_desc[i].block_write = sata_write;
+ 
+                rc = init_sata(i);
+-               rc = scan_sata(i);
+-               if ((sata_dev_desc[i].lba > 0) && (sata_dev_desc[i].blksz > 0))
+-                       init_part(&sata_dev_desc[i]);
+               if (!rc) {
+                       rc = scan_sata(i);
+                       if (!rc && (sata_dev_desc[i].lba > 0) &&
+                               (sata_dev_desc[i].blksz > 0))
+                               init_part(&sata_dev_desc[i]);
+               }
+        }
+        sata_curr_device = 0;
+        return rc;
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0003-MX53-add-function-to-set-SATA-clock-to-internal.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0003-MX53-add-function-to-set-SATA-clock-to-internal.patch
new file mode 100644
index 000000000..2a4eb9438
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0003-MX53-add-function-to-set-SATA-clock-to-internal.patch
@@ -0,0 +1,77 @@
+From b22729b27625107061733c718cb49a394fd41a4a Mon Sep 17 00:00:00 2001
+From: Stefano Babic <sbabic@denx.de>
+Date: Wed, 22 Feb 2012 00:24:38 +0000
+Subject: [PATCH 03/56] MX53: add function to set SATA clock to internal
+The MX53 SATA interface can use an internal clock (USB PHY1)
+instead of an external clock. This is an undocumented feature, but used
+on most Freescale's evaluation boards, such as MX53-loco.
+As stated by Freescale's support:
+Fuses (but not pins) may be used to configure SATA clocks.
+Particularly the i.MX53 Fuse_Map contains the next information
+about configuring SATA clocks :
+        SATA_ALT_REF_CLK[1:0] (offset 0x180C)
+'00' - 100MHz (External)
+'01' - 50MHz (External)
+'10' - 120MHz, internal (USB PHY)
+'11' - Reserved
+Signed-off-by: Stefano Babic <sbabic@denx.de>
+CC: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ arch/arm/cpu/armv7/mx5/clock.c        |   24 ++++++++++++++++++++++++
+ arch/arm/include/asm/arch-mx5/clock.h |    1 +
+ 2 files changed, 25 insertions(+)
+diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
+index 8f8d01c..d769a4d 100644
+--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
+@@ -399,6 +399,30 @@ u32 imx_get_fecclk(void)
+        return mxc_get_clock(MXC_IPG_CLK);
+ }
+ 
+#ifdef CONFIG_MX53
+/*
+ * The clock for the external interface can be set to use internal clock
+ * if fuse bank 4, row 3, bit 2 is set.
+ * This is an undocumented feature and it was confirmed by Freescale's support:
+ * Fuses (but not pins) may be used to configure SATA clocks.
+ * Particularly the i.MX53 Fuse_Map contains the next information
+ * about configuring SATA clocks :  SATA_ALT_REF_CLK[1:0] (offset 0x180C)
+ * '00' - 100MHz (External)
+ * '01' - 50MHz (External)
+ * '10' - 120MHz, internal (USB PHY)
+ * '11' - Reserved
+*/
+void mxc_set_sata_internal_clock(void)
+{
+       u32 *tmp_base =
+               (u32 *)(IIM_BASE_ADDR + 0x180c);
+
+       set_usb_phy1_clk();
+
+       writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base);
+}
+#endif
+
+ /*
+  * Dump some core clockes.
+  */
+diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
+index f9f82f3..e822809 100644
+--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
+@@ -45,5 +45,6 @@ void set_usb_phy2_clk(void);
+ void enable_usb_phy2_clk(unsigned char enable);
+ void set_usboh3_clk(void);
+ void enable_usboh3_clk(unsigned char enable);
+void mxc_set_sata_internal_clock(void);
+ 
+ #endif /* __ASM_ARCH_CLOCK_H */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0004-SATA-add-driver-for-MX5-MX6-SOCs.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0004-SATA-add-driver-for-MX5-MX6-SOCs.patch
new file mode 100644
index 000000000..e4e93a69d
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0004-SATA-add-driver-for-MX5-MX6-SOCs.patch
@@ -0,0 +1,1372 @@
+From 160e7d7c3fbbcbb60ba71eb984f633db26494646 Mon Sep 17 00:00:00 2001
+From: Stefano Babic <sbabic@denx.de>
+Date: Wed, 22 Feb 2012 00:24:39 +0000
+Subject: [PATCH 04/56] SATA: add driver for MX5 / MX6 SOCs
+This driver is part of Freescale's LTIB for
+MX5 / MX6.
+Signed-off-by: Stefano Babic <sbabic@denx.de>
+Signed-off-by: Terry Lv <r65388@freescale.com>
+CC: Fabio Estevam <fabio.estevam@freescale.com>
+CC: Dirk Behme <dirk.behme@de.bosch.com>
+---
+ drivers/block/Makefile     |    1 +
+ drivers/block/dwc_ahsata.c |  969 ++++++++++++++++++++++++++++++++++++++++++++
+ drivers/block/dwc_ahsata.h |  335 +++++++++++++++
+ include/ahci.h             |    5 +-
+ 4 files changed, 1308 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/block/dwc_ahsata.c
+ create mode 100644 drivers/block/dwc_ahsata.h
+diff --git a/drivers/block/Makefile b/drivers/block/Makefile
+index 98560ef..b9c2047 100644
+--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
+@@ -27,6 +27,7 @@ LIB   := $(obj)libblock.o
+ 
+ COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
+ COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o
+COBJS-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
+ COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o
+ COBJS-$(CONFIG_IDE_FTIDE020) += ftide020.o
+ COBJS-$(CONFIG_LIBATA) += libata.o
+diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
+new file mode 100644
+index 0000000..2703d3d
+--- /dev/null
+++ b/drivers/block/dwc_ahsata.c
+@@ -0,0 +1,969 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Terry Lv <r65388@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ *
+ */
+
+#include <libata.h>
+#include <ahci.h>
+#include <fis.h>
+
+#include <common.h>
+#include <malloc.h>
+#include <linux/ctype.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <asm/arch/clock.h>
+#include "dwc_ahsata.h"
+
+struct sata_port_regs {
+       u32 clb;
+       u32 clbu;
+       u32 fb;
+       u32 fbu;
+       u32 is;
+       u32 ie;
+       u32 cmd;
+       u32 res1[1];
+       u32 tfd;
+       u32 sig;
+       u32 ssts;
+       u32 sctl;
+       u32 serr;
+       u32 sact;
+       u32 ci;
+       u32 sntf;
+       u32 res2[1];
+       u32 dmacr;
+       u32 res3[1];
+       u32 phycr;
+       u32 physr;
+};
+
+struct sata_host_regs {
+       u32 cap;
+       u32 ghc;
+       u32 is;
+       u32 pi;
+       u32 vs;
+       u32 ccc_ctl;
+       u32 ccc_ports;
+       u32 res1[2];
+       u32 cap2;
+       u32 res2[30];
+       u32 bistafr;
+       u32 bistcr;
+       u32 bistfctr;
+       u32 bistsr;
+       u32 bistdecr;
+       u32 res3[2];
+       u32 oobr;
+       u32 res4[8];
+       u32 timer1ms;
+       u32 res5[1];
+       u32 gparam1r;
+       u32 gparam2r;
+       u32 pparamr;
+       u32 testr;
+       u32 versionr;
+       u32 idr;
+};
+
+#define MAX_DATA_BYTES_PER_SG  (4 * 1024 * 1024)
+#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
+
+#define writel_with_flush(a, b)        do { writel(a, b); readl(b); } while (0)
+
+static int is_ready;
+
+static inline u32 ahci_port_base(u32 base, u32 port)
+{
+       return base + 0x100 + (port * 0x80);
+}
+
+static int waiting_for_cmd_completed(u8 *offset,
+                                       int timeout_msec,
+                                       u32 sign)
+{
+       int i;
+       u32 status;
+
+       for (i = 0;
+               ((status = readl(offset)) & sign) && i < timeout_msec;
+               ++i)
+               mdelay(1);
+
+       return (i < timeout_msec) ? 0 : -1;
+}
+
+static int ahci_setup_oobr(struct ahci_probe_ent *probe_ent,
+                                               int clk)
+{
+       struct sata_host_regs *host_mmio =
+               (struct sata_host_regs *)probe_ent->mmio_base;
+
+       writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr));
+       writel(0x02060b14, &(host_mmio->oobr));
+
+       return 0;
+}
+
+static int ahci_host_init(struct ahci_probe_ent *probe_ent)
+{
+       u32 tmp, cap_save, num_ports;
+       int i, j, timeout = 1000;
+       struct sata_port_regs *port_mmio = NULL;
+       struct sata_host_regs *host_mmio =
+               (struct sata_host_regs *)probe_ent->mmio_base;
+       int clk = mxc_get_clock(MXC_SATA_CLK);
+
+       cap_save = readl(&(host_mmio->cap));
+       cap_save |= SATA_HOST_CAP_SSS;
+
+       /* global controller reset */
+       tmp = readl(&(host_mmio->ghc));
+       if ((tmp & SATA_HOST_GHC_HR) == 0)
+               writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc));
+
+       while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR)
+               && --timeout)
+               ;
+
+       if (timeout <= 0) {
+               debug("controller reset failed (0x%x)\n", tmp);
+               return -1;
+       }
+
+       /* Set timer 1ms */
+       writel(clk / 1000, &(host_mmio->timer1ms));
+
+       ahci_setup_oobr(probe_ent, 0);
+
+       writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc));
+       writel(cap_save, &(host_mmio->cap));
+       num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
+       writel_with_flush((1 << num_ports) - 1,
+                               &(host_mmio->pi));
+
+       /*
+        * Determine which Ports are implemented by the DWC_ahsata,
+        * by reading the PI register. This bit map value aids the
+        * software to determine how many Ports are available and
+        * which Port registers need to be initialized.
+        */
+       probe_ent->cap = readl(&(host_mmio->cap));
+       probe_ent->port_map = readl(&(host_mmio->pi));
+
+       /* Determine how many command slots the HBA supports */
+       probe_ent->n_ports =
+               (probe_ent->cap & SATA_HOST_CAP_NP_MASK) + 1;
+
+       debug("cap 0x%x  port_map 0x%x  n_ports %d\n",
+               probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
+
+       for (i = 0; i < probe_ent->n_ports; i++) {
+               probe_ent->port[i].port_mmio =
+                       ahci_port_base((u32)host_mmio, i);
+               port_mmio =
+                       (struct sata_port_regs *)probe_ent->port[i].port_mmio;
+
+               /* Ensure that the DWC_ahsata is in idle state */
+               tmp = readl(&(port_mmio->cmd));
+
+               /*
+                * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
+                * are all cleared, the Port is in an idle state.
+                */
+               if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
+                       SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
+
+                       /*
+                        * System software places a Port into the idle state by
+                        * clearing P#CMD.ST and waiting for P#CMD.CR to return
+                        * 0 when read.
+                        */
+                       tmp &= ~SATA_PORT_CMD_ST;
+                       writel_with_flush(tmp, &(port_mmio->cmd));
+
+                       /*
+                        * spec says 500 msecs for each bit, so
+                        * this is slightly incorrect.
+                        */
+                       mdelay(500);
+
+                       timeout = 1000;
+                       while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR)
+                               && --timeout)
+                               ;
+
+                       if (timeout <= 0) {
+                               debug("port reset failed (0x%x)\n", tmp);
+                               return -1;
+                       }
+               }
+
+               /* Spin-up device */
+               tmp = readl(&(port_mmio->cmd));
+               writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd));
+
+               /* Wait for spin-up to finish */
+               timeout = 1000;
+               while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD)
+                       && --timeout)
+                       ;
+               if (timeout <= 0) {
+                       debug("Spin-Up can't finish!\n");
+                       return -1;
+               }
+
+               for (j = 0; j < 100; ++j) {
+                       mdelay(10);
+                       tmp = readl(&(port_mmio->ssts));
+                       if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
+                               ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
+                               break;
+               }
+
+               /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
+               timeout = 1000;
+               while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X)
+                       && --timeout)
+                       ;
+               if (timeout <= 0) {
+                       debug("Can't find DIAG_X set!\n");
+                       return -1;
+               }
+
+               /*
+                * For each implemented Port, clear the P#SERR
+                * register, by writing ones to each implemented\
+                * bit location.
+                */
+               tmp = readl(&(port_mmio->serr));
+               debug("P#SERR 0x%x\n",
+                               tmp);
+               writel(tmp, &(port_mmio->serr));
+
+               /* Ack any pending irq events for this port */
+               tmp = readl(&(host_mmio->is));
+               debug("IS 0x%x\n", tmp);
+               if (tmp)
+                       writel(tmp, &(host_mmio->is));
+
+               writel(1 << i, &(host_mmio->is));
+
+               /* set irq mask (enables interrupts) */
+               writel(DEF_PORT_IRQ, &(port_mmio->ie));
+
+               /* register linkup ports */
+               tmp = readl(&(port_mmio->ssts));
+               debug("Port %d status: 0x%x\n", i, tmp);
+               if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
+                       probe_ent->link_port_map |= (0x01 << i);
+       }
+
+       tmp = readl(&(host_mmio->ghc));
+       debug("GHC 0x%x\n", tmp);
+       writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc));
+       tmp = readl(&(host_mmio->ghc));
+       debug("GHC 0x%x\n", tmp);
+
+       return 0;
+}
+
+static void ahci_print_info(struct ahci_probe_ent *probe_ent)
+{
+       struct sata_host_regs *host_mmio =
+               (struct sata_host_regs *)probe_ent->mmio_base;
+       u32 vers, cap, impl, speed;
+       const char *speed_s;
+       const char *scc_s;
+
+       vers = readl(&(host_mmio->vs));
+       cap = probe_ent->cap;
+       impl = probe_ent->port_map;
+
+       speed = (cap & SATA_HOST_CAP_ISS_MASK)
+               >> SATA_HOST_CAP_ISS_OFFSET;
+       if (speed == 1)
+               speed_s = "1.5";
+       else if (speed == 2)
+               speed_s = "3";
+       else
+               speed_s = "?";
+
+       scc_s = "SATA";
+
+       printf("AHCI %02x%02x.%02x%02x "
+               "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
+               (vers >> 24) & 0xff,
+               (vers >> 16) & 0xff,
+               (vers >> 8) & 0xff,
+               vers & 0xff,
+               ((cap >> 8) & 0x1f) + 1,
+               (cap & 0x1f) + 1,
+               speed_s,
+               impl,
+               scc_s);
+
+       printf("flags: "
+               "%s%s%s%s%s%s"
+               "%s%s%s%s%s%s%s\n",
+               cap & (1 << 31) ? "64bit " : "",
+               cap & (1 << 30) ? "ncq " : "",
+               cap & (1 << 28) ? "ilck " : "",
+               cap & (1 << 27) ? "stag " : "",
+               cap & (1 << 26) ? "pm " : "",
+               cap & (1 << 25) ? "led " : "",
+               cap & (1 << 24) ? "clo " : "",
+               cap & (1 << 19) ? "nz " : "",
+               cap & (1 << 18) ? "only " : "",
+               cap & (1 << 17) ? "pmp " : "",
+               cap & (1 << 15) ? "pio " : "",
+               cap & (1 << 14) ? "slum " : "",
+               cap & (1 << 13) ? "part " : "");
+}
+
+static int ahci_init_one(int pdev)
+{
+       int rc;
+       struct ahci_probe_ent *probe_ent = NULL;
+
+       probe_ent = malloc(sizeof(struct ahci_probe_ent));
+       memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
+       probe_ent->dev = pdev;
+
+       probe_ent->host_flags = ATA_FLAG_SATA
+                               | ATA_FLAG_NO_LEGACY
+                               | ATA_FLAG_MMIO
+                               | ATA_FLAG_PIO_DMA
+                               | ATA_FLAG_NO_ATAPI;
+
+       probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR;
+
+       /* initialize adapter */
+       rc = ahci_host_init(probe_ent);
+       if (rc)
+               goto err_out;
+
+       ahci_print_info(probe_ent);
+
+       /* Save the private struct to block device struct */
+       sata_dev_desc[pdev].priv = (void *)probe_ent;
+
+       return 0;
+
+err_out:
+       return rc;
+}
+
+static int ahci_fill_sg(struct ahci_probe_ent *probe_ent,
+                       u8 port, unsigned char *buf, int buf_len)
+{
+       struct ahci_ioports *pp = &(probe_ent->port[port]);
+       struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
+       u32 sg_count, max_bytes;
+       int i;
+
+       max_bytes = MAX_DATA_BYTES_PER_SG;
+       sg_count = ((buf_len - 1) / max_bytes) + 1;
+       if (sg_count > AHCI_MAX_SG) {
+               printf("Error:Too much sg!\n");
+               return -1;
+       }
+
+       for (i = 0; i < sg_count; i++) {
+               ahci_sg->addr =
+                       cpu_to_le32((u32)buf + i * max_bytes);
+               ahci_sg->addr_hi = 0;
+               ahci_sg->flags_size = cpu_to_le32(0x3fffff &
+                                       (buf_len < max_bytes
+                                       ? (buf_len - 1)
+                                       : (max_bytes - 1)));
+               ahci_sg++;
+               buf_len -= max_bytes;
+       }
+
+       return sg_count;
+}
+
+static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
+{
+       struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
+                                       AHCI_CMD_SLOT_SZ * cmd_slot);
+
+       memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
+       cmd_hdr->opts = cpu_to_le32(opts);
+       cmd_hdr->status = 0;
+       cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
+       cmd_hdr->tbl_addr_hi = 0;
+}
+
+#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
+
+static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent,
+               u8 port, struct sata_fis_h2d *cfis,
+               u8 *buf, u32 buf_len, s32 is_write)
+{
+       struct ahci_ioports *pp = &(probe_ent->port[port]);
+       struct sata_port_regs *port_mmio =
+                       (struct sata_port_regs *)pp->port_mmio;
+       u32 opts;
+       int sg_count = 0, cmd_slot = 0;
+
+       cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci)));
+       if (32 == cmd_slot) {
+               printf("Can't find empty command slot!\n");
+               return 0;
+       }
+
+       /* Check xfer length */
+       if (buf_len > MAX_BYTES_PER_TRANS) {
+               printf("Max transfer length is %dB\n\r",
+                       MAX_BYTES_PER_TRANS);
+               return 0;
+       }
+
+       memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
+       if (buf && buf_len)
+               sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len);
+       opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
+       if (is_write)
+               opts |= 0x40;
+       ahci_fill_cmd_slot(pp, cmd_slot, opts);
+
+       writel_with_flush(1 << cmd_slot, &(port_mmio->ci));
+
+       if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci),
+                               10000, 0x1 << cmd_slot)) {
+               printf("timeout exit!\n");
+               return -1;
+       }
+       debug("ahci_exec_ata_cmd: %d byte transferred.\n",
+             pp->cmd_slot->status);
+
+       return buf_len;
+}
+
+static void ahci_set_feature(u8 dev, u8 port)
+{
+       struct ahci_probe_ent *probe_ent =
+               (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+       struct sata_fis_h2d h2d, *cfis = &h2d;
+
+       memset(cfis, 0, sizeof(struct sata_fis_h2d));
+       cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+       cfis->pm_port_c = 1 << 7;
+       cfis->command = ATA_CMD_SET_FEATURES;
+       cfis->features = SETFEATURES_XFER;
+       cfis->sector_count = ffs(probe_ent->udma_mask + 1) + 0x3e;
+
+       ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, READ_CMD);
+}
+
+static int ahci_port_start(struct ahci_probe_ent *probe_ent,
+                                       u8 port)
+{
+       struct ahci_ioports *pp = &(probe_ent->port[port]);
+       struct sata_port_regs *port_mmio =
+               (struct sata_port_regs *)pp->port_mmio;
+       u32 port_status;
+       u32 mem;
+       int timeout = 10000000;
+
+       debug("Enter start port: %d\n", port);
+       port_status = readl(&(port_mmio->ssts));
+       debug("Port %d status: %x\n", port, port_status);
+       if ((port_status & 0xf) != 0x03) {
+               printf("No Link on this port!\n");
+               return -1;
+       }
+
+       mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
+       if (!mem) {
+               free(pp);
+               printf("No mem for table!\n");
+               return -ENOMEM;
+       }
+
+       mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
+       memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
+
+       /*
+        * First item in chunk of DMA memory: 32-slot command table,
+        * 32 bytes each in size
+        */
+       pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
+       debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
+       mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
+
+       /*
+        * Second item: Received-FIS area, 256-Byte aligned
+        */
+       pp->rx_fis = mem;
+       mem += AHCI_RX_FIS_SZ;
+
+       /*
+        * Third item: data area for storing a single command
+        * and its scatter-gather table
+        */
+       pp->cmd_tbl = mem;
+       debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
+
+       mem += AHCI_CMD_TBL_HDR;
+
+       writel_with_flush(0x00004444, &(port_mmio->dmacr));
+       pp->cmd_tbl_sg = (struct ahci_sg *)mem;
+       writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb));
+       writel_with_flush(pp->rx_fis, &(port_mmio->fb));
+
+       /* Enable FRE */
+       writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))),
+                       &(port_mmio->cmd));
+
+       /* Wait device ready */
+       while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR |
+               SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
+               && --timeout)
+               ;
+       if (timeout <= 0) {
+               debug("Device not ready for BSY, DRQ and"
+                       "ERR in TFD!\n");
+               return -1;
+       }
+
+       writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
+                         PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
+                         PORT_CMD_START, &(port_mmio->cmd));
+
+       debug("Exit start port %d\n", port);
+
+       return 0;
+}
+
+int init_sata(int dev)
+{
+       int i;
+       u32 linkmap;
+       struct ahci_probe_ent *probe_ent = NULL;
+
+       if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
+               printf("The sata index %d is out of ranges\n\r", dev);
+               return -1;
+       }
+
+       ahci_init_one(dev);
+
+       probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+       linkmap = probe_ent->link_port_map;
+
+       if (0 == linkmap) {
+               printf("No port device detected!\n");
+               return 1;
+       }
+
+       for (i = 0; i < probe_ent->n_ports; i++) {
+               if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
+                       if (ahci_port_start(probe_ent, (u8)i)) {
+                               printf("Can not start port %d\n", i);
+                               return 1;
+                       }
+                       probe_ent->hard_port_no = i;
+                       break;
+               }
+       }
+
+       return 0;
+}
+
+static void dwc_ahsata_print_info(int dev)
+{
+       block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
+
+       printf("SATA Device Info:\n\r");
+#ifdef CONFIG_SYS_64BIT_LBA
+       printf("S/N: %s\n\rProduct model number: %s\n\r"
+               "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
+               pdev->product, pdev->vendor, pdev->revision, pdev->lba);
+#else
+       printf("S/N: %s\n\rProduct model number: %s\n\r"
+               "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
+               pdev->product, pdev->vendor, pdev->revision, pdev->lba);
+#endif
+}
+
+static void dwc_ahsata_identify(int dev, u16 *id)
+{
+       struct ahci_probe_ent *probe_ent =
+               (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+       struct sata_fis_h2d h2d, *cfis = &h2d;
+       u8 port = probe_ent->hard_port_no;
+
+       memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+       cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+       cfis->pm_port_c = 0x80; /* is command */
+       cfis->command = ATA_CMD_ID_ATA;
+
+       ahci_exec_ata_cmd(probe_ent, port, cfis,
+                       (u8 *)id, ATA_ID_WORDS * 2, READ_CMD);
+       ata_swap_buf_le16(id, ATA_ID_WORDS);
+}
+
+static void dwc_ahsata_xfer_mode(int dev, u16 *id)
+{
+       struct ahci_probe_ent *probe_ent =
+               (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+
+       probe_ent->pio_mask = id[ATA_ID_PIO_MODES];
+       probe_ent->udma_mask = id[ATA_ID_UDMA_MODES];
+       debug("pio %04x, udma %04x\n\r",
+               probe_ent->pio_mask, probe_ent->udma_mask);
+}
+
+static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt,
+                               u8 *buffer, int is_write)
+{
+       struct ahci_probe_ent *probe_ent =
+               (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+       struct sata_fis_h2d h2d, *cfis = &h2d;
+       u8 port = probe_ent->hard_port_no;
+       u32 block;
+
+       block = start;
+
+       memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+       cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+       cfis->pm_port_c = 0x80; /* is command */
+       cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
+       cfis->device = ATA_LBA;
+
+       cfis->device |= (block >> 24) & 0xf;
+       cfis->lba_high = (block >> 16) & 0xff;
+       cfis->lba_mid = (block >> 8) & 0xff;
+       cfis->lba_low = block & 0xff;
+       cfis->sector_count = (u8)(blkcnt & 0xff);
+
+       if (ahci_exec_ata_cmd(probe_ent, port, cfis,
+                       buffer, ATA_SECT_SIZE * blkcnt, is_write) > 0)
+               return blkcnt;
+       else
+               return 0;
+}
+
+void dwc_ahsata_flush_cache(int dev)
+{
+       struct ahci_probe_ent *probe_ent =
+               (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+       struct sata_fis_h2d h2d, *cfis = &h2d;
+       u8 port = probe_ent->hard_port_no;
+
+       memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+       cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+       cfis->pm_port_c = 0x80; /* is command */
+       cfis->command = ATA_CMD_FLUSH;
+
+       ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
+}
+
+static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt,
+                               u8 *buffer, int is_write)
+{
+       struct ahci_probe_ent *probe_ent =
+               (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+       struct sata_fis_h2d h2d, *cfis = &h2d;
+       u8 port = probe_ent->hard_port_no;
+       u64 block;
+
+       block = (u64)start;
+
+       memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+       cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+       cfis->pm_port_c = 0x80; /* is command */
+
+       cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
+                                : ATA_CMD_READ_EXT;
+
+       cfis->lba_high_exp = (block >> 40) & 0xff;
+       cfis->lba_mid_exp = (block >> 32) & 0xff;
+       cfis->lba_low_exp = (block >> 24) & 0xff;
+       cfis->lba_high = (block >> 16) & 0xff;
+       cfis->lba_mid = (block >> 8) & 0xff;
+       cfis->lba_low = block & 0xff;
+       cfis->device = ATA_LBA;
+       cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
+       cfis->sector_count = blkcnt & 0xff;
+
+       if (ahci_exec_ata_cmd(probe_ent, port, cfis, buffer,
+                       ATA_SECT_SIZE * blkcnt, is_write) > 0)
+               return blkcnt;
+       else
+               return 0;
+}
+
+u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt,
+                               u8 *buffer, int is_write)
+{
+       struct ahci_probe_ent *probe_ent =
+               (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+       struct sata_fis_h2d h2d, *cfis = &h2d;
+       u8 port = probe_ent->hard_port_no;
+       u64 block;
+
+       if (sata_dev_desc[dev].lba48 != 1) {
+               printf("execute FPDMA command on non-LBA48 hard disk\n\r");
+               return -1;
+       }
+
+       block = (u64)start;
+
+       memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+       cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+       cfis->pm_port_c = 0x80; /* is command */
+
+       cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
+                                : ATA_CMD_FPDMA_READ;
+
+       cfis->lba_high_exp = (block >> 40) & 0xff;
+       cfis->lba_mid_exp = (block >> 32) & 0xff;
+       cfis->lba_low_exp = (block >> 24) & 0xff;
+       cfis->lba_high = (block >> 16) & 0xff;
+       cfis->lba_mid = (block >> 8) & 0xff;
+       cfis->lba_low = block & 0xff;
+
+       cfis->device = ATA_LBA;
+       cfis->features_exp = (blkcnt >> 8) & 0xff;
+       cfis->features = blkcnt & 0xff;
+
+       /* Use the latest queue */
+       ahci_exec_ata_cmd(probe_ent, port, cfis,
+                       buffer, ATA_SECT_SIZE * blkcnt, is_write);
+
+       return blkcnt;
+}
+
+void dwc_ahsata_flush_cache_ext(int dev)
+{
+       struct ahci_probe_ent *probe_ent =
+               (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+       struct sata_fis_h2d h2d, *cfis = &h2d;
+       u8 port = probe_ent->hard_port_no;
+
+       memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+       cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+       cfis->pm_port_c = 0x80; /* is command */
+       cfis->command = ATA_CMD_FLUSH_EXT;
+
+       ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
+}
+
+static void dwc_ahsata_init_wcache(int dev, u16 *id)
+{
+       struct ahci_probe_ent *probe_ent =
+               (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+
+       if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
+               probe_ent->flags |= SATA_FLAG_WCACHE;
+       if (ata_id_has_flush(id))
+               probe_ent->flags |= SATA_FLAG_FLUSH;
+       if (ata_id_has_flush_ext(id))
+               probe_ent->flags |= SATA_FLAG_FLUSH_EXT;
+}
+
+u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
+                               void *buffer, int is_write)
+{
+       u32 start, blks;
+       u8 *addr;
+       int max_blks;
+
+       start = blknr;
+       blks = blkcnt;
+       addr = (u8 *)buffer;
+
+       max_blks = ATA_MAX_SECTORS_LBA48;
+
+       do {
+               if (blks > max_blks) {
+                       if (max_blks != dwc_ahsata_rw_cmd_ext(dev, start,
+                                               max_blks, addr, is_write))
+                               return 0;
+                       start += max_blks;
+                       blks -= max_blks;
+                       addr += ATA_SECT_SIZE * max_blks;
+               } else {
+                       if (blks != dwc_ahsata_rw_cmd_ext(dev, start,
+                                               blks, addr, is_write))
+                               return 0;
+                       start += blks;
+                       blks = 0;
+                       addr += ATA_SECT_SIZE * blks;
+               }
+       } while (blks != 0);
+
+       return blkcnt;
+}
+
+u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
+                               void *buffer, int is_write)
+{
+       u32 start, blks;
+       u8 *addr;
+       int max_blks;
+
+       start = blknr;
+       blks = blkcnt;
+       addr = (u8 *)buffer;
+
+       max_blks = ATA_MAX_SECTORS;
+       do {
+               if (blks > max_blks) {
+                       if (max_blks != dwc_ahsata_rw_cmd(dev, start,
+                                               max_blks, addr, is_write))
+                               return 0;
+                       start += max_blks;
+                       blks -= max_blks;
+                       addr += ATA_SECT_SIZE * max_blks;
+               } else {
+                       if (blks != dwc_ahsata_rw_cmd(dev, start,
+                                               blks, addr, is_write))
+                               return 0;
+                       start += blks;
+                       blks = 0;
+                       addr += ATA_SECT_SIZE * blks;
+               }
+       } while (blks != 0);
+
+       return blkcnt;
+}
+
+/*
+ * SATA interface between low level driver and command layer
+ */
+ulong sata_read(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer)
+{
+       u32 rc;
+
+       if (sata_dev_desc[dev].lba48)
+               rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
+                                               buffer, READ_CMD);
+       else
+               rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
+                                               buffer, READ_CMD);
+       return rc;
+}
+
+ulong sata_write(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer)
+{
+       u32 rc;
+       struct ahci_probe_ent *probe_ent =
+               (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+       u32 flags = probe_ent->flags;
+
+       if (sata_dev_desc[dev].lba48) {
+               rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
+                                               buffer, WRITE_CMD);
+               if ((flags & SATA_FLAG_WCACHE) &&
+                       (flags & SATA_FLAG_FLUSH_EXT))
+                       dwc_ahsata_flush_cache_ext(dev);
+       } else {
+               rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
+                                               buffer, WRITE_CMD);
+               if ((flags & SATA_FLAG_WCACHE) &&
+                       (flags & SATA_FLAG_FLUSH))
+                       dwc_ahsata_flush_cache(dev);
+       }
+       return rc;
+}
+
+int scan_sata(int dev)
+{
+       u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
+       u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
+       u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
+       u16 *id;
+       u64 n_sectors;
+       struct ahci_probe_ent *probe_ent =
+               (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+       u8 port = probe_ent->hard_port_no;
+       block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
+
+       id = (u16 *)malloc(ATA_ID_WORDS * 2);
+       if (!id) {
+               printf("id malloc failed\n\r");
+               return -1;
+       }
+
+       /* Identify device to get information */
+       dwc_ahsata_identify(dev, id);
+
+       /* Serial number */
+       ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
+       memcpy(pdev->product, serial, sizeof(serial));
+
+       /* Firmware version */
+       ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
+       memcpy(pdev->revision, firmware, sizeof(firmware));
+
+       /* Product model */
+       ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
+       memcpy(pdev->vendor, product, sizeof(product));
+
+       /* Totoal sectors */
+       n_sectors = ata_id_n_sectors(id);
+       pdev->lba = (u32)n_sectors;
+
+       pdev->type = DEV_TYPE_HARDDISK;
+       pdev->blksz = ATA_SECT_SIZE;
+       pdev->lun = 0 ;
+
+       /* Check if support LBA48 */
+       if (ata_id_has_lba48(id)) {
+               pdev->lba48 = 1;
+               debug("Device support LBA48\n\r");
+       }
+
+       /* Get the NCQ queue depth from device */
+       probe_ent->flags &= (~SATA_FLAG_Q_DEP_MASK);
+       probe_ent->flags |= ata_id_queue_depth(id);
+
+       /* Get the xfer mode from device */
+       dwc_ahsata_xfer_mode(dev, id);
+
+       /* Get the write cache status from device */
+       dwc_ahsata_init_wcache(dev, id);
+
+       /* Set the xfer mode to highest speed */
+       ahci_set_feature(dev, port);
+
+       free((void *)id);
+
+       dwc_ahsata_print_info(dev);
+
+       is_ready = 1;
+
+       return 0;
+}
+diff --git a/drivers/block/dwc_ahsata.h b/drivers/block/dwc_ahsata.h
+new file mode 100644
+index 0000000..84860ea
+--- /dev/null
+++ b/drivers/block/dwc_ahsata.h
+@@ -0,0 +1,335 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Terry Lv <r65388@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_SATA_H__
+#define __FSL_SATA_H__
+
+#define DWC_AHSATA_MAX_CMD_SLOTS       32
+
+/* Max host controller numbers */
+#define SATA_HC_MAX_NUM                4
+/* Max command queue depth per host controller */
+#define DWC_AHSATA_HC_MAX_CMD  32
+/* Max port number per host controller */
+#define SATA_HC_MAX_PORT       16
+
+/* Generic Host Register */
+
+/* HBA Capabilities Register */
+#define SATA_HOST_CAP_S64A             0x80000000
+#define SATA_HOST_CAP_SNCQ             0x40000000
+#define SATA_HOST_CAP_SSNTF            0x20000000
+#define SATA_HOST_CAP_SMPS             0x10000000
+#define SATA_HOST_CAP_SSS              0x08000000
+#define SATA_HOST_CAP_SALP             0x04000000
+#define SATA_HOST_CAP_SAL              0x02000000
+#define SATA_HOST_CAP_SCLO             0x01000000
+#define SATA_HOST_CAP_ISS_MASK         0x00f00000
+#define SATA_HOST_CAP_ISS_OFFSET       20
+#define SATA_HOST_CAP_SNZO             0x00080000
+#define SATA_HOST_CAP_SAM              0x00040000
+#define SATA_HOST_CAP_SPM              0x00020000
+#define SATA_HOST_CAP_PMD              0x00008000
+#define SATA_HOST_CAP_SSC              0x00004000
+#define SATA_HOST_CAP_PSC              0x00002000
+#define SATA_HOST_CAP_NCS              0x00001f00
+#define SATA_HOST_CAP_CCCS             0x00000080
+#define SATA_HOST_CAP_EMS              0x00000040
+#define SATA_HOST_CAP_SXS              0x00000020
+#define SATA_HOST_CAP_NP_MASK          0x0000001f
+
+/* Global HBA Control Register */
+#define SATA_HOST_GHC_AE       0x80000000
+#define SATA_HOST_GHC_IE       0x00000002
+#define SATA_HOST_GHC_HR       0x00000001
+
+/* Interrupt Status Register */
+
+/* Ports Implemented Register */
+
+/* AHCI Version Register */
+#define SATA_HOST_VS_MJR_MASK  0xffff0000
+#define SATA_HOST_VS_MJR_OFFSET        16
+#define SATA_HOST_VS_MJR_MNR   0x0000ffff
+
+/* Command Completion Coalescing Control */
+#define SATA_HOST_CCC_CTL_TV_MASK      0xffff0000
+#define SATA_HOST_CCC_CTL_TV_OFFSET            16
+#define SATA_HOST_CCC_CTL_CC_MASK      0x0000ff00
+#define SATA_HOST_CCC_CTL_CC_OFFSET            8
+#define SATA_HOST_CCC_CTL_INT_MASK     0x000000f8
+#define SATA_HOST_CCC_CTL_INT_OFFSET   3
+#define SATA_HOST_CCC_CTL_EN   0x00000001
+
+/* Command Completion Coalescing Ports */
+
+/* HBA Capabilities Extended Register */
+#define SATA_HOST_CAP2_APST            0x00000004
+
+/* BIST Activate FIS Register */
+#define SATA_HOST_BISTAFR_NCP_MASK     0x0000ff00
+#define SATA_HOST_BISTAFR_NCP_OFFSET   8
+#define SATA_HOST_BISTAFR_PD_MASK      0x000000ff
+#define SATA_HOST_BISTAFR_PD_OFFSET            0
+
+/* BIST Control Register */
+#define SATA_HOST_BISTCR_FERLB 0x00100000
+#define SATA_HOST_BISTCR_TXO   0x00040000
+#define SATA_HOST_BISTCR_CNTCLR        0x00020000
+#define SATA_HOST_BISTCR_NEALB 0x00010000
+#define SATA_HOST_BISTCR_LLC_MASK      0x00000700
+#define SATA_HOST_BISTCR_LLC_OFFSET    8
+#define SATA_HOST_BISTCR_ERREN 0x00000040
+#define SATA_HOST_BISTCR_FLIP  0x00000020
+#define SATA_HOST_BISTCR_PV            0x00000010
+#define SATA_HOST_BISTCR_PATTERN_MASK  0x0000000f
+#define SATA_HOST_BISTCR_PATTERN_OFFSET        0
+
+/* BIST FIS Count Register */
+
+/* BIST Status Register */
+#define SATA_HOST_BISTSR_FRAMERR_MASK  0x0000ffff
+#define SATA_HOST_BISTSR_FRAMERR_OFFSET        0
+#define SATA_HOST_BISTSR_BRSTERR_MASK  0x00ff0000
+#define SATA_HOST_BISTSR_BRSTERR_OFFSET        16
+
+/* BIST DWORD Error Count Register */
+
+/* OOB Register*/
+#define SATA_HOST_OOBR_WE              0x80000000
+#define SATA_HOST_OOBR_cwMin_MASK      0x7f000000
+#define SATA_HOST_OOBR_cwMAX_MASK      0x00ff0000
+#define SATA_HOST_OOBR_ciMin_MASK      0x0000ff00
+#define SATA_HOST_OOBR_ciMax_MASK      0x000000ff
+
+/* Timer 1-ms Register */
+
+/* Global Parameter 1 Register */
+#define SATA_HOST_GPARAM1R_ALIGN_M     0x80000000
+#define SATA_HOST_GPARAM1R_RX_BUFFER   0x40000000
+#define SATA_HOST_GPARAM1R_PHY_DATA_MASK       0x30000000
+#define SATA_HOST_GPARAM1R_PHY_RST     0x08000000
+#define SATA_HOST_GPARAM1R_PHY_CTRL_MASK       0x07e00000
+#define SATA_HOST_GPARAM1R_PHY_STAT_MASK       0x001f8000
+#define SATA_HOST_GPARAM1R_LATCH_M     0x00004000
+#define SATA_HOST_GPARAM1R_BIST_M      0x00002000
+#define SATA_HOST_GPARAM1R_PHY_TYPE    0x00001000
+#define SATA_HOST_GPARAM1R_RETURN_ERR  0x00000400
+#define SATA_HOST_GPARAM1R_AHB_ENDIAN_MASK     0x00000300
+#define SATA_HOST_GPARAM1R_S_HADDR     0X00000080
+#define SATA_HOST_GPARAM1R_M_HADDR     0X00000040
+
+/* Global Parameter 2 Register */
+#define SATA_HOST_GPARAM2R_DEV_CP      0x00004000
+#define SATA_HOST_GPARAM2R_DEV_MP      0x00002000
+#define SATA_HOST_GPARAM2R_DEV_ENCODE_M        0x00001000
+#define SATA_HOST_GPARAM2R_RXOOB_CLK_M 0x00000800
+#define SATA_HOST_GPARAM2R_RXOOB_M     0x00000400
+#define SATA_HOST_GPARAM2R_TX_OOB_M    0x00000200
+#define SATA_HOST_GPARAM2R_RXOOB_CLK_MASK      0x000001ff
+
+/* Port Parameter Register */
+#define SATA_HOST_PPARAMR_TX_MEM_M     0x00000200
+#define SATA_HOST_PPARAMR_TX_MEM_S     0x00000100
+#define SATA_HOST_PPARAMR_RX_MEM_M     0x00000080
+#define SATA_HOST_PPARAMR_RX_MEM_S     0x00000040
+#define SATA_HOST_PPARAMR_TXFIFO_DEPTH_MASK    0x00000038
+#define SATA_HOST_PPARAMR_RXFIFO_DEPTH_MASK    0x00000007
+
+/* Test Register */
+#define SATA_HOST_TESTR_PSEL_MASK      0x00070000
+#define SATA_HOST_TESTR_TEST_IF                0x00000001
+
+/* Port Register Descriptions */
+/* Port# Command List Base Address Register */
+#define SATA_PORT_CLB_CLB_MASK         0xfffffc00
+
+/* Port# Command List Base Address Upper 32-Bits Register */
+
+/* Port# FIS Base Address Register */
+#define SATA_PORT_FB_FB_MASK           0xfffffff0
+
+/* Port# FIS Base Address Upper 32-Bits Register */
+
+/* Port# Interrupt Status Register */
+#define SATA_PORT_IS_CPDS              0x80000000
+#define SATA_PORT_IS_TFES              0x40000000
+#define SATA_PORT_IS_HBFS              0x20000000
+#define SATA_PORT_IS_HBDS              0x10000000
+#define SATA_PORT_IS_IFS               0x08000000
+#define SATA_PORT_IS_INFS              0x04000000
+#define SATA_PORT_IS_OFS               0x01000000
+#define SATA_PORT_IS_IPMS              0x00800000
+#define SATA_PORT_IS_PRCS              0x00400000
+#define SATA_PORT_IS_DMPS              0x00000080
+#define SATA_PORT_IS_PCS               0x00000040
+#define SATA_PORT_IS_DPS               0x00000020
+#define SATA_PORT_IS_UFS               0x00000010
+#define SATA_PORT_IS_SDBS              0x00000008
+#define SATA_PORT_IS_DSS               0x00000004
+#define SATA_PORT_IS_PSS               0x00000002
+#define SATA_PORT_IS_DHRS              0x00000001
+
+/* Port# Interrupt Enable Register */
+#define SATA_PORT_IE_CPDE              0x80000000
+#define SATA_PORT_IE_TFEE              0x40000000
+#define SATA_PORT_IE_HBFE              0x20000000
+#define SATA_PORT_IE_HBDE              0x10000000
+#define SATA_PORT_IE_IFE               0x08000000
+#define SATA_PORT_IE_INFE              0x04000000
+#define SATA_PORT_IE_OFE               0x01000000
+#define SATA_PORT_IE_IPME              0x00800000
+#define SATA_PORT_IE_PRCE              0x00400000
+#define SATA_PORT_IE_DMPE              0x00000080
+#define SATA_PORT_IE_PCE               0x00000040
+#define SATA_PORT_IE_DPE               0x00000020
+#define SATA_PORT_IE_UFE               0x00000010
+#define SATA_PORT_IE_SDBE              0x00000008
+#define SATA_PORT_IE_DSE               0x00000004
+#define SATA_PORT_IE_PSE               0x00000002
+#define SATA_PORT_IE_DHRE              0x00000001
+
+/* Port# Command Register */
+#define SATA_PORT_CMD_ICC_MASK         0xf0000000
+#define SATA_PORT_CMD_ASP              0x08000000
+#define SATA_PORT_CMD_ALPE             0x04000000
+#define SATA_PORT_CMD_DLAE             0x02000000
+#define SATA_PORT_CMD_ATAPI            0x01000000
+#define SATA_PORT_CMD_APSTE            0x00800000
+#define SATA_PORT_CMD_ESP              0x00200000
+#define SATA_PORT_CMD_CPD              0x00100000
+#define SATA_PORT_CMD_MPSP             0x00080000
+#define SATA_PORT_CMD_HPCP             0x00040000
+#define SATA_PORT_CMD_PMA              0x00020000
+#define SATA_PORT_CMD_CPS              0x00010000
+#define SATA_PORT_CMD_CR               0x00008000
+#define SATA_PORT_CMD_FR               0x00004000
+#define SATA_PORT_CMD_MPSS             0x00002000
+#define SATA_PORT_CMD_CCS_MASK         0x00001f00
+#define SATA_PORT_CMD_FRE              0x00000010
+#define SATA_PORT_CMD_CLO              0x00000008
+#define SATA_PORT_CMD_POD              0x00000004
+#define SATA_PORT_CMD_SUD              0x00000002
+#define SATA_PORT_CMD_ST               0x00000001
+
+/* Port# Task File Data Register */
+#define SATA_PORT_TFD_ERR_MASK         0x0000ff00
+#define SATA_PORT_TFD_STS_MASK         0x000000ff
+#define SATA_PORT_TFD_STS_ERR          0x00000001
+#define SATA_PORT_TFD_STS_DRQ          0x00000008
+#define SATA_PORT_TFD_STS_BSY          0x00000080
+
+/* Port# Signature Register */
+
+/* Port# Serial ATA Status {SStatus} Register */
+#define SATA_PORT_SSTS_IPM_MASK                0x00000f00
+#define SATA_PORT_SSTS_SPD_MASK                0x000000f0
+#define SATA_PORT_SSTS_DET_MASK                0x0000000f
+
+/* Port# Serial ATA Control {SControl} Register */
+#define SATA_PORT_SCTL_IPM_MASK                0x00000f00
+#define SATA_PORT_SCTL_SPD_MASK                0x000000f0
+#define SATA_PORT_SCTL_DET_MASK                0x0000000f
+
+/* Port# Serial ATA Error {SError} Register */
+#define SATA_PORT_SERR_DIAG_X          0x04000000
+#define SATA_PORT_SERR_DIAG_F          0x02000000
+#define SATA_PORT_SERR_DIAG_T          0x01000000
+#define SATA_PORT_SERR_DIAG_S          0x00800000
+#define SATA_PORT_SERR_DIAG_H          0x00400000
+#define SATA_PORT_SERR_DIAG_C          0x00200000
+#define SATA_PORT_SERR_DIAG_D          0x00100000
+#define SATA_PORT_SERR_DIAG_B          0x00080000
+#define SATA_PORT_SERR_DIAG_W          0x00040000
+#define SATA_PORT_SERR_DIAG_I          0x00020000
+#define SATA_PORT_SERR_DIAG_N          0x00010000
+#define SATA_PORT_SERR_ERR_E           0x00000800
+#define SATA_PORT_SERR_ERR_P           0x00000400
+#define SATA_PORT_SERR_ERR_C           0x00000200
+#define SATA_PORT_SERR_ERR_T           0x00000100
+#define SATA_PORT_SERR_ERR_M           0x00000002
+#define SATA_PORT_SERR_ERR_I           0x00000001
+
+/* Port# Serial ATA Active {SActive} Register */
+
+/* Port# Command Issue Register */
+
+/* Port# Serial ATA Notification Register */
+
+/* Port# DMA Control Register */
+#define SATA_PORT_DMACR_RXABL_MASK     0x0000f000
+#define SATA_PORT_DMACR_TXABL_MASK     0x00000f00
+#define SATA_PORT_DMACR_RXTS_MASK      0x000000f0
+#define SATA_PORT_DMACR_TXTS_MASK      0x0000000f
+
+/* Port# PHY Control Register */
+
+/* Port# PHY Status Register */
+
+#define SATA_HC_CMD_HDR_ENTRY_SIZE     sizeof(struct cmd_hdr_entry)
+
+/* DW0
+*/
+#define CMD_HDR_DI_CFL_MASK    0x0000001f
+#define CMD_HDR_DI_CFL_OFFSET  0
+#define CMD_HDR_DI_A                   0x00000020
+#define CMD_HDR_DI_W                   0x00000040
+#define CMD_HDR_DI_P                   0x00000080
+#define CMD_HDR_DI_R                   0x00000100
+#define CMD_HDR_DI_B                   0x00000200
+#define CMD_HDR_DI_C                   0x00000400
+#define CMD_HDR_DI_PMP_MASK    0x0000f000
+#define CMD_HDR_DI_PMP_OFFSET  12
+#define CMD_HDR_DI_PRDTL               0xffff0000
+#define CMD_HDR_DI_PRDTL_OFFSET        16
+
+/* prde_fis_len
+*/
+#define CMD_HDR_PRD_ENTRY_SHIFT        16
+#define CMD_HDR_PRD_ENTRY_MASK 0x003f0000
+#define CMD_HDR_FIS_LEN_SHIFT  2
+
+/* attribute
+*/
+#define CMD_HDR_ATTR_RES       0x00000800 /* Reserved bit, should be 1 */
+#define CMD_HDR_ATTR_VBIST     0x00000400 /* Vendor BIST */
+/* Snoop enable for all descriptor */
+#define CMD_HDR_ATTR_SNOOP     0x00000200
+#define CMD_HDR_ATTR_FPDMA     0x00000100 /* FPDMA queued command */
+#define CMD_HDR_ATTR_RESET     0x00000080 /* Reset - a SRST or device reset */
+/* BIST - require the host to enter BIST mode */
+#define CMD_HDR_ATTR_BIST      0x00000040
+#define CMD_HDR_ATTR_ATAPI     0x00000020 /* ATAPI command */
+#define CMD_HDR_ATTR_TAG       0x0000001f /* TAG mask */
+
+#define FLAGS_DMA      0x00000000
+#define FLAGS_FPDMA    0x00000001
+
+#define SATA_FLAG_Q_DEP_MASK   0x0000000f
+#define SATA_FLAG_WCACHE       0x00000100
+#define SATA_FLAG_FLUSH                0x00000200
+#define SATA_FLAG_FLUSH_EXT    0x00000400
+
+#define READ_CMD       0
+#define WRITE_CMD      1
+
+extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
+
+#endif /* __FSL_SATA_H__ */
+diff --git a/include/ahci.h b/include/ahci.h
+index 465ea7f..c4fb9e7 100644
+--- a/include/ahci.h
+++ b/include/ahci.h
+@@ -30,12 +30,13 @@
+ #define AHCI_PCI_BAR           0x24
+ #define AHCI_MAX_SG            56 /* hardware max is 64K */
+ #define AHCI_CMD_SLOT_SZ       32
+#define AHCI_MAX_CMD_SLOT      32
+ #define AHCI_RX_FIS_SZ         256
+ #define AHCI_CMD_TBL_HDR       0x80
+ #define AHCI_CMD_TBL_CDB       0x40
+ #define AHCI_CMD_TBL_SZ                AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
+-#define AHCI_PORT_PRIV_DMA_SZ  AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ      \
+-                               + AHCI_RX_FIS_SZ
+#define AHCI_PORT_PRIV_DMA_SZ  (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
+                               AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ)
+ #define AHCI_CMD_ATAPI         (1 << 5)
+ #define AHCI_CMD_WRITE         (1 << 6)
+ #define AHCI_CMD_PREFETCH      (1 << 7)
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0005-MX53-Add-support-to-ESG-ima3-board.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0005-MX53-Add-support-to-ESG-ima3-board.patch
new file mode 100644
index 000000000..25114ca4b
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0005-MX53-Add-support-to-ESG-ima3-board.patch
@@ -0,0 +1,781 @@
+From 4b78125dda9413f121aadc8ddb3a2ae2238de006 Mon Sep 17 00:00:00 2001
+From: Stefano Babic <sbabic@denx.de>
+Date: Wed, 22 Feb 2012 00:24:40 +0000
+Subject: [PATCH 05/56] MX53: Add support to ESG ima3 board
+The ESG ima3-mx53 board is based on the Freescale
+i.MX53 SOC. It boots from NOR (128 MB) and
+supports Ethernet (FEC), SATA.
+Signed-off-by: Stefano Babic <sbabic@denx.de>
+---
+ board/esg/ima3-mx53/Makefile     |   41 ++++++
+ board/esg/ima3-mx53/ima3-mx53.c  |  302 ++++++++++++++++++++++++++++++++++++++
+ board/esg/ima3-mx53/imximage.cfg |  108 ++++++++++++++
+ boards.cfg                       |    1 +
+ include/configs/ima3-mx53.h      |  269 +++++++++++++++++++++++++++++++++
+ 5 files changed, 721 insertions(+)
+ create mode 100644 board/esg/ima3-mx53/Makefile
+ create mode 100644 board/esg/ima3-mx53/ima3-mx53.c
+ create mode 100644 board/esg/ima3-mx53/imximage.cfg
+ create mode 100644 include/configs/ima3-mx53.h
+diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile
+new file mode 100644
+index 0000000..f3b13bc
+--- /dev/null
+++ b/board/esg/ima3-mx53/Makefile
+@@ -0,0 +1,41 @@
+#
+# Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+#
+# Based on ti/evm/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := ima3-mx53.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c
+new file mode 100644
+index 0000000..9ecf31d
+--- /dev/null
+++ b/board/esg/ima3-mx53/ima3-mx53.c
+@@ -0,0 +1,302 @@
+/*
+ * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+
+/* NOR flash configuration */
+#define IMA3_MX53_CS0GCR1      (CSEN | DSZ(2))
+#define IMA3_MX53_CS0GCR2      0
+#define IMA3_MX53_CS0RCR1      (RCSN(2) | OEN(1) | RWSC(15))
+#define IMA3_MX53_CS0RCR2      0
+#define IMA3_MX53_CS0WCR1      (WBED1 | WCSN(2) | WEN(1) | WWSC(15))
+#define IMA3_MX53_CS0WCR2      0
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void weim_nor_settings(void)
+{
+       struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+       writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1);
+       writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2);
+       writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1);
+       writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2);
+       writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1);
+       writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2);
+       writel(0x0, &weim_regs->wcr);
+
+       set_chipselect_size(CS0_128);
+}
+
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+                       PHYS_SDRAM_1_SIZE);
+       return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+       /* UART4 RXD */
+       mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2);
+       mxc_iomux_set_pad(MX53_PIN_CSI0_D13,
+               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
+               PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+       mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
+
+       /* UART4 TXD */
+       mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2);
+       mxc_iomux_set_pad(MX53_PIN_CSI0_D12,
+               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
+               PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+static void setup_iomux_fec(void)
+{
+       /*FEC_MDIO*/
+       mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
+       mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
+               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU |
+               PAD_CTL_ODE_OPENDRAIN_ENABLE);
+       mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+
+       /*FEC_MDC*/
+       mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
+       mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
+
+       /* FEC RXD3 */
+       mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6);
+       mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE |
+               PAD_CTL_PKE_ENABLE);
+
+       /* FEC RXD2 */
+       mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6);
+       mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE |
+               PAD_CTL_PKE_ENABLE);
+
+       /* FEC RXD1 */
+       mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
+       mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE |
+               PAD_CTL_PKE_ENABLE);
+
+       /* FEC RXD0 */
+       mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
+       mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE |
+               PAD_CTL_PKE_ENABLE);
+
+       /* FEC TXD3 */
+       mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6);
+       mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH);
+
+       /* FEC TXD2 */
+       mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6);
+       mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH);
+
+       /* FEC TXD1 */
+       mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
+       mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
+
+       /* FEC TXD0 */
+       mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
+       mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
+
+       /* FEC TX_EN */
+       mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
+       mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
+
+       /* FEC TX_CLK */
+       mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
+       mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE |
+               PAD_CTL_PKE_ENABLE);
+
+       /* FEC RX_ER */
+       mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
+       mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE |
+               PAD_CTL_PKE_ENABLE);
+
+       /* FEC RX_DV */
+       mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
+       mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE |
+               PAD_CTL_PKE_ENABLE);
+
+       /* FEC CRS */
+       mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6);
+       mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE |
+               PAD_CTL_PKE_ENABLE);
+
+       /* FEC COL */
+       mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6);
+       mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE |
+               PAD_CTL_PKE_ENABLE);
+       mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0);
+
+       /* FEC RX_CLK */
+       mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6);
+       mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE |
+               PAD_CTL_PKE_ENABLE);
+       mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR, 1 };
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       int ret;
+
+       ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
+
+       return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
+       mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+       mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
+       mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
+       mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
+       mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
+       mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
+       mxc_iomux_set_pad(MX53_PIN_GPIO_1,
+               PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+               PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
+               PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE);
+       gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
+
+       mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
+               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+               PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+       mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
+               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
+               PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH);
+       mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
+               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+               PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+       mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
+               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+               PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+       mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
+               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+               PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+       mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
+               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+               PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+
+       return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+#endif
+
+static void setup_iomux_spi(void)
+{
+       /* SCLK */
+       mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3);
+       mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
+               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+               PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+       mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1);
+       /* MOSI */
+       mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3);
+       mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
+               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+               PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+       mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1);
+       /* MISO */
+       mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3);
+       mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
+               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+               PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+       mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1);
+       /* SSEL 0 */
+       mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO);
+       mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
+               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+               PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+       gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1);
+}
+
+int board_early_init_f(void)
+{
+       /* configure I/O pads */
+       setup_iomux_uart();
+       setup_iomux_fec();
+
+       weim_nor_settings();
+
+       /* configure spi */
+       setup_iomux_spi();
+
+       return 0;
+}
+
+int board_init(void)
+{
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+       mxc_set_sata_internal_clock();
+
+       return 0;
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+#include <miiphy.h>
+
+void reset_phy(void)
+{
+       unsigned short reg;
+
+       /* reset the phy */
+       miiphy_reset("FEC", CONFIG_PHY_ADDR);
+
+       /* set hard link to 100Mbit, full-duplex */
+       miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, &reg);
+       reg &= ~BMCR_ANENABLE;
+       reg |= (BMCR_SPEED100 | BMCR_FULLDPLX);
+       miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg);
+
+       miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, &reg);
+       reg |= (1 << 5);
+       miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg);
+}
+#endif
+
+int checkboard(void)
+{
+       puts("Board: IMA3_MX53\n");
+
+       return 0;
+}
+diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
+new file mode 100644
+index 0000000..fa6b42d
+--- /dev/null
+++ b/board/esg/ima3-mx53/imximage.cfg
+@@ -0,0 +1,108 @@
+#
+# (C) Copyright 2012
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# image version
+
+IMAGE_VERSION 2
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM      nor
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type           Address        Value
+#
+# where:
+#      Addr-type register length (1,2 or 4 bytes)
+#      Address   absolute address of the register
+#      value     value to be stored in the register
+
+# IOMUX for RAM only
+DATA 4 0x53fa8554 0x300020
+DATA 4 0x53fa8560 0x300020
+DATA 4 0x53fa8594 0x300020
+DATA 4 0x53fa8584 0x300020
+DATA 4 0x53fa8558 0x300040
+DATA 4 0x53fa8568 0x300040
+DATA 4 0x53fa8590 0x300040
+DATA 4 0x53fa857c 0x300040
+DATA 4 0x53fa8564 0x300040
+DATA 4 0x53fa8580 0x300040
+DATA 4 0x53fa8570 0x300220
+DATA 4 0x53fa8578 0x300220
+DATA 4 0x53fa872c 0x300000
+DATA 4 0x53fa8728 0x300000
+DATA 4 0x53fa871c 0x300000
+DATA 4 0x53fa8718 0x300000
+DATA 4 0x53fa8574 0x300020
+DATA 4 0x53fa8588 0x300020
+DATA 4 0x53fa855c 0x0
+DATA 4 0x53fa858c 0x0
+DATA 4 0x53fa856c 0x300040
+DATA 4 0x53fa86f0 0x300000
+DATA 4 0x53fa8720 0x300000
+DATA 4 0x53fa86fc 0x0
+DATA 4 0x53fa86f4 0x0
+DATA 4 0x53fa8714 0x0
+DATA 4 0x53fa8724 0x4000000
+#
+# DDR RAM
+DATA 4 0x63fd9088 0x40404040
+DATA 4 0x63fd9090 0x40404040
+DATA 4 0x63fd907C 0x01420143
+DATA 4 0x63fd9080 0x01450146
+DATA 4 0x63fd9018 0x00111740
+DATA 4 0x63fd9000 0x84190000
+# esdcfgX
+DATA 4 0x63fd900C 0x9f5152e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+# Read/Write command delay
+DATA 4 0x63fd902c 0x000026d2
+# Out of reset delays
+DATA 4 0x63fd9030 0x00ff0e21
+# ESDCTL ODT timing control
+DATA 4 0x63fd9008 0x12273030
+# ESDCTL power down control
+DATA 4 0x63fd9004 0x0002002d
+# Set registers in DDR memory chips
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+# ESDCTL refresh control
+DATA 4 0x63fd9020 0x00005800
+# PHY ZQ HW control
+DATA 4 0x63fd9040 0x05380003
+# PHY ODT control
+DATA 4 0x63fd9058 0x00022222
+# start DDR3
+DATA 4 0x63fd901c 0x00000000
+diff --git a/boards.cfg b/boards.cfg
+index 3cf75c3..93ecae6 100644
+--- a/boards.cfg
+++ b/boards.cfg
+@@ -189,6 +189,7 @@ mx53ard                      arm         armv7       mx53ard             freesca
+ mx53evk                      arm         armv7       mx53evk             freescale      mx5            mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg
+ mx53loco                     arm         armv7       mx53loco            freescale      mx5            mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg
+ mx53smd                      arm         armv7       mx53smd             freescale      mx5            mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
+ima3-mx53                    arm         armv7       ima3-mx53           esg            mx5            ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
+ vision2                      arm         armv7       vision2             ttcontrol      mx5            vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
+ mx6qarm2                     arm         armv7       mx6qarm2            freescale      mx6            mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
+ mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6            mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg
+diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h
+new file mode 100644
+index 0000000..ea48d64
+--- /dev/null
+++ b/include/configs/ima3-mx53.h
+@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SOC type must be included before imx-regs.h */
+#define CONFIG_MX53
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+
+#define CONFIG_SYS_MX5_HCLK            24000000
+#define CONFIG_SYS_MX5_CLK32           32768
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG             /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_OF_LIBFDT
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Enable GPIOs */
+#define CONFIG_MXC_GPIO
+
+/* UART */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE   UART4_BASE_ADDR
+
+/* MMC */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_ESDHC_NUM       1
+
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+
+/* Ethernet on FEC */
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE                   FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR         0x01
+#define CONFIG_PHY_ADDR                        CONFIG_FEC_MXC_PHYADDR
+#define CONFIG_RESET_PHY_R
+#define CONFIG_FEC_MXC_NO_ANEG
+#define CONFIG_PRIME   "FEC0"
+
+/* SPI */
+#define CONFIG_HARD_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_DEFAULT_SPI_BUS         1
+#define CONFIG_DEFAULT_SPI_MODE                SPI_MODE_0
+
+/* SPI FLASH - not used for environment */
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_CS            (IOMUX_TO_GPIO(MX53_PIN_CSI0_D11) \
+                                                << 8) | 0
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED                25000000
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_BAUDRATE_TABLE      {9600, 19200, 38400, 57600, 115200}
+
+/* Command definition */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_GPIO
+
+#define CONFIG_BOOTDELAY       3
+
+#define CONFIG_LOADADDR                0x70800000      /* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE    0xf0001400 /* uboot in nor flash */
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP            /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER         /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_PROMPT              "IMA3 MX53 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS     16      /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x10000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ          1000
+#define CONFIG_CMDLINE_EDITING
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE       (128 * 1024)    /* regular stack */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS   1
+#define PHYS_SDRAM_1           CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE      (1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE          (PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR       (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE       (IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_MTD_DEVICE              /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT         "nor0=f0000000.flash"
+
+/* FLASH and environment organization */
+
+#define CONFIG_SYS_FLASH_BASE          0xF0000000
+#define CONFIG_SYS_FLASH_CFI           /* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER                /* Use the common driver */
+#define CONFIG_FLASH_CFI_MTD           /* with MTD support */
+#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_MAX_FLASH_SECT      1024
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
+
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE + \
+                               CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE   0x20000
+#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + \
+                                       CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+
+#define HOSTNAME ima3-mx53
+#define xstr(s)        str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME ima3-mx53
+#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
+       "netdev=eth0\0"                                                 \
+       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+               "nfsroot=${serverip}:${rootpath}\0"                     \
+       "ramargs=setenv bootargs root=/dev/ram0 rw\0"                   \
+       "addip_sta=setenv bootargs ${bootargs} "                        \
+               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
+               ":${hostname}:${netdev}:off panic=1\0"                  \
+       "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"               \
+       "addip=if test -n ${ipdyn};then run addip_dyn;"                 \
+               "else run addip_sta;fi\0"       \
+       "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
+       "addtty=setenv bootargs ${bootargs}"                            \
+               " console=${console},${baudrate}\0"                     \
+       "addmisc=setenv bootargs ${bootargs} ${misc}\0"                 \
+       "console=ttymxc3\0"                                             \
+       "loadaddr=70800000\0"                                           \
+       "kernel_addr_r=70800000\0"                                      \
+       "ramdisk_addr_r=71000000\0"                                     \
+       "hostname=" xstr(CONFIG_HOSTNAME) "\0"                          \
+       "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"                   \
+       "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0"             \
+       "mmcargs=setenv bootargs root=${mmcroot} "                      \
+               "rootfstype=${mmcrootfstype}\0"                         \
+       "mmcroot=/dev/mmcblk0p3 rw\0"                                   \
+       "mmcboot=echo Booting from mmc ...; "                           \
+               "run mmcargs addip addtty addmtd addmisc mmcload;"      \
+               "bootm\0"                                               \
+       "mmcload=fatload mmc ${mmcdev}:${mmcpart} "                     \
+               "${loadaddr} ${uimage}\0"                               \
+       "mmcrootfstype=ext3 rootwait\0"                                 \
+       "flash_self=run ramargs addip addtty addmtd addmisc;"           \
+               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
+       "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
+               "bootm ${kernel_addr}\0"                                \
+       "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
+               "run nfsargs addip addtty addmtd addmisc;"              \
+               "bootm ${kernel_addr_r}\0"                              \
+       "net_self_load=tftp ${ramdisk_addr_r} ${ramdisk_file};"         \
+               "tftp ${kernel_addr_r} ${bootfile}\0"                   \
+       "net_self=if run net_self_load;then "                           \
+               "run ramargs addip addtty addmtd addmisc;"              \
+               "bootm ${kernel_addr_r} ${ramdisk_addr_r};"             \
+               "else echo Images not loades;fi\0"                      \
+       "satargs=setenv bootargs root=/dev/sda1\0"                      \
+       "satafile=boot/uImage\0"                                        \
+       "ssdboot=echo Booting from ssd ...; "                           \
+               "run satargs addip addtty addmtd addmisc;"              \
+               "sata init;ext2load sata 0:1 ${kernel_addr_r} "         \
+               "${satafile};bootm\0"                                   \
+       "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.imx\0"                 \
+       "uimage=uImage\0"                                               \
+       "load=tftp ${loadaddr} ${u-boot}\0"                             \
+       "uboot_addr=0xf0001000\0"                                       \
+       "update=protect off 0xf0000000 +60000;"                         \
+               "erase ${uboot_addr} +60000;"                           \
+               "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"          \
+       "upd=if run load;then echo Updating u-boot;if run update;"      \
+               "then echo U-Boot updated;"                             \
+                       "else echo Error updating u-boot !;"            \
+                       "echo Board without bootloader !!;"             \
+               "fi;"                                                   \
+               "else echo U-Boot not downloaded..exiting;fi\0"         \
+       "bootcmd=run net_nfs\0"
+
+
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+       #define CONFIG_DWC_AHSATA
+       #define CONFIG_SYS_SATA_MAX_DEVICE      1
+       #define CONFIG_DWC_AHSATA_PORT_ID       0
+       #define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_BASE_ADDR
+       #define CONFIG_LBA48
+       #define CONFIG_LIBATA
+#endif
+
+#endif                         /* __CONFIG_H */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0006-MX53-mx53loco-Add-SATA-support.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0006-MX53-mx53loco-Add-SATA-support.patch
new file mode 100644
index 000000000..54b69b06b
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0006-MX53-mx53loco-Add-SATA-support.patch
@@ -0,0 +1,64 @@
+From d3ba981cb9e1e71abd34a23c06fa1d76ee722f77 Mon Sep 17 00:00:00 2001
+From: Stefano Babic <sbabic@denx.de>
+Date: Wed, 22 Feb 2012 00:24:41 +0000
+Subject: [PATCH 06/56] MX53: mx53loco: Add SATA support
+Signed-off-by: Stefano Babic <sbabic@denx.de>
+CC: Jason Liu <jason.hui@linaro.org>
+Acked-by: Jason Liu <jason.hui@linaro.org>
+---
+ board/freescale/mx53loco/mx53loco.c |    3 +++
+ include/configs/mx53loco.h          |   11 +++++++++++
+ 2 files changed, 14 insertions(+)
+diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
+index d736141..7ea9f6e 100644
+--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
+@@ -27,6 +27,7 @@
+ #include <asm/arch/mx5x_pins.h>
+ #include <asm/arch/sys_proto.h>
+ #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+ #include <asm/arch/iomux.h>
+ #include <asm/arch/clock.h>
+ #include <asm/errno.h>
+@@ -302,6 +303,8 @@ int board_init(void)
+ {
+        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+ 
+       mxc_set_sata_internal_clock();
+
+        return 0;
+ }
+ 
+diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
+index 34a4edd..af59307 100644
+--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
+@@ -56,6 +56,7 @@
+ #define CONFIG_CMD_MMC
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+ #define CONFIG_DOS_PARTITION
+ 
+ /* Eth Configs */
+@@ -193,4 +194,14 @@
+ 
+ #define CONFIG_OF_LIBFDT
+ 
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+       #define CONFIG_DWC_AHSATA
+       #define CONFIG_SYS_SATA_MAX_DEVICE      1
+       #define CONFIG_DWC_AHSATA_PORT_ID       0
+       #define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_BASE_ADDR
+       #define CONFIG_LBA48
+       #define CONFIG_LIBATA
+#endif
+
+ #endif                         /* __CONFIG_H */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0007-pmic-Add-support-for-the-Dialog-DA9053-PMIC.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0007-pmic-Add-support-for-the-Dialog-DA9053-PMIC.patch
new file mode 100644
index 000000000..cf733544d
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0007-pmic-Add-support-for-the-Dialog-DA9053-PMIC.patch
@@ -0,0 +1,267 @@
+From 15675c7082f3a80ee2a67b436fdbb6bc800e6662 Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Tue, 20 Mar 2012 11:40:06 +0000
+Subject: [PATCH 07/56] pmic: Add support for the Dialog DA9053 PMIC
+Add support for the Dialog DA9053 PMIC.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ drivers/misc/Makefile      |    1 +
+ drivers/misc/pmic_dialog.c |   37 +++++++++
+ include/dialog_pmic.h      |  187 ++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 225 insertions(+)
+ create mode 100644 drivers/misc/pmic_dialog.c
+ create mode 100644 include/dialog_pmic.h
+diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
+index a709707..29d768b 100644
+--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
+@@ -35,6 +35,7 @@ COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
+ COBJS-$(CONFIG_STATUS_LED) += status_led.o
+ COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
+ COBJS-$(CONFIG_PMIC) += pmic_core.o
+COBJS-$(CONFIG_DIALOG_PMIC) += pmic_dialog.o
+ COBJS-$(CONFIG_PMIC_FSL) += pmic_fsl.o
+ COBJS-$(CONFIG_PMIC_I2C) += pmic_i2c.o
+ COBJS-$(CONFIG_PMIC_SPI) += pmic_spi.o
+diff --git a/drivers/misc/pmic_dialog.c b/drivers/misc/pmic_dialog.c
+new file mode 100644
+index 0000000..7242073
+--- /dev/null
+++ b/drivers/misc/pmic_dialog.c
+@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2011 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <pmic.h>
+#include <dialog_pmic.h>
+
+int pmic_init(void)
+{
+       struct pmic *p = get_pmic();
+       static const char name[] = "DIALOG_PMIC";
+
+       p->name = name;
+       p->number_of_regs = PMIC_NUM_OF_REGS;
+
+       p->interface = PMIC_I2C;
+       p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR;
+       p->hw.i2c.tx_num = 1;
+       p->bus = I2C_PMIC;
+
+       return 0;
+}
+diff --git a/include/dialog_pmic.h b/include/dialog_pmic.h
+new file mode 100644
+index 0000000..b0925f5
+--- /dev/null
+++ b/include/dialog_pmic.h
+@@ -0,0 +1,187 @@
+/*
+ * da9053 register declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __DIALOG_PMIC_H__
+#define __DIALOG_PMIC_H__
+
+enum {
+       DA9053_PAGECON0_REG = 0,
+       DA9053_STATUSA_REG,
+       DA9053_STATUSB_REG,
+       DA9053_STATUSC_REG,
+       DA9053_STATUSD_REG,
+       DA9053_EVENTA_REG,
+       DA9053_EVENTB_REG,
+       DA9053_EVENTC_REG,
+       DA9053_EVENTD_REG,
+       DA9053_FAULTLOG_REG,
+       DA9053_IRQMASKA_REG,
+       DA9053_IRQMASKB_REG,
+       DA9053_IRQMASKC_REG,
+       DA9053_IRQMASKD_REG,
+       DA9053_CONTROLA_REG,
+       DA9053_CONTROLB_REG,
+       DA9053_CONTROLC_REG,
+       DA9053_CONTROLD_REG,
+       DA9053_PDDIS_REG,
+       DA9053_INTERFACE_REG,
+       DA9053_RESET_REG,
+       DA9053_GPIO0001_REG,
+       DA9053_GPIO0203_REG,
+       DA9053_GPIO0405_REG,
+       DA9053_GPIO0607_REG,
+       DA9053_GPIO0809_REG,
+       DA9053_GPIO1011_REG,
+       DA9053_GPIO1213_REG,
+       DA9053_GPIO1415_REG,
+       DA9053_ID01_REG,
+       DA9053_ID23_REG,
+       DA9053_ID45_REG,
+       DA9053_ID67_REG,
+       DA9053_ID89_REG,
+       DA9053_ID1011_REG,
+       DA9053_ID1213_REG,
+       DA9053_ID1415_REG,
+       DA9053_ID1617_REG,
+       DA9053_ID1819_REG,
+       DA9053_ID2021_REG,
+       DA9053_SEQSTATUS_REG,
+       DA9053_SEQA_REG,
+       DA9053_SEQB_REG,
+       DA9053_SEQTIMER_REG,
+       DA9053_BUCKA_REG,
+       DA9053_BUCKB_REG,
+       DA9053_BUCKCORE_REG,
+       DA9053_BUCKPRO_REG,
+       DA9053_BUCKMEM_REG,
+       DA9053_BUCKPERI_REG,
+       DA9053_LDO1_REG,
+       DA9053_LDO2_REG,
+       DA9053_LDO3_REG,
+       DA9053_LDO4_REG,
+       DA9053_LDO5_REG,
+       DA9053_LDO6_REG,
+       DA9053_LDO7_REG,
+       DA9053_LDO8_REG,
+       DA9053_LDO9_REG,
+       DA9053_LDO10_REG,
+       DA9053_SUPPLY_REG,
+       DA9053_PULLDOWN_REG,
+       DA9053_CHGBUCK_REG,
+       DA9053_WAITCONT_REG,
+       DA9053_ISET_REG,
+       DA9053_BATCHG_REG,
+       DA9053_CHGCONT_REG,
+       DA9053_INPUTCONT_REG,
+       DA9053_CHGTIME_REG,
+       DA9053_BBATCONT_REG,
+       DA9053_BOOST_REG,
+       DA9053_LEDCONT_REG,
+       DA9053_LEDMIN123_REG,
+       DA9053_LED1CONF_REG,
+       DA9053_LED2CONF_REG,
+       DA9053_LED3CONF_REG,
+       DA9053_LED1CONT_REG,
+       DA9053_LED2CONT_REG,
+       DA9053_LED3CONT_REG,
+       DA9053_LED4CONT_REG,
+       DA9053_LED5CONT_REG,
+       DA9053_ADCMAN_REG,
+       DA9053_ADCCONT_REG,
+       DA9053_ADCRESL_REG,
+       DA9053_ADCRESH_REG,
+       DA9053_VDDRES_REG,
+       DA9053_VDDMON_REG,
+       DA9053_ICHGAV_REG,
+       DA9053_ICHGTHD_REG,
+       DA9053_ICHGEND_REG,
+       DA9053_TBATRES_REG,
+       DA9053_TBATHIGHP_REG,
+       DA9053_TBATHIGHIN_REG,
+       DA9053_TBATLOW_REG,
+       DA9053_TOFFSET_REG,
+       DA9053_ADCIN4RES_REG,
+       DA9053_AUTO4HIGH_REG,
+       DA9053_AUTO4LOW_REG,
+       DA9053_ADCIN5RES_REG,
+       DA9053_AUTO5HIGH_REG,
+       DA9053_AUTO5LOW_REG,
+       DA9053_ADCIN6RES_REG,
+       DA9053_AUTO6HIGH_REG,
+       DA9053_AUTO6LOW_REG,
+       DA9053_TJUNCRES_REG,
+       DA9053_TSICONTA_REG,
+       DA9053_TSICONTB_REG,
+       DA9053_TSIXMSB_REG,
+       DA9053_TSIYMSB_REG,
+       DA9053_TSILSB_REG,
+       DA9053_TSIZMSB_REG,
+       DA9053_COUNTS_REG,
+       DA9053_COUNTMI_REG,
+       DA9053_COUNTH_REG,
+       DA9053_COUNTD_REG,
+       DA9053_COUNTMO_REG,
+       DA9053_COUNTY_REG,
+       DA9053_ALARMMI_REG,
+       DA9053_ALARMH_REG,
+       DA9053_ALARMD_REG,
+       DA9053_ALARMMO_REG,
+       DA9053_ALARMY_REG,
+       DA9053_SECONDA_REG,
+       DA9053_SECONDB_REG,
+       DA9053_SECONDC_REG,
+       DA9053_SECONDD_REG,
+       DA9053_PAGECON128_REG,
+       DA9053_CHIPID_REG,
+       DA9053_CONFIGID_REG,
+       DA9053_OTPCONT_REG,
+       DA9053_OSCTRIM_REG,
+       DA9053_GPID0_REG,
+       DA9053_GPID1_REG,
+       DA9053_GPID2_REG,
+       DA9053_GPID3_REG,
+       DA9053_GPID4_REG,
+       DA9053_GPID5_REG,
+       DA9053_GPID6_REG,
+       DA9053_GPID7_REG,
+       DA9053_GPID8_REG,
+       DA9053_GPID9_REG,
+       PMIC_NUM_OF_REGS,
+};
+
+#define DA_BUCKCORE_VBCORE_1_250V              0x1E
+
+/* BUCKCORE REGISTER */
+#define DA9052_BUCKCORE_BCORECONF               (1 << 7)
+#define DA9052_BUCKCORE_BCOREEN                 (1 << 6)
+#define DA9052_BUCKCORE_VBCORE                  63
+
+/* SUPPLY REGISTER */
+#define DA9052_SUPPLY_VLOCK                     (1 << 7)
+#define DA9052_SUPPLY_VMEMSWEN                  (1 << 6)
+#define DA9052_SUPPLY_VPERISWEN                 (1 << 5)
+#define DA9052_SUPPLY_VLDO3GO                   (1 << 4)
+#define DA9052_SUPPLY_VLDO2GO                   (1 << 3)
+#define DA9052_SUPPLY_VBMEMGO                   (1 << 2)
+#define DA9052_SUPPLY_VBPROGO                   (1 << 1)
+#define DA9052_SUPPLY_VBCOREGO                  (1 << 0)
+
+#endif /* __DIALOG_PMIC_H__ */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0008-mx6qsabrelite-No-need-to-set-the-direction-for-GPIO3.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0008-mx6qsabrelite-No-need-to-set-the-direction-for-GPIO3.patch
new file mode 100644
index 000000000..5514e23b1
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0008-mx6qsabrelite-No-need-to-set-the-direction-for-GPIO3.patch
@@ -0,0 +1,33 @@
+From 7bca215d56396abf4173e101f6a292117db2d373 Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <festevam@gmail.com>
+Date: Wed, 11 Apr 2012 10:22:24 +0000
+Subject: [PATCH 08/56] mx6qsabrelite: No need to set the direction for
+ GPIO3_23 again
+There is a 'gpio_direction_output(87, 0);' call previously, so the GPIO direction is
+already established.
+Use gpio_set_value() for changing the GPIO output then.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Acked-by: Dirk Behme <dirk.behme@googlemail.com>
+---
+ board/freescale/mx6qsabrelite/mx6qsabrelite.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+index fda3e41..b4d9519 100644
+--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+@@ -135,7 +135,7 @@ static void setup_iomux_enet(void)
+ 
+        /* Need delay 10ms according to KSZ9021 spec */
+        udelay(1000 * 10);
+-       gpio_direction_output(87, 1);  /* GPIO 3-23 */
+       gpio_set_value(87, 1);  /* GPIO 3-23 */
+ 
+        imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+ }
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0009-mx28evk-Allow-to-booting-a-dt-kernel.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0009-mx28evk-Allow-to-booting-a-dt-kernel.patch
new file mode 100644
index 000000000..29cfdb063
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0009-mx28evk-Allow-to-booting-a-dt-kernel.patch
@@ -0,0 +1,27 @@
+From aff99e861996d61fda4ea4158f727cf2657abc52 Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Mon, 23 Apr 2012 06:06:28 +0000
+Subject: [PATCH 09/56] mx28evk: Allow to booting a dt kernel
+Allow to booting a dt kernel.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ include/configs/mx28evk.h |    1 +
+ 1 file changed, 1 insertion(+)
+diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
+index 02f3366..cb4ff37 100644
+--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
+@@ -225,6 +225,7 @@
+ #define CONFIG_BOOTCOMMAND     "run bootcmd_net"
+ #define CONFIG_LOADADDR        0x42000000
+ #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+#define CONFIG_OF_LIBFDT
+ 
+ /*
+  * Extra Environments
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0010-m28evk-Allow-to-booting-a-dt-kernel.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0010-m28evk-Allow-to-booting-a-dt-kernel.patch
new file mode 100644
index 000000000..cf0ba98bc
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0010-m28evk-Allow-to-booting-a-dt-kernel.patch
@@ -0,0 +1,27 @@
+From 8b35d52540a88bc8ed2576a59c29cbe13619665d Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Mon, 23 Apr 2012 06:06:29 +0000
+Subject: [PATCH 10/56] m28evk: Allow to booting a dt kernel
+Allow to booting a dt kernel.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ include/configs/m28evk.h |    1 +
+ 1 file changed, 1 insertion(+)
+diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
+index 012381a..39d6a07 100644
+--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
+@@ -279,6 +279,7 @@
+ #define        CONFIG_BOOTCOMMAND      "run bootcmd_net"
+ #define        CONFIG_LOADADDR         0x42000000
+ #define        CONFIG_SYS_LOAD_ADDR    CONFIG_LOADADDR
+#define        CONFIG_OF_LIBFDT
+ 
+ /*
+  * Extra Environments
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0011-mx28evk-Allow-booting-a-zImage-kernel.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0011-mx28evk-Allow-booting-a-zImage-kernel.patch
new file mode 100644
index 000000000..6c235341a
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0011-mx28evk-Allow-booting-a-zImage-kernel.patch
@@ -0,0 +1,27 @@
+From bd41d70b1e3cb9188b387a37cd738782602ea611 Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Mon, 23 Apr 2012 06:31:15 +0000
+Subject: [PATCH 11/56] mx28evk: Allow booting a zImage kernel
+Allow booting a zImage kernel.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ include/configs/mx28evk.h |    1 +
+ 1 file changed, 1 insertion(+)
+diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
+index cb4ff37..31dc718 100644
+--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
+@@ -67,6 +67,7 @@
+ #define CONFIG_CMD_SF
+ #define CONFIG_CMD_SPI
+ #define CONFIG_CMD_USB
+#define CONFIG_CMD_BOOTZ
+ 
+ /*
+  * Memory configurations
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0012-mx6qsabrelite-Allow-booting-a-zImage-kernel.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0012-mx6qsabrelite-Allow-booting-a-zImage-kernel.patch
new file mode 100644
index 000000000..03ddeeb1a
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0012-mx6qsabrelite-Allow-booting-a-zImage-kernel.patch
@@ -0,0 +1,28 @@
+From ff7f1a06324041db0598e7439f907fd9f3d2e6a5 Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Mon, 23 Apr 2012 06:31:16 +0000
+Subject: [PATCH 12/56] mx6qsabrelite: Allow booting a zImage kernel
+Allow booting a zImage kernel.
+Cc: Jason Liu <r64343@freescale.com>
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ include/configs/mx6qsabrelite.h |    1 +
+ 1 file changed, 1 insertion(+)
+diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
+index 3f7e51d..492c618 100644
+--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
+@@ -211,6 +211,7 @@
+ #endif
+ 
+ #define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+ 
+ #define CONFIG_SYS_DCACHE_OFF
+ 
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0013-mx6qarm2-Allow-booting-a-zImage-kernel.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0013-mx6qarm2-Allow-booting-a-zImage-kernel.patch
new file mode 100644
index 000000000..98a94b2cc
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0013-mx6qarm2-Allow-booting-a-zImage-kernel.patch
@@ -0,0 +1,29 @@
+From 9d544113fe792e8b8f32b24db33630ba78f8fd47 Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Mon, 23 Apr 2012 06:31:17 +0000
+Subject: [PATCH 13/56] mx6qarm2: Allow booting a zImage kernel
+Allow booting a zImage kernel.
+Cc: Jason Liu <r64343@freescale.com>
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Acked-by: Jason Liu <r64343@freescale.com>
+---
+ include/configs/mx6qarm2.h |    1 +
+ 1 file changed, 1 insertion(+)
+diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
+index e83aec6..90652c6 100644
+--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
+@@ -168,6 +168,7 @@
+ #define CONFIG_SYS_MMC_ENV_DEV         1
+ 
+ #define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+ 
+ #define CONFIG_SYS_DCACHE_OFF
+ 
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0014-mx31pdk-Allow-booting-a-zImage-kernel.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0014-mx31pdk-Allow-booting-a-zImage-kernel.patch
new file mode 100644
index 000000000..3dc7533d2
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0014-mx31pdk-Allow-booting-a-zImage-kernel.patch
@@ -0,0 +1,27 @@
+From 4a2f5e4f606146c373d7421e1a340d2bdbb54ffe Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Mon, 23 Apr 2012 06:31:18 +0000
+Subject: [PATCH 14/56] mx31pdk: Allow booting a zImage kernel
+Allow booting a zImage kernel.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ include/configs/mx31pdk.h |    1 +
+ 1 file changed, 1 insertion(+)
+diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
+index 49d440b..6ce97bc 100644
+--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
+@@ -99,6 +99,7 @@
+ #define CONFIG_CMD_SPI
+ #define CONFIG_CMD_DATE
+ #define CONFIG_CMD_NAND
+#define CONFIG_CMD_BOOTZ
+ 
+ /*
+  * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0015-i.MX6Q-mx6qsabrelite-Add-keypress-support-to-alter-b.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0015-i.MX6Q-mx6qsabrelite-Add-keypress-support-to-alter-b.patch
new file mode 100644
index 000000000..1b263be12
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0015-i.MX6Q-mx6qsabrelite-Add-keypress-support-to-alter-b.patch
@@ -0,0 +1,195 @@
+From 92a45a8ec4bf1abe5ff5ac123bf4edd6ccb2f353 Mon Sep 17 00:00:00 2001
+From: Eric Nelson <eric.nelson@boundarydevices.com>
+Date: Wed, 25 Apr 2012 14:14:04 +0000
+Subject: [PATCH 15/56] i.MX6Q: mx6qsabrelite: Add keypress support to alter
+ boot flow
+Uses the 'magic_keys' idiom as described in doc/README.kbd:
+        http://lists.denx.de/pipermail/u-boot/2012-April/122502.html
+Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
+Acked-by: Marek Vasut <marex@denx.de>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ board/freescale/mx6qsabrelite/mx6qsabrelite.c |  122 ++++++++++++++++++++++++-
+ include/configs/mx6qsabrelite.h               |    3 +
+ 2 files changed, 123 insertions(+), 2 deletions(-)
+diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+index b4d9519..90773aa 100644
+--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+@@ -50,6 +50,10 @@ DECLARE_GLOBAL_DATA_PTR;
+        PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
+        PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+ 
+#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |           \
+       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
+       PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+ int dram_init(void)
+ {
+        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+@@ -122,6 +126,22 @@ iomux_v3_cfg_t enet_pads2[] = {
+        MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL     | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ };
+ 
+/* Button assignments for J14 */
+static iomux_v3_cfg_t button_pads[] = {
+       /* Menu */
+       MX6Q_PAD_NANDF_D1__GPIO_2_1     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+       /* Back */
+       MX6Q_PAD_NANDF_D2__GPIO_2_2     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+       /* Labelled Search (mapped to Power under Android) */
+       MX6Q_PAD_NANDF_D3__GPIO_2_3     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+       /* Home */
+       MX6Q_PAD_NANDF_D4__GPIO_2_4     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+       /* Volume Down */
+       MX6Q_PAD_GPIO_19__GPIO_4_5      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+       /* Volume Up */
+       MX6Q_PAD_GPIO_18__GPIO_7_13     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+};
+
+ static void setup_iomux_enet(void)
+ {
+        gpio_direction_output(87, 0);  /* GPIO 3-23 */
+@@ -267,11 +287,18 @@ int board_eth_init(bd_t *bis)
+        return 0;
+ }
+ 
+static void setup_buttons(void)
+{
+       imx_iomux_v3_setup_multiple_pads(button_pads,
+                                        ARRAY_SIZE(button_pads));
+}
+
+ int board_early_init_f(void)
+ {
+-       setup_iomux_uart();
+       setup_iomux_uart();
+       setup_buttons();
+ 
+-       return 0;
+       return 0;
+ }
+ 
+ int board_init(void)
+@@ -292,3 +319,94 @@ int checkboard(void)
+ 
+        return 0;
+ }
+
+struct button_key {
+       char const      *name;
+       unsigned        gpnum;
+       char            ident;
+};
+
+static struct button_key const buttons[] = {
+       {"back",        GPIO_NUMBER(2, 2),      'B'},
+       {"home",        GPIO_NUMBER(2, 4),      'H'},
+       {"menu",        GPIO_NUMBER(2, 1),      'M'},
+       {"search",      GPIO_NUMBER(2, 3),      'S'},
+       {"volup",       GPIO_NUMBER(7, 13),     'V'},
+       {"voldown",     GPIO_NUMBER(4, 5),      'v'},
+};
+
+/*
+ * generate a null-terminated string containing the buttons pressed
+ * returns number of keys pressed
+ */
+static int read_keys(char *buf)
+{
+       int i, numpressed = 0;
+       for (i = 0; i < ARRAY_SIZE(buttons); i++) {
+               if (!gpio_get_value(buttons[i].gpnum))
+                       buf[numpressed++] = buttons[i].ident;
+       }
+       buf[numpressed] = '\0';
+       return numpressed;
+}
+
+static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+       char envvalue[ARRAY_SIZE(buttons)+1];
+       int numpressed = read_keys(envvalue);
+       setenv("keybd", envvalue);
+       return numpressed == 0;
+}
+
+U_BOOT_CMD(
+       kbd, 1, 1, do_kbd,
+       "Tests for keypresses, sets 'keybd' environment variable",
+       "Returns 0 (true) to shell if key is pressed."
+);
+
+#ifdef CONFIG_PREBOOT
+static char const kbd_magic_prefix[] = "key_magic";
+static char const kbd_command_prefix[] = "key_cmd";
+
+static void preboot_keys(void)
+{
+       int numpressed;
+       char keypress[ARRAY_SIZE(buttons)+1];
+       numpressed = read_keys(keypress);
+       if (numpressed) {
+               char *kbd_magic_keys = getenv("magic_keys");
+               char *suffix;
+               /*
+                * loop over all magic keys
+                */
+               for (suffix = kbd_magic_keys; *suffix; ++suffix) {
+                       char *keys;
+                       char magic[sizeof(kbd_magic_prefix) + 1];
+                       sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
+                       keys = getenv(magic);
+                       if (keys) {
+                               if (!strcmp(keys, keypress))
+                                       break;
+                       }
+               }
+               if (*suffix) {
+                       char cmd_name[sizeof(kbd_command_prefix) + 1];
+                       char *cmd;
+                       sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
+                       cmd = getenv(cmd_name);
+                       if (cmd) {
+                               setenv("preboot", cmd);
+                               return;
+                       }
+               }
+       }
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_PREBOOT
+       preboot_keys();
+#endif
+       return 0;
+}
+diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
+index 492c618..48be6e6 100644
+--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
+@@ -42,6 +42,7 @@
+ 
+ #define CONFIG_ARCH_CPU_INIT
+ #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+ #define CONFIG_MXC_GPIO
+ 
+ #define CONFIG_MXC_UART
+@@ -110,6 +111,8 @@
+ 
+ #define CONFIG_BOOTDELAY              3
+ 
+#define CONFIG_PREBOOT                 ""
+
+ #define CONFIG_LOADADDR                               0x10800000
+ #define CONFIG_SYS_TEXT_BASE          0x17800000
+ 
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0016-imx-common-Factor-out-get_ahb_clk.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0016-imx-common-Factor-out-get_ahb_clk.patch
new file mode 100644
index 000000000..07879391a
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0016-imx-common-Factor-out-get_ahb_clk.patch
@@ -0,0 +1,1970 @@
+From a849600b9d2b702acf3d1b21b96bc3df8ea53e6d Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <festevam@gmail.com>
+Date: Sun, 29 Apr 2012 08:11:13 +0000
+Subject: [PATCH 16/56] imx-common: Factor out get_ahb_clk()
+get_ahb_clk() is a common function between mx5 and mx6.
+Place it into imx-common directory.
+Cc: Dirk Behme <dirk.behme@googlemail.com>
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ arch/arm/cpu/armv7/imx-common/cpu.c       |   13 +
+ arch/arm/cpu/armv7/mx5/clock.c            |   19 +-
+ arch/arm/cpu/armv7/mx6/clock.c            |   19 +-
+ arch/arm/include/asm/arch-mx5/sys_proto.h |    2 +
+ arch/arm/include/asm/arch-mx6/ccm_regs.h  |  892 -----------------------------
+ arch/arm/include/asm/arch-mx6/crm_regs.h  |  892 +++++++++++++++++++++++++++++
+ arch/arm/include/asm/arch-mx6/sys_proto.h |    3 +-
+ 7 files changed, 915 insertions(+), 925 deletions(-)
+ delete mode 100644 arch/arm/include/asm/arch-mx6/ccm_regs.h
+ create mode 100644 arch/arm/include/asm/arch-mx6/crm_regs.h
+diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c
+index 3d58d8a..b96fa5b 100644
+--- a/arch/arm/cpu/armv7/imx-common/cpu.c
+++ b/arch/arm/cpu/armv7/imx-common/cpu.c
+@@ -29,6 +29,7 @@
+ #include <asm/arch/imx-regs.h>
+ #include <asm/arch/clock.h>
+ #include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+ 
+ #ifdef CONFIG_FSL_ESDHC
+ #include <fsl_esdhc.h>
+@@ -127,3 +128,15 @@ void reset_cpu(ulong addr)
+ {
+        __raw_writew(4, WDOG1_BASE_ADDR);
+ }
+
+u32 get_ahb_clk(void)
+{
+       struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       u32 reg, ahb_podf;
+
+       reg = __raw_readl(&imx_ccm->cbcdr);
+       reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
+       ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+
+       return get_periph_clk() / (ahb_podf + 1);
+}
+diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
+index d769a4d..903e207 100644
+--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
+@@ -30,6 +30,7 @@
+ #include <asm/arch/crm_regs.h>
+ #include <asm/arch/clock.h>
+ #include <div64.h>
+#include <asm/arch/sys_proto.h>
+ 
+ enum pll_clocks {
+        PLL1_CLOCK = 0,
+@@ -192,7 +193,7 @@ u32 get_mcu_main_clk(void)
+ /*
+  * Get the rate of peripheral's root clock.
+  */
+-static u32 get_periph_clk(void)
+u32 get_periph_clk(void)
+ {
+        u32 reg;
+ 
+@@ -213,22 +214,6 @@ static u32 get_periph_clk(void)
+ }
+ 
+ /*
+- * Get the rate of ahb clock.
+- */
+-static u32 get_ahb_clk(void)
+-{
+-       uint32_t freq, div, reg;
+-
+-       freq = get_periph_clk();
+-
+-       reg = __raw_readl(&mxc_ccm->cbcdr);
+-       div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
+-                       MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
+-
+-       return freq / div;
+-}
+-
+-/*
+  * Get the rate of ipg clock.
+  */
+ static u32 get_ipg_clk(void)
+diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
+index ef98563..0f05432 100644
+--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
+@@ -24,8 +24,9 @@
+ #include <asm/io.h>
+ #include <asm/errno.h>
+ #include <asm/arch/imx-regs.h>
+-#include <asm/arch/ccm_regs.h>
+#include <asm/arch/crm_regs.h>
+ #include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+ 
+ enum pll_clocks {
+        PLL_SYS,        /* System PLL */
+@@ -34,7 +35,7 @@ enum pll_clocks {
+        PLL_ENET,       /* ENET PLL */
+ };
+ 
+-struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ 
+ void enable_usboh3_clk(unsigned char enable)
+ {
+@@ -92,7 +93,7 @@ static u32 get_mcu_main_clk(void)
+        return freq / (reg + 1);
+ }
+ 
+-static u32 get_periph_clk(void)
+u32 get_periph_clk(void)
+ {
+        u32 reg, freq = 0;
+ 
+@@ -139,18 +140,6 @@ static u32 get_periph_clk(void)
+        return freq;
+ }
+ 
+-
+-static u32 get_ahb_clk(void)
+-{
+-       u32 reg, ahb_podf;
+-
+-       reg = __raw_readl(&imx_ccm->cbcdr);
+-       reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
+-       ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+-
+-       return get_periph_clk() / (ahb_podf + 1);
+-}
+-
+ static u32 get_ipg_clk(void)
+ {
+        u32 reg, ipg_podf;
+diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
+index 13d12ee..3f10d29 100644
+--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
+@@ -35,5 +35,7 @@ void set_chipselect_size(int const);
+  */
+ 
+ int fecmxc_initialize(bd_t *bis);
+u32 get_ahb_clk(void);
+u32 get_periph_clk(void);
+ 
+ #endif
+diff --git a/arch/arm/include/asm/arch-mx6/ccm_regs.h b/arch/arm/include/asm/arch-mx6/ccm_regs.h
+deleted file mode 100644
+index 4af0b90..0000000
+--- a/arch/arm/include/asm/arch-mx6/ccm_regs.h
+++ /dev/null
+@@ -1,892 +0,0 @@
+-/*
+- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+- *
+- */
+-
+-#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+-#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+-
+-struct imx_ccm_reg {
+-       u32 ccr;        /* 0x0000 */
+-       u32 ccdr;
+-       u32 csr;
+-       u32 ccsr;
+-       u32 cacrr;      /* 0x0010*/
+-       u32 cbcdr;
+-       u32 cbcmr;
+-       u32 cscmr1;
+-       u32 cscmr2;     /* 0x0020 */
+-       u32 cscdr1;
+-       u32 cs1cdr;
+-       u32 cs2cdr;
+-       u32 cdcdr;      /* 0x0030 */
+-       u32 chscdr;
+-       u32 cscdr2;
+-       u32 cscdr3;
+-       u32 cscdr4;     /* 0x0040 */
+-       u32 resv0;
+-       u32 cdhipr;
+-       u32 cdcr;
+-       u32 ctor;       /* 0x0050 */
+-       u32 clpcr;
+-       u32 cisr;
+-       u32 cimr;
+-       u32 ccosr;      /* 0x0060 */
+-       u32 cgpr;
+-       u32 CCGR0;
+-       u32 CCGR1;
+-       u32 CCGR2;      /* 0x0070 */
+-       u32 CCGR3;
+-       u32 CCGR4;
+-       u32 CCGR5;
+-       u32 CCGR6;      /* 0x0080 */
+-       u32 CCGR7;
+-       u32 cmeor;
+-       u32 resv[0xfdd];
+-       u32 analog_pll_sys;                     /* 0x4000 */
+-       u32 analog_pll_sys_set;
+-       u32 analog_pll_sys_clr;
+-       u32 analog_pll_sys_tog;
+-       u32 analog_usb1_pll_480_ctrl;           /* 0x4010 */
+-       u32 analog_usb1_pll_480_ctrl_set;
+-       u32 analog_usb1_pll_480_ctrl_clr;
+-       u32 analog_usb1_pll_480_ctrl_tog;
+-       u32 analog_reserved0[4];
+-       u32 analog_pll_528;                     /* 0x4030 */
+-       u32 analog_pll_528_set;
+-       u32 analog_pll_528_clr;
+-       u32 analog_pll_528_tog;
+-       u32 analog_pll_528_ss;                  /* 0x4040 */
+-       u32 analog_reserved1[3];
+-       u32 analog_pll_528_num;                 /* 0x4050 */
+-       u32 analog_reserved2[3];
+-       u32 analog_pll_528_denom;               /* 0x4060 */
+-       u32 analog_reserved3[3];
+-       u32 analog_pll_audio;                   /* 0x4070 */
+-       u32 analog_pll_audio_set;
+-       u32 analog_pll_audio_clr;
+-       u32 analog_pll_audio_tog;
+-       u32 analog_pll_audio_num;               /* 0x4080*/
+-       u32 analog_reserved4[3];
+-       u32 analog_pll_audio_denom;             /* 0x4090 */
+-       u32 analog_reserved5[3];
+-       u32 analog_pll_video;                   /* 0x40a0 */
+-       u32 analog_pll_video_set;
+-       u32 analog_pll_video_clr;
+-       u32 analog_pll_video_tog;
+-       u32 analog_pll_video_num;               /* 0x40b0 */
+-       u32 analog_reserved6[3];
+-       u32 analog_pll_vedio_denon;             /* 0x40c0 */
+-       u32 analog_reserved7[7];
+-       u32 analog_pll_enet;                    /* 0x40e0 */
+-       u32 analog_pll_enet_set;
+-       u32 analog_pll_enet_clr;
+-       u32 analog_pll_enet_tog;
+-       u32 analog_pfd_480;                     /* 0x40f0 */
+-       u32 analog_pfd_480_set;
+-       u32 analog_pfd_480_clr;
+-       u32 analog_pfd_480_tog;
+-       u32 analog_pfd_528;                     /* 0x4100 */
+-       u32 analog_pfd_528_set;
+-       u32 analog_pfd_528_clr;
+-       u32 analog_pfd_528_tog;
+-};
+-
+-/* Define the bits in register CCR */
+-#define MXC_CCM_CCR_RBC_EN                             (1 << 27)
+-#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK                        (0x3F << 21)
+-#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET              21
+-#define MXC_CCM_CCR_WB_COUNT_MASK                      0x7
+-#define MXC_CCM_CCR_WB_COUNT_OFFSET                    (1 << 16)
+-#define MXC_CCM_CCR_COSC_EN                            (1 << 12)
+-#define MXC_CCM_CCR_OSCNT_MASK                         0xFF
+-#define MXC_CCM_CCR_OSCNT_OFFSET                       0
+-
+-/* Define the bits in register CCDR */
+-#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK                  (1 << 16)
+-#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK                  (1 << 17)
+-
+-/* Define the bits in register CSR */
+-#define MXC_CCM_CSR_COSC_READY                         (1 << 5)
+-#define MXC_CCM_CSR_REF_EN_B                           (1 << 0)
+-
+-/* Define the bits in register CCSR */
+-#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS                 (1 << 15)
+-#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS                 (1 << 14)
+-#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS                 (1 << 13)
+-#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS                 (1 << 12)
+-#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS                 (1 << 11)
+-#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS                 (1 << 10)
+-#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS                 (1 << 9)
+-#define MXC_CCM_CCSR_STEP_SEL                          (1 << 8)
+-#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL                   (1 << 2)
+-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL                   (1 << 1)
+-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL                   (1 << 0)
+-
+-/* Define the bits in register CACRR */
+-#define MXC_CCM_CACRR_ARM_PODF_OFFSET                  0
+-#define MXC_CCM_CACRR_ARM_PODF_MASK                    0x7
+-
+-/* Define the bits in register CBCDR */
+-#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK            (0x7 << 27)
+-#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET          27
+-#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL                 (1 << 26)
+-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL                   (1 << 25)
+-#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK               (0x7 << 19)
+-#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET             19
+-#define MXC_CCM_CBCDR_AXI_PODF_MASK                    (0x7 << 16)
+-#define MXC_CCM_CBCDR_AXI_PODF_OFFSET                  16
+-#define MXC_CCM_CBCDR_AHB_PODF_MASK                    (0x7 << 10)
+-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET                  10
+-#define MXC_CCM_CBCDR_IPG_PODF_MASK                    (0x3 << 8)
+-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET                  8
+-#define MXC_CCM_CBCDR_AXI_ALT_SEL                      (1 << 7)
+-#define MXC_CCM_CBCDR_AXI_SEL                          (1 << 6)
+-#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK               (0x7 << 3)
+-#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET             3
+-#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK           (0x7 << 0)
+-#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET         0
+-
+-/* Define the bits in register CBCMR */
+-#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK           (0x7 << 29)
+-#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET         29
+-#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK             (0x7 << 26)
+-#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET           26
+-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK             (0x7 << 23)
+-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET           23
+-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK         (0x3 << 21)
+-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET       21
+-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL             (1 << 20)
+-#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK          (0x3 << 18)
+-#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET                18
+-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK               (0x3 << 16)
+-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET             16
+-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK             (0x3 << 14)
+-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET           14
+-#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK             (0x3 << 12)
+-#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET           12
+-#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL                   (1 << 11)
+-#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL                 (1 << 10)
+-#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK                (0x3 << 8)
+-#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET      8
+-#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK          (0x3 << 4)
+-#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET                4
+-#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL                        (1 << 1)
+-#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL                        (1 << 0)
+-
+-/* Define the bits in register CSCMR1 */
+-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK              (0x3 << 29)
+-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET            29
+-#define MXC_CCM_CSCMR1_ACLK_EMI_MASK                   (0x3 << 27)
+-#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET                 27
+-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK         (0x7 << 23)
+-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET       23
+-#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK              (0x7 << 20)
+-#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET            20
+-#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL                  (1 << 19)
+-#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL                  (1 << 18)
+-#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL                  (1 << 17)
+-#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL                  (1 << 16)
+-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK               (0x3 << 14)
+-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET             14
+-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK               (0x3 << 12)
+-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET             12
+-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK               (0x3 << 10)
+-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET             10
+-#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                        0x3F
+-
+-/* Define the bits in register CSCMR2 */
+-#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK               (0x3 << 19)
+-#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET             19
+-#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV                 (1 << 11)
+-#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV                 (1 << 10)
+-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                        (0x3F << 2)
+-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET              2
+-
+-/* Define the bits in register CSCDR1 */
+-#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK               (0x7 << 25)
+-#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET             25
+-#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK                        (0x7 << 22)
+-#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET              22
+-#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK                        (0x7 << 19)
+-#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET              19
+-#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK                        (0x7 << 16)
+-#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET              16
+-#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK                        (0x7 << 11)
+-#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET              11
+-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET          8
+-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK            (0x7 << 8)
+-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET          6
+-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK            (0x3 << 6)
+-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              0x3F
+-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET            0
+-
+-/* Define the bits in register CS1CDR */
+-#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK              (0x3F << 25)
+-#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET            25
+-#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK              (0x3F << 16)
+-#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET            16
+-#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK              (0x3 << 9)
+-#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET            9
+-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK              (0x7 << 6)
+-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET            6
+-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK              0x3F
+-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET            0
+-
+-/* Define the bits in register CS2CDR */
+-#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK              (0x3F << 21)
+-#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET            21
+-#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK              (0x7 << 18)
+-#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET            18
+-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK               (0x3 << 16)
+-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET             16
+-#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK            (0x7 << 12)
+-#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET          12
+-#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK            (0x7 << 9)
+-#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET          9
+-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK              (0x7 << 6)
+-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET            6
+-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK              0x3F
+-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET            0
+-
+-/* Define the bits in register CDCDR */
+-#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK                 (0x7 << 29)
+-#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET               29
+-#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL                   (1 << 28)
+-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK             (0x7 << 25)
+-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET           25
+-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK             (0x7 << 19)
+-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET           19
+-#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK              (0x3 << 20)
+-#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET            20
+-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK             (0x7 << 12)
+-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET           12
+-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK             (0x7 << 9)
+-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET           9
+-#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK              (0x3 << 7)
+-#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET            7
+-
+-/* Define the bits in register CHSCCDR */
+-#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK      (0x7 << 15)
+-#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET    15
+-#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK             (0x7 << 12)
+-#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET           12
+-#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK          (0x7 << 9)
+-#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET                9
+-#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK      (0x7 << 6)
+-#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET    6
+-#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK             (0x7 << 3)
+-#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET           3
+-#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK          (0x7)
+-#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET                0
+-
+-/* Define the bits in register CSCDR2 */
+-#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK             (0x3F << 19)
+-#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET           19
+-#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK      (0x7 << 15)
+-#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET    15
+-#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK             (0x7 << 12)
+-#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET           12
+-#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK          (0x7 << 9)
+-#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET                9
+-#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK      (0x7 << 6)
+-#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET    6
+-#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK             (0x7 << 3)
+-#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET           3
+-#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK          0x7
+-#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET                0
+-
+-/* Define the bits in register CSCDR3 */
+-#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK              (0x7 << 16)
+-#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET            16
+-#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK           (0x3 << 14)
+-#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET         14
+-#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK              (0x7 << 11)
+-#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET            11
+-#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK           (0x3 << 9)
+-#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET         9
+-
+-/* Define the bits in register CDHIPR */
+-#define MXC_CCM_CDHIPR_ARM_PODF_BUSY                   (1 << 16)
+-#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY             (1 << 5)
+-#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY              (1 << 4)
+-#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY            (1 << 3)
+-#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY              (1 << 2)
+-#define MXC_CCM_CDHIPR_AHB_PODF_BUSY                   (1 << 1)
+-#define MXC_CCM_CDHIPR_AXI_PODF_BUSY                   1
+-
+-/* Define the bits in register CLPCR */
+-#define MXC_CCM_CLPCR_MASK_L2CC_IDLE                   (1 << 27)
+-#define MXC_CCM_CLPCR_MASK_SCU_IDLE                    (1 << 26)
+-#define MXC_CCM_CLPCR_MASK_CORE3_WFI                   (1 << 25)
+-#define MXC_CCM_CLPCR_MASK_CORE2_WFI                   (1 << 24)
+-#define MXC_CCM_CLPCR_MASK_CORE1_WFI                   (1 << 23)
+-#define MXC_CCM_CLPCR_MASK_CORE0_WFI                   (1 << 22)
+-#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS              (1 << 21)
+-#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS              (1 << 19)
+-#define MXC_CCM_CLPCR_WB_CORE_AT_LPM                   (1 << 17)
+-#define MXC_CCM_CLPCR_WB_PER_AT_LPM                    (1 << 17)
+-#define MXC_CCM_CLPCR_COSC_PWRDOWN                     (1 << 11)
+-#define MXC_CCM_CLPCR_STBY_COUNT_MASK                  (0x3 << 9)
+-#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET                        9
+-#define MXC_CCM_CLPCR_VSTBY                            (1 << 8)
+-#define MXC_CCM_CLPCR_DIS_REF_OSC                      (1 << 7)
+-#define MXC_CCM_CLPCR_SBYOS                            (1 << 6)
+-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM               (1 << 5)
+-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                        (0x3 << 3)
+-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET              3
+-#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY          (1 << 2)
+-#define MXC_CCM_CLPCR_LPM_MASK                         0x3
+-#define MXC_CCM_CLPCR_LPM_OFFSET                       0
+-
+-/* Define the bits in register CISR */
+-#define MXC_CCM_CISR_ARM_PODF_LOADED                   (1 << 26)
+-#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED              (1 << 23)
+-#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED             (1 << 22)
+-#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED              (1 << 21)
+-#define MXC_CCM_CISR_AHB_PODF_LOADED                   (1 << 20)
+-#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED            (1 << 19)
+-#define MXC_CCM_CISR_AXI_PODF_LOADED                   (1 << 17)
+-#define MXC_CCM_CISR_COSC_READY                                (1 << 6)
+-#define MXC_CCM_CISR_LRF_PLL                           1
+-
+-/* Define the bits in register CIMR */
+-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED              (1 << 26)
+-#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED         (1 << 23)
+-#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED                (1 << 22)
+-#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED         (1 << 21)
+-#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED              (1 << 20)
+-#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED       (1 << 22)
+-#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED              (1 << 17)
+-#define MXC_CCM_CIMR_MASK_COSC_READY                   (1 << 6)
+-#define MXC_CCM_CIMR_MASK_LRF_PLL                      1
+-
+-/* Define the bits in register CCOSR */
+-#define MXC_CCM_CCOSR_CKO2_EN_OFFSET                   (1 << 24)
+-#define MXC_CCM_CCOSR_CKO2_DIV_MASK                    (0x7 << 21)
+-#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                  21
+-#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                  16
+-#define MXC_CCM_CCOSR_CKO2_SEL_MASK                    (0x1F << 16)
+-#define MXC_CCM_CCOSR_CKOL_EN                          (0x1 << 7)
+-#define MXC_CCM_CCOSR_CKOL_DIV_MASK                    (0x7 << 4)
+-#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                  4
+-#define MXC_CCM_CCOSR_CKOL_SEL_MASK                    0xF
+-#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                  0
+-
+-/* Define the bits in registers CGPR */
+-#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE            (1 << 4)
+-#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS                  (1 << 2)
+-#define MXC_CCM_CGPR_PMIC_DELAY_SCALER                 1
+-
+-/* Define the bits in registers CCGRx */
+-#define MXC_CCM_CCGR_CG_MASK                           3
+-
+-#define MXC_CCM_CCGR0_CG15_OFFSET                      30
+-#define MXC_CCM_CCGR0_CG15_MASK                        (0x3 << 30)
+-#define MXC_CCM_CCGR0_CG14_OFFSET                      28
+-#define MXC_CCM_CCGR0_CG14_MASK                        (0x3 << 28)
+-#define MXC_CCM_CCGR0_CG13_OFFSET                      26
+-#define MXC_CCM_CCGR0_CG13_MASK                        (0x3 << 26)
+-#define MXC_CCM_CCGR0_CG12_OFFSET                      24
+-#define MXC_CCM_CCGR0_CG12_MASK                        (0x3 << 24)
+-#define MXC_CCM_CCGR0_CG11_OFFSET                      22
+-#define MXC_CCM_CCGR0_CG11_MASK                        (0x3 << 22)
+-#define MXC_CCM_CCGR0_CG10_OFFSET                      20
+-#define MXC_CCM_CCGR0_CG10_MASK                        (0x3 << 20)
+-#define MXC_CCM_CCGR0_CG9_OFFSET                       18
+-#define MXC_CCM_CCGR0_CG9_MASK                 (0x3 << 18)
+-#define MXC_CCM_CCGR0_CG8_OFFSET                       16
+-#define MXC_CCM_CCGR0_CG8_MASK                 (0x3 << 16)
+-#define MXC_CCM_CCGR0_CG7_OFFSET                       14
+-#define MXC_CCM_CCGR0_CG6_OFFSET                       12
+-#define MXC_CCM_CCGR0_CG5_OFFSET                       10
+-#define MXC_CCM_CCGR0_CG5_MASK                 (0x3 << 10)
+-#define MXC_CCM_CCGR0_CG4_OFFSET                       8
+-#define MXC_CCM_CCGR0_CG4_MASK                 (0x3 << 8)
+-#define MXC_CCM_CCGR0_CG3_OFFSET                       6
+-#define MXC_CCM_CCGR0_CG3_MASK                 (0x3 << 6)
+-#define MXC_CCM_CCGR0_CG2_OFFSET                       4
+-#define MXC_CCM_CCGR0_CG2_MASK                 (0x3 << 4)
+-#define MXC_CCM_CCGR0_CG1_OFFSET                       2
+-#define MXC_CCM_CCGR0_CG1_MASK                 (0x3 << 2)
+-#define MXC_CCM_CCGR0_CG0_OFFSET                       0
+-#define MXC_CCM_CCGR0_CG0_MASK                         3
+-
+-#define MXC_CCM_CCGR1_CG15_OFFSET                      30
+-#define MXC_CCM_CCGR1_CG14_OFFSET                      28
+-#define MXC_CCM_CCGR1_CG13_OFFSET                      26
+-#define MXC_CCM_CCGR1_CG12_OFFSET                      24
+-#define MXC_CCM_CCGR1_CG11_OFFSET                      22
+-#define MXC_CCM_CCGR1_CG10_OFFSET                      20
+-#define MXC_CCM_CCGR1_CG9_OFFSET                       18
+-#define MXC_CCM_CCGR1_CG8_OFFSET                       16
+-#define MXC_CCM_CCGR1_CG7_OFFSET                       14
+-#define MXC_CCM_CCGR1_CG6_OFFSET                       12
+-#define MXC_CCM_CCGR1_CG5_OFFSET                       10
+-#define MXC_CCM_CCGR1_CG4_OFFSET                       8
+-#define MXC_CCM_CCGR1_CG3_OFFSET                       6
+-#define MXC_CCM_CCGR1_CG2_OFFSET                       4
+-#define MXC_CCM_CCGR1_CG1_OFFSET                       2
+-#define MXC_CCM_CCGR1_CG0_OFFSET                       0
+-
+-#define MXC_CCM_CCGR2_CG15_OFFSET                      30
+-#define MXC_CCM_CCGR2_CG14_OFFSET                      28
+-#define MXC_CCM_CCGR2_CG13_OFFSET                      26
+-#define MXC_CCM_CCGR2_CG12_OFFSET                      24
+-#define MXC_CCM_CCGR2_CG11_OFFSET                      22
+-#define MXC_CCM_CCGR2_CG10_OFFSET                      20
+-#define MXC_CCM_CCGR2_CG9_OFFSET                       18
+-#define MXC_CCM_CCGR2_CG8_OFFSET                       16
+-#define MXC_CCM_CCGR2_CG7_OFFSET                       14
+-#define MXC_CCM_CCGR2_CG6_OFFSET                       12
+-#define MXC_CCM_CCGR2_CG5_OFFSET                       10
+-#define MXC_CCM_CCGR2_CG4_OFFSET                       8
+-#define MXC_CCM_CCGR2_CG3_OFFSET                       6
+-#define MXC_CCM_CCGR2_CG2_OFFSET                       4
+-#define MXC_CCM_CCGR2_CG1_OFFSET                       2
+-#define MXC_CCM_CCGR2_CG0_OFFSET                       0
+-
+-#define MXC_CCM_CCGR3_CG15_OFFSET                      30
+-#define MXC_CCM_CCGR3_CG14_OFFSET                      28
+-#define MXC_CCM_CCGR3_CG13_OFFSET                      26
+-#define MXC_CCM_CCGR3_CG12_OFFSET                      24
+-#define MXC_CCM_CCGR3_CG11_OFFSET                      22
+-#define MXC_CCM_CCGR3_CG10_OFFSET                      20
+-#define MXC_CCM_CCGR3_CG9_OFFSET                       18
+-#define MXC_CCM_CCGR3_CG8_OFFSET                       16
+-#define MXC_CCM_CCGR3_CG7_OFFSET                       14
+-#define MXC_CCM_CCGR3_CG6_OFFSET                       12
+-#define MXC_CCM_CCGR3_CG5_OFFSET                       10
+-#define MXC_CCM_CCGR3_CG4_OFFSET                       8
+-#define MXC_CCM_CCGR3_CG3_OFFSET                       6
+-#define MXC_CCM_CCGR3_CG2_OFFSET                       4
+-#define MXC_CCM_CCGR3_CG1_OFFSET                       2
+-#define MXC_CCM_CCGR3_CG0_OFFSET                       0
+-
+-#define MXC_CCM_CCGR4_CG15_OFFSET                      30
+-#define MXC_CCM_CCGR4_CG14_OFFSET                      28
+-#define MXC_CCM_CCGR4_CG13_OFFSET                      26
+-#define MXC_CCM_CCGR4_CG12_OFFSET                      24
+-#define MXC_CCM_CCGR4_CG11_OFFSET                      22
+-#define MXC_CCM_CCGR4_CG10_OFFSET                      20
+-#define MXC_CCM_CCGR4_CG9_OFFSET                       18
+-#define MXC_CCM_CCGR4_CG8_OFFSET                       16
+-#define MXC_CCM_CCGR4_CG7_OFFSET                       14
+-#define MXC_CCM_CCGR4_CG6_OFFSET                       12
+-#define MXC_CCM_CCGR4_CG5_OFFSET                       10
+-#define MXC_CCM_CCGR4_CG4_OFFSET                       8
+-#define MXC_CCM_CCGR4_CG3_OFFSET                       6
+-#define MXC_CCM_CCGR4_CG2_OFFSET                       4
+-#define MXC_CCM_CCGR4_CG1_OFFSET                       2
+-#define MXC_CCM_CCGR4_CG0_OFFSET                       0
+-
+-#define MXC_CCM_CCGR5_CG15_OFFSET                      30
+-#define MXC_CCM_CCGR5_CG14_OFFSET                      28
+-#define MXC_CCM_CCGR5_CG14_MASK                        (0x3 << 28)
+-#define MXC_CCM_CCGR5_CG13_OFFSET                      26
+-#define MXC_CCM_CCGR5_CG13_MASK                        (0x3 << 26)
+-#define MXC_CCM_CCGR5_CG12_OFFSET                      24
+-#define MXC_CCM_CCGR5_CG12_MASK                        (0x3 << 24)
+-#define MXC_CCM_CCGR5_CG11_OFFSET                      22
+-#define MXC_CCM_CCGR5_CG11_MASK                        (0x3 << 22)
+-#define MXC_CCM_CCGR5_CG10_OFFSET                      20
+-#define MXC_CCM_CCGR5_CG10_MASK                        (0x3 << 20)
+-#define MXC_CCM_CCGR5_CG9_OFFSET                       18
+-#define MXC_CCM_CCGR5_CG9_MASK                 (0x3 << 18)
+-#define MXC_CCM_CCGR5_CG8_OFFSET                       16
+-#define MXC_CCM_CCGR5_CG8_MASK                 (0x3 << 16)
+-#define MXC_CCM_CCGR5_CG7_OFFSET                       14
+-#define MXC_CCM_CCGR5_CG7_MASK                 (0x3 << 14)
+-#define MXC_CCM_CCGR5_CG6_OFFSET                       12
+-#define MXC_CCM_CCGR5_CG6_MASK                 (0x3 << 12)
+-#define MXC_CCM_CCGR5_CG5_OFFSET                       10
+-#define MXC_CCM_CCGR5_CG4_OFFSET                       8
+-#define MXC_CCM_CCGR5_CG3_OFFSET                       6
+-#define MXC_CCM_CCGR5_CG2_OFFSET                       4
+-#define MXC_CCM_CCGR5_CG2_MASK                 (0x3 << 4)
+-#define MXC_CCM_CCGR5_CG1_OFFSET                       2
+-#define MXC_CCM_CCGR5_CG0_OFFSET                       0
+-
+-#define MXC_CCM_CCGR6_CG15_OFFSET                      30
+-#define MXC_CCM_CCGR6_CG14_OFFSET                      28
+-#define MXC_CCM_CCGR6_CG14_MASK                        (0x3 << 28)
+-#define MXC_CCM_CCGR6_CG13_OFFSET                      26
+-#define MXC_CCM_CCGR6_CG13_MASK                        (0x3 << 26)
+-#define MXC_CCM_CCGR6_CG12_OFFSET                      24
+-#define MXC_CCM_CCGR6_CG12_MASK                        (0x3 << 24)
+-#define MXC_CCM_CCGR6_CG11_OFFSET                      22
+-#define MXC_CCM_CCGR6_CG11_MASK                        (0x3 << 22)
+-#define MXC_CCM_CCGR6_CG10_OFFSET                      20
+-#define MXC_CCM_CCGR6_CG10_MASK                        (0x3 << 20)
+-#define MXC_CCM_CCGR6_CG9_OFFSET                       18
+-#define MXC_CCM_CCGR6_CG9_MASK                 (0x3 << 18)
+-#define MXC_CCM_CCGR6_CG8_OFFSET                       16
+-#define MXC_CCM_CCGR6_CG8_MASK                 (0x3 << 16)
+-#define MXC_CCM_CCGR6_CG7_OFFSET                       14
+-#define MXC_CCM_CCGR6_CG7_MASK                 (0x3 << 14)
+-#define MXC_CCM_CCGR6_CG6_OFFSET                       12
+-#define MXC_CCM_CCGR6_CG6_MASK                 (0x3 << 12)
+-#define MXC_CCM_CCGR6_CG5_OFFSET                       10
+-#define MXC_CCM_CCGR6_CG4_OFFSET                       8
+-#define MXC_CCM_CCGR6_CG3_OFFSET                       6
+-#define MXC_CCM_CCGR6_CG2_OFFSET                       4
+-#define MXC_CCM_CCGR6_CG2_MASK                 (0x3 << 4)
+-#define MXC_CCM_CCGR6_CG1_OFFSET                       2
+-#define MXC_CCM_CCGR6_CG0_OFFSET                       0
+-
+-#define MXC_CCM_CCGR7_CG15_OFFSET                      30
+-#define MXC_CCM_CCGR7_CG14_OFFSET                      28
+-#define MXC_CCM_CCGR7_CG14_MASK                        (0x3 << 28)
+-#define MXC_CCM_CCGR7_CG13_OFFSET                      26
+-#define MXC_CCM_CCGR7_CG13_MASK                        (0x3 << 26)
+-#define MXC_CCM_CCGR7_CG12_OFFSET                      24
+-#define MXC_CCM_CCGR7_CG12_MASK                        (0x3 << 24)
+-#define MXC_CCM_CCGR7_CG11_OFFSET                      22
+-#define MXC_CCM_CCGR7_CG11_MASK                        (0x3 << 22)
+-#define MXC_CCM_CCGR7_CG10_OFFSET                      20
+-#define MXC_CCM_CCGR7_CG10_MASK                        (0x3 << 20)
+-#define MXC_CCM_CCGR7_CG9_OFFSET                       18
+-#define MXC_CCM_CCGR7_CG9_MASK                 (0x3 << 18)
+-#define MXC_CCM_CCGR7_CG8_OFFSET                       16
+-#define MXC_CCM_CCGR7_CG8_MASK                 (0x3 << 16)
+-#define MXC_CCM_CCGR7_CG7_OFFSET                       14
+-#define MXC_CCM_CCGR7_CG7_MASK                 (0x3 << 14)
+-#define MXC_CCM_CCGR7_CG6_OFFSET                       12
+-#define MXC_CCM_CCGR7_CG6_MASK                 (0x3 << 12)
+-#define MXC_CCM_CCGR7_CG5_OFFSET                       10
+-#define MXC_CCM_CCGR7_CG4_OFFSET                       8
+-#define MXC_CCM_CCGR7_CG3_OFFSET                       6
+-#define MXC_CCM_CCGR7_CG2_OFFSET                       4
+-#define MXC_CCM_CCGR7_CG2_MASK                 (0x3 << 4)
+-#define MXC_CCM_CCGR7_CG1_OFFSET                       2
+-#define MXC_CCM_CCGR7_CG0_OFFSET                       0
+-#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
+-#define BP_ANADIG_PLL_SYS_RSVD0      20
+-#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
+-#define BF_ANADIG_PLL_SYS_RSVD0(v)  \
+-       (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
+-#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
+-#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
+-#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
+-#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
+-#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC      14
+-#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
+-#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v)  \
+-       (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
+-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M  0x0
+-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
+-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
+-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR      0x3
+-#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
+-#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
+-#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
+-#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
+-#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
+-#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
+-#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
+-#define BP_ANADIG_PLL_SYS_DIV_SELECT      0
+-#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
+-#define BF_ANADIG_PLL_SYS_DIV_SELECT(v)  \
+-       (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
+-
+-#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
+-#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1      17
+-#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
+-#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v)  \
+-       (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
+-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
+-#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC      14
+-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
+-#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v)  \
+-       (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M  0x0
+-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
+-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
+-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR      0x3
+-#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
+-#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
+-#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
+-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
+-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
+-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
+-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
+-#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
+-#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
+-#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0      2
+-#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
+-#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v)  \
+-       (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+-#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT      0
+-#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
+-#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v)  \
+-       (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+-
+-#define BM_ANADIG_PLL_528_LOCK 0x80000000
+-#define BP_ANADIG_PLL_528_RSVD1      19
+-#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
+-#define BF_ANADIG_PLL_528_RSVD1(v)  \
+-       (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
+-#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
+-#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
+-#define BM_ANADIG_PLL_528_BYPASS 0x00010000
+-#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC      14
+-#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
+-#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v)  \
+-       (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
+-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M  0x0
+-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
+-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
+-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR      0x3
+-#define BM_ANADIG_PLL_528_ENABLE 0x00002000
+-#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
+-#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
+-#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
+-#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
+-#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
+-#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
+-#define BP_ANADIG_PLL_528_RSVD0      1
+-#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
+-#define BF_ANADIG_PLL_528_RSVD0(v)  \
+-       (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
+-#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
+-
+-#define BP_ANADIG_PLL_528_SS_STOP      16
+-#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
+-#define BF_ANADIG_PLL_528_SS_STOP(v) \
+-       (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
+-#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
+-#define BP_ANADIG_PLL_528_SS_STEP      0
+-#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
+-#define BF_ANADIG_PLL_528_SS_STEP(v)  \
+-       (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
+-
+-#define BP_ANADIG_PLL_528_NUM_RSVD0      30
+-#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
+-#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
+-       (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
+-#define BP_ANADIG_PLL_528_NUM_A      0
+-#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
+-#define BF_ANADIG_PLL_528_NUM_A(v)  \
+-       (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
+-
+-#define BP_ANADIG_PLL_528_DENOM_RSVD0      30
+-#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
+-#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
+-       (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
+-#define BP_ANADIG_PLL_528_DENOM_B      0
+-#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
+-#define BF_ANADIG_PLL_528_DENOM_B(v)  \
+-       (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
+-
+-#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
+-#define BP_ANADIG_PLL_AUDIO_RSVD0      22
+-#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
+-#define BF_ANADIG_PLL_AUDIO_RSVD0(v)  \
+-       (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
+-#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
+-#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT      19
+-#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
+-#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)  \
+-       (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+-#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
+-#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
+-#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
+-#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC      14
+-#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
+-#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)  \
+-       (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M  0x0
+-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR      0x3
+-#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
+-#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
+-#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
+-#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
+-#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
+-#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
+-#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
+-#define BP_ANADIG_PLL_AUDIO_DIV_SELECT      0
+-#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
+-#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)  \
+-       (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+-
+-#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0      30
+-#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
+-#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
+-       (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
+-#define BP_ANADIG_PLL_AUDIO_NUM_A      0
+-#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
+-#define BF_ANADIG_PLL_AUDIO_NUM_A(v)  \
+-       (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
+-
+-#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0      30
+-#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
+-#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
+-       (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
+-#define BP_ANADIG_PLL_AUDIO_DENOM_B      0
+-#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
+-#define BF_ANADIG_PLL_AUDIO_DENOM_B(v)  \
+-       (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
+-
+-#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
+-#define BP_ANADIG_PLL_VIDEO_RSVD0      22
+-#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
+-#define BF_ANADIG_PLL_VIDEO_RSVD0(v)  \
+-       (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
+-#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
+-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT      19
+-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
+-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v)  \
+-       (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+-#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
+-#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
+-#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
+-#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC      14
+-#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
+-#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)  \
+-       (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M  0x0
+-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR      0x3
+-#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
+-#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
+-#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
+-#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
+-#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
+-#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
+-#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
+-#define BP_ANADIG_PLL_VIDEO_DIV_SELECT      0
+-#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
+-#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)  \
+-       (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+-
+-#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0      30
+-#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
+-#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
+-       (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
+-#define BP_ANADIG_PLL_VIDEO_NUM_A      0
+-#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
+-#define BF_ANADIG_PLL_VIDEO_NUM_A(v)  \
+-       (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
+-
+-#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0      30
+-#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
+-#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
+-       (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
+-#define BP_ANADIG_PLL_VIDEO_DENOM_B      0
+-#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
+-#define BF_ANADIG_PLL_VIDEO_DENOM_B(v)  \
+-       (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
+-
+-#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
+-#define BP_ANADIG_PLL_ENET_RSVD1      21
+-#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
+-#define BF_ANADIG_PLL_ENET_RSVD1(v)  \
+-       (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
+-#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
+-#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
+-#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
+-#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
+-#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
+-#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC      14
+-#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
+-#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)  \
+-       (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M  0x0
+-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR      0x3
+-#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
+-#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
+-#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
+-#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
+-#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
+-#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
+-#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
+-#define BP_ANADIG_PLL_ENET_RSVD0      2
+-#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
+-#define BF_ANADIG_PLL_ENET_RSVD0(v)  \
+-       (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
+-#define BP_ANADIG_PLL_ENET_DIV_SELECT      0
+-#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
+-#define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  \
+-       (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
+-
+-#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
+-#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
+-#define BP_ANADIG_PFD_480_PFD3_FRAC      24
+-#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
+-#define BF_ANADIG_PFD_480_PFD3_FRAC(v)  \
+-       (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
+-#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
+-#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
+-#define BP_ANADIG_PFD_480_PFD2_FRAC      16
+-#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
+-#define BF_ANADIG_PFD_480_PFD2_FRAC(v)  \
+-       (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
+-#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
+-#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
+-#define BP_ANADIG_PFD_480_PFD1_FRAC      8
+-#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
+-#define BF_ANADIG_PFD_480_PFD1_FRAC(v)  \
+-       (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
+-#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
+-#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
+-#define BP_ANADIG_PFD_480_PFD0_FRAC      0
+-#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
+-#define BF_ANADIG_PFD_480_PFD0_FRAC(v)  \
+-       (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
+-
+-#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
+-#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
+-#define BP_ANADIG_PFD_528_PFD3_FRAC      24
+-#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
+-#define BF_ANADIG_PFD_528_PFD3_FRAC(v)  \
+-       (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
+-#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
+-#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
+-#define BP_ANADIG_PFD_528_PFD2_FRAC      16
+-#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
+-#define BF_ANADIG_PFD_528_PFD2_FRAC(v)  \
+-       (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
+-#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
+-#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
+-#define BP_ANADIG_PFD_528_PFD1_FRAC      8
+-#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
+-#define BF_ANADIG_PFD_528_PFD1_FRAC(v)  \
+-       (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
+-#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
+-#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
+-#define BP_ANADIG_PFD_528_PFD0_FRAC      0
+-#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
+-#define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
+-       (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
+-
+-#define PLL2_PFD0_FREQ         352000000
+-#define PLL2_PFD1_FREQ         594000000
+-#define PLL2_PFD2_FREQ         400000000
+-#define PLL2_PFD2_DIV_FREQ     200000000
+-#define PLL3_PFD0_FREQ         720000000
+-#define PLL3_PFD1_FREQ         540000000
+-#define PLL3_PFD2_FREQ         508200000
+-#define PLL3_PFD3_FREQ         454700000
+-#define PLL3_80M               80000000
+-#define PLL3_60M               60000000
+-
+-#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
+diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
+new file mode 100644
+index 0000000..0e605c2
+--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
+@@ -0,0 +1,892 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+
+struct mxc_ccm_reg {
+       u32 ccr;        /* 0x0000 */
+       u32 ccdr;
+       u32 csr;
+       u32 ccsr;
+       u32 cacrr;      /* 0x0010*/
+       u32 cbcdr;
+       u32 cbcmr;
+       u32 cscmr1;
+       u32 cscmr2;     /* 0x0020 */
+       u32 cscdr1;
+       u32 cs1cdr;
+       u32 cs2cdr;
+       u32 cdcdr;      /* 0x0030 */
+       u32 chscdr;
+       u32 cscdr2;
+       u32 cscdr3;
+       u32 cscdr4;     /* 0x0040 */
+       u32 resv0;
+       u32 cdhipr;
+       u32 cdcr;
+       u32 ctor;       /* 0x0050 */
+       u32 clpcr;
+       u32 cisr;
+       u32 cimr;
+       u32 ccosr;      /* 0x0060 */
+       u32 cgpr;
+       u32 CCGR0;
+       u32 CCGR1;
+       u32 CCGR2;      /* 0x0070 */
+       u32 CCGR3;
+       u32 CCGR4;
+       u32 CCGR5;
+       u32 CCGR6;      /* 0x0080 */
+       u32 CCGR7;
+       u32 cmeor;
+       u32 resv[0xfdd];
+       u32 analog_pll_sys;                     /* 0x4000 */
+       u32 analog_pll_sys_set;
+       u32 analog_pll_sys_clr;
+       u32 analog_pll_sys_tog;
+       u32 analog_usb1_pll_480_ctrl;           /* 0x4010 */
+       u32 analog_usb1_pll_480_ctrl_set;
+       u32 analog_usb1_pll_480_ctrl_clr;
+       u32 analog_usb1_pll_480_ctrl_tog;
+       u32 analog_reserved0[4];
+       u32 analog_pll_528;                     /* 0x4030 */
+       u32 analog_pll_528_set;
+       u32 analog_pll_528_clr;
+       u32 analog_pll_528_tog;
+       u32 analog_pll_528_ss;                  /* 0x4040 */
+       u32 analog_reserved1[3];
+       u32 analog_pll_528_num;                 /* 0x4050 */
+       u32 analog_reserved2[3];
+       u32 analog_pll_528_denom;               /* 0x4060 */
+       u32 analog_reserved3[3];
+       u32 analog_pll_audio;                   /* 0x4070 */
+       u32 analog_pll_audio_set;
+       u32 analog_pll_audio_clr;
+       u32 analog_pll_audio_tog;
+       u32 analog_pll_audio_num;               /* 0x4080*/
+       u32 analog_reserved4[3];
+       u32 analog_pll_audio_denom;             /* 0x4090 */
+       u32 analog_reserved5[3];
+       u32 analog_pll_video;                   /* 0x40a0 */
+       u32 analog_pll_video_set;
+       u32 analog_pll_video_clr;
+       u32 analog_pll_video_tog;
+       u32 analog_pll_video_num;               /* 0x40b0 */
+       u32 analog_reserved6[3];
+       u32 analog_pll_vedio_denon;             /* 0x40c0 */
+       u32 analog_reserved7[7];
+       u32 analog_pll_enet;                    /* 0x40e0 */
+       u32 analog_pll_enet_set;
+       u32 analog_pll_enet_clr;
+       u32 analog_pll_enet_tog;
+       u32 analog_pfd_480;                     /* 0x40f0 */
+       u32 analog_pfd_480_set;
+       u32 analog_pfd_480_clr;
+       u32 analog_pfd_480_tog;
+       u32 analog_pfd_528;                     /* 0x4100 */
+       u32 analog_pfd_528_set;
+       u32 analog_pfd_528_clr;
+       u32 analog_pfd_528_tog;
+};
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_RBC_EN                             (1 << 27)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK                        (0x3F << 21)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET              21
+#define MXC_CCM_CCR_WB_COUNT_MASK                      0x7
+#define MXC_CCM_CCR_WB_COUNT_OFFSET                    (1 << 16)
+#define MXC_CCM_CCR_COSC_EN                            (1 << 12)
+#define MXC_CCM_CCR_OSCNT_MASK                         0xFF
+#define MXC_CCM_CCR_OSCNT_OFFSET                       0
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK                  (1 << 16)
+#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK                  (1 << 17)
+
+/* Define the bits in register CSR */
+#define MXC_CCM_CSR_COSC_READY                         (1 << 5)
+#define MXC_CCM_CSR_REF_EN_B                           (1 << 0)
+
+/* Define the bits in register CCSR */
+#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS                 (1 << 15)
+#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS                 (1 << 14)
+#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS                 (1 << 13)
+#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS                 (1 << 12)
+#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS                 (1 << 11)
+#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS                 (1 << 10)
+#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS                 (1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL                          (1 << 8)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL                   (1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL                   (1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL                   (1 << 0)
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET                  0
+#define MXC_CCM_CACRR_ARM_PODF_MASK                    0x7
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK            (0x7 << 27)
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET          27
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL                 (1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL                   (1 << 25)
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK               (0x7 << 19)
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET             19
+#define MXC_CCM_CBCDR_AXI_PODF_MASK                    (0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_PODF_OFFSET                  16
+#define MXC_CCM_CBCDR_AHB_PODF_MASK                    (0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET                  10
+#define MXC_CCM_CBCDR_IPG_PODF_MASK                    (0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET                  8
+#define MXC_CCM_CBCDR_AXI_ALT_SEL                      (1 << 7)
+#define MXC_CCM_CBCDR_AXI_SEL                          (1 << 6)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK               (0x7 << 3)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET             3
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK           (0x7 << 0)
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET         0
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK           (0x7 << 29)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET         29
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK             (0x7 << 26)
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET           26
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK             (0x7 << 23)
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET           23
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK         (0x3 << 21)
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET       21
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL             (1 << 20)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK          (0x3 << 18)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET                18
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK               (0x3 << 16)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET             16
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK             (0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET           14
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK             (0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET           12
+#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL                   (1 << 11)
+#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL                 (1 << 10)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK                (0x3 << 8)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET      8
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK          (0x3 << 4)
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET                4
+#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL                        (1 << 1)
+#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL                        (1 << 0)
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK              (0x3 << 29)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET            29
+#define MXC_CCM_CSCMR1_ACLK_EMI_MASK                   (0x3 << 27)
+#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET                 27
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK         (0x7 << 23)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET       23
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK              (0x7 << 20)
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET            20
+#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL                  (1 << 19)
+#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL                  (1 << 18)
+#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL                  (1 << 17)
+#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL                  (1 << 16)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK               (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET             14
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK               (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET             12
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK               (0x3 << 10)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET             10
+#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                        0x3F
+
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK               (0x3 << 19)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET             19
+#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV                 (1 << 11)
+#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV                 (1 << 10)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                        (0x3F << 2)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET              2
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK               (0x7 << 25)
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET             25
+#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK                        (0x7 << 22)
+#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET              22
+#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK                        (0x7 << 19)
+#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET              19
+#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK                        (0x7 << 16)
+#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET              16
+#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK                        (0x7 << 11)
+#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET              11
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET          8
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK            (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET          6
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK            (0x3 << 6)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              0x3F
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET            0
+
+/* Define the bits in register CS1CDR */
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK              (0x3F << 25)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET            25
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK              (0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET            16
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK              (0x3 << 9)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET            9
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET            6
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK              0x3F
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET            0
+
+/* Define the bits in register CS2CDR */
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK              (0x3F << 21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET            21
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK              (0x7 << 18)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET            18
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK               (0x3 << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET             16
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK            (0x7 << 12)
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET          12
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK            (0x7 << 9)
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET          9
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET            6
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK              0x3F
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET            0
+
+/* Define the bits in register CDCDR */
+#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK                 (0x7 << 29)
+#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET               29
+#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL                   (1 << 28)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK             (0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET           25
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK             (0x7 << 19)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET           19
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK              (0x3 << 20)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET            20
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK             (0x7 << 12)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET           12
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK             (0x7 << 9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET           9
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK              (0x3 << 7)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET            7
+
+/* Define the bits in register CHSCCDR */
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK      (0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET    15
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK             (0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET           12
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK          (0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET                9
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK      (0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET    6
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK             (0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET           3
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK          (0x7)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET                0
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK             (0x3F << 19)
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET           19
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK      (0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET    15
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK             (0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET           12
+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK          (0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET                9
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK      (0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET    6
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK             (0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET           3
+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK          0x7
+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET                0
+
+/* Define the bits in register CSCDR3 */
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK              (0x7 << 16)
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET            16
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK           (0x3 << 14)
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET         14
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK              (0x7 << 11)
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET            11
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK           (0x3 << 9)
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET         9
+
+/* Define the bits in register CDHIPR */
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY                   (1 << 16)
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY             (1 << 5)
+#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY              (1 << 4)
+#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY            (1 << 3)
+#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY              (1 << 2)
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY                   (1 << 1)
+#define MXC_CCM_CDHIPR_AXI_PODF_BUSY                   1
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_MASK_L2CC_IDLE                   (1 << 27)
+#define MXC_CCM_CLPCR_MASK_SCU_IDLE                    (1 << 26)
+#define MXC_CCM_CLPCR_MASK_CORE3_WFI                   (1 << 25)
+#define MXC_CCM_CLPCR_MASK_CORE2_WFI                   (1 << 24)
+#define MXC_CCM_CLPCR_MASK_CORE1_WFI                   (1 << 23)
+#define MXC_CCM_CLPCR_MASK_CORE0_WFI                   (1 << 22)
+#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS              (1 << 21)
+#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS              (1 << 19)
+#define MXC_CCM_CLPCR_WB_CORE_AT_LPM                   (1 << 17)
+#define MXC_CCM_CLPCR_WB_PER_AT_LPM                    (1 << 17)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN                     (1 << 11)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK                  (0x3 << 9)
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET                        9
+#define MXC_CCM_CLPCR_VSTBY                            (1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC                      (1 << 7)
+#define MXC_CCM_CLPCR_SBYOS                            (1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM               (1 << 5)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                        (0x3 << 3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET              3
+#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY          (1 << 2)
+#define MXC_CCM_CLPCR_LPM_MASK                         0x3
+#define MXC_CCM_CLPCR_LPM_OFFSET                       0
+
+/* Define the bits in register CISR */
+#define MXC_CCM_CISR_ARM_PODF_LOADED                   (1 << 26)
+#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED              (1 << 23)
+#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED             (1 << 22)
+#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED              (1 << 21)
+#define MXC_CCM_CISR_AHB_PODF_LOADED                   (1 << 20)
+#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED            (1 << 19)
+#define MXC_CCM_CISR_AXI_PODF_LOADED                   (1 << 17)
+#define MXC_CCM_CISR_COSC_READY                                (1 << 6)
+#define MXC_CCM_CISR_LRF_PLL                           1
+
+/* Define the bits in register CIMR */
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED              (1 << 26)
+#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED         (1 << 23)
+#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED                (1 << 22)
+#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED         (1 << 21)
+#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED              (1 << 20)
+#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED       (1 << 22)
+#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED              (1 << 17)
+#define MXC_CCM_CIMR_MASK_COSC_READY                   (1 << 6)
+#define MXC_CCM_CIMR_MASK_LRF_PLL                      1
+
+/* Define the bits in register CCOSR */
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET                   (1 << 24)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK                    (0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                  21
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                  16
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK                    (0x1F << 16)
+#define MXC_CCM_CCOSR_CKOL_EN                          (0x1 << 7)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK                    (0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                  4
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK                    0xF
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                  0
+
+/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE            (1 << 4)
+#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS                  (1 << 2)
+#define MXC_CCM_CGPR_PMIC_DELAY_SCALER                 1
+
+/* Define the bits in registers CCGRx */
+#define MXC_CCM_CCGR_CG_MASK                           3
+
+#define MXC_CCM_CCGR0_CG15_OFFSET                      30
+#define MXC_CCM_CCGR0_CG15_MASK                        (0x3 << 30)
+#define MXC_CCM_CCGR0_CG14_OFFSET                      28
+#define MXC_CCM_CCGR0_CG14_MASK                        (0x3 << 28)
+#define MXC_CCM_CCGR0_CG13_OFFSET                      26
+#define MXC_CCM_CCGR0_CG13_MASK                        (0x3 << 26)
+#define MXC_CCM_CCGR0_CG12_OFFSET                      24
+#define MXC_CCM_CCGR0_CG12_MASK                        (0x3 << 24)
+#define MXC_CCM_CCGR0_CG11_OFFSET                      22
+#define MXC_CCM_CCGR0_CG11_MASK                        (0x3 << 22)
+#define MXC_CCM_CCGR0_CG10_OFFSET                      20
+#define MXC_CCM_CCGR0_CG10_MASK                        (0x3 << 20)
+#define MXC_CCM_CCGR0_CG9_OFFSET                       18
+#define MXC_CCM_CCGR0_CG9_MASK                 (0x3 << 18)
+#define MXC_CCM_CCGR0_CG8_OFFSET                       16
+#define MXC_CCM_CCGR0_CG8_MASK                 (0x3 << 16)
+#define MXC_CCM_CCGR0_CG7_OFFSET                       14
+#define MXC_CCM_CCGR0_CG6_OFFSET                       12
+#define MXC_CCM_CCGR0_CG5_OFFSET                       10
+#define MXC_CCM_CCGR0_CG5_MASK                 (0x3 << 10)
+#define MXC_CCM_CCGR0_CG4_OFFSET                       8
+#define MXC_CCM_CCGR0_CG4_MASK                 (0x3 << 8)
+#define MXC_CCM_CCGR0_CG3_OFFSET                       6
+#define MXC_CCM_CCGR0_CG3_MASK                 (0x3 << 6)
+#define MXC_CCM_CCGR0_CG2_OFFSET                       4
+#define MXC_CCM_CCGR0_CG2_MASK                 (0x3 << 4)
+#define MXC_CCM_CCGR0_CG1_OFFSET                       2
+#define MXC_CCM_CCGR0_CG1_MASK                 (0x3 << 2)
+#define MXC_CCM_CCGR0_CG0_OFFSET                       0
+#define MXC_CCM_CCGR0_CG0_MASK                         3
+
+#define MXC_CCM_CCGR1_CG15_OFFSET                      30
+#define MXC_CCM_CCGR1_CG14_OFFSET                      28
+#define MXC_CCM_CCGR1_CG13_OFFSET                      26
+#define MXC_CCM_CCGR1_CG12_OFFSET                      24
+#define MXC_CCM_CCGR1_CG11_OFFSET                      22
+#define MXC_CCM_CCGR1_CG10_OFFSET                      20
+#define MXC_CCM_CCGR1_CG9_OFFSET                       18
+#define MXC_CCM_CCGR1_CG8_OFFSET                       16
+#define MXC_CCM_CCGR1_CG7_OFFSET                       14
+#define MXC_CCM_CCGR1_CG6_OFFSET                       12
+#define MXC_CCM_CCGR1_CG5_OFFSET                       10
+#define MXC_CCM_CCGR1_CG4_OFFSET                       8
+#define MXC_CCM_CCGR1_CG3_OFFSET                       6
+#define MXC_CCM_CCGR1_CG2_OFFSET                       4
+#define MXC_CCM_CCGR1_CG1_OFFSET                       2
+#define MXC_CCM_CCGR1_CG0_OFFSET                       0
+
+#define MXC_CCM_CCGR2_CG15_OFFSET                      30
+#define MXC_CCM_CCGR2_CG14_OFFSET                      28
+#define MXC_CCM_CCGR2_CG13_OFFSET                      26
+#define MXC_CCM_CCGR2_CG12_OFFSET                      24
+#define MXC_CCM_CCGR2_CG11_OFFSET                      22
+#define MXC_CCM_CCGR2_CG10_OFFSET                      20
+#define MXC_CCM_CCGR2_CG9_OFFSET                       18
+#define MXC_CCM_CCGR2_CG8_OFFSET                       16
+#define MXC_CCM_CCGR2_CG7_OFFSET                       14
+#define MXC_CCM_CCGR2_CG6_OFFSET                       12
+#define MXC_CCM_CCGR2_CG5_OFFSET                       10
+#define MXC_CCM_CCGR2_CG4_OFFSET                       8
+#define MXC_CCM_CCGR2_CG3_OFFSET                       6
+#define MXC_CCM_CCGR2_CG2_OFFSET                       4
+#define MXC_CCM_CCGR2_CG1_OFFSET                       2
+#define MXC_CCM_CCGR2_CG0_OFFSET                       0
+
+#define MXC_CCM_CCGR3_CG15_OFFSET                      30
+#define MXC_CCM_CCGR3_CG14_OFFSET                      28
+#define MXC_CCM_CCGR3_CG13_OFFSET                      26
+#define MXC_CCM_CCGR3_CG12_OFFSET                      24
+#define MXC_CCM_CCGR3_CG11_OFFSET                      22
+#define MXC_CCM_CCGR3_CG10_OFFSET                      20
+#define MXC_CCM_CCGR3_CG9_OFFSET                       18
+#define MXC_CCM_CCGR3_CG8_OFFSET                       16
+#define MXC_CCM_CCGR3_CG7_OFFSET                       14
+#define MXC_CCM_CCGR3_CG6_OFFSET                       12
+#define MXC_CCM_CCGR3_CG5_OFFSET                       10
+#define MXC_CCM_CCGR3_CG4_OFFSET                       8
+#define MXC_CCM_CCGR3_CG3_OFFSET                       6
+#define MXC_CCM_CCGR3_CG2_OFFSET                       4
+#define MXC_CCM_CCGR3_CG1_OFFSET                       2
+#define MXC_CCM_CCGR3_CG0_OFFSET                       0
+
+#define MXC_CCM_CCGR4_CG15_OFFSET                      30
+#define MXC_CCM_CCGR4_CG14_OFFSET                      28
+#define MXC_CCM_CCGR4_CG13_OFFSET                      26
+#define MXC_CCM_CCGR4_CG12_OFFSET                      24
+#define MXC_CCM_CCGR4_CG11_OFFSET                      22
+#define MXC_CCM_CCGR4_CG10_OFFSET                      20
+#define MXC_CCM_CCGR4_CG9_OFFSET                       18
+#define MXC_CCM_CCGR4_CG8_OFFSET                       16
+#define MXC_CCM_CCGR4_CG7_OFFSET                       14
+#define MXC_CCM_CCGR4_CG6_OFFSET                       12
+#define MXC_CCM_CCGR4_CG5_OFFSET                       10
+#define MXC_CCM_CCGR4_CG4_OFFSET                       8
+#define MXC_CCM_CCGR4_CG3_OFFSET                       6
+#define MXC_CCM_CCGR4_CG2_OFFSET                       4
+#define MXC_CCM_CCGR4_CG1_OFFSET                       2
+#define MXC_CCM_CCGR4_CG0_OFFSET                       0
+
+#define MXC_CCM_CCGR5_CG15_OFFSET                      30
+#define MXC_CCM_CCGR5_CG14_OFFSET                      28
+#define MXC_CCM_CCGR5_CG14_MASK                        (0x3 << 28)
+#define MXC_CCM_CCGR5_CG13_OFFSET                      26
+#define MXC_CCM_CCGR5_CG13_MASK                        (0x3 << 26)
+#define MXC_CCM_CCGR5_CG12_OFFSET                      24
+#define MXC_CCM_CCGR5_CG12_MASK                        (0x3 << 24)
+#define MXC_CCM_CCGR5_CG11_OFFSET                      22
+#define MXC_CCM_CCGR5_CG11_MASK                        (0x3 << 22)
+#define MXC_CCM_CCGR5_CG10_OFFSET                      20
+#define MXC_CCM_CCGR5_CG10_MASK                        (0x3 << 20)
+#define MXC_CCM_CCGR5_CG9_OFFSET                       18
+#define MXC_CCM_CCGR5_CG9_MASK                 (0x3 << 18)
+#define MXC_CCM_CCGR5_CG8_OFFSET                       16
+#define MXC_CCM_CCGR5_CG8_MASK                 (0x3 << 16)
+#define MXC_CCM_CCGR5_CG7_OFFSET                       14
+#define MXC_CCM_CCGR5_CG7_MASK                 (0x3 << 14)
+#define MXC_CCM_CCGR5_CG6_OFFSET                       12
+#define MXC_CCM_CCGR5_CG6_MASK                 (0x3 << 12)
+#define MXC_CCM_CCGR5_CG5_OFFSET                       10
+#define MXC_CCM_CCGR5_CG4_OFFSET                       8
+#define MXC_CCM_CCGR5_CG3_OFFSET                       6
+#define MXC_CCM_CCGR5_CG2_OFFSET                       4
+#define MXC_CCM_CCGR5_CG2_MASK                 (0x3 << 4)
+#define MXC_CCM_CCGR5_CG1_OFFSET                       2
+#define MXC_CCM_CCGR5_CG0_OFFSET                       0
+
+#define MXC_CCM_CCGR6_CG15_OFFSET                      30
+#define MXC_CCM_CCGR6_CG14_OFFSET                      28
+#define MXC_CCM_CCGR6_CG14_MASK                        (0x3 << 28)
+#define MXC_CCM_CCGR6_CG13_OFFSET                      26
+#define MXC_CCM_CCGR6_CG13_MASK                        (0x3 << 26)
+#define MXC_CCM_CCGR6_CG12_OFFSET                      24
+#define MXC_CCM_CCGR6_CG12_MASK                        (0x3 << 24)
+#define MXC_CCM_CCGR6_CG11_OFFSET                      22
+#define MXC_CCM_CCGR6_CG11_MASK                        (0x3 << 22)
+#define MXC_CCM_CCGR6_CG10_OFFSET                      20
+#define MXC_CCM_CCGR6_CG10_MASK                        (0x3 << 20)
+#define MXC_CCM_CCGR6_CG9_OFFSET                       18
+#define MXC_CCM_CCGR6_CG9_MASK                 (0x3 << 18)
+#define MXC_CCM_CCGR6_CG8_OFFSET                       16
+#define MXC_CCM_CCGR6_CG8_MASK                 (0x3 << 16)
+#define MXC_CCM_CCGR6_CG7_OFFSET                       14
+#define MXC_CCM_CCGR6_CG7_MASK                 (0x3 << 14)
+#define MXC_CCM_CCGR6_CG6_OFFSET                       12
+#define MXC_CCM_CCGR6_CG6_MASK                 (0x3 << 12)
+#define MXC_CCM_CCGR6_CG5_OFFSET                       10
+#define MXC_CCM_CCGR6_CG4_OFFSET                       8
+#define MXC_CCM_CCGR6_CG3_OFFSET                       6
+#define MXC_CCM_CCGR6_CG2_OFFSET                       4
+#define MXC_CCM_CCGR6_CG2_MASK                 (0x3 << 4)
+#define MXC_CCM_CCGR6_CG1_OFFSET                       2
+#define MXC_CCM_CCGR6_CG0_OFFSET                       0
+
+#define MXC_CCM_CCGR7_CG15_OFFSET                      30
+#define MXC_CCM_CCGR7_CG14_OFFSET                      28
+#define MXC_CCM_CCGR7_CG14_MASK                        (0x3 << 28)
+#define MXC_CCM_CCGR7_CG13_OFFSET                      26
+#define MXC_CCM_CCGR7_CG13_MASK                        (0x3 << 26)
+#define MXC_CCM_CCGR7_CG12_OFFSET                      24
+#define MXC_CCM_CCGR7_CG12_MASK                        (0x3 << 24)
+#define MXC_CCM_CCGR7_CG11_OFFSET                      22
+#define MXC_CCM_CCGR7_CG11_MASK                        (0x3 << 22)
+#define MXC_CCM_CCGR7_CG10_OFFSET                      20
+#define MXC_CCM_CCGR7_CG10_MASK                        (0x3 << 20)
+#define MXC_CCM_CCGR7_CG9_OFFSET                       18
+#define MXC_CCM_CCGR7_CG9_MASK                 (0x3 << 18)
+#define MXC_CCM_CCGR7_CG8_OFFSET                       16
+#define MXC_CCM_CCGR7_CG8_MASK                 (0x3 << 16)
+#define MXC_CCM_CCGR7_CG7_OFFSET                       14
+#define MXC_CCM_CCGR7_CG7_MASK                 (0x3 << 14)
+#define MXC_CCM_CCGR7_CG6_OFFSET                       12
+#define MXC_CCM_CCGR7_CG6_MASK                 (0x3 << 12)
+#define MXC_CCM_CCGR7_CG5_OFFSET                       10
+#define MXC_CCM_CCGR7_CG4_OFFSET                       8
+#define MXC_CCM_CCGR7_CG3_OFFSET                       6
+#define MXC_CCM_CCGR7_CG2_OFFSET                       4
+#define MXC_CCM_CCGR7_CG2_MASK                 (0x3 << 4)
+#define MXC_CCM_CCGR7_CG1_OFFSET                       2
+#define MXC_CCM_CCGR7_CG0_OFFSET                       0
+#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
+#define BP_ANADIG_PLL_SYS_RSVD0      20
+#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
+#define BF_ANADIG_PLL_SYS_RSVD0(v)  \
+       (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
+#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
+#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
+#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
+#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
+#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v)  \
+       (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
+#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_SYS_DIV_SELECT      0
+#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_SYS_DIV_SELECT(v)  \
+       (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
+
+#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
+#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1      17
+#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
+#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v)  \
+       (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
+#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC      14
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v)  \
+       (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
+#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
+#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
+#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
+#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
+#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0      2
+#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
+#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v)  \
+       (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT      0
+#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
+#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v)  \
+       (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+
+#define BM_ANADIG_PLL_528_LOCK 0x80000000
+#define BP_ANADIG_PLL_528_RSVD1      19
+#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
+#define BF_ANADIG_PLL_528_RSVD1(v)  \
+       (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
+#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_528_BYPASS 0x00010000
+#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v)  \
+       (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_528_ENABLE 0x00002000
+#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_528_RSVD0      1
+#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
+#define BF_ANADIG_PLL_528_RSVD0(v)  \
+       (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
+#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
+
+#define BP_ANADIG_PLL_528_SS_STOP      16
+#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
+#define BF_ANADIG_PLL_528_SS_STOP(v) \
+       (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
+#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
+#define BP_ANADIG_PLL_528_SS_STEP      0
+#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
+#define BF_ANADIG_PLL_528_SS_STEP(v)  \
+       (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
+
+#define BP_ANADIG_PLL_528_NUM_RSVD0      30
+#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
+       (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
+#define BP_ANADIG_PLL_528_NUM_A      0
+#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_528_NUM_A(v)  \
+       (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
+
+#define BP_ANADIG_PLL_528_DENOM_RSVD0      30
+#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
+       (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
+#define BP_ANADIG_PLL_528_DENOM_B      0
+#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_528_DENOM_B(v)  \
+       (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
+
+#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
+#define BP_ANADIG_PLL_AUDIO_RSVD0      22
+#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
+#define BF_ANADIG_PLL_AUDIO_RSVD0(v)  \
+       (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
+#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
+#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT      19
+#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)  \
+       (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)  \
+       (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
+#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT      0
+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)  \
+       (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0      30
+#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
+       (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
+#define BP_ANADIG_PLL_AUDIO_NUM_A      0
+#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_NUM_A(v)  \
+       (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
+
+#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0      30
+#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
+       (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
+#define BP_ANADIG_PLL_AUDIO_DENOM_B      0
+#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_DENOM_B(v)  \
+       (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
+
+#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
+#define BP_ANADIG_PLL_VIDEO_RSVD0      22
+#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
+#define BF_ANADIG_PLL_VIDEO_RSVD0(v)  \
+       (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
+#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
+#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT      19
+#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v)  \
+       (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)  \
+       (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
+#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT      0
+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)  \
+       (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0      30
+#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
+       (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
+#define BP_ANADIG_PLL_VIDEO_NUM_A      0
+#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_VIDEO_NUM_A(v)  \
+       (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
+
+#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0      30
+#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
+       (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
+#define BP_ANADIG_PLL_VIDEO_DENOM_B      0
+#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_VIDEO_DENOM_B(v)  \
+       (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
+
+#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
+#define BP_ANADIG_PLL_ENET_RSVD1      21
+#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
+#define BF_ANADIG_PLL_ENET_RSVD1(v)  \
+       (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
+#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)  \
+       (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
+#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_ENET_RSVD0      2
+#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
+#define BF_ANADIG_PLL_ENET_RSVD0(v)  \
+       (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
+#define BP_ANADIG_PLL_ENET_DIV_SELECT      0
+#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
+#define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  \
+       (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
+
+#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
+#define BP_ANADIG_PFD_480_PFD3_FRAC      24
+#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_480_PFD3_FRAC(v)  \
+       (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
+#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
+#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
+#define BP_ANADIG_PFD_480_PFD2_FRAC      16
+#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
+#define BF_ANADIG_PFD_480_PFD2_FRAC(v)  \
+       (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
+#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
+#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
+#define BP_ANADIG_PFD_480_PFD1_FRAC      8
+#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
+#define BF_ANADIG_PFD_480_PFD1_FRAC(v)  \
+       (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
+#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
+#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
+#define BP_ANADIG_PFD_480_PFD0_FRAC      0
+#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
+#define BF_ANADIG_PFD_480_PFD0_FRAC(v)  \
+       (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
+
+#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
+#define BP_ANADIG_PFD_528_PFD3_FRAC      24
+#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_528_PFD3_FRAC(v)  \
+       (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
+#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
+#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
+#define BP_ANADIG_PFD_528_PFD2_FRAC      16
+#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
+#define BF_ANADIG_PFD_528_PFD2_FRAC(v)  \
+       (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
+#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
+#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
+#define BP_ANADIG_PFD_528_PFD1_FRAC      8
+#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
+#define BF_ANADIG_PFD_528_PFD1_FRAC(v)  \
+       (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
+#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
+#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
+#define BP_ANADIG_PFD_528_PFD0_FRAC      0
+#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
+#define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
+       (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
+
+#define PLL2_PFD0_FREQ         352000000
+#define PLL2_PFD1_FREQ         594000000
+#define PLL2_PFD2_FREQ         400000000
+#define PLL2_PFD2_DIV_FREQ     200000000
+#define PLL3_PFD0_FREQ         720000000
+#define PLL3_PFD1_FREQ         540000000
+#define PLL3_PFD2_FREQ         508200000
+#define PLL3_PFD3_FREQ         454700000
+#define PLL3_80M               80000000
+#define PLL3_60M               60000000
+
+#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
+diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
+index 668e77a..69687a8 100644
+--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
+@@ -34,5 +34,6 @@ u32 get_cpu_rev(void);
+  */
+ 
+ int fecmxc_initialize(bd_t *bis);
+-
+u32 get_ahb_clk(void);
+u32 get_periph_clk(void);
+ #endif
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0017-mx5-Add-clock-config-interface.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0017-mx5-Add-clock-config-interface.patch
new file mode 100644
index 000000000..a99550219
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0017-mx5-Add-clock-config-interface.patch
@@ -0,0 +1,574 @@
+From a835391f8dddc9ca51c880e5328979577cb0685d Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <festevam@gmail.com>
+Date: Mon, 30 Apr 2012 08:12:02 +0000
+Subject: [PATCH 17/56] mx5: Add clock config interface
+mx5: Add clock config interface
+Add clock config interface support, so that we
+can configure CPU or DDR clock in the later init
+Signed-off-by: Jason Liu <jason.hui@linaro.org>
+Signed-off-by: Eric Miao <eric.miao@linaro.org>
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ arch/arm/cpu/armv7/mx5/clock.c           |  448 +++++++++++++++++++++++++++++-
+ arch/arm/include/asm/arch-mx5/clock.h    |    5 +-
+ arch/arm/include/asm/arch-mx5/crm_regs.h |    6 +
+ 3 files changed, 454 insertions(+), 5 deletions(-)
+diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
+index 903e207..fc2406b 100644
+--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
+@@ -49,6 +49,42 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
+ #endif
+ };
+ 
+#define AHB_CLK_ROOT    133333333
+#define SZ_DEC_1M       1000000
+#define PLL_PD_MAX      16      /* Actual pd+1 */
+#define PLL_MFI_MAX     15
+#define PLL_MFI_MIN     5
+#define ARM_DIV_MAX     8
+#define IPG_DIV_MAX     4
+#define AHB_DIV_MAX     8
+#define EMI_DIV_MAX     8
+#define NFC_DIV_MAX     8
+
+#define MX5_CBCMR      0x00015154
+#define MX5_CBCDR      0x02888945
+
+struct fixed_pll_mfd {
+       u32 ref_clk_hz;
+       u32 mfd;
+};
+
+const struct fixed_pll_mfd fixed_mfd[] = {
+       {CONFIG_SYS_MX5_HCLK, 24 * 16},
+};
+
+struct pll_param {
+       u32 pd;
+       u32 mfi;
+       u32 mfn;
+       u32 mfd;
+};
+
+#define PLL_FREQ_MAX(ref_clk)  (4 * (ref_clk) * PLL_MFI_MAX)
+#define PLL_FREQ_MIN(ref_clk) \
+               ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+#define MAX_DDR_CLK     420000000
+#define NFC_CLK_MAX     34000000
+
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ 
+ void set_usboh3_clk(void)
+@@ -291,7 +327,7 @@ static u32 get_uart_clk(void)
+ /*
+  * This function returns the low power audio clock.
+  */
+-u32 get_lp_apm(void)
+static u32 get_lp_apm(void)
+ {
+        u32 ret_val = 0;
+        u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+@@ -307,7 +343,7 @@ u32 get_lp_apm(void)
+ /*
+  * get cspi clock rate.
+  */
+-u32 imx_get_cspiclk(void)
+static u32 imx_get_cspiclk(void)
+ {
+        u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+        u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
+@@ -344,8 +380,77 @@ u32 imx_get_cspiclk(void)
+        return ret_val;
+ }
+ 
+static u32 get_axi_a_clk(void)
+{
+       u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
+       u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
+                       >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
+
+       return  get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_axi_b_clk(void)
+{
+       u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
+       u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
+                       >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
+
+       return  get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_emi_slow_clk(void)
+{
+       u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+       u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
+       u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
+                       >> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+
+       if (emi_clk_sel)
+               return  get_ahb_clk() / (pdf + 1);
+
+       return  get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_ddr_clk(void)
+{
+       u32 ret_val = 0;
+       u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
+       u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
+                               >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+#ifdef CONFIG_MX51
+       u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+       if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
+               u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
+                                       MXC_CCM_CBCDR_DDR_PODF_OFFSET;
+
+               ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+               ret_val /= ddr_clk_podf + 1;
+
+               return ret_val;
+       }
+#endif
+       switch (ddr_clk_sel) {
+       case 0:
+               ret_val = get_axi_a_clk();
+               break;
+       case 1:
+               ret_val = get_axi_b_clk();
+               break;
+       case 2:
+               ret_val = get_emi_slow_clk();
+               break;
+       case 3:
+               ret_val = get_ahb_clk();
+               break;
+       default:
+               break;
+       }
+
+       return ret_val;
+}
+
+ /*
+- * The API of get mxc clockes.
+ * The API of get mxc clocks.
+  */
+ unsigned int mxc_get_clock(enum mxc_clock clk)
+ {
+@@ -367,10 +472,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
+                                    CONFIG_SYS_MX5_HCLK);
+        case MXC_SATA_CLK:
+                return get_ahb_clk();
+       case MXC_DDR_CLK:
+               return get_ddr_clk();
+        default:
+                break;
+        }
+-       return -1;
+       return -EINVAL;
+ }
+ 
+ u32 imx_get_uartclk(void)
+@@ -384,6 +491,338 @@ u32 imx_get_fecclk(void)
+        return mxc_get_clock(MXC_IPG_CLK);
+ }
+ 
+static int gcd(int m, int n)
+{
+       int t;
+       while (m > 0) {
+               if (n > m) {
+                       t = m;
+                       m = n;
+                       n = t;
+               } /* swap */
+               m -= n;
+       }
+       return n;
+}
+
+/*
+ * This is to calculate various parameters based on reference clock and
+ * targeted clock based on the equation:
+ *      t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
+ * This calculation is based on a fixed MFD value for simplicity.
+ */
+static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
+{
+       u64 pd, mfi = 1, mfn, mfd, t1;
+       u32 n_target = target;
+       u32 n_ref = ref, i;
+
+       /*
+        * Make sure targeted freq is in the valid range.
+        * Otherwise the following calculation might be wrong!!!
+        */
+       if (n_target < PLL_FREQ_MIN(ref) ||
+               n_target > PLL_FREQ_MAX(ref)) {
+               printf("Targeted peripheral clock should be"
+                       "within [%d - %d]\n",
+                       PLL_FREQ_MIN(ref) / SZ_DEC_1M,
+                       PLL_FREQ_MAX(ref) / SZ_DEC_1M);
+               return -EINVAL;
+       }
+
+       for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
+               if (fixed_mfd[i].ref_clk_hz == ref) {
+                       mfd = fixed_mfd[i].mfd;
+                       break;
+               }
+       }
+
+       if (i == ARRAY_SIZE(fixed_mfd))
+               return -EINVAL;
+
+       /* Use n_target and n_ref to avoid overflow */
+       for (pd = 1; pd <= PLL_PD_MAX; pd++) {
+               t1 = n_target * pd;
+               do_div(t1, (4 * n_ref));
+               mfi = t1;
+               if (mfi > PLL_MFI_MAX)
+                       return -EINVAL;
+               else if (mfi < 5)
+                       continue;
+               break;
+       }
+       /*
+        * Now got pd and mfi already
+        *
+        * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
+        */
+       t1 = n_target * pd;
+       do_div(t1, 4);
+       t1 -= n_ref * mfi;
+       t1 *= mfd;
+       do_div(t1, n_ref);
+       mfn = t1;
+       debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
+               ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
+       i = 1;
+       if (mfn != 0)
+               i = gcd(mfd, mfn);
+       pll->pd = (u32)pd;
+       pll->mfi = (u32)mfi;
+       do_div(mfn, i);
+       pll->mfn = (u32)mfn;
+       do_div(mfd, i);
+       pll->mfd = (u32)mfd;
+
+       return 0;
+}
+
+#define calc_div(tgt_clk, src_clk, limit) ({           \
+               u32 v = 0;                              \
+               if (((src_clk) % (tgt_clk)) <= 100)     \
+                       v = (src_clk) / (tgt_clk);      \
+               else                                    \
+                       v = ((src_clk) / (tgt_clk)) + 1;\
+               if (v > limit)                          \
+                       v = limit;                      \
+               (v - 1);                                \
+       })
+
+#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
+       {       \
+               __raw_writel(0x1232, &pll->ctrl);               \
+               __raw_writel(0x2, &pll->config);                \
+               __raw_writel((((pd) - 1) << 0) | ((fi) << 4),   \
+                       &pll->op);                              \
+               __raw_writel(fn, &(pll->mfn));                  \
+               __raw_writel((fd) - 1, &pll->mfd);              \
+               __raw_writel((((pd) - 1) << 0) | ((fi) << 4),   \
+                       &pll->hfs_op);                          \
+               __raw_writel(fn, &pll->hfs_mfn);                \
+               __raw_writel((fd) - 1, &pll->hfs_mfd);          \
+               __raw_writel(0x1232, &pll->ctrl);               \
+               while (!__raw_readl(&pll->ctrl) & 0x1)          \
+                       ;\
+       }
+
+static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
+{
+       u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+       struct mxc_pll_reg *pll = mxc_plls[index];
+
+       switch (index) {
+       case PLL1_CLOCK:
+               /* Switch ARM to PLL2 clock */
+               __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
+               CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+                                       pll_param->mfi, pll_param->mfn,
+                                       pll_param->mfd);
+               /* Switch back */
+               __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
+               break;
+       case PLL2_CLOCK:
+               /* Switch to pll2 bypass clock */
+               __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
+               CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+                                       pll_param->mfi, pll_param->mfn,
+                                       pll_param->mfd);
+               /* Switch back */
+               __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
+               break;
+       case PLL3_CLOCK:
+               /* Switch to pll3 bypass clock */
+               __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
+               CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+                                       pll_param->mfi, pll_param->mfn,
+                                       pll_param->mfd);
+               /* Switch back */
+               __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
+               break;
+       case PLL4_CLOCK:
+               /* Switch to pll4 bypass clock */
+               __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
+               CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+                                       pll_param->mfi, pll_param->mfn,
+                                       pll_param->mfd);
+               /* Switch back */
+               __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+/* Config CPU clock */
+static int config_core_clk(u32 ref, u32 freq)
+{
+       int ret = 0;
+       struct pll_param pll_param;
+
+       memset(&pll_param, 0, sizeof(struct pll_param));
+
+       /* The case that periph uses PLL1 is not considered here */
+       ret = calc_pll_params(ref, freq, &pll_param);
+       if (ret != 0) {
+               printf("Error:Can't find pll parameters: %d\n", ret);
+               return ret;
+       }
+
+       return config_pll_clk(PLL1_CLOCK, &pll_param);
+}
+
+static int config_nfc_clk(u32 nfc_clk)
+{
+       u32 reg;
+       u32 parent_rate = get_emi_slow_clk();
+       u32 div = parent_rate / nfc_clk;
+
+       if (nfc_clk <= 0)
+               return -EINVAL;
+       if (div == 0)
+               div++;
+       if (parent_rate / div > NFC_CLK_MAX)
+               div++;
+       reg = __raw_readl(&mxc_ccm->cbcdr);
+       reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
+       reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+       __raw_writel(reg, &mxc_ccm->cbcdr);
+       while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+               ;
+       return 0;
+}
+
+/* Config main_bus_clock for periphs */
+static int config_periph_clk(u32 ref, u32 freq)
+{
+       int ret = 0;
+       struct pll_param pll_param;
+
+       memset(&pll_param, 0, sizeof(struct pll_param));
+
+       if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+               ret = calc_pll_params(ref, freq, &pll_param);
+               if (ret != 0) {
+                       printf("Error:Can't find pll parameters: %d\n",
+                               ret);
+                       return ret;
+               }
+               switch ((__raw_readl(&mxc_ccm->cbcmr) & \
+                       MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
+                       MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+               case 0:
+                       return config_pll_clk(PLL1_CLOCK, &pll_param);
+                       break;
+               case 1:
+                       return config_pll_clk(PLL3_CLOCK, &pll_param);
+                       break;
+               default:
+                       return -EINVAL;
+               }
+       }
+
+       return 0;
+}
+
+static int config_ddr_clk(u32 emi_clk)
+{
+       u32 clk_src;
+       s32 shift = 0, clk_sel, div = 1;
+       u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
+       u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+
+       if (emi_clk > MAX_DDR_CLK) {
+               printf("Warning:DDR clock should not exceed %d MHz\n",
+                       MAX_DDR_CLK / SZ_DEC_1M);
+               emi_clk = MAX_DDR_CLK;
+       }
+
+       clk_src = get_periph_clk();
+       /* Find DDR clock input */
+       clk_sel = (cbcmr >> 10) & 0x3;
+       switch (clk_sel) {
+       case 0:
+               shift = 16;
+               break;
+       case 1:
+               shift = 19;
+               break;
+       case 2:
+               shift = 22;
+               break;
+       case 3:
+               shift = 10;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       if ((clk_src % emi_clk) < 10000000)
+               div = clk_src / emi_clk;
+       else
+               div = (clk_src / emi_clk) + 1;
+       if (div > 8)
+               div = 8;
+
+       cbcdr = cbcdr & ~(0x7 << shift);
+       cbcdr |= ((div - 1) << shift);
+       __raw_writel(cbcdr, &mxc_ccm->cbcdr);
+       while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+               ;
+       __raw_writel(0x0, &mxc_ccm->ccdr);
+
+       return 0;
+}
+
+/*
+ * This function assumes the expected core clock has to be changed by
+ * modifying the PLL. This is NOT true always but for most of the times,
+ * it is. So it assumes the PLL output freq is the same as the expected
+ * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
+ * In the latter case, it will try to increase the presc value until
+ * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
+ * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
+ * on the targeted PLL and reference input clock to the PLL. Lastly,
+ * it sets the register based on these values along with the dividers.
+ * Note 1) There is no value checking for the passed-in divider values
+ *         so the caller has to make sure those values are sensible.
+ *      2) Also adjust the NFC divider such that the NFC clock doesn't
+ *         exceed NFC_CLK_MAX.
+ *      3) IPU HSP clock is independent of AHB clock. Even it can go up to
+ *         177MHz for higher voltage, this function fixes the max to 133MHz.
+ *      4) This function should not have allowed diag_printf() calls since
+ *         the serial driver has been stoped. But leave then here to allow
+ *         easy debugging by NOT calling the cyg_hal_plf_serial_stop().
+ */
+int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
+{
+       freq *= SZ_DEC_1M;
+
+       switch (clk) {
+       case MXC_ARM_CLK:
+               if (config_core_clk(ref, freq))
+                       return -EINVAL;
+               break;
+       case MXC_PERIPH_CLK:
+               if (config_periph_clk(ref, freq))
+                       return -EINVAL;
+               break;
+       case MXC_DDR_CLK:
+               if (config_ddr_clk(freq))
+                       return -EINVAL;
+               break;
+       case MXC_NFC_CLK:
+               if (config_nfc_clk(freq))
+                       return -EINVAL;
+               break;
+       default:
+               printf("Warning:Unsupported or invalid clock type\n");
+       }
+
+       return 0;
+}
+
+ #ifdef CONFIG_MX53
+ /*
+  * The clock for the external interface can be set to use internal clock
+@@ -430,6 +869,7 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+        printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+        printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+        printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
+       printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+ 
+        return 0;
+ }
+diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
+index e822809..35ee815 100644
+--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
+@@ -33,6 +33,9 @@ enum mxc_clock {
+        MXC_CSPI_CLK,
+        MXC_FEC_CLK,
+        MXC_SATA_CLK,
+       MXC_DDR_CLK,
+       MXC_NFC_CLK,
+       MXC_PERIPH_CLK,
+ };
+ 
+ unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
+@@ -40,7 +43,7 @@ unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
+ u32 imx_get_uartclk(void);
+ u32 imx_get_fecclk(void);
+ unsigned int mxc_get_clock(enum mxc_clock clk);
+-
+int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
+ void set_usb_phy2_clk(void);
+ void enable_usb_phy2_clk(unsigned char enable);
+ void set_usboh3_clk(void);
+diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
+index bdeafbc..4e0fc1b 100644
+--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
+@@ -76,6 +76,9 @@ struct mxc_ccm_reg {
+        u32 CCGR4;
+        u32 CCGR5;
+        u32 CCGR6;      /* 0x0080 */
+#ifdef CONFIG_MX53
+       u32 CCGR7;      /* 0x0084 */
+#endif
+        u32 cmeor;
+ };
+ 
+@@ -84,6 +87,9 @@ struct mxc_ccm_reg {
+ #define MXC_CCM_CACRR_ARM_PODF_MASK            0x7
+ 
+ /* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL           (0x1 << 30)
+#define MXC_CCM_CBCDR_DDR_PODF_MASK            (0x7 << 27)
+#define MXC_CCM_CBCDR_DDR_PODF_OFFSET          27
+ #define MXC_CCM_CBCDR_EMI_CLK_SEL              (0x1 << 26)
+ #define MXC_CCM_CBCDR_PERIPH_CLK_SEL           (0x1 << 25)
+ #define MXC_CCM_CBCDR_EMI_PODF_OFFSET          22
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0018-mx53loco-Allow-to-print-CPU-information-at-a-later-s.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0018-mx53loco-Allow-to-print-CPU-information-at-a-later-s.patch
new file mode 100644
index 000000000..79fd89991
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0018-mx53loco-Allow-to-print-CPU-information-at-a-later-s.patch
@@ -0,0 +1,93 @@
+From 255fe9c082f3a409d366517bb5e92d299fdbf2ff Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <festevam@gmail.com>
+Date: Mon, 30 Apr 2012 08:12:03 +0000
+Subject: [PATCH 18/56] mx53loco: Allow to print CPU information at a later
+ stage
+Print CPU information within board_late_init().
+This is in preparation for adding 1GHz support, which requires programming a PMIC
+via I2C. As I2C is only available after relocation, print the CPU information
+later at board_late_init(), so that the CPU frequency can be printed correctly.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ arch/arm/cpu/armv7/imx-common/cpu.c       |    2 +-
+ arch/arm/include/asm/arch-mx5/sys_proto.h |    1 +
+ board/freescale/mx53loco/mx53loco.c       |   22 ++++++++++++++++++++++
+ include/configs/mx53loco.h                |    1 -
+ 4 files changed, 24 insertions(+), 2 deletions(-)
+diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c
+index b96fa5b..b3195dd 100644
+--- a/arch/arm/cpu/armv7/imx-common/cpu.c
+++ b/arch/arm/cpu/armv7/imx-common/cpu.c
+@@ -35,7 +35,7 @@
+ #include <fsl_esdhc.h>
+ #endif
+ 
+-static char *get_reset_cause(void)
+char *get_reset_cause(void)
+ {
+        u32 cause;
+        struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
+index 3f10d29..7b5246e 100644
+--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
+@@ -37,5 +37,6 @@ void set_chipselect_size(int const);
+ int fecmxc_initialize(bd_t *bis);
+ u32 get_ahb_clk(void);
+ u32 get_periph_clk(void);
+char *get_reset_cause(void);
+ 
+ #endif
+diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
+index 7ea9f6e..46aaeb2 100644
+--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
+@@ -299,6 +299,28 @@ int board_early_init_f(void)
+        return 0;
+ }
+ 
+int print_cpuinfo(void)
+{
+       u32 cpurev;
+
+       cpurev = get_cpu_rev();
+       printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
+               (cpurev & 0xFF000) >> 12,
+               (cpurev & 0x000F0) >> 4,
+               (cpurev & 0x0000F) >> 0,
+               mxc_get_clock(MXC_ARM_CLK) / 1000000);
+       printf("Reset cause: %s\n", get_reset_cause());
+       return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+       print_cpuinfo();
+       return 0;
+}
+#endif
+
+ int board_init(void)
+ {
+        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
+index af59307..0778bde 100644
+--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
+@@ -27,7 +27,6 @@
+ 
+ #define CONFIG_SYS_MX5_HCLK    24000000
+ #define CONFIG_SYS_MX5_CLK32           32768
+-#define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+ 
+ #define CONFIG_MACH_TYPE       MACH_TYPE_MX53_LOCO
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0019-mx53loco-Add-support-for-1GHz-operation-for-DA9053-b.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0019-mx53loco-Add-support-for-1GHz-operation-for-DA9053-b.patch
new file mode 100644
index 000000000..e9e2c1bb9
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0019-mx53loco-Add-support-for-1GHz-operation-for-DA9053-b.patch
@@ -0,0 +1,155 @@
+From f658ecfa1294ec653afde9deb6ebedb1fe7d1afd Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <festevam@gmail.com>
+Date: Mon, 30 Apr 2012 08:12:04 +0000
+Subject: [PATCH 19/56] mx53loco: Add support for 1GHz operation for
+ DA9053-based boards
+There are two types of mx53loco boards: initial boards were built with a Dialog
+DA9053 PMIC and more recent version is based on a Freescale MC34708 PMIC.
+Add DA9053 PMIC support and adjust the required voltages and clocks for running
+the CPU at 1GHz.
+Tested on both versions of mx53loco boards.
+In the case of a MC34708-based board the CPU operating voltage remains at 800MHz.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Acked-by : Stefano Babic <sbabic@denx.de>
+---
+ board/freescale/mx53loco/mx53loco.c |   71 +++++++++++++++++++++++++++++++++++
+ include/configs/mx53loco.h          |   14 +++++++
+ 2 files changed, 85 insertions(+)
+diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
+index 46aaeb2..0dcec9b 100644
+--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
+@@ -36,6 +36,8 @@
+ #include <mmc.h>
+ #include <fsl_esdhc.h>
+ #include <asm/gpio.h>
+#include <pmic.h>
+#include <dialog_pmic.h>
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+@@ -291,6 +293,71 @@ int board_mmc_init(bd_t *bis)
+ }
+ #endif
+ 
+static void setup_iomux_i2c(void)
+{
+       /* I2C1 SDA */
+       mxc_request_iomux(MX53_PIN_CSI0_D8,
+               IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+       mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+               INPUT_CTL_PATH0);
+       mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
+               PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+               PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
+               PAD_CTL_PUE_PULL |
+               PAD_CTL_ODE_OPENDRAIN_ENABLE);
+       /* I2C1 SCL */
+       mxc_request_iomux(MX53_PIN_CSI0_D9,
+               IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+       mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+               INPUT_CTL_PATH0);
+       mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
+               PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+               PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
+               PAD_CTL_PUE_PULL |
+               PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+static int power_init(void)
+{
+       unsigned int val, ret;
+       struct pmic *p;
+
+       pmic_init();
+       p = get_pmic();
+
+       /* Set VDDA to 1.25V */
+       val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
+       ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
+
+       ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+       val |= DA9052_SUPPLY_VBCOREGO;
+       ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+
+       /* Set Vcc peripheral to 1.35V */
+       ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
+       ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+
+       return ret;
+}
+
+static void clock_1GHz(void)
+{
+       int ret;
+       u32 ref_clk = CONFIG_SYS_MX5_HCLK;
+       /*
+        * After increasing voltage to 1.25V, we can switch
+        * CPU clock to 1GHz and DDR to 400MHz safely
+        */
+       ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+       if (ret)
+               printf("CPU:   Switch CPU clock to 1GHZ failed\n");
+
+       ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+       ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+       if (ret)
+               printf("CPU:   Switch DDR clock to 400MHz failed\n");
+}
+
+ int board_early_init_f(void)
+ {
+        setup_iomux_uart();
+@@ -316,7 +383,11 @@ int print_cpuinfo(void)
+ #ifdef CONFIG_BOARD_LATE_INIT
+ int board_late_init(void)
+ {
+       setup_iomux_i2c();
+       if (!power_init())
+               clock_1GHz();
+        print_cpuinfo();
+
+        return 0;
+ }
+ #endif
+diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
+index 0778bde..8f43eec 100644
+--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
+@@ -41,6 +41,7 @@
+ #define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+ 
+ #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+ #define CONFIG_MXC_GPIO
+ 
+ #define CONFIG_MXC_UART
+@@ -85,6 +86,19 @@
+ #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+ #define CONFIG_MXC_USB_FLAGS   0
+ 
+/* I2C Configs */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX53_PORT1
+#define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_SYS_I2C_SLAVE           0xfe
+
+/* PMIC Controller */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_DIALOG_PMIC
+#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR        0x48
+
+ /* allow to overwrite serial and ethaddr */
+ #define CONFIG_ENV_OVERWRITE
+ #define CONFIG_CONS_INDEX              1
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0020-M28-Enable-FDT-support.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0020-M28-Enable-FDT-support.patch
new file mode 100644
index 000000000..9a660d54f
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0020-M28-Enable-FDT-support.patch
@@ -0,0 +1,33 @@
+From 8c96682f52e8e9bf7591fad07e9f9bc51e1da7d4 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marex@denx.de>
+Date: Thu, 3 May 2012 05:47:21 +0000
+Subject: [PATCH 20/56] M28: Enable FDT support
+This will eventually be needed with Linux 3.5, which will be the point when
+MXS will be switched to FDT.
+Signed-off-by: Marek Vasut <marex@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Fabio Estevam <festevam@gmail.com>
+---
+ include/configs/m28evk.h |    2 ++
+ 1 file changed, 2 insertions(+)
+diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
+index 39d6a07..40845d3 100644
+--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
+@@ -43,6 +43,8 @@
+ #define        CONFIG_ARCH_CPU_INIT
+ #define        CONFIG_ARCH_MISC_INIT
+ 
+#define CONFIG_OF_LIBFDT
+
+ /*
+  * SPL
+  */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0021-Revert-i.MX28-Enable-additional-DRAM-address-bits.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0021-Revert-i.MX28-Enable-additional-DRAM-address-bits.patch
new file mode 100644
index 000000000..8ad0bf00b
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0021-Revert-i.MX28-Enable-additional-DRAM-address-bits.patch
@@ -0,0 +1,50 @@
+From 3dfa10c1a1d49b3b5b7cf6652fe965d088d4abc0 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marex@denx.de>
+Date: Thu, 3 May 2012 05:47:18 +0000
+Subject: [PATCH 21/56] Revert "i.MX28: Enable additional DRAM address bits"
+This reverts commit 69d26d09de1cb93e0a09ca71d9f0d41a66f0756a.
+Apparently, this commit got mainline only because of out-of-tree
+port and causes breakage on board that is mainline. Revert.
+Reason:
+* The OOT board has 512MB of DRAM, enabling this additional address
+  line enabled it to work fine with 512MB of RAM.
+* Every mainline port has max. 256MB of DRAM, therefore this revert
+  has no impact on any mainline port
+* Though this caused a problem with new M28 board with 256MB of DRAM
+  where the chips are wired differently. The patch-to-be-reverted
+  caused the DRAM to behave like this:
+  [128MB chunk #1][128MB chunk #1 again][128MB chunk #2][128MB chunk #2 again]
+Therefore to retain the current one-memory-init-rules-them-all situation,
+revert this patch until another board emerges and will actually be pushed
+mainline that needs different setup.
+Signed-off-by: Marek Vasut <marex@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Fabio Estevam <festevam@gmail.com>
+---
+ arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+index 911bbef..0f825ed 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+@@ -39,7 +39,7 @@ uint32_t dram_vals[] = {
+        0x00000000, 0x00000100, 0x00000000, 0x00000000,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x00000000, 0x00000000, 0x00010101, 0x01010101,
+-       0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101,
+       0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
+        0x00000100, 0x00000100, 0x00000000, 0x00000002,
+        0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
+        0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612,
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0022-M28-Scan-only-first-512-MB-of-DRAM-to-avoid-memory-w.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0022-M28-Scan-only-first-512-MB-of-DRAM-to-avoid-memory-w.patch
new file mode 100644
index 000000000..1176aeaee
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0022-M28-Scan-only-first-512-MB-of-DRAM-to-avoid-memory-w.patch
@@ -0,0 +1,31 @@
+From 0ab1b7fdcbe4fe014ae05f6a803d2ac84f98bd43 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marex@denx.de>
+Date: Thu, 3 May 2012 05:47:19 +0000
+Subject: [PATCH 22/56] M28: Scan only first 512 MB of DRAM to avoid memory
+ wraparound
+Signed-off-by: Marek Vasut <marex@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Fabio Estevam <festevam@gmail.com>
+---
+ include/configs/m28evk.h |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
+index 40845d3..8cd5f31 100644
+--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
+@@ -86,7 +86,7 @@
+  */
+ #define        CONFIG_NR_DRAM_BANKS            1               /* 1 bank of DRAM */
+ #define        PHYS_SDRAM_1                    0x40000000      /* Base address */
+-#define        PHYS_SDRAM_1_SIZE               0x40000000      /* Max 1 GB RAM */
+#define        PHYS_SDRAM_1_SIZE               0x20000000      /* Max 512 MB RAM */
+ #define        CONFIG_STACKSIZE                0x00010000      /* 128 KB stack */
+ #define        CONFIG_SYS_MALLOC_LEN           0x00400000      /* 4 MB for malloc */
+ #define        CONFIG_SYS_GBL_DATA_SIZE        128             /* Initial data */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0023-USB-ehci-mx6-Fix-broken-IO-access.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0023-USB-ehci-mx6-Fix-broken-IO-access.patch
new file mode 100644
index 000000000..36176084a
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0023-USB-ehci-mx6-Fix-broken-IO-access.patch
@@ -0,0 +1,42 @@
+From 50b03cd90c32aced81d62f9b1c5385dd0bd7173d Mon Sep 17 00:00:00 2001
+From: Wolfgang Grandegger <wg@denx.de>
+Date: Wed, 2 May 2012 04:36:39 +0000
+Subject: [PATCH 23/56] USB: ehci-mx6: Fix broken IO access
+To get USB working again on the i.MX6, this patch fixes a bug introduced
+with commit 522b2a0 "Add proper IO accessors for mx6 usb registers.".
+At that occasion, I also added the missing __iomem directive.
+Cc: Marek Vasut <marex@denx.de>
+CC: Fabio Estevam <festevam@gmail.com>
+Signed-off-by: Wolfgang Grandegger <wg@denx.de>
+---
+ drivers/usb/host/ehci-mx6.c |    5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
+index 5dec673..42c77fe 100644
+--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
+@@ -73,7 +73,8 @@ static void usbh1_internal_phy_clock_gate(int on)
+ 
+ static void usbh1_power_config(void)
+ {
+-       struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+       struct anatop_regs __iomem *anatop =
+               (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+        /*
+         * Some phy and power's special controls for host1
+         * 1. The external charger detector needs to be disabled
+@@ -87,7 +88,7 @@ static void usbh1_power_config(void)
+                     &anatop->usb2_chrg_detect);
+ 
+        __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
+-                    &anatop->usb2_pll_480_ctrl);
+                    &anatop->usb2_pll_480_ctrl_clr);
+ 
+        __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
+                     ANADIG_USB2_PLL_480_CTRL_POWER |
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0024-mx28evk-add-NAND-support.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0024-mx28evk-add-NAND-support.patch
new file mode 100644
index 000000000..7cfa72d2a
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0024-mx28evk-add-NAND-support.patch
@@ -0,0 +1,78 @@
+From 292a6fbe8085eb476c9cc6e9b2d23cad5c7e3ae4 Mon Sep 17 00:00:00 2001
+From: Lauri Hintsala <lauri.hintsala@bluegiga.com>
+Date: Tue, 17 Apr 2012 00:35:46 +0000
+Subject: [PATCH 24/56] mx28evk: add NAND support
+NAND support is not enabled by default because Eval Kit is not delivered
+with NAND chip. To enable NAND support add CONFIG_CMD_NAND to board config.
+Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
+Acked-by: Marek Vasut <marex@denx.de>
+---
+ board/freescale/mx28evk/iomux.c |   21 +++++++++++++++++++++
+ include/configs/mx28evk.h       |   10 ++++++++++
+ 2 files changed, 31 insertions(+)
+diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
+index 396761b..6587c45 100644
+--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
+@@ -26,6 +26,7 @@
+ #include <asm/arch/sys_proto.h>
+ 
+ #define        MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define        MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+ #define        MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+ #define        MUX_CONFIG_EMI  (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+ #define        MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+@@ -55,6 +56,26 @@ const iomux_cfg_t iomux_setup[] = {
+        MX28_PAD_PWM3__GPIO_3_28 |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+ 
+#ifdef CONFIG_NAND_MXS
+       /* GPMI NAND */
+       MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_RDN__GPMI_RDN |
+               (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+       MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+       MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+#endif
+
+        /* FEC0 */
+        MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
+index 31dc718..5cd9730 100644
+--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
+@@ -149,6 +149,16 @@
+ #endif
+ 
+ /*
+ * NAND Driver
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x60000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#endif
+
+/*
+  * Ethernet on SOC (FEC)
+  */
+ #ifdef CONFIG_CMD_NET
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0025-i.MX6-Add-ANATOP-regulator-init.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0025-i.MX6-Add-ANATOP-regulator-init.patch
new file mode 100644
index 000000000..65b13bc9f
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0025-i.MX6-Add-ANATOP-regulator-init.patch
@@ -0,0 +1,84 @@
+From 15616b5ca6f7dc2b728930cfc729d787869edc9e Mon Sep 17 00:00:00 2001
+From: Dirk Behme <dirk.behme@de.bosch.com>
+Date: Wed, 2 May 2012 02:12:17 +0000
+Subject: [PATCH 25/56] i.MX6: Add ANATOP regulator init
+Init the core regulator voltage to 1.2V. This is required for the correct
+functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
+workaround to fix some memory clock jitter.
+Note: This should be but can't be done in the DCD. The bootloader
+      prevents access to the ANATOP registers.
+Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
+CC: Jason Chen <b02280@freescale.com>
+CC: Jason Liu <r64343@freescale.com>
+CC: Ranjani Vaidyanathan <ra5478@freescale.com>
+CC: Stefano Babic <sbabic@denx.de>
+CC: Fabio Estevam <festevam@gmail.com>
+---
+ arch/arm/cpu/armv7/mx6/soc.c              |   30 +++++++++++++++++++++++++++++
+ arch/arm/include/asm/arch-mx6/sys_proto.h |    2 ++
+ 2 files changed, 32 insertions(+)
+diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
+index 543b2cc..90f2088 100644
+--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
+@@ -77,10 +77,40 @@ void init_aips(void)
+        writel(0x00000000, &aips2->opacr4);
+ }
+ 
+/*
+ * Set the VDDSOC
+ *
+ * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
+ * them to the specified millivolt level.
+ * Possible values are from 0.725V to 1.450V in steps of
+ * 0.025V (25mV).
+ */
+void set_vddsoc(u32 mv)
+{
+       struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+       u32 val, reg = readl(&anatop->reg_core);
+
+       if (mv < 725)
+               val = 0x00;     /* Power gated off */
+       else if (mv > 1450)
+               val = 0x1F;     /* Power FET switched full on. No regulation */
+       else
+               val = (mv - 700) / 25;
+
+       /*
+        * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
+        * and set them to the calculated value (0.7V + val * 0.25V)
+        */
+       reg = (reg & ~(0x1F << 18)) | (val << 18);
+       writel(reg, &anatop->reg_core);
+}
+
+ int arch_cpu_init(void)
+ {
+        init_aips();
+ 
+       set_vddsoc(1200);       /* Set VDDSOC to 1.2V */
+
+        return 0;
+ }
+ #endif
+diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
+index 69687a8..711b30d 100644
+--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
+@@ -28,6 +28,8 @@
+ 
+ u32 get_cpu_rev(void);
+ 
+void set_vddsoc(u32 mv);
+
+ /*
+  * Initializes on-chip ethernet controllers.
+  * to override, implement board_eth_init()
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0026-i.MX6-add-enable_sata_clock.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0026-i.MX6-add-enable_sata_clock.patch
new file mode 100644
index 000000000..cd26a2408
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0026-i.MX6-add-enable_sata_clock.patch
@@ -0,0 +1,209 @@
+From 46a009987c6ddb738f934e487181b78ea272c104 Mon Sep 17 00:00:00 2001
+From: Eric Nelson <eric.nelson@boundarydevices.com>
+Date: Tue, 27 Mar 2012 09:52:21 +0000
+Subject: [PATCH 26/56] i.MX6: add enable_sata_clock()
+Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
+Signed-off-by: Stefano Babic <sbabic@denx.de>
+---
+ arch/arm/cpu/armv7/mx6/clock.c           |   31 +++++++++
+ arch/arm/include/asm/arch-mx6/clock.h    |    1 +
+ arch/arm/include/asm/arch-mx6/imx-regs.h |    9 +++
+ arch/arm/include/asm/arch-mx6/iomux-v3.h |  111 ++++++++++++++++++++++++++++++
+ 4 files changed, 152 insertions(+)
+diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
+index 0f05432..52d5dc4 100644
+--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
+@@ -292,6 +292,37 @@ u32 imx_get_fecclk(void)
+        return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
+ }
+ 
+int enable_sata_clock(void)
+{
+       u32 reg = 0;
+       s32 timeout = 100000;
+       struct mxc_ccm_reg *const imx_ccm
+               = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
+
+       /* Enable sata clock */
+       reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
+       reg |= MXC_CCM_CCGR5_CG2_MASK;
+       writel(reg, &imx_ccm->CCGR5);
+
+       /* Enable PLLs */
+       reg = readl(&imx_ccm->analog_pll_enet);
+       reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
+       writel(reg, &imx_ccm->analog_pll_enet);
+       reg |= BM_ANADIG_PLL_SYS_ENABLE;
+       while (timeout--) {
+               if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
+                       break;
+       }
+       if (timeout <= 0)
+               return -EIO;
+       reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
+       writel(reg, &imx_ccm->analog_pll_enet);
+       reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
+       writel(reg, &imx_ccm->analog_pll_enet);
+
+       return 0 ;
+}
+
+ unsigned int mxc_get_clock(enum mxc_clock clk)
+ {
+        switch (clk) {
+diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
+index 613809b..b91d8bf 100644
+--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
+@@ -47,5 +47,6 @@ u32 imx_get_uartclk(void);
+ u32 imx_get_fecclk(void);
+ unsigned int mxc_get_clock(enum mxc_clock clk);
+ void enable_usboh3_clk(unsigned char enable);
+int enable_sata_clock(void);
+ 
+ #endif /* __ASM_ARCH_CLOCK_H */
+diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
+index 6d25c8d..e165810 100644
+--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
+@@ -436,5 +436,14 @@ struct anatop_regs {
+        u32     digprog;                /* 0x260 */
+ };
+ 
+struct iomuxc_base_regs {
+       u32     gpr[14];        /* 0x000 */
+       u32     obsrv[5];       /* 0x038 */
+       u32     swmux_ctl[197]; /* 0x04c */
+       u32     swpad_ctl[250]; /* 0x360 */
+       u32     swgrp[26];      /* 0x748 */
+       u32     daisy[104];     /* 0x7b0..94c */
+};
+
+ #endif /* __ASSEMBLER__*/
+ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
+diff --git a/arch/arm/include/asm/arch-mx6/iomux-v3.h b/arch/arm/include/asm/arch-mx6/iomux-v3.h
+index 4558f4f..788b413 100644
+--- a/arch/arm/include/asm/arch-mx6/iomux-v3.h
+++ b/arch/arm/include/asm/arch-mx6/iomux-v3.h
+@@ -100,4 +100,115 @@ typedef u64 iomux_v3_cfg_t;
+ int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
+ int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
+ 
+/*
+ * IOMUXC_GPR13 bit fields
+ */
+#define IOMUXC_GPR13_SDMA_STOP_REQ     (1<<30)
+#define IOMUXC_GPR13_CAN2_STOP_REQ     (1<<29)
+#define IOMUXC_GPR13_CAN1_STOP_REQ     (1<<28)
+#define IOMUXC_GPR13_ENET_STOP_REQ     (1<<27)
+#define IOMUXC_GPR13_SATA_PHY_8_MASK   (7<<24)
+#define IOMUXC_GPR13_SATA_PHY_7_MASK   (0x1f<<19)
+#define IOMUXC_GPR13_SATA_PHY_6_SHIFT  16
+#define IOMUXC_GPR13_SATA_PHY_6_MASK   (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+#define IOMUXC_GPR13_SATA_SPEED_MASK   (1<<15)
+#define IOMUXC_GPR13_SATA_PHY_5_MASK   (1<<14)
+#define IOMUXC_GPR13_SATA_PHY_4_MASK   (7<<11)
+#define IOMUXC_GPR13_SATA_PHY_3_MASK   (0x1f<<7)
+#define IOMUXC_GPR13_SATA_PHY_2_MASK   (0x1f<<2)
+#define IOMUXC_GPR13_SATA_PHY_1_MASK   (3<<0)
+
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB     (0b000<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB     (0b001<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB     (0b010<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB     (0b011<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB     (0b100<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB     (0b101<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB     (0b110<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB     (0b111<<24)
+
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19)
+
+#define IOMUXC_GPR13_SATA_SPEED_1P5G   (0<<15)
+#define IOMUXC_GPR13_SATA_SPEED_3G     (1<<15)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED       (0<<14)
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED                (1<<14)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16       (0<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16       (1<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16       (2<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16       (3<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16                (4<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16                (5<<11)
+
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB        (0b0000<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB        (0b0001<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB        (0b0010<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB        (0b0011<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB        (0b0100<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB        (0b0101<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB        (0b0110<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB        (0b0111<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB        (0b1000<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB        (0b1001<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB        (0b1010<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB        (0b1011<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB        (0b1100<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB        (0b1101<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB        (0b1110<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB        (0b1111<<7)
+
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V      (0b00000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V      (0b00001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V      (0b00010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V      (0b00011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V      (0b00100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V      (0b00101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V      (0b00110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V      (0b00111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V      (0b01000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V      (0b01001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V      (0b01010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V      (0b01011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V      (0b01100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V      (0b01101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V      (0b01110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V      (0b01111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V      (0b10000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V      (0b10001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V      (0b10010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V      (0b10011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V      (0b10100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V      (0b10101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V      (0b10110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V      (0b10111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V      (0b11000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V      (0b11001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V      (0b11010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V      (0b11011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V      (0b11100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V      (0b11101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V      (0b11110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V      (0b11111<<2)
+
+#define IOMUXC_GPR13_SATA_PHY_1_FAST   0
+#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
+#define IOMUXC_GPR13_SATA_PHY_1_SLOW   2
+
+#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_7_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_6_MASK \
+                               |IOMUXC_GPR13_SATA_SPEED_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_5_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_4_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_3_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_2_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_1_MASK)
+
+ #endif /* __MACH_IOMUX_V3_H__*/
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0027-i.MX6-mx6q_sabrelite-add-SATA-bindings.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0027-i.MX6-mx6q_sabrelite-add-SATA-bindings.patch
new file mode 100644
index 000000000..65c52295d
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0027-i.MX6-mx6q_sabrelite-add-SATA-bindings.patch
@@ -0,0 +1,96 @@
+From 95d9b53d5f0afdfe3487c5bd55a23f9503a2adad Mon Sep 17 00:00:00 2001
+From: Eric Nelson <eric.nelson@boundarydevices.com>
+Date: Tue, 1 May 2012 09:55:11 +0000
+Subject: [PATCH 27/56] i.MX6: mx6q_sabrelite: add SATA bindings
+Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
+Acked-by: Marek Vasut <marex@denx.de>
+Acked-by: stefano Babic <sbabic@denx.de>
+---
+ board/freescale/mx6qsabrelite/mx6qsabrelite.c |   31 +++++++++++++++++++++++++
+ include/configs/mx6qsabrelite.h               |   13 +++++++++++
+ 2 files changed, 44 insertions(+)
+diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+index 90773aa..29cbfed 100644
+--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+@@ -25,6 +25,7 @@
+ #include <asm/arch/imx-regs.h>
+ #include <asm/arch/mx6x_pins.h>
+ #include <asm/arch/iomux-v3.h>
+#include <asm/arch/clock.h>
+ #include <asm/errno.h>
+ #include <asm/gpio.h>
+ #include <mmc.h>
+@@ -293,6 +294,32 @@ static void setup_buttons(void)
+                                         ARRAY_SIZE(button_pads));
+ }
+ 
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+       struct iomuxc_base_regs *const iomuxc_regs
+               = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+       int ret = enable_sata_clock();
+       if (ret)
+               return ret;
+
+       clrsetbits_le32(&iomuxc_regs->gpr[13],
+                       IOMUXC_GPR13_SATA_MASK,
+                       IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+                       |IOMUXC_GPR13_SATA_PHY_7_SATA2M
+                       |IOMUXC_GPR13_SATA_SPEED_3G
+                       |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+                       |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+                       |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+                       |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+                       |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+                       |IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+       return 0;
+}
+#endif
+
+ int board_early_init_f(void)
+ {
+        setup_iomux_uart();
+@@ -310,6 +337,10 @@ int board_init(void)
+        setup_spi();
+ #endif
+ 
+#ifdef CONFIG_CMD_SATA
+       setup_sata();
+#endif
+
+        return 0;
+ }
+ 
+diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
+index 48be6e6..feabc05 100644
+--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
+@@ -72,6 +72,19 @@
+ #define CONFIG_CMD_FAT
+ #define CONFIG_DOS_PARTITION
+ 
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE     1
+#define CONFIG_DWC_AHSATA_PORT_ID      0
+#define CONFIG_DWC_AHSATA_BASE_ADDR    SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+ #define CONFIG_CMD_PING
+ #define CONFIG_CMD_DHCP
+ #define CONFIG_CMD_MII
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0028-i.MX25-esdhc-Add-mxc_get_clock-infrastructure.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0028-i.MX25-esdhc-Add-mxc_get_clock-infrastructure.patch
new file mode 100644
index 000000000..4ebbc1b8e
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0028-i.MX25-esdhc-Add-mxc_get_clock-infrastructure.patch
@@ -0,0 +1,114 @@
+From b5e9dc88dbb9636129d3a600d9874477d2059716 Mon Sep 17 00:00:00 2001
+From: Timo Ketola <timo@exertus.fi>
+Date: Wed, 18 Apr 2012 22:55:28 +0000
+Subject: [PATCH 28/56] i.MX25: esdhc: Add mxc_get_clock infrastructure
+Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's
+implement get_clocks function. This is how it seems to be implemented
+elsewhere.
+Signed-off-by: Timo Ketola <timo@exertus.fi>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ arch/arm/cpu/arm926ejs/mx25/generic.c  |   27 +++++++++++++++++++++++++++
+ arch/arm/include/asm/arch-mx25/clock.h |   23 +++++++++++++++++++++++
+ 2 files changed, 50 insertions(+)
+diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
+index 9cadb7c..8b07dae 100644
+--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
+@@ -28,10 +28,15 @@
+ #include <asm/io.h>
+ #include <asm/arch/imx-regs.h>
+ #include <asm/arch/imx25-pinmux.h>
+#include <asm/arch/clock.h>
+ #ifdef CONFIG_MXC_MMC
+ #include <asm/arch/mxcmmc.h>
+ #endif
+ 
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+ /*
+  *  get the system pll clock in Hz
+  *
+@@ -105,6 +110,20 @@ ulong imx_get_perclk(int clk)
+        return lldiv(fref, div);
+ }
+ 
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+       if (clk >= MXC_CLK_NUM)
+               return -1;
+       switch (clk) {
+       case MXC_ARM_CLK:
+               return imx_get_armclk();
+       case MXC_FEC_CLK:
+               return imx_get_ahbclk();
+       default:
+               return imx_get_perclk(clk);
+       }
+}
+
+ u32 get_cpu_rev(void)
+ {
+        u32 srev;
+@@ -182,6 +201,14 @@ int cpu_eth_init(bd_t *bis)
+ #endif
+ }
+ 
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+       return 0;
+}
+
+ /*
+  * Initializes on-chip MMC controllers.
+  * to override, implement board_mmc_init()
+diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h
+index c59f588..0f47eaf 100644
+--- a/arch/arm/include/asm/arch-mx25/clock.h
+++ b/arch/arm/include/asm/arch-mx25/clock.h
+@@ -26,11 +26,34 @@
+ #ifndef __ASM_ARCH_CLOCK_H
+ #define __ASM_ARCH_CLOCK_H
+ 
+enum mxc_clock {
+       MXC_CSI_CLK,
+       MXC_EPIT_CLK,
+       MXC_ESAI_CLK,
+       MXC_ESDHC1_CLK,
+       MXC_ESDHC2_CLK,
+       MXC_GPT_CLK,
+       MXC_I2C_CLK,
+       MXC_LCDC_CLK,
+       MXC_NFC_CLK,
+       MXC_OWIRE_CLK,
+       MXC_PWM_CLK,
+       MXC_SIM1_CLK,
+       MXC_SIM2_CLK,
+       MXC_SSI1_CLK,
+       MXC_SSI2_CLK,
+       MXC_UART_CLK,
+       MXC_ARM_CLK,
+       MXC_FEC_CLK,
+       MXC_CLK_NUM
+};
+
+ ulong imx_get_perclk(int clk);
+ ulong imx_get_ahbclk(void);
+ 
+ #define imx_get_uartclk() imx_get_perclk(15)
+ #define imx_get_fecclk() (imx_get_ahbclk()/2)
+ 
+unsigned int mxc_get_clock(enum mxc_clock clk);
+ 
+ #endif /* __ASM_ARCH_CLOCK_H */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0029-i.MX25-This-architecture-has-a-GPIO4-too.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0029-i.MX25-This-architecture-has-a-GPIO4-too.patch
new file mode 100644
index 000000000..23750edc7
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0029-i.MX25-This-architecture-has-a-GPIO4-too.patch
@@ -0,0 +1,28 @@
+From 30a6bfcb371cf21afc98624989fcdb7114069b9d Mon Sep 17 00:00:00 2001
+From: Timo Ketola <timo@exertus.fi>
+Date: Wed, 18 Apr 2012 22:55:29 +0000
+Subject: [PATCH 29/56] i.MX25: This architecture has a GPIO4 too
+Signed-off-by: Timo Ketola <timo@exertus.fi>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ drivers/gpio/mxc_gpio.c |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
+index f1b1c16..6615535 100644
+--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
+@@ -41,7 +41,8 @@ static unsigned long gpio_ports[] = {
+        [0] = GPIO1_BASE_ADDR,
+        [1] = GPIO2_BASE_ADDR,
+        [2] = GPIO3_BASE_ADDR,
+-#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
+               defined(CONFIG_MX6Q)
+        [3] = GPIO4_BASE_ADDR,
+ #endif
+ #if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0030-imx-nand-Support-flash-based-BBT.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0030-imx-nand-Support-flash-based-BBT.patch
new file mode 100644
index 000000000..cea0842d1
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0030-imx-nand-Support-flash-based-BBT.patch
@@ -0,0 +1,64 @@
+From b288061f27dca116f164b39a24844932d74c3b88 Mon Sep 17 00:00:00 2001
+From: Timo Ketola <timo@exertus.fi>
+Date: Wed, 18 Apr 2012 22:55:31 +0000
+Subject: [PATCH 30/56] imx: nand: Support flash based BBT
+Signed-off-by: Timo Ketola <timo@exertus.fi>
+Acked-by: Scott Wood <scottwood@freescale.com>
+---
+ drivers/mtd/nand/mxc_nand.c |   33 +++++++++++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
+index 35e89a0..936186f 100644
+--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
+@@ -1302,12 +1302,45 @@ static void mxc_setup_config1(void)
+ #define mxc_setup_config1()
+ #endif
+ 
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+
+static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
+static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+       .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+                  NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+       .offs = 0,
+       .len = 4,
+       .veroffs = 4,
+       .maxblocks = 4,
+       .pattern = bbt_pattern,
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+       .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+                  NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+       .offs = 0,
+       .len = 4,
+       .veroffs = 4,
+       .maxblocks = 4,
+       .pattern = mirror_pattern,
+};
+
+#endif
+
+ int board_nand_init(struct nand_chip *this)
+ {
+        struct mtd_info *mtd;
+        uint16_t tmp;
+        int err = 0;
+ 
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+       this->options |= NAND_USE_FLASH_BBT;
+       this->bbt_td = &bbt_main_descr;
+       this->bbt_md = &bbt_mirror_descr;
+#endif
+
+        /* structures must be linked */
+        mtd = &host->mtd;
+        mtd->priv = this;
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0031-i.MX25-usb-Set-PORTSCx-register.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0031-i.MX25-usb-Set-PORTSCx-register.patch
new file mode 100644
index 000000000..f1eb111a0
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0031-i.MX25-usb-Set-PORTSCx-register.patch
@@ -0,0 +1,34 @@
+From 6ac02672f1a34125de09864788b1ecb653b1b3bd Mon Sep 17 00:00:00 2001
+From: Timo Ketola <timo@exertus.fi>
+Date: Wed, 18 Apr 2012 22:55:32 +0000
+Subject: [PATCH 31/56] i.MX25: usb: Set PORTSCx register
+The USB controller in i.MX25 has a PORTSCx registers which should be
+set. In this regard it is similar to the controller in i.MX31. As this
+file is compiled only with i.MX25 and -31, #ifdef check can be removed.
+Signed-off-by: Timo Ketola <timo@exertus.fi>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ drivers/usb/host/ehci-mxc.c |    2 --
+ 1 file changed, 2 deletions(-)
+diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
+index 61dbccd..7384580 100644
+--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
+@@ -125,11 +125,9 @@ int ehci_hcd_init(void)
+        hcor = (struct ehci_hcor *)((uint32_t) hccr +
+                        HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+        setbits_le32(&ehci->usbmode, CM_HOST);
+-#ifdef CONFIG_MX31
+        setbits_le32(&ehci->control, USB_EN);
+ 
+        __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+-#endif
+        mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
+ 
+        udelay(10000);
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0032-imx-usb-There-is-no-such-register.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0032-imx-usb-There-is-no-such-register.patch
new file mode 100644
index 000000000..9b99c058d
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0032-imx-usb-There-is-no-such-register.patch
@@ -0,0 +1,31 @@
+From 75aeb21482b9487c5f6cfd99a605b01343ef3440 Mon Sep 17 00:00:00 2001
+From: Timo Ketola <timo@exertus.fi>
+Date: Wed, 18 Apr 2012 22:55:33 +0000
+Subject: [PATCH 32/56] imx: usb: There is no such register
+The reference manual of i.MX25 (nor i.MX31) does not define such
+register. This seems to access read only UH2_CAPLENGTH register (if
+CONFIG_MXC_USB_PORT is zero).
+Signed-off-by: Timo Ketola <timo@exertus.fi>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ drivers/usb/host/ehci-mxc.c |    2 --
+ 1 file changed, 2 deletions(-)
+diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
+index 7384580..45cbd18 100644
+--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
+@@ -125,8 +125,6 @@ int ehci_hcd_init(void)
+        hcor = (struct ehci_hcor *)((uint32_t) hccr +
+                        HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+        setbits_le32(&ehci->usbmode, CM_HOST);
+-       setbits_le32(&ehci->control, USB_EN);
+-
+        __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+        mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
+ 
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0033-i.MX2-Include-asm-types.h-in-arch-mx25-imx-regs.h.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0033-i.MX2-Include-asm-types.h-in-arch-mx25-imx-regs.h.patch
new file mode 100644
index 000000000..ba62b1a26
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0033-i.MX2-Include-asm-types.h-in-arch-mx25-imx-regs.h.patch
@@ -0,0 +1,36 @@
+From 8c1283e4c08528b009789303e112694d174cc1d1 Mon Sep 17 00:00:00 2001
+From: Timo Ketola <timo@exertus.fi>
+Date: Wed, 18 Apr 2012 22:55:34 +0000
+Subject: [PATCH 33/56] i.MX2: Include asm/types.h in arch-mx25/imx-regs.h
+types.h must be included in imx-regs.h if one wants to include
+imx-regs.h in a board configuration file. That for one's part is
+necessary, if one wants to use addresses defined in imx-regs.h.
+For example, fsl_esdhc.c needs CONFIG_SYS_FSL_ESDHC_ADDR defined and
+a proper thing is to define it with IMX_MMC_SDHCx_BASE in board
+configuration file. This patch fixes the build in that case.
+Signed-off-by: Timo Ketola <timo@exertus.fi>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ arch/arm/include/asm/arch-mx25/imx-regs.h |    3 +++
+ 1 file changed, 3 insertions(+)
+diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
+index 7f9449b..cf925d7 100644
+--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
+@@ -34,6 +34,9 @@
+ #define _IMX_REGS_H
+ 
+ #ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
+ #ifdef CONFIG_FEC_MXC
+ extern void mx25_fec_init_pins(void);
+ #endif
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0034-imx-Add-u-boot.imx-as-target-for-ARM9-i.MX-SOCs.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0034-imx-Add-u-boot.imx-as-target-for-ARM9-i.MX-SOCs.patch
new file mode 100644
index 000000000..692d16a4d
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0034-imx-Add-u-boot.imx-as-target-for-ARM9-i.MX-SOCs.patch
@@ -0,0 +1,28 @@
+From b2f6a61134714190757c7aa81c3ed935cff106fa Mon Sep 17 00:00:00 2001
+From: Timo Ketola <timo@exertus.fi>
+Date: Wed, 18 Apr 2012 22:55:35 +0000
+Subject: [PATCH 34/56] imx: Add u-boot.imx as target for ARM9 i.MX SOCs
+Signed-off-by: Timo Ketola <timo@exertus.fi>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ arch/arm/cpu/arm926ejs/config.mk |    6 ++++++
+ 1 file changed, 6 insertions(+)
+diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
+index ffb2e6c..6a3a1bb 100644
+--- a/arch/arm/cpu/arm926ejs/config.mk
+++ b/arch/arm/cpu/arm926ejs/config.mk
+@@ -31,3 +31,9 @@ PLATFORM_CPPFLAGS += -march=armv5te
+ # =========================================================================
+ PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
+ PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+
+ifneq ($(CONFIG_IMX_CONFIG),)
+
+ALL-y  += $(obj)u-boot.imx
+
+endif
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0035-pmic-dialog-Avoid-name-conflicts.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0035-pmic-dialog-Avoid-name-conflicts.patch
new file mode 100644
index 000000000..6675f8785
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0035-pmic-dialog-Avoid-name-conflicts.patch
@@ -0,0 +1,80 @@
+From dcb3005b3fec92efb7a874eceb7074d6062b07ab Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Mon, 7 May 2012 10:25:58 +0000
+Subject: [PATCH 35/56] pmic: dialog: Avoid name conflicts
+As mx53loco board has two variants: one with Dialog PMIC and another with FSL MC34708 PMIC,
+we need to be able to build both drivers.
+Change pmic_init() and PMIC_NUM_OF_REGS names to avoid build conflicts when both drivers are present.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ board/freescale/mx53loco/mx53loco.c |    2 +-
+ drivers/misc/pmic_dialog.c          |    4 ++--
+ include/dialog_pmic.h               |    2 +-
+ include/pmic.h                      |    1 +
+ 4 files changed, 5 insertions(+), 4 deletions(-)
+diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
+index 0dcec9b..7ed5c4e 100644
+--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
+@@ -322,7 +322,7 @@ static int power_init(void)
+        unsigned int val, ret;
+        struct pmic *p;
+ 
+-       pmic_init();
+       pmic_dialog_init();
+        p = get_pmic();
+ 
+        /* Set VDDA to 1.25V */
+diff --git a/drivers/misc/pmic_dialog.c b/drivers/misc/pmic_dialog.c
+index 7242073..e97af1d 100644
+--- a/drivers/misc/pmic_dialog.c
+++ b/drivers/misc/pmic_dialog.c
+@@ -20,13 +20,13 @@
+ #include <pmic.h>
+ #include <dialog_pmic.h>
+ 
+-int pmic_init(void)
+int pmic_dialog_init(void)
+ {
+        struct pmic *p = get_pmic();
+        static const char name[] = "DIALOG_PMIC";
+ 
+        p->name = name;
+-       p->number_of_regs = PMIC_NUM_OF_REGS;
+       p->number_of_regs = DIALOG_NUM_OF_REGS;
+ 
+        p->interface = PMIC_I2C;
+        p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR;
+diff --git a/include/dialog_pmic.h b/include/dialog_pmic.h
+index b0925f5..8d43585 100644
+--- a/include/dialog_pmic.h
+++ b/include/dialog_pmic.h
+@@ -164,7 +164,7 @@ enum {
+        DA9053_GPID7_REG,
+        DA9053_GPID8_REG,
+        DA9053_GPID9_REG,
+-       PMIC_NUM_OF_REGS,
+       DIALOG_NUM_OF_REGS,
+ };
+ 
+ #define DA_BUCKCORE_VBCORE_1_250V              0x1E
+diff --git a/include/pmic.h b/include/pmic.h
+index 52a1526..6a05b40 100644
+--- a/include/pmic.h
+++ b/include/pmic.h
+@@ -55,6 +55,7 @@ struct pmic {
+ };
+ 
+ int pmic_init(void);
+int pmic_dialog_init(void);
+ int check_reg(u32 reg);
+ struct pmic *get_pmic(void);
+ int pmic_probe(struct pmic *p);
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0036-mx53loco-Add-mc34708-support-and-set-mx53-frequency-.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0036-mx53loco-Add-mc34708-support-and-set-mx53-frequency-.patch
new file mode 100644
index 000000000..d6b353bd3
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0036-mx53loco-Add-mc34708-support-and-set-mx53-frequency-.patch
@@ -0,0 +1,124 @@
+From bb46787a684ee948eff96d5d9a7e6ff1632016ea Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Mon, 7 May 2012 10:25:59 +0000
+Subject: [PATCH 36/56] mx53loco: Add mc34708 support and set mx53 frequency
+ at 1GHz
+Add mc34708 support and set mx53 core frequency at its maximum value of 1GHz.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Acked-by: Jason Liu <r64343@freescale.com>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ board/freescale/mx53loco/mx53loco.c |   48 ++++++++++++++++++++++++++---------
+ include/configs/mx53loco.h          |    2 ++
+ include/fsl_pmic.h                  |   10 ++++++++
+ 3 files changed, 48 insertions(+), 12 deletions(-)
+diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
+index 7ed5c4e..8f5ded9 100644
+--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
+@@ -38,6 +38,7 @@
+ #include <asm/gpio.h>
+ #include <pmic.h>
+ #include <dialog_pmic.h>
+#include <fsl_pmic.h>
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+@@ -319,23 +320,46 @@ static void setup_iomux_i2c(void)
+ 
+ static int power_init(void)
+ {
+-       unsigned int val, ret;
+       unsigned int val;
+       int ret = -1;
+        struct pmic *p;
+ 
+-       pmic_dialog_init();
+-       p = get_pmic();
+       if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
+               pmic_dialog_init();
+               p = get_pmic();
+ 
+-       /* Set VDDA to 1.25V */
+-       val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
+-       ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
+               /* Set VDDA to 1.25V */
+               val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
+               ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
+ 
+-       ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+-       val |= DA9052_SUPPLY_VBCOREGO;
+-       ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+               ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+               val |= DA9052_SUPPLY_VBCOREGO;
+               ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+ 
+-       /* Set Vcc peripheral to 1.35V */
+-       ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
+-       ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+               /* Set Vcc peripheral to 1.30V */
+               ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
+               ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+       }
+
+       if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
+               pmic_init();
+               p = get_pmic();
+
+               /* Set VDDGP to 1.25V for 1GHz on SW1 */
+               pmic_reg_read(p, REG_SW_0, &val);
+               val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
+               ret = pmic_reg_write(p, REG_SW_0, val);
+
+               /* Set VCC as 1.30V on SW2 */
+               pmic_reg_read(p, REG_SW_1, &val);
+               val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
+               ret |= pmic_reg_write(p, REG_SW_1, val);
+
+               /* Set global reset timer to 4s */
+               pmic_reg_read(p, REG_POWER_CTL2, &val);
+               val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
+               ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
+       }
+ 
+        return ret;
+ }
+diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
+index 8f43eec..87f6ed1 100644
+--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
+@@ -97,7 +97,9 @@
+ #define CONFIG_PMIC
+ #define CONFIG_PMIC_I2C
+ #define CONFIG_DIALOG_PMIC
+#define CONFIG_PMIC_FSL
+ #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR        0x48
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR   0x8
+ 
+ /* allow to overwrite serial and ethaddr */
+ #define CONFIG_ENV_OVERWRITE
+diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h
+index 742f2e1..3b7cd37 100644
+--- a/include/fsl_pmic.h
+++ b/include/fsl_pmic.h
+@@ -122,4 +122,14 @@ enum {
+ /* Interrupt status 1 */
+ #define RTCRSTI                (1 << 7)
+ 
+/* MC34708 Definitions */
+#define SWx_VOLT_MASK_MC34708  0x3F
+#define SWx_1_250V_MC34708     0x30
+#define SWx_1_300V_MC34708     0x34
+#define TIMER_MASK_MC34708     0x300
+#define TIMER_4S_MC34708       0x100
+#define VUSBSEL_MC34708                (1 << 2)
+#define VUSBEN_MC34708         (1 << 3)
+#define SWBST_CTRL             31
+
+ #endif
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0037-mx53loco-Turn-on-VUSB-regulator.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0037-mx53loco-Turn-on-VUSB-regulator.patch
new file mode 100644
index 000000000..783c46040
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0037-mx53loco-Turn-on-VUSB-regulator.patch
@@ -0,0 +1,59 @@
+From b2297ec8b5d8efeee9adfed046afd8594f020b51 Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Mon, 7 May 2012 10:26:00 +0000
+Subject: [PATCH 37/56] mx53loco: Turn on VUSB regulator
+On the mx53loco board with mc34708 PMIC it is necessary to turn on VUSB regulator
+so that the mx53 USBH1 PHY receives the 3.3V voltage.
+Tested by inserting a USB pen drive in the upper USB slot (USBH1) and then issued the
+commands:
+usb start
+usb info
+,which correctly detected and printed the USB pen drive information.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Acked-by: Jason Liu <r64343@freescale.com>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ board/freescale/mx53loco/mx53loco.c |    9 +++++++++
+ include/fsl_pmic.h                  |    1 +
+ 2 files changed, 10 insertions(+)
+diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
+index 8f5ded9..a49b00a 100644
+--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
+@@ -359,6 +359,15 @@ static int power_init(void)
+                pmic_reg_read(p, REG_POWER_CTL2, &val);
+                val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
+                ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
+
+               /* Set VUSBSEL and VUSBEN for USB PHY supply*/
+               pmic_reg_read(p, REG_MODE_0, &val);
+               val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
+               ret |= pmic_reg_write(p, REG_MODE_0, val);
+
+               /* Set SWBST to 5V in auto mode */
+               val = SWBST_AUTO;
+               ret |= pmic_reg_write(p, SWBST_CTRL, val);
+        }
+ 
+        return ret;
+diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h
+index 3b7cd37..64c1e2e 100644
+--- a/include/fsl_pmic.h
+++ b/include/fsl_pmic.h
+@@ -131,5 +131,6 @@ enum {
+ #define VUSBSEL_MC34708                (1 << 2)
+ #define VUSBEN_MC34708         (1 << 3)
+ #define SWBST_CTRL             31
+#define SWBST_AUTO             0x8
+ 
+ #endif
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0038-mx53loco-Add-CONFIG_REVISION_TAG.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0038-mx53loco-Add-CONFIG_REVISION_TAG.patch
new file mode 100644
index 000000000..d6ee8e890
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0038-mx53loco-Add-CONFIG_REVISION_TAG.patch
@@ -0,0 +1,73 @@
+From c5d52c5258d93702c8963c608a770e5142c76167 Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Tue, 8 May 2012 03:40:49 +0000
+Subject: [PATCH 38/56] mx53loco: Add CONFIG_REVISION_TAG
+FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information.
+The kernel uses this data to distinguish between Dialog versus mc34708 based boards,
+and also to distinguish between revA and revB of the mc34708 based boards.
+Suggested-by: Yu Li <yk@magniel.com>
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ arch/arm/include/asm/arch-mx5/imx-regs.h |    5 +++++
+ board/freescale/mx53loco/mx53loco.c      |   12 ++++++++++++
+ include/configs/mx53loco.h               |    1 +
+ 3 files changed, 18 insertions(+)
+diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
+index 262517e..21c1bf5 100644
+--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
+@@ -486,6 +486,11 @@ struct iim_regs {
+        } bank[4];
+ };
+ 
+struct fuse_bank0_regs {
+       u32     fuse0_23[24];
+       u32     gp[8];
+};
+
+ struct fuse_bank1_regs {
+        u32     fuse0_8[9];
+        u32     mac_addr[6];
+diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
+index a49b00a..fb13895 100644
+--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
+@@ -62,6 +62,18 @@ void dram_init_banksize(void)
+        gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ }
+ 
+u32 get_board_rev(void)
+{
+       struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+       struct fuse_bank *bank = &iim->bank[0];
+       struct fuse_bank0_regs *fuse =
+               (struct fuse_bank0_regs *)bank->fuse_regs;
+
+       int rev = readl(&fuse->gp[6]);
+
+       return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+ static void setup_iomux_uart(void)
+ {
+        /* UART1 RXD */
+diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
+index 87f6ed1..eab0e27 100644
+--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
+@@ -43,6 +43,7 @@
+ #define CONFIG_BOARD_EARLY_INIT_F
+ #define CONFIG_BOARD_LATE_INIT
+ #define CONFIG_MXC_GPIO
+#define CONFIG_REVISION_TAG
+ 
+ #define CONFIG_MXC_UART
+ #define CONFIG_MXC_UART_BASE   UART1_BASE
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0039-mx53loco-Remove-unneeded-gpio_set_value.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0039-mx53loco-Remove-unneeded-gpio_set_value.patch
new file mode 100644
index 000000000..3c9135364
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0039-mx53loco-Remove-unneeded-gpio_set_value.patch
@@ -0,0 +1,36 @@
+From ab4f8321498b5d9605d2e1754fcba5752f1b9d2b Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Mon, 7 May 2012 10:42:57 +0000
+Subject: [PATCH 39/56] mx53loco: Remove unneeded gpio_set_value()
+There is no need to set the VBUS power enable to 0 first and then to 1.
+Set it to 1 in the gpio_direction_output() function.
+While at it, use the standard naming convention for the GPIO comment.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ board/freescale/mx53loco/mx53loco.c |    5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
+index fb13895..dec966d 100644
+--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
+@@ -97,10 +97,9 @@ static void setup_iomux_uart(void)
+ #ifdef CONFIG_USB_EHCI_MX5
+ int board_ehci_hcd_init(int port)
+ {
+-       /* request VBUS power enable pin, GPIO[8}, gpio7 */
+       /* request VBUS power enable pin, GPIO7_8 */
+        mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
+-       gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
+-       gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
+       gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
+        return 0;
+ }
+ #endif
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0040-spi-mxs-Introduce-spi_cs_is_valid.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0040-spi-mxs-Introduce-spi_cs_is_valid.patch
new file mode 100644
index 000000000..5af00e8c5
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0040-spi-mxs-Introduce-spi_cs_is_valid.patch
@@ -0,0 +1,47 @@
+From 99e963384668bdd678cea944c02ce47d223e7f0d Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Mon, 23 Apr 2012 08:30:49 +0000
+Subject: [PATCH 40/56] spi: mxs: Introduce spi_cs_is_valid()
+Introduce spi_cs_is_valid() for validating spi bus and chip select numbers.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Acked-by: Marek Vasut <marex@denx.de>
+Acked-by: Mike Frysinger <vapier@gentoo.org>
+---
+ drivers/spi/mxs_spi.c |   13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
+index 4e6f14e..e7237e7 100644
+--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
+@@ -51,14 +51,23 @@ void spi_init(void)
+ {
+ }
+ 
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       /* MXS SPI: 4 ports and 3 chip selects maximum */
+       if (bus > 3 || cs > 2)
+               return 0;
+       else
+               return 1;
+}
+
+ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+                                  unsigned int max_hz, unsigned int mode)
+ {
+        struct mxs_spi_slave *mxs_slave;
+        uint32_t addr;
+ 
+-       if (bus > 3) {
+-               printf("MXS SPI: Max bus number is 3\n");
+       if (!spi_cs_is_valid(bus, cs)) {
+               printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
+                return NULL;
+        }
+ 
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0041-spi-mxs-Allow-other-chip-selects-to-work.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0041-spi-mxs-Allow-other-chip-selects-to-work.patch
new file mode 100644
index 000000000..03a4fe9cc
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0041-spi-mxs-Allow-other-chip-selects-to-work.patch
@@ -0,0 +1,57 @@
+From f61ed79b5e9e95a15a7fa1e2180dfe7d64cd2d17 Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Mon, 23 Apr 2012 08:30:50 +0000
+Subject: [PATCH 41/56] spi: mxs: Allow other chip selects to work
+MXS SSP controller may have up to three chip selects per port: SS0, SS1 and SS2.
+Currently only SS0 is supported in the mxs_spi driver.
+Allow all the three chip select to work by selecting the desired one
+in bits 20 and 21 of the HW_SSP_CTRL0 register.
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+Acked-by: Marek Vasut <marex@denx.de>
+---
+ drivers/spi/mxs_spi.c |   10 ++++++++++
+ 1 file changed, 10 insertions(+)
+diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
+index e7237e7..7859536 100644
+--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
+@@ -34,6 +34,8 @@
+ 
+ #define        MXS_SPI_MAX_TIMEOUT     1000000
+ #define        MXS_SPI_PORT_OFFSET     0x2000
+#define MXS_SSP_CHIPSELECT_MASK                0x00300000
+#define MXS_SSP_CHIPSELECT_SHIFT       20
+ 
+ struct mxs_spi_slave {
+        struct spi_slave        slave;
+@@ -65,6 +67,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ {
+        struct mxs_spi_slave *mxs_slave;
+        uint32_t addr;
+       struct mx28_ssp_regs *ssp_regs;
+       int reg;
+ 
+        if (!spi_cs_is_valid(bus, cs)) {
+                printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
+@@ -82,7 +86,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+        mxs_slave->max_khz = max_hz / 1000;
+        mxs_slave->mode = mode;
+        mxs_slave->regs = (struct mx28_ssp_regs *)addr;
+       ssp_regs = mxs_slave->regs;
+ 
+       reg = readl(&ssp_regs->hw_ssp_ctrl0);
+       reg &= ~(MXS_SSP_CHIPSELECT_MASK);
+       reg |= cs << MXS_SSP_CHIPSELECT_SHIFT;
+
+       writel(reg, &ssp_regs->hw_ssp_ctrl0);
+        return &mxs_slave->slave;
+ }
+ 
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0042-i.MX28-Add-delay-after-CPU-bypass-is-cleared.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0042-i.MX28-Add-delay-after-CPU-bypass-is-cleared.patch
new file mode 100644
index 000000000..af60aa40c
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0042-i.MX28-Add-delay-after-CPU-bypass-is-cleared.patch
@@ -0,0 +1,53 @@
+From 070bb8e23c0f2eb5106854adbc432c67b3177598 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marex@denx.de>
+Date: Fri, 4 May 2012 01:32:50 +0000
+Subject: [PATCH 42/56] i.MX28: Add delay after CPU bypass is cleared
+This solves issues when larger amount of DRAM is used, like 256MB.
+Behave the same in case of CPU bypass as we do in case of EMI
+bypass, but wait 15 ms. We need to wait until the clock domain
+stabilizes.
+This issue seemed to have been caused by not waiting after frobbing
+with the CPU bypass, it was unrelated to memory, but had a direct
+impact, causing trouble. This was yet another X-File of the
+imx-bootlets, sigh. The conclusion is, trying a semi-random delay
+(there is delay after the EMI bypass change), the issue is fixed.
+Another possible explanation is that we do not do the "simple memory
+test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of
+the memory, while also outputing something on the serial port). This
+might have caused the similar delay in the imx-bootlets and therefore
+they didn't need to add this explicitly.
+For now, this seems good fix enough, but to me, whole that memory
+init code in imx-bootlets is completely flunked and it'd need deeper
+investigation.
+Signed-off-by: Marek Vasut <marex@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Fabio Estevam <festevam@gmail.com>
+Acked-by: Stefano Babic <sbabic@denx.de>
+Acked-by: Detlev Zundel <dzu@denx.de>
+---
+ arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c |    2 ++
+ 1 file changed, 2 insertions(+)
+diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+index 0f825ed..69c865e 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+@@ -149,6 +149,8 @@ void mx28_mem_setup_cpu_and_hbus(void)
+        /* Disable CPU bypass */
+        writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+                &clkctrl_regs->hw_clkctrl_clkseq_clr);
+
+       early_delay(15000);
+ }
+ 
+ void mx28_mem_setup_vdda(void)
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0043-MX5-PAD_CTL_DRV_VOT_LOW-and-PAD_CTL_DRV_VOT_HIGH-exc.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0043-MX5-PAD_CTL_DRV_VOT_LOW-and-PAD_CTL_DRV_VOT_HIGH-exc.patch
new file mode 100644
index 000000000..d6bf84a49
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0043-MX5-PAD_CTL_DRV_VOT_LOW-and-PAD_CTL_DRV_VOT_HIGH-exc.patch
@@ -0,0 +1,45 @@
+From 31b19f2736b7d1c5c209ff22a99aec1c3449fedc Mon Sep 17 00:00:00 2001
+From: Stefano Babic <sbabic@denx.de>
+Date: Wed, 9 May 2012 12:07:31 +0200
+Subject: [PATCH 43/56] MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH
+ exchanged
+After an update to the MX51 reference manual (Rev. 5), the
+values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH
+are now clearly wrong:
+"Bit 13:
+High / Low Output Voltage Range. This bit selects the output voltage mode for
+SD2_CMD. 0 High output voltage mode
+1 Low output voltage mode"
+The values are currently negated in code - fixed.
+Reported-by: David Jander <david.jander@protonic.nl>
+Signed-off-by: Stefano Babic <sbabic@denx.de>
+CC: Marek Vasut <marek.vasut@gmail.com>
+CC: David Jander <david.jander@protonic.nl>
+Acked-by: David Jander <david.jander@protonic.nl>
+Acked-by: Marek Vasut <marek.vasut@gmail.com>
+---
+ arch/arm/include/asm/arch-mx5/iomux.h |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h
+index 760371b..e3765a3 100644
+--- a/arch/arm/include/asm/arch-mx5/iomux.h
+++ b/arch/arm/include/asm/arch-mx5/iomux.h
+@@ -66,8 +66,8 @@ typedef enum iomux_pad_config {
+        PAD_CTL_HYS_ENABLE = 0x1 << 8,  /* Hysteresis enabled */
+        PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
+        PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
+-       PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */
+-       PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */
+       PAD_CTL_DRV_VOT_LOW = 0x1 << 13, /* Low voltage mode */
+       PAD_CTL_DRV_VOT_HIGH = 0x0 << 13,/* High voltage mode */
+ } iomux_pad_config_t;
+ 
+ /* various IOMUX input functions */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0044-M28EVK-Implement-support-for-new-board-V2.0.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0044-M28EVK-Implement-support-for-new-board-V2.0.patch
new file mode 100644
index 000000000..7b1e4f7c6
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0044-M28EVK-Implement-support-for-new-board-V2.0.patch
@@ -0,0 +1,92 @@
+From 890ec079f7ada8cd197e7dcc30ec00435b2560d5 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marex@denx.de>
+Date: Tue, 1 May 2012 11:09:42 +0000
+Subject: [PATCH 44/56] M28EVK: Implement support for new board V2.0
+Signed-off-by: Marek Vasut <marex@denx.de>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Fabio Estevam <fabio.estevam@freescale.com>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+---
+ board/denx/m28evk/m28evk.c   |   20 +++++++++++++++++++-
+ board/denx/m28evk/spl_boot.c |    8 ++++++--
+ 2 files changed, 25 insertions(+), 3 deletions(-)
+diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c
+index 53df476..3d28ea8 100644
+--- a/board/denx/m28evk/m28evk.c
+++ b/board/denx/m28evk/m28evk.c
+@@ -90,6 +90,8 @@ int board_mmc_init(bd_t *bis)
+ {
+        /* Configure WP as input. */
+        gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
+       /* Turn on the power to the card. */
+       gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+ 
+        return mxsmmc_initialize(bis, 0, m28_mmc_wp);
+ }
+@@ -103,10 +105,18 @@ int board_mmc_init(bd_t *bis)
+ 
+ int fecmxc_mii_postcall(int phy)
+ {
+#if    defined(CONFIG_DENX_M28_V11) || defined(CONFIG_DENX_M28_V10)
+       /* KZ8031 PHY on old boards. */
+       const uint32_t freq = 0x0080;
+#else
+       /* KZ8021 PHY on new boards. */
+       const uint32_t freq = 0x0000;
+#endif
+
+        miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
+        miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
+        if (phy == 3)
+-               miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
+               miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq);
+        return 0;
+ }
+ 
+@@ -123,6 +133,14 @@ int board_eth_init(bd_t *bis)
+                CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
+                CLKCTRL_ENET_TIME_SEL_RMII_CLK);
+ 
+#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
+       /* Reset the new PHY */
+       gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
+       udelay(10000);
+       gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1);
+       udelay(10000);
+#endif
+
+        ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+        if (ret) {
+                printf("FEC MXS: Unable to init FEC0\n");
+diff --git a/board/denx/m28evk/spl_boot.c b/board/denx/m28evk/spl_boot.c
+index a04fe18..7a12592 100644
+--- a/board/denx/m28evk/spl_boot.c
+++ b/board/denx/m28evk/spl_boot.c
+@@ -109,8 +109,9 @@ const iomux_cfg_t iomux_setup[] = {
+                (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+        MX28_PAD_SSP0_SCK__SSP0_SCK |
+                (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+-       MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0,     /* Power .. FIXME */
+-       MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP ... FIXME */
+       MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 |
+               (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),  /* Power */
+       MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP */
+ 
+        /* GPMI NAND */
+        MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+@@ -147,6 +148,9 @@ const iomux_cfg_t iomux_setup[] = {
+        MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+        MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
+        MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
+       MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */
+#endif
+ 
+        /* I2C */
+        MX28_PAD_I2C0_SCL__I2C0_SCL,
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0045-M28EVK-Add-SD-update-command.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0045-M28EVK-Add-SD-update-command.patch
new file mode 100644
index 000000000..c9a4d194f
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0045-M28EVK-Add-SD-update-command.patch
@@ -0,0 +1,47 @@
+From 9877804a0ec14f0582641bba8e5c9eec34e25c0e Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marex@denx.de>
+Date: Tue, 1 May 2012 11:09:43 +0000
+Subject: [PATCH 45/56] M28EVK: Add SD update command
+Add "update_sd_firmware" command to easily reload the SD card of
+m28evk kit. This comes handy when the board boots from SD card.
+Signed-off-by: Marek Vasut <marex@denx.de>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Fabio Estevam <fabio.estevam@freescale.com>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+---
+ include/configs/m28evk.h |    9 +++++++++
+ 1 file changed, 9 insertions(+)
+diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
+index 8cd5f31..60f8a6c 100644
+--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
+@@ -289,6 +289,7 @@
+ #define        CONFIG_EXTRA_ENV_SETTINGS                                       \
+        "update_nand_full_filename=u-boot.nand\0"                       \
+        "update_nand_firmware_filename=u-boot.sb\0"                     \
+       "update_sd_firmware_filename=u-boot.sd\0"                       \
+        "update_nand_firmware_maxsz=0x100000\0"                         \
+        "update_nand_stride=0x40\0"     /* MX28 datasheet ch. 12.12 */  \
+        "update_nand_count=0x4\0"       /* MX28 datasheet ch. 12.12 */  \
+@@ -315,6 +316,14 @@
+                "nand erase ${fcb_sz} ${fw_sz} ; "                      \
+                "nand write ${loadaddr} ${fcb_sz} ${filesize} ; "       \
+                "nand write ${loadaddr} ${fw_off} ${filesize} ; "       \
+               "fi\0"                                                  \
+       "update_sd_firmware="           /* Update the SD firmware partition */ \
+               "if mmc rescan ; then "                                 \
+               "if tftp ${update_sd_firmware_filename} ; then "        \
+               "setexpr fw_sz ${filesize} / 0x200 ; "  /* SD block size */ \
+               "setexpr fw_sz ${fw_sz} + 1 ; "                         \
+               "mmc write ${loadaddr} 0x800 ${fw_sz} ; "               \
+               "fi ; "                                                 \
+                "fi\0"
+ 
+ #endif /* __M28_H__ */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0046-i.MX28-Improve-passing-of-data-from-SPL-to-U-Boot.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0046-i.MX28-Improve-passing-of-data-from-SPL-to-U-Boot.patch
new file mode 100644
index 000000000..e84bd249c
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0046-i.MX28-Improve-passing-of-data-from-SPL-to-U-Boot.patch
@@ -0,0 +1,148 @@
+From b4a826714297d304a42bfbe6622e66bbdebe0f61 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marex@denx.de>
+Date: Tue, 1 May 2012 11:09:44 +0000
+Subject: [PATCH 46/56] i.MX28: Improve passing of data from SPL to U-Boot
+Pass memory size from SPL via structure located in SRAM instead of SCRATCH
+registers. This allows passing more data about boot from SPL to U-Boot, like the
+boot mode pads configuration.
+Signed-off-by: Marek Vasut <marex@denx.de>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Fabio Estevam <fabio.estevam@freescale.com>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+---
+ arch/arm/cpu/arm926ejs/mx28/mx28.c         |   16 +++++-----------
+ arch/arm/cpu/arm926ejs/mx28/mx28_init.h    |    1 +
+ arch/arm/cpu/arm926ejs/mx28/spl_boot.c     |    7 +++++++
+ arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c |   10 +++-------
+ arch/arm/include/asm/arch-mx28/sys_proto.h |    4 ++++
+ 5 files changed, 20 insertions(+), 18 deletions(-)
+diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c
+index dc0338d..54a68e1 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
+@@ -279,22 +279,16 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+ 
+ int mx28_dram_init(void)
+ {
+-       struct mx28_digctl_regs *digctl_regs =
+-               (struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
+-       uint32_t sz[2];
+       struct mx28_spl_data *data = (struct mx28_spl_data *)
+               ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+ 
+-       sz[0] = readl(&digctl_regs->hw_digctl_scratch0);
+-       sz[1] = readl(&digctl_regs->hw_digctl_scratch1);
+-
+-       if (sz[0] != sz[1]) {
+       if (data->mem_dram_size == 0) {
+                printf("MX28:\n"
+-                       "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n"
+-                       "HW_DIGCTRL_SCRATCH1 is not the same. Please\n"
+-                       "verify these two registers contain valid RAM size!\n");
+                       "Error, the RAM size passed up from SPL is 0!\n");
+                hang();
+        }
+ 
+-       gd->ram_size = sz[0];
+       gd->ram_size = data->mem_dram_size;
+        return 0;
+ }
+ 
+diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h
+index 98d3631..8eac958 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h
+@@ -37,5 +37,6 @@ static inline void mx28_power_wait_pswitch(void) { }
+ #endif
+ 
+ void mx28_mem_init(void);
+uint32_t mx28_mem_get_size(void);
+ 
+ #endif /* __M28_INIT_H__ */
+diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c
+index dfb8309..37e1eb7 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c
+@@ -28,6 +28,7 @@
+ #include <asm/io.h>
+ #include <asm/arch/iomux-mx28.h>
+ #include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+ 
+ #include "mx28_init.h"
+ 
+@@ -49,9 +50,15 @@ void early_delay(int delay)
+ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+                        const unsigned int iomux_size)
+ {
+       struct mx28_spl_data *data = (struct mx28_spl_data *)
+               ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+
+        mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
+        mx28_power_init();
+
+        mx28_mem_init();
+       data->mem_dram_size = mx28_mem_get_size();
+
+        mx28_power_wait_pswitch();
+ }
+ 
+diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+index 69c865e..9fa5d29 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+@@ -175,10 +175,8 @@ void mx28_mem_setup_vddd(void)
+                &power_regs->hw_power_vdddctrl);
+ }
+ 
+-void mx28_mem_get_size(void)
+uint32_t mx28_mem_get_size(void)
+ {
+-       struct mx28_digctl_regs *digctl_regs =
+-               (struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
+        uint32_t sz, da;
+        uint32_t *vt = (uint32_t *)0x20;
+        /* The following is "subs pc, r14, #4", used as return from DABT. */
+@@ -189,11 +187,11 @@ void mx28_mem_get_size(void)
+        vt[4] = data_abort_memdetect_handler;
+ 
+        sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+-       writel(sz, &digctl_regs->hw_digctl_scratch0);
+-       writel(sz, &digctl_regs->hw_digctl_scratch1);
+ 
+        /* Restore the old DABT handler. */
+        vt[4] = da;
+
+       return sz;
+ }
+ 
+ void mx28_mem_init(void)
+@@ -241,6 +239,4 @@ void mx28_mem_init(void)
+        early_delay(10000);
+ 
+        mx28_mem_setup_cpu_and_hbus();
+-
+-       mx28_mem_get_size();
+ }
+diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h
+index 15d8de3..04f2e4d 100644
+--- a/arch/arm/include/asm/arch-mx28/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx28/sys_proto.h
+@@ -39,6 +39,10 @@ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+                        const unsigned int iomux_size);
+ #endif
+ 
+struct mx28_spl_data {
+       uint32_t        mem_dram_size;
+};
+
+ int mx28_dram_init(void);
+ 
+ #endif /* __MX28_H__ */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0047-i.MX28-Implement-boot-pads-sampling-and-reporting.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0047-i.MX28-Implement-boot-pads-sampling-and-reporting.patch
new file mode 100644
index 000000000..e9153723c
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0047-i.MX28-Implement-boot-pads-sampling-and-reporting.patch
@@ -0,0 +1,181 @@
+From a950701d418e2e103cdfcd2f5880816dc1c6e6ec Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marex@denx.de>
+Date: Tue, 1 May 2012 11:09:45 +0000
+Subject: [PATCH 47/56] i.MX28: Implement boot pads sampling and reporting
+This patch implements code that samples i.MX28 boot pads and reports boot mode
+accordingly.
+Signed-off-by: Marek Vasut <marex@denx.de>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Fabio Estevam <fabio.estevam@freescale.com>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+---
+ arch/arm/cpu/arm926ejs/mx28/mx28.c         |    4 +++
+ arch/arm/cpu/arm926ejs/mx28/spl_boot.c     |   48 ++++++++++++++++++++++++++++
+ arch/arm/include/asm/arch-mx28/sys_proto.h |   26 +++++++++++++++
+ include/configs/m28evk.h                   |    1 +
+ include/configs/mx28evk.h                  |    1 +
+ 5 files changed, 80 insertions(+)
+diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c
+index 54a68e1..865dbb3 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
+@@ -185,8 +185,12 @@ int arch_cpu_init(void)
+ #if defined(CONFIG_DISPLAY_CPUINFO)
+ int print_cpuinfo(void)
+ {
+       struct mx28_spl_data *data = (struct mx28_spl_data *)
+               ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+
+        printf("Freescale i.MX28 family at %d MHz\n",
+                        mxc_get_clock(MXC_ARM_CLK) / 1000000);
+       printf("BOOT:  %s\n", mx28_boot_modes[data->boot_mode_idx].mode);
+        return 0;
+ }
+ #endif
+diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c
+index 37e1eb7..c9b4566 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c
+@@ -29,6 +29,7 @@
+ #include <asm/arch/iomux-mx28.h>
+ #include <asm/arch/imx-regs.h>
+ #include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+ 
+ #include "mx28_init.h"
+ 
+@@ -47,11 +48,56 @@ void early_delay(int delay)
+                ;
+ }
+ 
+#define        MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+const iomux_cfg_t iomux_boot[] = {
+       MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
+       MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
+       MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
+       MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
+       MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
+       MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
+};
+
+uint8_t mx28_get_bootmode_index(void)
+{
+       uint8_t bootmode = 0;
+       int i;
+       uint8_t masked;
+
+       /* Setup IOMUX of bootmode pads to GPIO */
+       mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
+
+       /* Setup bootmode pins as GPIO input */
+       gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0);
+       gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1);
+       gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2);
+       gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3);
+       gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4);
+       gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5);
+
+       /* Read bootmode pads */
+       bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
+       bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
+       bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
+       bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
+       bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
+       bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
+
+       for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) {
+               masked = bootmode & mx28_boot_modes[i].boot_mask;
+               if (masked == mx28_boot_modes[i].boot_pads)
+                       break;
+       }
+
+       return i;
+}
+
+ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+                        const unsigned int iomux_size)
+ {
+        struct mx28_spl_data *data = (struct mx28_spl_data *)
+                ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+       uint8_t bootmode = mx28_get_bootmode_index();
+ 
+        mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
+        mx28_power_init();
+@@ -59,6 +105,8 @@ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+        mx28_mem_init();
+        data->mem_dram_size = mx28_mem_get_size();
+ 
+       data->boot_mode_idx = bootmode;
+
+        mx28_power_wait_pswitch();
+ }
+ 
+diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h
+index 04f2e4d..e701c64 100644
+--- a/arch/arm/include/asm/arch-mx28/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx28/sys_proto.h
+@@ -39,7 +39,33 @@ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+                        const unsigned int iomux_size);
+ #endif
+ 
+struct mx28_pair {
+       uint8_t boot_pads;
+       uint8_t boot_mask;
+       const char *mode;
+};
+
+static const struct mx28_pair mx28_boot_modes[] = {
+       { 0x00, 0x0f, "USB #0" },
+       { 0x01, 0x1f, "I2C #0, master, 3V3" },
+       { 0x11, 0x1f, "I2C #0, master, 1V8" },
+       { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
+       { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
+       { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
+       { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
+       { 0x04, 0x1f, "NAND, 3V3" },
+       { 0x14, 0x1f, "NAND, 1V8" },
+       { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
+       { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
+       { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
+       { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
+       { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
+       { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
+       { 0x00, 0x00, "Reserved/Unknown/Wrong" },
+};
+
+ struct mx28_spl_data {
+       uint8_t         boot_mode_idx;
+        uint32_t        mem_dram_size;
+ };
+ 
+diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
+index 60f8a6c..c62f4d0 100644
+--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
+@@ -54,6 +54,7 @@
+ #define        CONFIG_SPL_LDSCRIPT     "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
+ #define        CONFIG_SPL_LIBCOMMON_SUPPORT
+ #define        CONFIG_SPL_LIBGENERIC_SUPPORT
+#define        CONFIG_SPL_GPIO_SUPPORT
+ 
+ /*
+  * U-Boot Commands
+diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
+index 5cd9730..0c18e50 100644
+--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
+@@ -46,6 +46,7 @@
+ #define CONFIG_SPL_LDSCRIPT    "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
+ #define CONFIG_SPL_LIBCOMMON_SUPPORT
+ #define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+ 
+ /*
+  * U-Boot Commands
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0048-i.MX28-Add-LCDIF-register-definitions.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0048-i.MX28-Add-LCDIF-register-definitions.patch
new file mode 100644
index 000000000..f7f8c79d4
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0048-i.MX28-Add-LCDIF-register-definitions.patch
@@ -0,0 +1,249 @@
+From c4132c660f8e5e2f05b4f7e284f0ae516a10bb8a Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Tue, 1 May 2012 11:09:46 +0000
+Subject: [PATCH 48/56] i.MX28: Add LCDIF register definitions
+Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Fabio Estevam <festevam@gmail.com>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+---
+ arch/arm/include/asm/arch-mx28/imx-regs.h   |    1 +
+ arch/arm/include/asm/arch-mx28/regs-lcdif.h |  212 +++++++++++++++++++++++++++
+ 2 files changed, 213 insertions(+)
+ create mode 100644 arch/arm/include/asm/arch-mx28/regs-lcdif.h
+diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h
+index f9e6c53..581bf0a 100644
+--- a/arch/arm/include/asm/arch-mx28/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx28/imx-regs.h
+@@ -30,6 +30,7 @@
+ #include <asm/arch/regs-digctl.h>
+ #include <asm/arch/regs-gpmi.h>
+ #include <asm/arch/regs-i2c.h>
+#include <asm/arch/regs-lcdif.h>
+ #include <asm/arch/regs-ocotp.h>
+ #include <asm/arch/regs-pinctrl.h>
+ #include <asm/arch/regs-power.h>
+diff --git a/arch/arm/include/asm/arch-mx28/regs-lcdif.h b/arch/arm/include/asm/arch-mx28/regs-lcdif.h
+new file mode 100644
+index 0000000..cb47e41
+--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-lcdif.h
+@@ -0,0 +1,212 @@
+/*
+ * Freescale i.MX28 LCDIF Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_LCDIF_H__
+#define __MX28_REGS_LCDIF_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef        __ASSEMBLY__
+struct mx28_lcdif_regs {
+       mx28_reg_32(hw_lcdif_ctrl)              /* 0x00 */
+       mx28_reg_32(hw_lcdif_ctrl1)             /* 0x10 */
+       mx28_reg_32(hw_lcdif_ctrl2)             /* 0x20 */
+       mx28_reg_32(hw_lcdif_transfer_count)    /* 0x30 */
+       mx28_reg_32(hw_lcdif_cur_buf)           /* 0x40 */
+       mx28_reg_32(hw_lcdif_next_buf)          /* 0x50 */
+       mx28_reg_32(hw_lcdif_timing)            /* 0x60 */
+       mx28_reg_32(hw_lcdif_vdctrl0)           /* 0x70 */
+       mx28_reg_32(hw_lcdif_vdctrl1)           /* 0x80 */
+       mx28_reg_32(hw_lcdif_vdctrl2)           /* 0x90 */
+       mx28_reg_32(hw_lcdif_vdctrl3)           /* 0xa0 */
+       mx28_reg_32(hw_lcdif_vdctrl4)           /* 0xb0 */
+       mx28_reg_32(hw_lcdif_dvictrl0)          /* 0xc0 */
+       mx28_reg_32(hw_lcdif_dvictrl1)          /* 0xd0 */
+       mx28_reg_32(hw_lcdif_dvictrl2)          /* 0xe0 */
+       mx28_reg_32(hw_lcdif_dvictrl3)          /* 0xf0 */
+       mx28_reg_32(hw_lcdif_dvictrl4)          /* 0x100 */
+       mx28_reg_32(hw_lcdif_csc_coeffctrl0)    /* 0x110 */
+       mx28_reg_32(hw_lcdif_csc_coeffctrl1)    /* 0x120 */
+       mx28_reg_32(hw_lcdif_csc_coeffctrl2)    /* 0x130 */
+       mx28_reg_32(hw_lcdif_csc_coeffctrl3)    /* 0x140 */
+       mx28_reg_32(hw_lcdif_csc_coeffctrl4)    /* 0x150 */
+       mx28_reg_32(hw_lcdif_csc_offset)        /* 0x160 */
+       mx28_reg_32(hw_lcdif_csc_limit)         /* 0x170 */
+       mx28_reg_32(hw_lcdif_data)              /* 0x180 */
+       mx28_reg_32(hw_lcdif_bm_error_stat)     /* 0x190 */
+       mx28_reg_32(hw_lcdif_crc_stat)          /* 0x1a0 */
+       mx28_reg_32(hw_lcdif_lcdif_stat)        /* 0x1b0 */
+       mx28_reg_32(hw_lcdif_version)           /* 0x1c0 */
+       mx28_reg_32(hw_lcdif_debug0)            /* 0x1d0 */
+       mx28_reg_32(hw_lcdif_debug1)            /* 0x1e0 */
+       mx28_reg_32(hw_lcdif_debug2)            /* 0x1f0 */
+};
+#endif
+
+#define        LCDIF_CTRL_SFTRST                                       (1 << 31)
+#define        LCDIF_CTRL_CLKGATE                                      (1 << 30)
+#define        LCDIF_CTRL_YCBCR422_INPUT                               (1 << 29)
+#define        LCDIF_CTRL_READ_WRITEB                                  (1 << 28)
+#define        LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                          (1 << 27)
+#define        LCDIF_CTRL_DATA_SHIFT_DIR                               (1 << 26)
+#define        LCDIF_CTRL_SHIFT_NUM_BITS_MASK                          (0x1f << 21)
+#define        LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET                        21
+#define        LCDIF_CTRL_DVI_MODE                                     (1 << 20)
+#define        LCDIF_CTRL_BYPASS_COUNT                                 (1 << 19)
+#define        LCDIF_CTRL_VSYNC_MODE                                   (1 << 18)
+#define        LCDIF_CTRL_DOTCLK_MODE                                  (1 << 17)
+#define        LCDIF_CTRL_DATA_SELECT                                  (1 << 16)
+#define        LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK                      (0x3 << 14)
+#define        LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET                    14
+#define        LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK                        (0x3 << 12)
+#define        LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET                      12
+#define        LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK                       (0x3 << 10)
+#define        LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET                     10
+#define        LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT                      (0 << 10)
+#define        LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT                       (1 << 10)
+#define        LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT                      (2 << 10)
+#define        LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT                      (3 << 10)
+#define        LCDIF_CTRL_WORD_LENGTH_MASK                             (0x3 << 8)
+#define        LCDIF_CTRL_WORD_LENGTH_OFFSET                           8
+#define        LCDIF_CTRL_WORD_LENGTH_16BIT                            (0 << 8)
+#define        LCDIF_CTRL_WORD_LENGTH_8BIT                             (1 << 8)
+#define        LCDIF_CTRL_WORD_LENGTH_18BIT                            (2 << 8)
+#define        LCDIF_CTRL_WORD_LENGTH_24BIT                            (3 << 8)
+#define        LCDIF_CTRL_RGB_TO_YCBCR422_CSC                          (1 << 7)
+#define        LCDIF_CTRL_LCDIF_MASTER                                 (1 << 5)
+#define        LCDIF_CTRL_DATA_FORMAT_16_BIT                           (1 << 3)
+#define        LCDIF_CTRL_DATA_FORMAT_18_BIT                           (1 << 2)
+#define        LCDIF_CTRL_DATA_FORMAT_24_BIT                           (1 << 1)
+#define        LCDIF_CTRL_RUN                                          (1 << 0)
+
+#define        LCDIF_CTRL1_COMBINE_MPU_WR_STRB                         (1 << 27)
+#define        LCDIF_CTRL1_BM_ERROR_IRQ_EN                             (1 << 26)
+#define        LCDIF_CTRL1_BM_ERROR_IRQ                                (1 << 25)
+#define        LCDIF_CTRL1_RECOVER_ON_UNDERFLOW                        (1 << 24)
+#define        LCDIF_CTRL1_INTERLACE_FIELDS                            (1 << 23)
+#define        LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD           (1 << 22)
+#define        LCDIF_CTRL1_FIFO_CLEAR                                  (1 << 21)
+#define        LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS                     (1 << 20)
+#define        LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK                    (0xf << 16)
+#define        LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET                  16
+#define        LCDIF_CTRL1_OVERFLOW_IRQ_EN                             (1 << 15)
+#define        LCDIF_CTRL1_UNDERFLOW_IRQ_EN                            (1 << 14)
+#define        LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                       (1 << 13)
+#define        LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                           (1 << 12)
+#define        LCDIF_CTRL1_OVERFLOW_IRQ                                (1 << 11)
+#define        LCDIF_CTRL1_UNDERFLOW_IRQ                               (1 << 10)
+#define        LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                          (1 << 9)
+#define        LCDIF_CTRL1_VSYNC_EDGE_IRQ                              (1 << 8)
+#define        LCDIF_CTRL1_BUSY_ENABLE                                 (1 << 2)
+#define        LCDIF_CTRL1_MODE86                                      (1 << 1)
+#define        LCDIF_CTRL1_RESET                                       (1 << 0)
+
+#define        LCDIF_CTRL2_OUTSTANDING_REQS_MASK                       (0x7 << 21)
+#define        LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET                     21
+#define        LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1                      (0x0 << 21)
+#define        LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2                      (0x1 << 21)
+#define        LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4                      (0x2 << 21)
+#define        LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8                      (0x3 << 21)
+#define        LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16                     (0x4 << 21)
+#define        LCDIF_CTRL2_BURST_LEN_8                                 (1 << 20)
+#define        LCDIF_CTRL2_ODD_LINE_PATTERN_MASK                       (0x7 << 16)
+#define        LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET                     16
+#define        LCDIF_CTRL2_ODD_LINE_PATTERN_RGB                        (0x0 << 16)
+#define        LCDIF_CTRL2_ODD_LINE_PATTERN_RBG                        (0x1 << 16)
+#define        LCDIF_CTRL2_ODD_LINE_PATTERN_GBR                        (0x2 << 16)
+#define        LCDIF_CTRL2_ODD_LINE_PATTERN_GRB                        (0x3 << 16)
+#define        LCDIF_CTRL2_ODD_LINE_PATTERN_BRG                        (0x4 << 16)
+#define        LCDIF_CTRL2_ODD_LINE_PATTERN_BGR                        (0x5 << 16)
+#define        LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK                      (0x7 << 12)
+#define        LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET                    12
+#define        LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB                       (0x0 << 12)
+#define        LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG                       (0x1 << 12)
+#define        LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR                       (0x2 << 12)
+#define        LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB                       (0x3 << 12)
+#define        LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG                       (0x4 << 12)
+#define        LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR                       (0x5 << 12)
+#define        LCDIF_CTRL2_READ_PACK_DIR                               (1 << 10)
+#define        LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT              (1 << 9)
+#define        LCDIF_CTRL2_READ_MODE_6_BIT_INPUT                       (1 << 8)
+#define        LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK          (0x7 << 4)
+#define        LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET        4
+#define        LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK                     (0x7 << 1)
+#define        LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET                   1
+
+#define        LCDIF_TRANSFER_COUNT_V_COUNT_MASK                       (0xffff << 16)
+#define        LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET                     16
+#define        LCDIF_TRANSFER_COUNT_H_COUNT_MASK                       (0xffff << 0)
+#define        LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET                     0
+
+#define        LCDIF_CUR_BUF_ADDR_MASK                                 0xffffffff
+#define        LCDIF_CUR_BUF_ADDR_OFFSET                               0
+
+#define        LCDIF_NEXT_BUF_ADDR_MASK                                0xffffffff
+#define        LCDIF_NEXT_BUF_ADDR_OFFSET                              0
+
+#define        LCDIF_TIMING_CMD_HOLD_MASK                              (0xff << 24)
+#define        LCDIF_TIMING_CMD_HOLD_OFFSET                            24
+#define        LCDIF_TIMING_CMD_SETUP_MASK                             (0xff << 16)
+#define        LCDIF_TIMING_CMD_SETUP_OFFSET                           16
+#define        LCDIF_TIMING_DATA_HOLD_MASK                             (0xff << 8)
+#define        LCDIF_TIMING_DATA_HOLD_OFFSET                           8
+#define        LCDIF_TIMING_DATA_SETUP_MASK                            (0xff << 0)
+#define        LCDIF_TIMING_DATA_SETUP_OFFSET                          0
+
+#define        LCDIF_VDCTRL0_VSYNC_OEB                                 (1 << 29)
+#define        LCDIF_VDCTRL0_ENABLE_PRESENT                            (1 << 28)
+#define        LCDIF_VDCTRL0_VSYNC_POL                                 (1 << 27)
+#define        LCDIF_VDCTRL0_HSYNC_POL                                 (1 << 26)
+#define        LCDIF_VDCTRL0_DOTCLK_POL                                (1 << 25)
+#define        LCDIF_VDCTRL0_ENABLE_POL                                (1 << 24)
+#define        LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT                         (1 << 21)
+#define        LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT                    (1 << 20)
+#define        LCDIF_VDCTRL0_HALF_LINE                                 (1 << 19)
+#define        LCDIF_VDCTRL0_HALF_LINE_MODE                            (1 << 18)
+#define        LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK                    0x3ffff
+#define        LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET                  0
+
+#define        LCDIF_VDCTRL1_VSYNC_PERIOD_MASK                         0xffffffff
+#define        LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET                       0
+
+#define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK                    (0x3fff << 18)
+#define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET                  18
+#define        LCDIF_VDCTRL2_HSYNC_PERIOD_MASK                         0x3ffff
+#define        LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET                       0
+
+#define        LCDIF_VDCTRL3_MUX_SYNC_SIGNALS                          (1 << 29)
+#define        LCDIF_VDCTRL3_VSYNC_ONLY                                (1 << 28)
+#define        LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK                  (0xfff << 16)
+#define        LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET                16
+#define        LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK                    (0xffff << 0)
+#define        LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET                  0
+
+#define        LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK                       (0x7 << 29)
+#define        LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET                     29
+#define        LCDIF_VDCTRL4_SYNC_SIGNALS_ON                           (1 << 18)
+#define        LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK              0x3ffff
+#define        LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET            0
+
+#endif /* __MX28_REGS_LCDIF_H__ */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0049-i.MX28-Shut-down-the-LCD-controller-before-reset.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0049-i.MX28-Shut-down-the-LCD-controller-before-reset.patch
new file mode 100644
index 000000000..724477fa2
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0049-i.MX28-Shut-down-the-LCD-controller-before-reset.patch
@@ -0,0 +1,43 @@
+From 589511bd8e847c1990216aa89e56dca0fabac4e2 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marex@denx.de>
+Date: Tue, 1 May 2012 11:09:47 +0000
+Subject: [PATCH 49/56] i.MX28: Shut down the LCD controller before reset
+If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF
+data pins interferes with the BootROM's boot mode sampling. So shut the
+controller down.
+Signed-off-by: Marek Vasut <marex@denx.de>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Fabio Estevam <festevam@gmail.com>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+---
+ arch/arm/cpu/arm926ejs/mx28/mx28.c |    9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c
+index 865dbb3..a82ff25 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
+@@ -51,9 +51,16 @@ void reset_cpu(ulong ignored) __attribute__((noreturn));
+ 
+ void reset_cpu(ulong ignored)
+ {
+-
+        struct mx28_rtc_regs *rtc_regs =
+                (struct mx28_rtc_regs *)MXS_RTC_BASE;
+       struct mx28_lcdif_regs *lcdif_regs =
+               (struct mx28_lcdif_regs *)MXS_LCDIF_BASE;
+
+       /*
+        * Shut down the LCD controller as it interferes with BootROM boot mode
+        * pads sampling.
+        */
+       writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
+ 
+        /* Wait 1 uS before doing the actual watchdog reset */
+        writel(1, &rtc_regs->hw_rtc_watchdog);
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0050-i.MX28-Add-LRADC-register-definitions.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0050-i.MX28-Add-LRADC-register-definitions.patch
new file mode 100644
index 000000000..0717e16b1
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0050-i.MX28-Add-LRADC-register-definitions.patch
@@ -0,0 +1,437 @@
+From dfc17c49a75e682b9ef56985bdb5793863019f6b Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Tue, 1 May 2012 11:09:48 +0000
+Subject: [PATCH 50/56] i.MX28: Add LRADC register definitions
+Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Fabio Estevam <fabio.estevam@freescale.com>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+---
+ arch/arm/include/asm/arch-mx28/imx-regs.h   |    1 +
+ arch/arm/include/asm/arch-mx28/regs-lradc.h |  400 +++++++++++++++++++++++++++
+ 2 files changed, 401 insertions(+)
+ create mode 100644 arch/arm/include/asm/arch-mx28/regs-lradc.h
+diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h
+index 581bf0a..37d0a93 100644
+--- a/arch/arm/include/asm/arch-mx28/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx28/imx-regs.h
+@@ -31,6 +31,7 @@
+ #include <asm/arch/regs-gpmi.h>
+ #include <asm/arch/regs-i2c.h>
+ #include <asm/arch/regs-lcdif.h>
+#include <asm/arch/regs-lradc.h>
+ #include <asm/arch/regs-ocotp.h>
+ #include <asm/arch/regs-pinctrl.h>
+ #include <asm/arch/regs-power.h>
+diff --git a/arch/arm/include/asm/arch-mx28/regs-lradc.h b/arch/arm/include/asm/arch-mx28/regs-lradc.h
+new file mode 100644
+index 0000000..16e2bbf
+--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-lradc.h
+@@ -0,0 +1,400 @@
+/*
+ * Freescale i.MX28 LRADC Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_LRADC_H__
+#define __MX28_REGS_LRADC_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef        __ASSEMBLY__
+struct mx28_lradc_regs {
+       mx28_reg_32(hw_lradc_ctrl0);
+       mx28_reg_32(hw_lradc_ctrl1);
+       mx28_reg_32(hw_lradc_ctrl2);
+       mx28_reg_32(hw_lradc_ctrl3);
+       mx28_reg_32(hw_lradc_status);
+       mx28_reg_32(hw_lradc_ch0);
+       mx28_reg_32(hw_lradc_ch1);
+       mx28_reg_32(hw_lradc_ch2);
+       mx28_reg_32(hw_lradc_ch3);
+       mx28_reg_32(hw_lradc_ch4);
+       mx28_reg_32(hw_lradc_ch5);
+       mx28_reg_32(hw_lradc_ch6);
+       mx28_reg_32(hw_lradc_ch7);
+       mx28_reg_32(hw_lradc_delay0);
+       mx28_reg_32(hw_lradc_delay1);
+       mx28_reg_32(hw_lradc_delay2);
+       mx28_reg_32(hw_lradc_delay3);
+       mx28_reg_32(hw_lradc_debug0);
+       mx28_reg_32(hw_lradc_debug1);
+       mx28_reg_32(hw_lradc_conversion);
+       mx28_reg_32(hw_lradc_ctrl4);
+       mx28_reg_32(hw_lradc_treshold0);
+       mx28_reg_32(hw_lradc_treshold1);
+       mx28_reg_32(hw_lradc_version);
+};
+#endif
+
+#define        LRADC_CTRL0_SFTRST                                      (1 << 31)
+#define        LRADC_CTRL0_CLKGATE                                     (1 << 30)
+#define        LRADC_CTRL0_ONCHIP_GROUNDREF                            (1 << 26)
+#define        LRADC_CTRL0_BUTTON1_DETECT_ENABLE                       (1 << 25)
+#define        LRADC_CTRL0_BUTTON0_DETECT_ENABLE                       (1 << 24)
+#define        LRADC_CTRL0_TOUCH_DETECT_ENABLE                         (1 << 23)
+#define        LRADC_CTRL0_TOUCH_SCREEN_TYPE                           (1 << 22)
+#define        LRADC_CTRL0_YNLRSW                                      (1 << 21)
+#define        LRADC_CTRL0_YPLLSW_MASK                                 (0x3 << 19)
+#define        LRADC_CTRL0_YPLLSW_OFFSET                               19
+#define        LRADC_CTRL0_XNURSW_MASK                                 (0x3 << 17)
+#define        LRADC_CTRL0_XNURSW_OFFSET                               17
+#define        LRADC_CTRL0_XPULSW                                      (1 << 16)
+#define        LRADC_CTRL0_SCHEDULE_MASK                               0xff
+#define        LRADC_CTRL0_SCHEDULE_OFFSET                             0
+
+#define        LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN                       (1 << 28)
+#define        LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN                       (1 << 27)
+#define        LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN                    (1 << 26)
+#define        LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN                    (1 << 25)
+#define        LRADC_CTRL1_TOUCH_DETECT_IRQ_EN                         (1 << 24)
+#define        LRADC_CTRL1_LRADC7_IRQ_EN                               (1 << 23)
+#define        LRADC_CTRL1_LRADC6_IRQ_EN                               (1 << 22)
+#define        LRADC_CTRL1_LRADC5_IRQ_EN                               (1 << 21)
+#define        LRADC_CTRL1_LRADC4_IRQ_EN                               (1 << 20)
+#define        LRADC_CTRL1_LRADC3_IRQ_EN                               (1 << 19)
+#define        LRADC_CTRL1_LRADC2_IRQ_EN                               (1 << 18)
+#define        LRADC_CTRL1_LRADC1_IRQ_EN                               (1 << 17)
+#define        LRADC_CTRL1_LRADC0_IRQ_EN                               (1 << 16)
+#define        LRADC_CTRL1_BUTTON1_DETECT_IRQ                          (1 << 12)
+#define        LRADC_CTRL1_BUTTON0_DETECT_IRQ                          (1 << 11)
+#define        LRADC_CTRL1_THRESHOLD1_DETECT_IRQ                       (1 << 10)
+#define        LRADC_CTRL1_THRESHOLD0_DETECT_IRQ                       (1 << 9)
+#define        LRADC_CTRL1_TOUCH_DETECT_IRQ                            (1 << 8)
+#define        LRADC_CTRL1_LRADC7_IRQ                                  (1 << 7)
+#define        LRADC_CTRL1_LRADC6_IRQ                                  (1 << 6)
+#define        LRADC_CTRL1_LRADC5_IRQ                                  (1 << 5)
+#define        LRADC_CTRL1_LRADC4_IRQ                                  (1 << 4)
+#define        LRADC_CTRL1_LRADC3_IRQ                                  (1 << 3)
+#define        LRADC_CTRL1_LRADC2_IRQ                                  (1 << 2)
+#define        LRADC_CTRL1_LRADC1_IRQ                                  (1 << 1)
+#define        LRADC_CTRL1_LRADC0_IRQ                                  (1 << 0)
+
+#define        LRADC_CTRL2_DIVIDE_BY_TWO_MASK                          (0xff << 24)
+#define        LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET                        24
+#define        LRADC_CTRL2_TEMPSENSE_PWD                               (1 << 15)
+#define        LRADC_CTRL2_VTHSENSE_MASK                               (0x3 << 13)
+#define        LRADC_CTRL2_VTHSENSE_OFFSET                             13
+#define        LRADC_CTRL2_DISABLE_MUXAMP_BYPASS                       (1 << 12)
+#define        LRADC_CTRL2_TEMP_SENSOR_IENABLE1                        (1 << 9)
+#define        LRADC_CTRL2_TEMP_SENSOR_IENABLE0                        (1 << 8)
+#define        LRADC_CTRL2_TEMP_ISRC1_MASK                             (0xf << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_OFFSET                           4
+#define        LRADC_CTRL2_TEMP_ISRC1_300                              (0xf << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_280                              (0xe << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_260                              (0xd << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_240                              (0xc << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_220                              (0xb << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_200                              (0xa << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_180                              (0x9 << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_160                              (0x8 << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_140                              (0x7 << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_120                              (0x6 << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_100                              (0x5 << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_80                               (0x4 << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_60                               (0x3 << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_40                               (0x2 << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_20                               (0x1 << 4)
+#define        LRADC_CTRL2_TEMP_ISRC1_ZERO                             (0x0 << 4)
+#define        LRADC_CTRL2_TEMP_ISRC0_MASK                             (0xf << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_OFFSET                           0
+#define        LRADC_CTRL2_TEMP_ISRC0_300                              (0xf << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_280                              (0xe << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_260                              (0xd << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_240                              (0xc << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_220                              (0xb << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_200                              (0xa << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_180                              (0x9 << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_160                              (0x8 << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_140                              (0x7 << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_120                              (0x6 << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_100                              (0x5 << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_80                               (0x4 << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_60                               (0x3 << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_40                               (0x2 << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_20                               (0x1 << 0)
+#define        LRADC_CTRL2_TEMP_ISRC0_ZERO                             (0x0 << 0)
+
+#define        LRADC_CTRL3_DISCARD_MASK                                (0x3 << 24)
+#define        LRADC_CTRL3_DISCARD_OFFSET                              24
+#define        LRADC_CTRL3_DISCARD_1_SAMPLE                            (0x1 << 24)
+#define        LRADC_CTRL3_DISCARD_2_SAMPLES                           (0x2 << 24)
+#define        LRADC_CTRL3_DISCARD_3_SAMPLES                           (0x3 << 24)
+#define        LRADC_CTRL3_FORCE_ANALOG_PWUP                           (1 << 23)
+#define        LRADC_CTRL3_FORCE_ANALOG_PWDN                           (1 << 22)
+#define        LRADC_CTRL3_CYCLE_TIME_MASK                             (0x3 << 8)
+#define        LRADC_CTRL3_CYCLE_TIME_OFFSET                           8
+#define        LRADC_CTRL3_CYCLE_TIME_6MHZ                             (0x0 << 8)
+#define        LRADC_CTRL3_CYCLE_TIME_4MHZ                             (0x1 << 8)
+#define        LRADC_CTRL3_CYCLE_TIME_3MHZ                             (0x2 << 8)
+#define        LRADC_CTRL3_CYCLE_TIME_2MHZ                             (0x3 << 8)
+#define        LRADC_CTRL3_HIGH_TIME_MASK                              (0x3 << 4)
+#define        LRADC_CTRL3_HIGH_TIME_OFFSET                            4
+#define        LRADC_CTRL3_HIGH_TIME_42NS                              (0x0 << 4)
+#define        LRADC_CTRL3_HIGH_TIME_83NS                              (0x1 << 4)
+#define        LRADC_CTRL3_HIGH_TIME_125NS                             (0x2 << 4)
+#define        LRADC_CTRL3_HIGH_TIME_250NS                             (0x3 << 4)
+#define        LRADC_CTRL3_DELAY_CLOCK                                 (1 << 1)
+#define        LRADC_CTRL3_INVERT_CLOCK                                (1 << 0)
+
+#define        LRADC_STATUS_BUTTON1_PRESENT                            (1 << 28)
+#define        LRADC_STATUS_BUTTON0_PRESENT                            (1 << 27)
+#define        LRADC_STATUS_TEMP1_PRESENT                              (1 << 26)
+#define        LRADC_STATUS_TEMP0_PRESENT                              (1 << 25)
+#define        LRADC_STATUS_TOUCH_PANEL_PRESENT                        (1 << 24)
+#define        LRADC_STATUS_CHANNEL7_PRESENT                           (1 << 23)
+#define        LRADC_STATUS_CHANNEL6_PRESENT                           (1 << 22)
+#define        LRADC_STATUS_CHANNEL5_PRESENT                           (1 << 21)
+#define        LRADC_STATUS_CHANNEL4_PRESENT                           (1 << 20)
+#define        LRADC_STATUS_CHANNEL3_PRESENT                           (1 << 19)
+#define        LRADC_STATUS_CHANNEL2_PRESENT                           (1 << 18)
+#define        LRADC_STATUS_CHANNEL1_PRESENT                           (1 << 17)
+#define        LRADC_STATUS_CHANNEL0_PRESENT                           (1 << 16)
+#define        LRADC_STATUS_BUTTON1_DETECT_RAW                         (1 << 2)
+#define        LRADC_STATUS_BUTTON0_DETECT_RAW                         (1 << 1)
+#define        LRADC_STATUS_TOUCH_DETECT_RAW                           (1 << 0)
+
+#define        LRADC_CH_TOGGLE                                         (1 << 31)
+#define        LRADC_CH7_TESTMODE_TOGGLE                               (1 << 30)
+#define        LRADC_CH_ACCUMULATE                                     (1 << 29)
+#define        LRADC_CH_NUM_SAMPLES_MASK                               (0x1f << 24)
+#define        LRADC_CH_NUM_SAMPLES_OFFSET                             24
+#define        LRADC_CH_VALUE_MASK                                     0x3ffff
+#define        LRADC_CH_VALUE_OFFSET                                   0
+
+#define        LRADC_DELAY_TRIGGER_LRADCS_MASK                         (0xff << 24)
+#define        LRADC_DELAY_TRIGGER_LRADCS_OFFSET                       24
+#define        LRADC_DELAY_KICK                                        (1 << 20)
+#define        LRADC_DELAY_TRIGGER_DELAYS_MASK                         (0xf << 16)
+#define        LRADC_DELAY_TRIGGER_DELAYS_OFFSET                       16
+#define        LRADC_DELAY_LOOP_COUNT_MASK                             (0x1f << 11)
+#define        LRADC_DELAY_LOOP_COUNT_OFFSET                           11
+#define        LRADC_DELAY_DELAY_MASK                                  0x7ff
+#define        LRADC_DELAY_DELAY_OFFSET                                0
+
+#define        LRADC_DEBUG0_READONLY_MASK                              (0xffff << 16)
+#define        LRADC_DEBUG0_READONLY_OFFSET                            16
+#define        LRADC_DEBUG0_STATE_MASK                                 (0xfff << 0)
+#define        LRADC_DEBUG0_STATE_OFFSET                               0
+
+#define        LRADC_DEBUG1_REQUEST_MASK                               (0xff << 16)
+#define        LRADC_DEBUG1_REQUEST_OFFSET                             16
+#define        LRADC_DEBUG1_TESTMODE_COUNT_MASK                        (0x1f << 8)
+#define        LRADC_DEBUG1_TESTMODE_COUNT_OFFSET                      8
+#define        LRADC_DEBUG1_TESTMODE6                                  (1 << 2)
+#define        LRADC_DEBUG1_TESTMODE5                                  (1 << 1)
+#define        LRADC_DEBUG1_TESTMODE                                   (1 << 0)
+
+#define        LRADC_CONVERSION_AUTOMATIC                              (1 << 20)
+#define        LRADC_CONVERSION_SCALE_FACTOR_MASK                      (0x3 << 16)
+#define        LRADC_CONVERSION_SCALE_FACTOR_OFFSET                    16
+#define        LRADC_CONVERSION_SCALE_FACTOR_NIMH                      (0x0 << 16)
+#define        LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH                 (0x1 << 16)
+#define        LRADC_CONVERSION_SCALE_FACTOR_LI_ION                    (0x2 << 16)
+#define        LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION                (0x3 << 16)
+#define        LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK               0x3ff
+#define        LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET             0
+
+#define        LRADC_CTRL4_LRADC7SELECT_MASK                           (0xf << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_OFFSET                         28
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL0                       (0x0 << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL1                       (0x1 << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL2                       (0x2 << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL3                       (0x3 << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL4                       (0x4 << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL5                       (0x5 << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL6                       (0x6 << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL7                       (0x7 << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL8                       (0x8 << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL9                       (0x9 << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL10                      (0xa << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL11                      (0xb << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL12                      (0xc << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL13                      (0xd << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL14                      (0xe << 28)
+#define        LRADC_CTRL4_LRADC7SELECT_CHANNEL15                      (0xf << 28)
+#define        LRADC_CTRL4_LRADC6SELECT_MASK                           (0xf << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_OFFSET                         24
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL0                       (0x0 << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL1                       (0x1 << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL2                       (0x2 << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL3                       (0x3 << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL4                       (0x4 << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL5                       (0x5 << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL6                       (0x6 << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL7                       (0x7 << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL8                       (0x8 << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL9                       (0x9 << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL10                      (0xa << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL11                      (0xb << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL12                      (0xc << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL13                      (0xd << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL14                      (0xe << 24)
+#define        LRADC_CTRL4_LRADC6SELECT_CHANNEL15                      (0xf << 24)
+#define        LRADC_CTRL4_LRADC5SELECT_MASK                           (0xf << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_OFFSET                         20
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL0                       (0x0 << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL1                       (0x1 << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL2                       (0x2 << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL3                       (0x3 << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL4                       (0x4 << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL5                       (0x5 << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL6                       (0x6 << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL7                       (0x7 << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL8                       (0x8 << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL9                       (0x9 << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL10                      (0xa << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL11                      (0xb << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL12                      (0xc << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL13                      (0xd << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL14                      (0xe << 20)
+#define        LRADC_CTRL4_LRADC5SELECT_CHANNEL15                      (0xf << 20)
+#define        LRADC_CTRL4_LRADC4SELECT_MASK                           (0xf << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_OFFSET                         16
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL0                       (0x0 << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL1                       (0x1 << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL2                       (0x2 << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL3                       (0x3 << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL4                       (0x4 << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL5                       (0x5 << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL6                       (0x6 << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL7                       (0x7 << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL8                       (0x8 << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL9                       (0x9 << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL10                      (0xa << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL11                      (0xb << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL12                      (0xc << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL13                      (0xd << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL14                      (0xe << 16)
+#define        LRADC_CTRL4_LRADC4SELECT_CHANNEL15                      (0xf << 16)
+#define        LRADC_CTRL4_LRADC3SELECT_MASK                           (0xf << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_OFFSET                         12
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL0                       (0x0 << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL1                       (0x1 << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL2                       (0x2 << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL3                       (0x3 << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL4                       (0x4 << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL5                       (0x5 << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL6                       (0x6 << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL7                       (0x7 << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL8                       (0x8 << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL9                       (0x9 << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL10                      (0xa << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL11                      (0xb << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL12                      (0xc << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL13                      (0xd << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL14                      (0xe << 12)
+#define        LRADC_CTRL4_LRADC3SELECT_CHANNEL15                      (0xf << 12)
+#define        LRADC_CTRL4_LRADC2SELECT_MASK                           (0xf << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_OFFSET                         8
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL0                       (0x0 << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL1                       (0x1 << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL2                       (0x2 << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL3                       (0x3 << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL4                       (0x4 << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL5                       (0x5 << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL6                       (0x6 << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL7                       (0x7 << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL8                       (0x8 << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL9                       (0x9 << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL10                      (0xa << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL11                      (0xb << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL12                      (0xc << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL13                      (0xd << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL14                      (0xe << 8)
+#define        LRADC_CTRL4_LRADC2SELECT_CHANNEL15                      (0xf << 8)
+#define        LRADC_CTRL4_LRADC1SELECT_MASK                           (0xf << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_OFFSET                         4
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL0                       (0x0 << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL1                       (0x1 << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL2                       (0x2 << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL3                       (0x3 << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL4                       (0x4 << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL5                       (0x5 << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL6                       (0x6 << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL7                       (0x7 << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL8                       (0x8 << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL9                       (0x9 << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL10                      (0xa << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL11                      (0xb << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL12                      (0xc << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL13                      (0xd << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL14                      (0xe << 4)
+#define        LRADC_CTRL4_LRADC1SELECT_CHANNEL15                      (0xf << 4)
+#define        LRADC_CTRL4_LRADC0SELECT_MASK                           0xf
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL0                       (0x0 << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL1                       (0x1 << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL2                       (0x2 << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL3                       (0x3 << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL4                       (0x4 << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL5                       (0x5 << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL6                       (0x6 << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL7                       (0x7 << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL8                       (0x8 << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL9                       (0x9 << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL10                      (0xa << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL11                      (0xb << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL12                      (0xc << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL13                      (0xd << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL14                      (0xe << 0)
+#define        LRADC_CTRL4_LRADC0SELECT_CHANNEL15                      (0xf << 0)
+
+#define        LRADC_THRESHOLD_ENABLE                                  (1 << 24)
+#define        LRADC_THRESHOLD_BATTCHRG_DISABLE                        (1 << 23)
+#define        LRADC_THRESHOLD_CHANNEL_SEL_MASK                        (0x7 << 20)
+#define        LRADC_THRESHOLD_CHANNEL_SEL_OFFSET                      20
+#define        LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0                    (0x0 << 20)
+#define        LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1                    (0x1 << 20)
+#define        LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2                    (0x2 << 20)
+#define        LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3                    (0x3 << 20)
+#define        LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4                    (0x4 << 20)
+#define        LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5                    (0x5 << 20)
+#define        LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6                    (0x6 << 20)
+#define        LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7                    (0x7 << 20)
+#define        LRADC_THRESHOLD_SETTING_MASK                            (0x3 << 18)
+#define        LRADC_THRESHOLD_SETTING_OFFSET                          18
+#define        LRADC_THRESHOLD_SETTING_NO_COMPARE                      (0x0 << 18)
+#define        LRADC_THRESHOLD_SETTING_DETECT_LOW                      (0x1 << 18)
+#define        LRADC_THRESHOLD_SETTING_DETECT_HIGH                     (0x2 << 18)
+#define        LRADC_THRESHOLD_SETTING_RESERVED                        (0x3 << 18)
+#define        LRADC_THRESHOLD_VALUE_MASK                              0x3ffff
+#define        LRADC_THRESHOLD_VALUE_OFFSET                            0
+
+#define        LRADC_VERSION_MAJOR_MASK                                (0xff << 24)
+#define        LRADC_VERSION_MAJOR_OFFSET                              24
+#define        LRADC_VERSION_MINOR_MASK                                (0xff << 16)
+#define        LRADC_VERSION_MINOR_OFFSET                              16
+#define        LRADC_VERSION_STEP_MASK                                 0xffff
+#define        LRADC_VERSION_STEP_OFFSET                               0
+
+#endif /* __MX28_REGS_LRADC_H__ */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0051-i.MX28-Add-LRADC-init-to-i.MX28-SPL.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0051-i.MX28-Add-LRADC-init-to-i.MX28-SPL.patch
new file mode 100644
index 000000000..51417819e
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0051-i.MX28-Add-LRADC-init-to-i.MX28-SPL.patch
@@ -0,0 +1,168 @@
+From c9d426383e2d672d72e646801cbe19fea9653cba Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Tue, 1 May 2012 11:09:49 +0000
+Subject: [PATCH 51/56] i.MX28: Add LRADC init to i.MX28 SPL
+This code is part of battery boot support for i.MX28.
+Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Fabio Estevam <fabio.estevam@freescale.com>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+---
+ arch/arm/cpu/arm926ejs/mx28/Makefile         |    2 +-
+ arch/arm/cpu/arm926ejs/mx28/mx28_init.h      |    3 +
+ arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c |   86 ++++++++++++++++++++++++++
+ arch/arm/cpu/arm926ejs/mx28/spl_power_init.c |   10 +++
+ 4 files changed, 100 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c
+diff --git a/arch/arm/cpu/arm926ejs/mx28/Makefile b/arch/arm/cpu/arm926ejs/mx28/Makefile
+index a2e3f77..674a3af 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx28/Makefile
+@@ -28,7 +28,7 @@ LIB   = $(obj)lib$(SOC).o
+ COBJS  = clock.o mx28.o iomux.o timer.o
+ 
+ ifdef  CONFIG_SPL_BUILD
+-COBJS  += spl_boot.o spl_mem_init.o spl_power_init.o
+COBJS  += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
+ endif
+ 
+ SRCS   := $(START:.o=.S) $(COBJS:.o=.c)
+diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h
+index 8eac958..e3a4493 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h
+@@ -39,4 +39,7 @@ static inline void mx28_power_wait_pswitch(void) { }
+ void mx28_mem_init(void);
+ uint32_t mx28_mem_get_size(void);
+ 
+void mx28_lradc_init(void);
+void mx28_lradc_enable_batt_measurement(void);
+
+ #endif /* __M28_INIT_H__ */
+diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c
+new file mode 100644
+index 0000000..88a603c
+--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c
+@@ -0,0 +1,86 @@
+/*
+ * Freescale i.MX28 Battery measurement init
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+#include "mx28_init.h"
+
+void mx28_lradc_init(void)
+{
+       struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+
+       writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
+       writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
+       writel(LRADC_CTRL0_ONCHIP_GROUNDREF, &regs->hw_lradc_ctrl0_clr);
+
+       clrsetbits_le32(&regs->hw_lradc_ctrl3,
+                       LRADC_CTRL3_CYCLE_TIME_MASK,
+                       LRADC_CTRL3_CYCLE_TIME_6MHZ);
+
+       clrsetbits_le32(&regs->hw_lradc_ctrl4,
+                       LRADC_CTRL4_LRADC7SELECT_MASK |
+                       LRADC_CTRL4_LRADC6SELECT_MASK,
+                       LRADC_CTRL4_LRADC7SELECT_CHANNEL7 |
+                       LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
+}
+
+void mx28_lradc_enable_batt_measurement(void)
+{
+       struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+
+       /* Check if the channel is present at all. */
+       if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
+               return;
+
+       writel(LRADC_CTRL1_LRADC7_IRQ_EN, &regs->hw_lradc_ctrl1_clr);
+       writel(LRADC_CTRL1_LRADC7_IRQ, &regs->hw_lradc_ctrl1_clr);
+
+       clrsetbits_le32(&regs->hw_lradc_conversion,
+                       LRADC_CONVERSION_SCALE_FACTOR_MASK,
+                       LRADC_CONVERSION_SCALE_FACTOR_LI_ION);
+       writel(LRADC_CONVERSION_AUTOMATIC, &regs->hw_lradc_conversion_set);
+
+       /* Configure the channel. */
+       writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
+               &regs->hw_lradc_ctrl2_clr);
+       writel(0xffffffff, &regs->hw_lradc_ch7_clr);
+       clrbits_le32(&regs->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK);
+       writel(LRADC_CH_ACCUMULATE, &regs->hw_lradc_ch7_clr);
+
+       /* Schedule the channel. */
+       writel(1 << 7, &regs->hw_lradc_ctrl0_set);
+
+       /* Start the channel sampling. */
+       writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) |
+               ((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) |
+               100, &regs->hw_lradc_delay3);
+
+       writel(0xffffffff, &regs->hw_lradc_ch7_clr);
+
+       writel(LRADC_DELAY_KICK, &regs->hw_lradc_delay3_set);
+}
+diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+index aa4117d..dfb62eb 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+@@ -883,6 +883,13 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
+                        new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+ }
+ 
+void mx28_setup_batt_detect(void)
+{
+       mx28_lradc_init();
+       mx28_lradc_enable_batt_measurement();
+       early_delay(10);
+}
+
+ void mx28_power_init(void)
+ {
+        struct mx28_power_regs *power_regs =
+@@ -892,6 +899,9 @@ void mx28_power_init(void)
+        mx28_power_clear_auto_restart();
+        mx28_power_set_linreg();
+        mx28_power_setup_5v_detect();
+
+       mx28_setup_batt_detect();
+
+        mx28_power_configure_power_source();
+        mx28_enable_output_rail_protection();
+ 
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0052-i.MX28-Reorder-battery-status-functions-in-SPL.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0052-i.MX28-Reorder-battery-status-functions-in-SPL.patch
new file mode 100644
index 000000000..6c7d89a87
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0052-i.MX28-Reorder-battery-status-functions-in-SPL.patch
@@ -0,0 +1,162 @@
+From cd97dc62732fe84ee4a979e002515c89f37fc477 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Tue, 1 May 2012 11:09:50 +0000
+Subject: [PATCH 52/56] i.MX28: Reorder battery status functions in SPL
+Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Fabio Estevam <fabio.estevam@freescale.com>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+---
+ arch/arm/cpu/arm926ejs/mx28/spl_power_init.c |  120 ++++++++++++--------------
+ 1 file changed, 56 insertions(+), 64 deletions(-)
+diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+index dfb62eb..ac942b4 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+@@ -104,6 +104,62 @@ void mx28_power_set_linreg(void)
+                        POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
+ }
+ 
+int mx28_get_batt_volt(void)
+{
+       struct mx28_power_regs *power_regs =
+               (struct mx28_power_regs *)MXS_POWER_BASE;
+       uint32_t volt = readl(&power_regs->hw_power_battmonitor);
+       volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+       volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+       volt *= 8;
+       return volt;
+}
+
+int mx28_is_batt_ready(void)
+{
+       return (mx28_get_batt_volt() >= 3600);
+}
+
+int mx28_is_batt_good(void)
+{
+       struct mx28_power_regs *power_regs =
+               (struct mx28_power_regs *)MXS_POWER_BASE;
+       uint32_t volt = mx28_get_batt_volt();
+
+       if ((volt >= 2400) && (volt <= 4300))
+               return 1;
+
+       clrsetbits_le32(&power_regs->hw_power_5vctrl,
+               POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+               0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+       writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+               &power_regs->hw_power_5vctrl_clr);
+
+       clrsetbits_le32(&power_regs->hw_power_charge,
+               POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+               POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
+
+       writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
+       writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+               &power_regs->hw_power_5vctrl_clr);
+
+       early_delay(500000);
+
+       volt = mx28_get_batt_volt();
+
+       if (volt >= 3500)
+               return 0;
+
+       if (volt >= 2400)
+               return 1;
+
+       writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+               &power_regs->hw_power_charge_clr);
+       writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+
+       return 0;
+}
+
+ void mx28_power_setup_5v_detect(void)
+ {
+        struct mx28_power_regs *power_regs =
+@@ -486,22 +542,6 @@ void mx28_handle_5v_conflict(void)
+        }
+ }
+ 
+-int mx28_get_batt_volt(void)
+-{
+-       struct mx28_power_regs *power_regs =
+-               (struct mx28_power_regs *)MXS_POWER_BASE;
+-       uint32_t volt = readl(&power_regs->hw_power_battmonitor);
+-       volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+-       volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+-       volt *= 8;
+-       return volt;
+-}
+-
+-int mx28_is_batt_ready(void)
+-{
+-       return (mx28_get_batt_volt() >= 3600);
+-}
+-
+ void mx28_5v_boot(void)
+ {
+        struct mx28_power_regs *power_regs =
+@@ -553,54 +593,6 @@ void mx28_switch_vddd_to_dcdc_source(void)
+                POWER_VDDDCTRL_DISABLE_STEPPING);
+ }
+ 
+-int mx28_is_batt_good(void)
+-{
+-       struct mx28_power_regs *power_regs =
+-               (struct mx28_power_regs *)MXS_POWER_BASE;
+-       uint32_t volt;
+-
+-       volt = readl(&power_regs->hw_power_battmonitor);
+-       volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+-       volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+-       volt *= 8;
+-
+-       if ((volt >= 2400) && (volt <= 4300))
+-               return 1;
+-
+-       clrsetbits_le32(&power_regs->hw_power_5vctrl,
+-               POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+-               0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+-       writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+-               &power_regs->hw_power_5vctrl_clr);
+-
+-       clrsetbits_le32(&power_regs->hw_power_charge,
+-               POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+-               POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
+-
+-       writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
+-       writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+-               &power_regs->hw_power_5vctrl_clr);
+-
+-       early_delay(500000);
+-
+-       volt = readl(&power_regs->hw_power_battmonitor);
+-       volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+-       volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+-       volt *= 8;
+-
+-       if (volt >= 3500)
+-               return 0;
+-
+-       if (volt >= 2400)
+-               return 1;
+-
+-       writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+-               &power_regs->hw_power_charge_clr);
+-       writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+-
+-       return 0;
+-}
+-
+ void mx28_power_configure_power_source(void)
+ {
+        mx28_src_power_init();
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0053-i.MX28-Add-battery-boot-components-to-SPL.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0053-i.MX28-Add-battery-boot-components-to-SPL.patch
new file mode 100644
index 000000000..8da6d971d
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0053-i.MX28-Add-battery-boot-components-to-SPL.patch
@@ -0,0 +1,162 @@
+From 2e5adad8385127605c3ad3e3a006d65deeccde38 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marek.vasut@gmail.com>
+Date: Tue, 1 May 2012 11:09:51 +0000
+Subject: [PATCH 53/56] i.MX28: Add battery boot components to SPL
+Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Fabio Estevam <fabio.estevam@freescale.com>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+---
+ arch/arm/cpu/arm926ejs/mx28/spl_power_init.c |  100 +++++++++++++++++++++++---
+ 1 file changed, 92 insertions(+), 8 deletions(-)
+diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+index ac942b4..4b09b0c 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+@@ -45,11 +45,11 @@ void mx28_power_clock2pll(void)
+        struct mx28_clkctrl_regs *clkctrl_regs =
+                (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ 
+-       writel(CLKCTRL_PLL0CTRL0_POWER,
+-               &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
+       setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
+                       CLKCTRL_PLL0CTRL0_POWER);
+        early_delay(100);
+-       writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+-               &clkctrl_regs->hw_clkctrl_clkseq_clr);
+       setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
+                       CLKCTRL_CLKSEQ_BYPASS_CPU);
+ }
+ 
+ void mx28_power_clear_auto_restart(void)
+@@ -455,9 +455,14 @@ void mx28_power_enable_4p2(void)
+        mx28_power_init_4p2_regulator();
+ 
+        /* Shutdown battery (none present) */
+-       clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
+-       writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+-       writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
+       if (!mx28_is_batt_ready()) {
+               clrbits_le32(&power_regs->hw_power_dcdc4p2,
+                               POWER_DCDC4P2_BO_MASK);
+               writel(POWER_CTRL_DCDC4P2_BO_IRQ,
+                               &power_regs->hw_power_ctrl_clr);
+               writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
+                               &power_regs->hw_power_ctrl_clr);
+       }
+ 
+        mx28_power_init_dcdc_4p2_source();
+ 
+@@ -515,6 +520,50 @@ void mx28_powerdown(void)
+                &power_regs->hw_power_reset);
+ }
+ 
+void mx28_batt_boot(void)
+{
+       struct mx28_power_regs *power_regs =
+               (struct mx28_power_regs *)MXS_POWER_BASE;
+
+       clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
+       clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
+
+       clrbits_le32(&power_regs->hw_power_dcdc4p2,
+                       POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
+       writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
+
+       /* 5V to battery handoff. */
+       setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+       early_delay(30);
+       clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+
+       writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
+
+       clrsetbits_le32(&power_regs->hw_power_minpwr,
+                       POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
+
+       mx28_power_set_linreg();
+
+       clrbits_le32(&power_regs->hw_power_vdddctrl,
+               POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
+
+       clrbits_le32(&power_regs->hw_power_vddactrl,
+               POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
+
+       clrbits_le32(&power_regs->hw_power_vddioctrl,
+               POWER_VDDIOCTRL_DISABLE_FET);
+
+       setbits_le32(&power_regs->hw_power_5vctrl,
+               POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
+
+       setbits_le32(&power_regs->hw_power_5vctrl,
+               POWER_5VCTRL_ENABLE_DCDC);
+
+       clrsetbits_le32(&power_regs->hw_power_5vctrl,
+               POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+               0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+}
+
+ void mx28_handle_5v_conflict(void)
+ {
+        struct mx28_power_regs *power_regs =
+@@ -539,6 +588,11 @@ void mx28_handle_5v_conflict(void)
+                        mx28_powerdown();
+                        break;
+                }
+
+               if (tmp & POWER_STS_PSWITCH_MASK) {
+                       mx28_batt_boot();
+                       break;
+               }
+        }
+ }
+ 
+@@ -595,12 +649,42 @@ void mx28_switch_vddd_to_dcdc_source(void)
+ 
+ void mx28_power_configure_power_source(void)
+ {
+       int batt_ready, batt_good;
+       struct mx28_power_regs *power_regs =
+               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mx28_lradc_regs *lradc_regs =
+               (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+
+        mx28_src_power_init();
+ 
+-       mx28_5v_boot();
+       batt_ready = mx28_is_batt_ready();
+
+       if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+               batt_good = mx28_is_batt_good();
+               if (batt_ready) {
+                       /* 5V source detected, good battery detected. */
+                       mx28_batt_boot();
+               } else {
+                       if (batt_good) {
+                               /* 5V source detected, low battery detceted. */
+                       } else {
+                               /* 5V source detected, bad battery detected. */
+                               writel(LRADC_CONVERSION_AUTOMATIC,
+                                       &lradc_regs->hw_lradc_conversion_clr);
+                               clrbits_le32(&power_regs->hw_power_battmonitor,
+                                       POWER_BATTMONITOR_BATT_VAL_MASK);
+                       }
+                       mx28_5v_boot();
+               }
+       } else {
+               /* 5V not detected, booting from battery. */
+               mx28_batt_boot();
+       }
+
+        mx28_power_clock2pll();
+ 
+        mx28_init_batt_bo();
+
+        mx28_switch_vddd_to_dcdc_source();
+ }
+ 
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0054-i.MX28-Check-if-WP-detection-is-implemented-at-all.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0054-i.MX28-Check-if-WP-detection-is-implemented-at-all.patch
new file mode 100644
index 000000000..476ab900b
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0054-i.MX28-Check-if-WP-detection-is-implemented-at-all.patch
@@ -0,0 +1,34 @@
+From a79af9bfd334db959881ebbe917976ebc7824c35 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marex@denx.de>
+Date: Tue, 1 May 2012 11:09:52 +0000
+Subject: [PATCH 54/56] i.MX28: Check if WP detection is implemented at all
+If the WP function is NULL, simply assume the card is always RW.
+Signed-off-by: Marek Vasut <marex@denx.de>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Fabio Estevam <fabio.estevam@freescale.com>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ drivers/mmc/mxsmmc.c |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
+index 35c6bda..c7200ee 100644
+--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
+@@ -133,7 +133,8 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+                /* READ or WRITE */
+                if (data->flags & MMC_DATA_READ) {
+                        ctrl0 |= SSP_CTRL0_READ;
+-               } else if (priv->mmc_is_wp(mmc->block_dev.dev)) {
+               } else if (priv->mmc_is_wp &&
+                       priv->mmc_is_wp(mmc->block_dev.dev)) {
+                        printf("MMC%d: Can not write a locked card!\n",
+                                mmc->block_dev.dev);
+                        return UNUSABLE_ERR;
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0055-i.MX28-Avoid-redefining-serial_put-cs.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0055-i.MX28-Avoid-redefining-serial_put-cs.patch
new file mode 100644
index 000000000..ef237e87c
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0055-i.MX28-Avoid-redefining-serial_put-cs.patch
@@ -0,0 +1,36 @@
+From b72b9a019acd1646ad8ae2518c8e7901f4ca8a90 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marex@denx.de>
+Date: Tue, 1 May 2012 11:09:53 +0000
+Subject: [PATCH 55/56] i.MX28: Avoid redefining serial_put[cs]()
+Do not define serial_putc() and serial_puts() calls if
+CONFIG_SPL_SERIAL_SUPPORT is set.
+Signed-off-by: Marek Vasut <marex@denx.de>
+Cc: Detlev Zundel <dzu@denx.de>
+Cc: Fabio Estevam <fabio.estevam@freescale.com>
+Cc: Stefano Babic <sbabic@denx.de>
+Cc: Wolfgang Denk <wd@denx.de>
+Acked-by: Stefano Babic <sbabic@denx.de>
+---
+ arch/arm/cpu/arm926ejs/mx28/spl_boot.c |    2 ++
+ 1 file changed, 2 insertions(+)
+diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c
+index c9b4566..a6dfca3 100644
+--- a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c
+@@ -123,8 +123,10 @@ inline void board_init_r(gd_t *id, ulong dest_addr)
+                ;
+ }
+ 
+#ifndef CONFIG_SPL_SERIAL_SUPPORT
+ void serial_putc(const char c) {}
+ void serial_puts(const char *s) {}
+#endif
+ void hang(void) __attribute__ ((noreturn));
+ void hang(void)
+ {
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0056-mx28evk-Scan-only-first-128MB-of-DRAM-to-avoid-memor.patch b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0056-mx28evk-Scan-only-first-128MB-of-DRAM-to-avoid-memor.patch
new file mode 100644
index 000000000..b3946a1f0
--- /dev/null
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot-2012.04.01/0056-mx28evk-Scan-only-first-128MB-of-DRAM-to-avoid-memor.patch
@@ -0,0 +1,32 @@
+From 694d7164c05e3b785ac3c7055d0bd605bfc6a5ee Mon Sep 17 00:00:00 2001
+From: Fabio Estevam <fabio.estevam@freescale.com>
+Date: Sat, 12 May 2012 14:14:13 -0300
+Subject: [PATCH 56/56] mx28evk: Scan only first 128MB of DRAM to avoid memory
+ wraparound
+Scan only first 128MB of DRAM to avoid memory wraparound.
+This fixes mx28evk boot and it follows the same idea of commit
+19a2066b57 (M28: Scan only first 512 MB of DRAM to avoid memory wraparound)
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ include/configs/mx28evk.h |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
+index 0c18e50..41037fc 100644
+--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
+@@ -75,7 +75,7 @@
+  */
+ #define CONFIG_NR_DRAM_BANKS           1               /* 1 bank of DRAM */
+ #define PHYS_SDRAM_1                   0x40000000      /* Base address */
+-#define PHYS_SDRAM_1_SIZE              0x40000000      /* Max 1 GB RAM */
+#define PHYS_SDRAM_1_SIZE              0x08000000      /* 128MB RAM */
+ #define CONFIG_STACKSIZE               (128 * 1024)    /* 128 KB stack */
+ #define CONFIG_SYS_MALLOC_LEN          0x00400000      /* 4 MB for malloc */
+ #define CONFIG_SYS_MEMTEST_START       0x40000000      /* Memtest start adr */
+-- 
+1.7.10
diff --git a/meta-fsl-arm/recipes-bsp/u-boot/u-boot_2012.04.01.bb b/meta-fsl-arm/recipes-bsp/u-boot/u-boot_2012.04.01.bb
index e217306be..85c1d2f8b 100644
--- a/meta-fsl-arm/recipes-bsp/u-boot/u-boot_2012.04.01.bb
+++ b/meta-fsl-arm/recipes-bsp/u-boot/u-boot_2012.04.01.bb
@@ -10,7 +10,64 @@ SRCREV = "415d386877df49eb051b85ef74fa59a16dc17c7d"
 PV = "v2012.04.01"
-SRC_URI = "git://git.denx.de/u-boot.git;branch=master;protocol=git"
+SRC_URI = "git://git.denx.de/u-boot.git;branch=master;protocol=git \
+           file://0001-MX5-Add-definitions-for-SATA-controller.patch \
+           file://0002-SATA-check-for-return-value-from-sata-functions.patch \
+           file://0003-MX53-add-function-to-set-SATA-clock-to-internal.patch \
+           file://0004-SATA-add-driver-for-MX5-MX6-SOCs.patch \
+           file://0005-MX53-Add-support-to-ESG-ima3-board.patch \
+           file://0006-MX53-mx53loco-Add-SATA-support.patch \
+           file://0007-pmic-Add-support-for-the-Dialog-DA9053-PMIC.patch \
+           file://0008-mx6qsabrelite-No-need-to-set-the-direction-for-GPIO3.patch \
+           file://0009-mx28evk-Allow-to-booting-a-dt-kernel.patch \
+           file://0010-m28evk-Allow-to-booting-a-dt-kernel.patch \
+           file://0011-mx28evk-Allow-booting-a-zImage-kernel.patch \
+           file://0012-mx6qsabrelite-Allow-booting-a-zImage-kernel.patch \
+           file://0013-mx6qarm2-Allow-booting-a-zImage-kernel.patch \
+           file://0014-mx31pdk-Allow-booting-a-zImage-kernel.patch \
+           file://0015-i.MX6Q-mx6qsabrelite-Add-keypress-support-to-alter-b.patch \
+           file://0016-imx-common-Factor-out-get_ahb_clk.patch \
+           file://0017-mx5-Add-clock-config-interface.patch \
+           file://0018-mx53loco-Allow-to-print-CPU-information-at-a-later-s.patch \
+           file://0019-mx53loco-Add-support-for-1GHz-operation-for-DA9053-b.patch \
+           file://0020-M28-Enable-FDT-support.patch \
+           file://0021-Revert-i.MX28-Enable-additional-DRAM-address-bits.patch \
+           file://0022-M28-Scan-only-first-512-MB-of-DRAM-to-avoid-memory-w.patch \
+           file://0023-USB-ehci-mx6-Fix-broken-IO-access.patch \
+           file://0024-mx28evk-add-NAND-support.patch \
+           file://0025-i.MX6-Add-ANATOP-regulator-init.patch \
+           file://0026-i.MX6-add-enable_sata_clock.patch \
+           file://0027-i.MX6-mx6q_sabrelite-add-SATA-bindings.patch \
+           file://0028-i.MX25-esdhc-Add-mxc_get_clock-infrastructure.patch \
+           file://0029-i.MX25-This-architecture-has-a-GPIO4-too.patch \
+           file://0030-imx-nand-Support-flash-based-BBT.patch \
+           file://0031-i.MX25-usb-Set-PORTSCx-register.patch \
+           file://0032-imx-usb-There-is-no-such-register.patch \
+           file://0033-i.MX2-Include-asm-types.h-in-arch-mx25-imx-regs.h.patch \
+           file://0034-imx-Add-u-boot.imx-as-target-for-ARM9-i.MX-SOCs.patch \
+           file://0035-pmic-dialog-Avoid-name-conflicts.patch \
+           file://0036-mx53loco-Add-mc34708-support-and-set-mx53-frequency-.patch \
+           file://0037-mx53loco-Turn-on-VUSB-regulator.patch \
+           file://0038-mx53loco-Add-CONFIG_REVISION_TAG.patch \
+           file://0039-mx53loco-Remove-unneeded-gpio_set_value.patch \
+           file://0040-spi-mxs-Introduce-spi_cs_is_valid.patch \
+           file://0041-spi-mxs-Allow-other-chip-selects-to-work.patch \
+           file://0042-i.MX28-Add-delay-after-CPU-bypass-is-cleared.patch \
+           file://0043-MX5-PAD_CTL_DRV_VOT_LOW-and-PAD_CTL_DRV_VOT_HIGH-exc.patch \
+           file://0044-M28EVK-Implement-support-for-new-board-V2.0.patch \
+           file://0045-M28EVK-Add-SD-update-command.patch \
+           file://0046-i.MX28-Improve-passing-of-data-from-SPL-to-U-Boot.patch \
+           file://0047-i.MX28-Implement-boot-pads-sampling-and-reporting.patch \
+           file://0048-i.MX28-Add-LCDIF-register-definitions.patch \
+           file://0049-i.MX28-Shut-down-the-LCD-controller-before-reset.patch \
+           file://0050-i.MX28-Add-LRADC-register-definitions.patch \
+           file://0051-i.MX28-Add-LRADC-init-to-i.MX28-SPL.patch \
+           file://0052-i.MX28-Reorder-battery-status-functions-in-SPL.patch \
+           file://0053-i.MX28-Add-battery-boot-components-to-SPL.patch \
+           file://0054-i.MX28-Check-if-WP-detection-is-implemented-at-all.patch \
+           file://0055-i.MX28-Avoid-redefining-serial_put-cs.patch \
+           file://0056-mx28evk-Scan-only-first-128MB-of-DRAM-to-avoid-memor.patch \
+"
 S = "${WORKDIR}/git"