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authorGary Bisson <bisson.gary@gmail.com>2014-12-03 18:23:56 -0800
committerOtavio Salvador <otavio@ossystems.com.br>2014-12-04 09:16:09 -0200
commit7354fa248f2860fd8dff160cf168db07626d7c74 (patch)
treecd08b8a8e6a681dfb2fccb5ec543b24d1402aae3 /meta-fsl-arm/classes
parent6a77181fe771a64b585364fd7cddcda9e08a8683 (diff)
downloadmeta-freescale-7354fa248f2860fd8dff160cf168db07626d7c74.tar.gz
linux-imx: add clock patch for revision T0 1.0 of i.MX6Q
The post dividers do not work on i.MX6Q rev T0 1.0 so they must be fixed to 1. As the table index was wrong, a divider a of 4 could still be requested which implied the clock not to be set properly. This is the root cause of the HDMI not working at high resolution on rev T0 1.0 of the SoC, giving the following error: mxc_sdc_fb fb.27: timeout when waiting for flip irq Signed-off-by: Gary Bisson <bisson.gary@gmail.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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