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<title>linux/meta-freescale.git/meta-fsl-arm/recipes-bsp/rcw/rcw_git.bb, branch master</title>
<subtitle>Mirror of github.com/Freescale/meta-freescale</subtitle>
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<updated>2015-07-16T18:01:29+00:00</updated>
<entry>
<title>Move meta-fsl-arm content to layer root</title>
<updated>2015-07-16T18:01:29+00:00</updated>
<author>
<name>Otavio Salvador</name>
<email>otavio@ossystems.com.br</email>
</author>
<published>2015-07-15T20:14:27+00:00</published>
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<id>urn:sha1:f8517afc7a5ada4538b3b7d397fa32586d57ffe5</id>
<content type='text'>
The meta-fsl-arm is going to be used as the base for this layer. It
contains a clean history and allowing a more granullar set of changes.

This commit is just a rename of all contents of meta-fsl-arm
subdirectory to this layer's root, subsequent changes are based on top
of that.

Signed-off-by: Otavio Salvador &lt;otavio@ossystems.com.br&gt;
</content>
</entry>
<entry>
<title>rcw: update to revision 426f7a6</title>
<updated>2015-07-13T17:00:59+00:00</updated>
<author>
<name>Ting Liu</name>
<email>ting.liu@freescale.com</email>
</author>
<published>2015-07-10T09:45:16+00:00</published>
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<id>urn:sha1:4eb1f76f151ae88c5ea0a50458ace6fa15792913</id>
<content type='text'>
This imports following changes:

426f7a6 SECURE BOOT: Add missing RCW's for T4240QDS
756454f SECURE BOOT: Rename the RCW's
7782087 SECURE BOOT: Remove Unwanted RCW's
e93c210 LS1021: Unset BOOT_HO bit in rcw.
4375fc4 t1023rdb: update IFC_MODE to 0x2F for errata A-009138
5cf9bc5 T4240QDS: Add four 1800MHz/Core RCW files for T4240QDS board
cff536a t1023rdb: set RTC=1 to enable GPIO1[14]
a5983f2 T4240RDB: Add one new RCW for T4240RDB board
3a6ae48 ls1021a: fix some serdes settings for SATA
31078e1 ls1021atwr: do not power down PLL which is used by SATA
c6d72e3 t2080qds: rcw: Add eMMC DDR mode RCW
c77415c T104xD4RDB: update SRDS_PLL_REF_CLK_SEL_S1 value
e2c0844 ls1021atwr: add USB 2.0 support
fd0c1df p5020/p5040: NAND Secure Boot RCW added with PBI commands
259d57d t1023rdb: add rcw for t1023rdb board
c3ab906 T1042: Add t1042d4rdb rcw files for serdes protocol 0x86
ae39560 T1040: Add t1040d4rdb rcw files for serdes protocol 0x66
b9d3c22 p3041: NAND Secure Boot RCW added with PBI commands
dc0fad9 t2080rdb: update ddr to 1866MT/s
03c5ee6 t2080: update platform clock to 600MHz
72945fa rcw: ls102xa: merge rcw for lpuart and dcu
6678741 rcw: ls102xa: Adjust the features supported in SD boot
f7a54c1 arm: ls102xa: Increase IO drive strength for LS1021AQDS board
3dd07fa B4860-As-B3: Add two new RCW files
69a041c B4860QDS: Add HWA_CGA_M3_CLK_SEL bits define in b4860.rcwi file
87289d5 ls102xa: rcw: Add QSPI boot RCW for LS1021A TWR board
13bf692 t1024: update FM1_MAC_RAT from 0 to 1
5b94b3e t1024rdb: add new rcw 0x135 and minor update

Signed-off-by: Ting Liu &lt;ting.liu@freescale.com&gt;
Signed-off-by: Otavio Salvador &lt;otavio@ossystems.com.br&gt;
</content>
</entry>
<entry>
<title>rcw: Added change-file-endianess as DEPENDS</title>
<updated>2015-02-06T01:08:27+00:00</updated>
<author>
<name>Chunrong Guo</name>
<email>B40290@freescale.com</email>
</author>
<published>2015-02-04T07:18:12+00:00</published>
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<id>urn:sha1:cd7c18c2c3ad1ae282c9c9c9b83e847061b371d1</id>
<content type='text'>
Signed-off-by: Chunrong Guo &lt;B40290@freescale.com&gt;
Signed-off-by: Otavio Salvador &lt;otavio@ossystems.com.br&gt;
</content>
</entry>
<entry>
<title>rcw: update to sdk v1.7 release</title>
<updated>2015-01-06T11:22:00+00:00</updated>
<author>
<name>Chunrong Guo</name>
<email>B40290@freescale.com</email>
</author>
<published>2015-01-06T06:42:12+00:00</published>
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<id>urn:sha1:01787cad5f86465828e2cbf2b96914012bbe402b</id>
<content type='text'>
Signed-off-by: Chunrong Guo &lt;B40290@freescale.com&gt;
Signed-off-by: Otavio Salvador &lt;otavio@ossystems.com.br&gt;
</content>
</entry>
<entry>
<title>rcw : Update to 38ec2c9 revision</title>
<updated>2014-11-08T19:30:52+00:00</updated>
<author>
<name>Chunrong Guo</name>
<email>B40290@freescale.com</email>
</author>
<published>2014-11-05T03:34:25+00:00</published>
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<id>urn:sha1:3e72b6e2f742921837d3e45b3a4c5bc2a852ff7b</id>
<content type='text'>
   This includes following changes:

   69c87db ls1021aqds: set value of uboot entry address for qspiboot
   a59bea9 ls1021a: add rcw for enable sai
   ca0b3d1 ls1021aqds: sdboot: fix value of PBI_SRC and IFC_MODE
   3ac85c8 ls1021atwr: add rcw for SD card boot
   43707fa ls1021aqds: add rcw for NAND boot
   1948685 ls1021a: remove custom part number "letech"

Signed-off-by: Chunrong Guo &lt;B40290@freescale.com&gt;
Signed-off-by: Otavio Salvador &lt;otavio@ossystems.com.br&gt;
</content>
</entry>
<entry>
<title>rcw: add recipes for Layerscape1 support</title>
<updated>2014-09-15T12:35:13+00:00</updated>
<author>
<name>Zhenhua Luo</name>
<email>zhenhua.luo@freescale.com</email>
</author>
<published>2014-09-04T04:33:17+00:00</published>
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<id>urn:sha1:697ad1578d9bbcaf2ca638324f094f1e288d484b</id>
<content type='text'>
The reset configuration word (RCW) manages the hardware configuration
info for QorIQ targets, rcw is used by the preboot loader to begin
system configuration.

Signed-off-by: Zhenhua Luo &lt;zhenhua.luo@freescale.com&gt;
Signed-off-by: Otavio Salvador &lt;otavio@ossystems.com.br&gt;
</content>
</entry>
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