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<title>linux/enea-kernel-cache.git/features/apic, branch intel-5.10</title>
<subtitle>[no description]</subtitle>
<id>https://git.enea.com/cgit/linux/enea-kernel-cache.git/atom?h=intel-5.10</id>
<link rel='self' href='https://git.enea.com/cgit/linux/enea-kernel-cache.git/atom?h=intel-5.10'/>
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<updated>2019-05-13T07:29:49+00:00</updated>
<entry>
<title>Add x2APIC support</title>
<updated>2019-05-13T07:29:49+00:00</updated>
<author>
<name>Adrian Calianu</name>
<email>adrian.calianu@enea.com</email>
</author>
<published>2019-05-13T07:29:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/enea-kernel-cache.git/commit/?id=12f0763e9384b52f8618fba5b7a70748d4a2da05'/>
<id>urn:sha1:12f0763e9384b52f8618fba5b7a70748d4a2da05</id>
<content type='text'>
It provides interrupt re-mapping support. In case
x2APIC is not available xAPIC will be enabled which also
support interrupt re-mapping.

Change-Id: I7c61194d9b9d8cb6d82d5f978000c363824c58a3
Signed-off-by: Adrian Calianu &lt;adrian.calianu@enea.com&gt;
</content>
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