From 12e2d10541b0b7b1cc6bd601d8b2519a104cc29f Mon Sep 17 00:00:00 2001 From: Richard Purdie Date: Thu, 4 May 2023 11:39:58 +0100 Subject: qemu: Add fix for powerpc instruction fallback issue See the patch for more details, fixes a regression in qemu causing illegal instructions in libm on powerpc, triggered by a libinput upgrade. https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=f1c56cdff09f650ad721fae026eb6a3651631f3d was the glibc code generating the instruction and triggering the issue. (From OE-Core rev: bf0e4c8bb6ba22274d17d74c1df69a78f8aa157c) Signed-off-by: Richard Purdie --- meta/recipes-devtools/qemu/qemu/ppc.patch | 70 +++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 meta/recipes-devtools/qemu/qemu/ppc.patch (limited to 'meta/recipes-devtools/qemu/qemu') diff --git a/meta/recipes-devtools/qemu/qemu/ppc.patch b/meta/recipes-devtools/qemu/qemu/ppc.patch new file mode 100644 index 0000000000..ade1daf61f --- /dev/null +++ b/meta/recipes-devtools/qemu/qemu/ppc.patch @@ -0,0 +1,70 @@ +target/ppc: Fix fallback to MFSS for MFFSCRN, MFFSCRNI, MFFSCE and MFFSL + +The following commits changed the code such that these instructions became invalid +on pre 3.0 ISAs: + + bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to decodetree + 394c2e2fda70da722f20fb60412d6c0ca4bfaa03 - target/ppc: Move mffsce to decodetree + 3e5bce70efe6bd1f684efbb21fd2a316cbf0657e - target/ppc: Move mffsl to decodetree + +The hardware will handle them as a MFFS instruction as the code did previously. +Restore that behaviour. This means applications that were segfaulting under qemu +when encountering these instructions now operate correctly. The instruction +is used in glibc libm functions for example. + +Upstream-Status: Submitted [https://lore.kernel.org/qemu-devel/20230504110150.3044402-1-richard.purdie@linuxfoundation.org/] + +Signed-off-by: Richard Purdie + +Index: qemu-8.0.0/target/ppc/translate/fp-impl.c.inc +=================================================================== +--- qemu-8.0.0.orig/target/ppc/translate/fp-impl.c.inc ++++ qemu-8.0.0/target/ppc/translate/fp-impl.c.inc +@@ -584,7 +584,10 @@ static bool trans_MFFSCE(DisasContext *c + { + TCGv_i64 fpscr; + +- REQUIRE_INSNS_FLAGS2(ctx, ISA300); ++ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { ++ return trans_MFFS(ctx, a); ++ } ++ + REQUIRE_FPU(ctx); + + gen_reset_fpstatus(); +@@ -597,7 +600,10 @@ static bool trans_MFFSCRN(DisasContext * + { + TCGv_i64 t1, fpscr; + +- REQUIRE_INSNS_FLAGS2(ctx, ISA300); ++ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { ++ return trans_MFFS(ctx, a); ++ } ++ + REQUIRE_FPU(ctx); + + t1 = tcg_temp_new_i64(); +@@ -631,7 +637,10 @@ static bool trans_MFFSCRNI(DisasContext + { + TCGv_i64 t1, fpscr; + +- REQUIRE_INSNS_FLAGS2(ctx, ISA300); ++ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { ++ return trans_MFFS(ctx, a); ++ } ++ + REQUIRE_FPU(ctx); + + t1 = tcg_temp_new_i64(); +@@ -661,7 +670,10 @@ static bool trans_MFFSCDRNI(DisasContext + + static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a) + { +- REQUIRE_INSNS_FLAGS2(ctx, ISA300); ++ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { ++ return trans_MFFS(ctx, a); ++ } ++ + REQUIRE_FPU(ctx); + + gen_reset_fpstatus(); -- cgit v1.2.3-54-g00ecf