From b1650772a269f0c939662237bc3a1db953acf9f4 Mon Sep 17 00:00:00 2001 From: Martin Jansa Date: Fri, 15 Sep 2023 22:42:47 +0200 Subject: gcc: backport a fix for ICE caused by CVE-2023-4039.patch * see: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111418 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111411 * add git headers to 0025-gcc-testsuite-mips.patch so that it does easily apply with other patches with git am (From OE-Core rev: 760068c5868380b0e833155020365735f55314c3) Signed-off-by: Martin Jansa Signed-off-by: Richard Purdie --- meta/recipes-devtools/gcc/gcc-13.2.inc | 3 +- .../gcc/gcc/0025-gcc-testsuite-mips.patch | 225 -------------------- .../0025-gcc-testsuite-tweaks-for-mips-OE.patch | 233 +++++++++++++++++++++ ...6-aarch64-Fix-loose-ldpstp-check-PR111411.patch | 117 +++++++++++ 4 files changed, 352 insertions(+), 226 deletions(-) delete mode 100644 meta/recipes-devtools/gcc/gcc/0025-gcc-testsuite-mips.patch create mode 100644 meta/recipes-devtools/gcc/gcc/0025-gcc-testsuite-tweaks-for-mips-OE.patch create mode 100644 meta/recipes-devtools/gcc/gcc/0026-aarch64-Fix-loose-ldpstp-check-PR111411.patch (limited to 'meta/recipes-devtools/gcc') diff --git a/meta/recipes-devtools/gcc/gcc-13.2.inc b/meta/recipes-devtools/gcc/gcc-13.2.inc index 0922251e18..d96f3171e4 100644 --- a/meta/recipes-devtools/gcc/gcc-13.2.inc +++ b/meta/recipes-devtools/gcc/gcc-13.2.inc @@ -64,8 +64,9 @@ SRC_URI = "${BASEURI} \ file://0022-libatomic-Do-not-enforce-march-on-aarch64.patch \ file://0023-Fix-install-path-of-linux64.h.patch \ file://0024-Avoid-hardcoded-build-paths-into-ppc-libgcc.patch \ - file://0025-gcc-testsuite-mips.patch \ + file://0025-gcc-testsuite-tweaks-for-mips-OE.patch \ file://CVE-2023-4039.patch \ + file://0026-aarch64-Fix-loose-ldpstp-check-PR111411.patch \ " SRC_URI[sha256sum] = "e275e76442a6067341a27f04c5c6b83d8613144004c0413528863dc6b5c743da" diff --git a/meta/recipes-devtools/gcc/gcc/0025-gcc-testsuite-mips.patch b/meta/recipes-devtools/gcc/gcc/0025-gcc-testsuite-mips.patch deleted file mode 100644 index 49eaece923..0000000000 --- a/meta/recipes-devtools/gcc/gcc/0025-gcc-testsuite-mips.patch +++ /dev/null @@ -1,225 +0,0 @@ -gcc testsuite tweaks for mips/OE - -Disable loongson-mmi runtine, qemu doesn't appear to fully support them even if some -of the instruction decoding is there. - -Also disable MSA mips runtime extensions. For some reason qemu appears to accept the test -code when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them. - -MIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops -multiple times through the vector testsuite. In the case of the two above, we can -compile/link them but not run them. Even with the runtime disabled, if the code -marks it as a runtime test, it will elevate itself to that. Setting the default -target to compile therefore isn't enough. - -Therefore add code to downgrade runtime tests to link tests if the hardware -support isn't there to run them. This avoids thousands of test failures. To do -this we have to hook downgrade code into the main test runner. - -Enable that downgrading for other cases where hardware to run vector extensions is -unavailable to remove test failures on other architectures too. - -Also, for gcc.target tests, add checks on wheter loongson or msa code can -be run before trying that, allowing downgrading of tests there to work too. - -Upstream-Status: Pending -[Parts of the patch may be able to be split off and acceptable to upstream with -discussion. Need to investigate why qemu-user passes the 'bad' instructions'] - -Signed-off-by: Richard Purdie - -Index: gcc-13.2.0/gcc/testsuite/lib/target-supports.exp -=================================================================== ---- gcc-13.2.0.orig/gcc/testsuite/lib/target-supports.exp -+++ gcc-13.2.0/gcc/testsuite/lib/target-supports.exp -@@ -2155,14 +2155,7 @@ proc check_mips_loongson_mmi_hw_availabl - if { !([istarget mips*-*-*]) } { - expr 0 - } else { -- check_runtime_nocache mips_loongson_mmi_hw_available { -- #include -- int main() -- { -- asm volatile ("paddw $f2,$f4,$f6"); -- return 0; -- } -- } "-mloongson-mmi" -+ expr 0 - } - }] - } -@@ -2176,29 +2169,7 @@ proc check_mips_msa_hw_available { } { - if { !([istarget mips*-*-*]) } { - expr 0 - } else { -- check_runtime_nocache mips_msa_hw_available { -- #if !defined(__mips_msa) -- #error "MSA NOT AVAIL" -- #else -- #if !(((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2)) -- #error "MSA NOT AVAIL FOR ISA REV < 2" -- #endif -- #if !defined(__mips_hard_float) -- #error "MSA HARD_FLOAT REQUIRED" -- #endif -- #if __mips_fpr != 64 -- #error "MSA 64-bit FPR REQUIRED" -- #endif -- #include -- -- int main() -- { -- v8i16 v = __builtin_msa_ldi_h (0); -- v[0] = 0; -- return v[0]; -- } -- #endif -- } "-mmsa" -+ expr 0 - } - }] - } -@@ -9187,6 +9158,7 @@ proc is-effective-target-keyword { arg } - - proc et-dg-runtest { runtest testcases flags default-extra-flags } { - global dg-do-what-default -+ global do-what-limit - global EFFECTIVE_TARGETS - global et_index - -@@ -9194,6 +9166,7 @@ proc et-dg-runtest { runtest testcases f - foreach target $EFFECTIVE_TARGETS { - set target_flags $flags - set dg-do-what-default compile -+ set do-what-limit link - set et_index [lsearch -exact $EFFECTIVE_TARGETS $target] - if { [info procs add_options_for_${target}] != [list] } { - set target_flags [add_options_for_${target} "$flags"] -@@ -9201,8 +9174,10 @@ proc et-dg-runtest { runtest testcases f - if { [info procs check_effective_target_${target}_runtime] - != [list] && [check_effective_target_${target}_runtime] } { - set dg-do-what-default run -+ set do-what-limit run - } - $runtest $testcases $target_flags ${default-extra-flags} -+ unset do-what-limit - } - } else { - set et_index 0 -@@ -10789,6 +10764,7 @@ proc check_effective_target_sigsetjmp {} - proc check_vect_support_and_set_flags { } { - global DEFAULT_VECTCFLAGS - global dg-do-what-default -+ global do-what-limit - global EFFECTIVE_TARGETS - - if [istarget powerpc-*paired*] { -@@ -10797,6 +10773,7 @@ proc check_vect_support_and_set_flags { - set dg-do-what-default run - } else { - set dg-do-what-default compile -+ set do-what-limit link - } - } elseif [istarget powerpc*-*-*] { - # Skip targets not supporting -maltivec. -@@ -10821,6 +10798,7 @@ proc check_vect_support_and_set_flags { - lappend DEFAULT_VECTCFLAGS "-mcpu=970" - } - set dg-do-what-default compile -+ set do-what-limit link - } - } elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } { - lappend DEFAULT_VECTCFLAGS "-msse2" -@@ -10828,6 +10806,7 @@ proc check_vect_support_and_set_flags { - set dg-do-what-default run - } else { - set dg-do-what-default compile -+ set do-what-limit link - } - } elseif { [istarget mips*-*-*] - && [check_effective_target_nomips16] } { -@@ -10847,6 +10826,7 @@ proc check_vect_support_and_set_flags { - set dg-do-what-default run - } else { - set dg-do-what-default compile -+ set do-what-limit link - } - } elseif [istarget alpha*-*-*] { - # Alpha's vectorization capabilities are extremely limited. -@@ -10860,6 +10840,7 @@ proc check_vect_support_and_set_flags { - set dg-do-what-default run - } else { - set dg-do-what-default compile -+ set do-what-limit link - } - } elseif [istarget ia64-*-*] { - set dg-do-what-default run -@@ -10873,6 +10854,7 @@ proc check_vect_support_and_set_flags { - set dg-do-what-default run - } else { - set dg-do-what-default compile -+ set do-what-limit link - } - } elseif [istarget aarch64*-*-*] { - set dg-do-what-default run -@@ -10897,6 +10879,7 @@ proc check_vect_support_and_set_flags { - } else { - lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch" - set dg-do-what-default compile -+ set do-what-limit link - } - } elseif [istarget amdgcn-*-*] { - set dg-do-what-default run -Index: gcc-13.2.0/gcc/testsuite/gcc.target/mips/mips.exp -=================================================================== ---- gcc-13.2.0.orig/gcc/testsuite/gcc.target/mips/mips.exp -+++ gcc-13.2.0/gcc/testsuite/gcc.target/mips/mips.exp -@@ -709,7 +709,23 @@ proc mips_first_unsupported_option { ups - global mips_option_tests - upvar $upstatus status - -+ if { [mips_have_test_option_p status "-mmsa"] } { -+ verbose -log "Found -mmsa" -+ if { ![check_mips_msa_hw_available] } { -+ verbose -log "No MSA avail" -+ return "-mmsa" -+ } -+ } -+ if { [mips_have_test_option_p status "-mloongson-mmi"] } { -+ verbose -log "Found -mloonson-mmi" -+ if { ![check_mips_loongson_mmi_hw_available] } { -+ verbose -log "No MMI avail" -+ return "-mloonson-mmi" -+ } -+ } -+ - foreach { option code } [array get mips_option_tests] { -+ - if { [mips_have_test_option_p status $option] } { - regsub -all "\n" $code "\\n\\\n" asm - # Use check_runtime from target-supports.exp, which caches -Index: gcc-13.2.0/gcc/testsuite/lib/gcc-dg.exp -=================================================================== ---- gcc-13.2.0.orig/gcc/testsuite/lib/gcc-dg.exp -+++ gcc-13.2.0/gcc/testsuite/lib/gcc-dg.exp -@@ -240,9 +240,20 @@ proc schedule-cleanups { opts } { - - proc gcc-dg-test-1 { target_compile prog do_what extra_tool_flags } { - # Set up the compiler flags, based on what we're going to do. -+ global do-what-limit - - set options [list] - -+ if [info exists do-what-limit] then { -+ # Demote run tests to $do-what-limit if set -+ switch $do_what { -+ run { -+ set do_what $do-what-limit -+ set dg-do-what $do-what-limit -+ } -+ } -+ } -+ - switch $do_what { - "preprocess" { - set compile_type "preprocess" diff --git a/meta/recipes-devtools/gcc/gcc/0025-gcc-testsuite-tweaks-for-mips-OE.patch b/meta/recipes-devtools/gcc/gcc/0025-gcc-testsuite-tweaks-for-mips-OE.patch new file mode 100644 index 0000000000..c405d8d484 --- /dev/null +++ b/meta/recipes-devtools/gcc/gcc/0025-gcc-testsuite-tweaks-for-mips-OE.patch @@ -0,0 +1,233 @@ +From f12acc6a383546d48da3bdfb2f25ca2adb7976d7 Mon Sep 17 00:00:00 2001 +From: Richard Purdie +Date: Sun, 13 Aug 2023 10:24:05 +0100 +Subject: [PATCH] gcc testsuite tweaks for mips/OE + +Disable loongson-mmi runtine, qemu doesn't appear to fully support them even if some +of the instruction decoding is there. + +Also disable MSA mips runtime extensions. For some reason qemu appears to accept the test +code when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them. + +MIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops +multiple times through the vector testsuite. In the case of the two above, we can +compile/link them but not run them. Even with the runtime disabled, if the code +marks it as a runtime test, it will elevate itself to that. Setting the default +target to compile therefore isn't enough. + +Therefore add code to downgrade runtime tests to link tests if the hardware +support isn't there to run them. This avoids thousands of test failures. To do +this we have to hook downgrade code into the main test runner. + +Enable that downgrading for other cases where hardware to run vector extensions is +unavailable to remove test failures on other architectures too. + +Also, for gcc.target tests, add checks on wheter loongson or msa code can +be run before trying that, allowing downgrading of tests there to work too. + +Upstream-Status: Pending +[Parts of the patch may be able to be split off and acceptable to upstream with +discussion. Need to investigate why qemu-user passes the 'bad' instructions'] + +Signed-off-by: Richard Purdie +--- + gcc/testsuite/gcc.target/mips/mips.exp | 16 +++++++++ + gcc/testsuite/lib/gcc-dg.exp | 11 +++++++ + gcc/testsuite/lib/target-supports.exp | 45 ++++++++------------------ + 3 files changed, 41 insertions(+), 31 deletions(-) + +diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp +index 15d574202d3..2cef9709774 100644 +--- a/gcc/testsuite/gcc.target/mips/mips.exp ++++ b/gcc/testsuite/gcc.target/mips/mips.exp +@@ -709,7 +709,23 @@ proc mips_first_unsupported_option { upstatus } { + global mips_option_tests + upvar $upstatus status + ++ if { [mips_have_test_option_p status "-mmsa"] } { ++ verbose -log "Found -mmsa" ++ if { ![check_mips_msa_hw_available] } { ++ verbose -log "No MSA avail" ++ return "-mmsa" ++ } ++ } ++ if { [mips_have_test_option_p status "-mloongson-mmi"] } { ++ verbose -log "Found -mloonson-mmi" ++ if { ![check_mips_loongson_mmi_hw_available] } { ++ verbose -log "No MMI avail" ++ return "-mloonson-mmi" ++ } ++ } ++ + foreach { option code } [array get mips_option_tests] { ++ + if { [mips_have_test_option_p status $option] } { + regsub -all "\n" $code "\\n\\\n" asm + # Use check_runtime from target-supports.exp, which caches +diff --git a/gcc/testsuite/lib/gcc-dg.exp b/gcc/testsuite/lib/gcc-dg.exp +index 9d79b9402e9..e0e5cbb1af8 100644 +--- a/gcc/testsuite/lib/gcc-dg.exp ++++ b/gcc/testsuite/lib/gcc-dg.exp +@@ -240,9 +240,20 @@ proc schedule-cleanups { opts } { + + proc gcc-dg-test-1 { target_compile prog do_what extra_tool_flags } { + # Set up the compiler flags, based on what we're going to do. ++ global do-what-limit + + set options [list] + ++ if [info exists do-what-limit] then { ++ # Demote run tests to $do-what-limit if set ++ switch $do_what { ++ run { ++ set do_what $do-what-limit ++ set dg-do-what $do-what-limit ++ } ++ } ++ } ++ + switch $do_what { + "preprocess" { + set compile_type "preprocess" +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index 40f71e9ed8b..10e267fa16d 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -2155,14 +2155,7 @@ proc check_mips_loongson_mmi_hw_available { } { + if { !([istarget mips*-*-*]) } { + expr 0 + } else { +- check_runtime_nocache mips_loongson_mmi_hw_available { +- #include +- int main() +- { +- asm volatile ("paddw $f2,$f4,$f6"); +- return 0; +- } +- } "-mloongson-mmi" ++ expr 0 + } + }] + } +@@ -2176,29 +2169,7 @@ proc check_mips_msa_hw_available { } { + if { !([istarget mips*-*-*]) } { + expr 0 + } else { +- check_runtime_nocache mips_msa_hw_available { +- #if !defined(__mips_msa) +- #error "MSA NOT AVAIL" +- #else +- #if !(((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2)) +- #error "MSA NOT AVAIL FOR ISA REV < 2" +- #endif +- #if !defined(__mips_hard_float) +- #error "MSA HARD_FLOAT REQUIRED" +- #endif +- #if __mips_fpr != 64 +- #error "MSA 64-bit FPR REQUIRED" +- #endif +- #include +- +- int main() +- { +- v8i16 v = __builtin_msa_ldi_h (0); +- v[0] = 0; +- return v[0]; +- } +- #endif +- } "-mmsa" ++ expr 0 + } + }] + } +@@ -9187,6 +9158,7 @@ proc is-effective-target-keyword { arg } { + + proc et-dg-runtest { runtest testcases flags default-extra-flags } { + global dg-do-what-default ++ global do-what-limit + global EFFECTIVE_TARGETS + global et_index + +@@ -9194,6 +9166,7 @@ proc et-dg-runtest { runtest testcases flags default-extra-flags } { + foreach target $EFFECTIVE_TARGETS { + set target_flags $flags + set dg-do-what-default compile ++ set do-what-limit link + set et_index [lsearch -exact $EFFECTIVE_TARGETS $target] + if { [info procs add_options_for_${target}] != [list] } { + set target_flags [add_options_for_${target} "$flags"] +@@ -9201,8 +9174,10 @@ proc et-dg-runtest { runtest testcases flags default-extra-flags } { + if { [info procs check_effective_target_${target}_runtime] + != [list] && [check_effective_target_${target}_runtime] } { + set dg-do-what-default run ++ set do-what-limit run + } + $runtest $testcases $target_flags ${default-extra-flags} ++ unset do-what-limit + } + } else { + set et_index 0 +@@ -10789,6 +10764,7 @@ proc check_effective_target_sigsetjmp {} { + proc check_vect_support_and_set_flags { } { + global DEFAULT_VECTCFLAGS + global dg-do-what-default ++ global do-what-limit + global EFFECTIVE_TARGETS + + if [istarget powerpc-*paired*] { +@@ -10797,6 +10773,7 @@ proc check_vect_support_and_set_flags { } { + set dg-do-what-default run + } else { + set dg-do-what-default compile ++ set do-what-limit link + } + } elseif [istarget powerpc*-*-*] { + # Skip targets not supporting -maltivec. +@@ -10821,6 +10798,7 @@ proc check_vect_support_and_set_flags { } { + lappend DEFAULT_VECTCFLAGS "-mcpu=970" + } + set dg-do-what-default compile ++ set do-what-limit link + } + } elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } { + lappend DEFAULT_VECTCFLAGS "-msse2" +@@ -10828,6 +10806,7 @@ proc check_vect_support_and_set_flags { } { + set dg-do-what-default run + } else { + set dg-do-what-default compile ++ set do-what-limit link + } + } elseif { [istarget mips*-*-*] + && [check_effective_target_nomips16] } { +@@ -10847,6 +10826,7 @@ proc check_vect_support_and_set_flags { } { + set dg-do-what-default run + } else { + set dg-do-what-default compile ++ set do-what-limit link + } + } elseif [istarget alpha*-*-*] { + # Alpha's vectorization capabilities are extremely limited. +@@ -10860,6 +10840,7 @@ proc check_vect_support_and_set_flags { } { + set dg-do-what-default run + } else { + set dg-do-what-default compile ++ set do-what-limit link + } + } elseif [istarget ia64-*-*] { + set dg-do-what-default run +@@ -10873,6 +10854,7 @@ proc check_vect_support_and_set_flags { } { + set dg-do-what-default run + } else { + set dg-do-what-default compile ++ set do-what-limit link + } + } elseif [istarget aarch64*-*-*] { + set dg-do-what-default run +@@ -10897,6 +10879,7 @@ proc check_vect_support_and_set_flags { } { + } else { + lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch" + set dg-do-what-default compile ++ set do-what-limit link + } + } elseif [istarget amdgcn-*-*] { + set dg-do-what-default run diff --git a/meta/recipes-devtools/gcc/gcc/0026-aarch64-Fix-loose-ldpstp-check-PR111411.patch b/meta/recipes-devtools/gcc/gcc/0026-aarch64-Fix-loose-ldpstp-check-PR111411.patch new file mode 100644 index 0000000000..a408a98698 --- /dev/null +++ b/meta/recipes-devtools/gcc/gcc/0026-aarch64-Fix-loose-ldpstp-check-PR111411.patch @@ -0,0 +1,117 @@ +From adb60dc78e0da4877747f32347cee339364775be Mon Sep 17 00:00:00 2001 +From: Richard Sandiford +Date: Fri, 15 Sep 2023 09:19:14 +0100 +Subject: [PATCH] aarch64: Fix loose ldpstp check [PR111411] + +aarch64_operands_ok_for_ldpstp contained the code: + + /* One of the memory accesses must be a mempair operand. + If it is not the first one, they need to be swapped by the + peephole. */ + if (!aarch64_mem_pair_operand (mem_1, GET_MODE (mem_1)) + && !aarch64_mem_pair_operand (mem_2, GET_MODE (mem_2))) + return false; + +But the requirement isn't just that one of the accesses must be a +valid mempair operand. It's that the lower access must be, since +that's the access that will be used for the instruction operand. + +gcc/ + PR target/111411 + * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp): Require + the lower memory access to a mem-pair operand. + +gcc/testsuite/ + PR target/111411 + * gcc.dg/rtl/aarch64/pr111411.c: New test. + +Upstream-Status: Backport [https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=2d38f45bcca62ca0c7afef4b579f82c5c2a01610] +Signed-off-by: Martin Jansa +--- + gcc/config/aarch64/aarch64.cc | 8 ++- + gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c | 57 +++++++++++++++++++++ + 2 files changed, 60 insertions(+), 5 deletions(-) + create mode 100644 gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c + +diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc +index 6118a3354ac..9b1f791ca8b 100644 +--- a/gcc/config/aarch64/aarch64.cc ++++ b/gcc/config/aarch64/aarch64.cc +@@ -26154,11 +26154,9 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load, + gcc_assert (known_eq (GET_MODE_SIZE (GET_MODE (mem_1)), + GET_MODE_SIZE (GET_MODE (mem_2)))); + +- /* One of the memory accesses must be a mempair operand. +- If it is not the first one, they need to be swapped by the +- peephole. */ +- if (!aarch64_mem_pair_operand (mem_1, GET_MODE (mem_1)) +- && !aarch64_mem_pair_operand (mem_2, GET_MODE (mem_2))) ++ /* The lower memory access must be a mem-pair operand. */ ++ rtx lower_mem = reversed ? mem_2 : mem_1; ++ if (!aarch64_mem_pair_operand (lower_mem, GET_MODE (lower_mem))) + return false; + + if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1))) +diff --git a/gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c b/gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c +new file mode 100644 +index 00000000000..ad07e9c6c89 +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/rtl/aarch64/pr111411.c +@@ -0,0 +1,57 @@ ++/* { dg-do compile { target aarch64*-*-* } } */ ++/* { dg-require-effective-target lp64 } */ ++/* { dg-options "-O -fdisable-rtl-postreload -fpeephole2 -fno-schedule-fusion" } */ ++ ++extern int data[]; ++ ++void __RTL (startwith ("ira")) foo (void *ptr) ++{ ++ (function "foo" ++ (param "ptr" ++ (DECL_RTL (reg/v:DI <0> [ ptr ])) ++ (DECL_RTL_INCOMING (reg/v:DI x0 [ ptr ])) ++ ) ;; param "ptr" ++ (insn-chain ++ (block 2 ++ (edge-from entry (flags "FALLTHRU")) ++ (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) ++ (insn 4 (set (reg:DI <0>) (reg:DI x0))) ++ (insn 5 (set (reg:DI <1>) ++ (plus:DI (reg:DI <0>) (const_int 768)))) ++ (insn 6 (set (mem:SI (plus:DI (reg:DI <0>) ++ (const_int 508)) [1 &data+508 S4 A4]) ++ (const_int 0))) ++ (insn 7 (set (mem:SI (plus:DI (reg:DI <1>) ++ (const_int -256)) [1 &data+512 S4 A4]) ++ (const_int 0))) ++ (edge-to exit (flags "FALLTHRU")) ++ ) ;; block 2 ++ ) ;; insn-chain ++ ) ;; function ++} ++ ++void __RTL (startwith ("ira")) bar (void *ptr) ++{ ++ (function "bar" ++ (param "ptr" ++ (DECL_RTL (reg/v:DI <0> [ ptr ])) ++ (DECL_RTL_INCOMING (reg/v:DI x0 [ ptr ])) ++ ) ;; param "ptr" ++ (insn-chain ++ (block 2 ++ (edge-from entry (flags "FALLTHRU")) ++ (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) ++ (insn 4 (set (reg:DI <0>) (reg:DI x0))) ++ (insn 5 (set (reg:DI <1>) ++ (plus:DI (reg:DI <0>) (const_int 768)))) ++ (insn 6 (set (mem:SI (plus:DI (reg:DI <1>) ++ (const_int -256)) [1 &data+512 S4 A4]) ++ (const_int 0))) ++ (insn 7 (set (mem:SI (plus:DI (reg:DI <0>) ++ (const_int 508)) [1 &data+508 S4 A4]) ++ (const_int 0))) ++ (edge-to exit (flags "FALLTHRU")) ++ ) ;; block 2 ++ ) ;; insn-chain ++ ) ;; function ++} -- cgit v1.2.3-54-g00ecf