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-rw-r--r--meta/recipes-devtools/gcc/gcc-4.8.inc1
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.8/0052-PR-rtl-optimization-61801.patch36
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.9.inc1
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.9/0055-PR-rtl-optimization-61801.patch36
4 files changed, 74 insertions, 0 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.8.inc b/meta/recipes-devtools/gcc/gcc-4.8.inc
index dbe1ba6ee0..18a6692687 100644
--- a/meta/recipes-devtools/gcc/gcc-4.8.inc
+++ b/meta/recipes-devtools/gcc/gcc-4.8.inc
@@ -72,6 +72,7 @@ SRC_URI = "\
72 file://0048-PR58854_fix_arm_apcs_epilogue.patch \ 72 file://0048-PR58854_fix_arm_apcs_epilogue.patch \
73 file://0049-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch \ 73 file://0049-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch \
74 file://0050-PR-target-58595.patch \ 74 file://0050-PR-target-58595.patch \
75 file://0052-PR-rtl-optimization-61801.patch \
75" 76"
76SRC_URI[md5sum] = "a3d7d63b9cb6b6ea049469a0c4a43c9d" 77SRC_URI[md5sum] = "a3d7d63b9cb6b6ea049469a0c4a43c9d"
77SRC_URI[sha256sum] = "09dc2276c73424bbbfda1dbddc62bbbf900c9f185acf7f3e1d773ce2d7e3cdc8" 78SRC_URI[sha256sum] = "09dc2276c73424bbbfda1dbddc62bbbf900c9f185acf7f3e1d773ce2d7e3cdc8"
diff --git a/meta/recipes-devtools/gcc/gcc-4.8/0052-PR-rtl-optimization-61801.patch b/meta/recipes-devtools/gcc/gcc-4.8/0052-PR-rtl-optimization-61801.patch
new file mode 100644
index 0000000000..300b2042b2
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.8/0052-PR-rtl-optimization-61801.patch
@@ -0,0 +1,36 @@
1From 8dfe30973ab03f0480f1e249f320e78f210dc230 Mon Sep 17 00:00:00 2001
2From: rguenth <rguenth@138bc75d-0d04-0410-961f-82ee72b054a4>
3Date: Thu, 17 Jul 2014 07:49:44 +0000
4Subject: [PATCH] 2014-07-17 Richard Biener <rguenther@suse.de>
5
6 PR rtl-optimization/61801
7 * sched-deps.c (sched_analyze_2): For ASM_OPERANDS and
8 ASM_INPUT don't set reg_pending_barrier if it appears in a
9 debug-insn.
10
11
12git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@212740 138bc75d-0d04-0410-961f-82ee72b054a4
13
14Upstream-Status: Backport [https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61801]
15Signed-off-by: Peter A. Bigot <pab@pabigot.com>
16
17---
18 gcc/sched-deps.c | 3 ++-
19
20diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c
21index 07857f2..4ac2542 100644
22--- a/gcc/sched-deps.c
23+++ b/gcc/sched-deps.c
24@@ -2744,7 +2744,8 @@ sched_analyze_2 (struct deps_desc *deps, rtx x, rtx insn)
25 Consider for instance a volatile asm that changes the fpu rounding
26 mode. An insn should not be moved across this even if it only uses
27 pseudo-regs because it might give an incorrectly rounded result. */
28- if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
29+ if ((code != ASM_OPERANDS || MEM_VOLATILE_P (x))
30+ && !DEBUG_INSN_P (insn))
31 reg_pending_barrier = TRUE_BARRIER;
32
33 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
34--
351.8.5.5
36
diff --git a/meta/recipes-devtools/gcc/gcc-4.9.inc b/meta/recipes-devtools/gcc/gcc-4.9.inc
index bdea3405ea..25778bd272 100644
--- a/meta/recipes-devtools/gcc/gcc-4.9.inc
+++ b/meta/recipes-devtools/gcc/gcc-4.9.inc
@@ -69,6 +69,7 @@ SRC_URI = "\
69 file://0051-eabispe.patch \ 69 file://0051-eabispe.patch \
70 file://0053-gcc-fix-segfault-from-calling-free-on-non-malloc-d-a.patch \ 70 file://0053-gcc-fix-segfault-from-calling-free-on-non-malloc-d-a.patch \
71 file://0054-gcc-Makefile.in-fix-parallel-building-failure.patch \ 71 file://0054-gcc-Makefile.in-fix-parallel-building-failure.patch \
72 file://0055-PR-rtl-optimization-61801.patch \
72" 73"
73SRC_URI[md5sum] = "fddf71348546af523353bd43d34919c1" 74SRC_URI[md5sum] = "fddf71348546af523353bd43d34919c1"
74SRC_URI[sha256sum] = "d334781a124ada6f38e63b545e2a3b8c2183049515a1abab6d513f109f1d717e" 75SRC_URI[sha256sum] = "d334781a124ada6f38e63b545e2a3b8c2183049515a1abab6d513f109f1d717e"
diff --git a/meta/recipes-devtools/gcc/gcc-4.9/0055-PR-rtl-optimization-61801.patch b/meta/recipes-devtools/gcc/gcc-4.9/0055-PR-rtl-optimization-61801.patch
new file mode 100644
index 0000000000..b27abdef38
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.9/0055-PR-rtl-optimization-61801.patch
@@ -0,0 +1,36 @@
1From 556537c4ad0df4cbebb74197bb2bdea75cf5dd35 Mon Sep 17 00:00:00 2001
2From: rguenth <rguenth@138bc75d-0d04-0410-961f-82ee72b054a4>
3Date: Thu, 17 Jul 2014 07:48:49 +0000
4Subject: [PATCH] 2014-07-17 Richard Biener <rguenther@suse.de>
5
6 PR rtl-optimization/61801
7 * sched-deps.c (sched_analyze_2): For ASM_OPERANDS and
8 ASM_INPUT don't set reg_pending_barrier if it appears in a
9 debug-insn.
10
11
12git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@212739 138bc75d-0d04-0410-961f-82ee72b054a4
13
14Upstream-Status: Backport [https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61801]
15Signed-off-by: Peter A. Bigot <pab@pabigot.com>
16
17---
18 gcc/sched-deps.c | 3 ++-
19
20diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c
21index efc4223..df29bd3 100644
22--- a/gcc/sched-deps.c
23+++ b/gcc/sched-deps.c
24@@ -2750,7 +2750,8 @@ sched_analyze_2 (struct deps_desc *deps, rtx x, rtx insn)
25 Consider for instance a volatile asm that changes the fpu rounding
26 mode. An insn should not be moved across this even if it only uses
27 pseudo-regs because it might give an incorrectly rounded result. */
28- if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
29+ if ((code != ASM_OPERANDS || MEM_VOLATILE_P (x))
30+ && !DEBUG_INSN_P (insn))
31 reg_pending_barrier = TRUE_BARRIER;
32
33 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
34--
351.8.5.5
36