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-rw-r--r--meta/recipes-devtools/binutils/binutils-2.25.1.inc1
-rw-r--r--meta/recipes-devtools/binutils/binutils/binutils-octeon3.patch272
2 files changed, 273 insertions, 0 deletions
diff --git a/meta/recipes-devtools/binutils/binutils-2.25.1.inc b/meta/recipes-devtools/binutils/binutils-2.25.1.inc
index 15ef36ceca..ef85fd460b 100644
--- a/meta/recipes-devtools/binutils/binutils-2.25.1.inc
+++ b/meta/recipes-devtools/binutils/binutils-2.25.1.inc
@@ -32,6 +32,7 @@ SRC_URI = "\
32 file://0012-Add-XLP-instructions-support.patch \ 32 file://0012-Add-XLP-instructions-support.patch \
33 file://0013-Fix-an-internal-error-in-do_print_to_mapfile-seen-wi.patch \ 33 file://0013-Fix-an-internal-error-in-do_print_to_mapfile-seen-wi.patch \
34 file://0014-gold-arm-Skip-pic-check-for-R_ARM_REL32.patch \ 34 file://0014-gold-arm-Skip-pic-check-for-R_ARM_REL32.patch \
35 file://binutils-octeon3.patch \
35 " 36 "
36S = "${WORKDIR}/git" 37S = "${WORKDIR}/git"
37 38
diff --git a/meta/recipes-devtools/binutils/binutils/binutils-octeon3.patch b/meta/recipes-devtools/binutils/binutils/binutils-octeon3.patch
new file mode 100644
index 0000000000..e5beaae197
--- /dev/null
+++ b/meta/recipes-devtools/binutils/binutils/binutils-octeon3.patch
@@ -0,0 +1,272 @@
1Upstream Status: Backport
2
3https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=2c62985659da21a3fe16062d211a7158f79ad2e9
4
5Signed-off-By: Armin Kuster <akuster@mvista.com>
6
7Index: git/bfd/archures.c
8===================================================================
9--- git.orig/bfd/archures.c
10+++ git/bfd/archures.c
11@@ -179,6 +179,7 @@ DESCRIPTION
12 .#define bfd_mach_mips_octeon 6501
13 .#define bfd_mach_mips_octeonp 6601
14 .#define bfd_mach_mips_octeon2 6502
15+.#define bfd_mach_mips_octeon3 6503
16 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
17 .#define bfd_mach_mips_xlp 887680 {* decimal 'XLP' *}
18 .#define bfd_mach_mipsisa32 32
19Index: git/bfd/bfd-in2.h
20===================================================================
21--- git.orig/bfd/bfd-in2.h
22+++ git/bfd/bfd-in2.h
23@@ -1969,6 +1969,7 @@ enum bfd_architecture
24 #define bfd_mach_mips_octeon 6501
25 #define bfd_mach_mips_octeonp 6601
26 #define bfd_mach_mips_octeon2 6502
27+#define bfd_mach_mips_octeon3 6503
28 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
29 #define bfd_mach_mips_xlp 887680 /* decimal 'XLP' */
30 #define bfd_mach_mipsisa32 32
31Index: git/bfd/cpu-mips.c
32===================================================================
33--- git.orig/bfd/cpu-mips.c
34+++ git/bfd/cpu-mips.c
35@@ -102,6 +102,7 @@ enum
36 I_mipsocteon,
37 I_mipsocteonp,
38 I_mipsocteon2,
39+ I_mipsocteon3,
40 I_xlr,
41 I_micromips,
42 I_xlp
43@@ -153,6 +154,7 @@ static const bfd_arch_info_type arch_inf
44 N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
45 N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
46 N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
47+ N (64, 64, bfd_mach_mips_octeon3,"mips:octeon3", FALSE, NN(I_mipsocteon3)),
48 N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
49 N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)),
50 N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0)
51Index: git/bfd/elfxx-mips.c
52===================================================================
53--- git.orig/bfd/elfxx-mips.c
54+++ git/bfd/elfxx-mips.c
55@@ -6604,6 +6604,9 @@ _bfd_elf_mips_mach (flagword flags)
56 case E_MIPS_MACH_LS3A:
57 return bfd_mach_mips_loongson_3a;
58
59+ case E_MIPS_MACH_OCTEON3:
60+ return bfd_mach_mips_octeon3;
61+
62 case E_MIPS_MACH_OCTEON2:
63 return bfd_mach_mips_octeon2;
64
65@@ -11878,6 +11881,10 @@ mips_set_isa_flags (bfd *abfd)
66 val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
67 break;
68
69+ case bfd_mach_mips_octeon3:
70+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON3;
71+ break;
72+
73 case bfd_mach_mips_xlr:
74 val = E_MIPS_ARCH_64 | E_MIPS_MACH_XLR;
75 break;
76@@ -14773,6 +14780,7 @@ struct mips_mach_extension
77 static const struct mips_mach_extension mips_mach_extensions[] =
78 {
79 /* MIPS64r2 extensions. */
80+ { bfd_mach_mips_octeon3, bfd_mach_mips_octeon2 },
81 { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
82 { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
83 { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
84Index: git/gas/config/tc-mips.c
85===================================================================
86--- git.orig/gas/config/tc-mips.c
87+++ git/gas/config/tc-mips.c
88@@ -306,7 +306,7 @@ static unsigned int file_ase_explicit;
89 unsigned long mips_gprmask;
90 unsigned long mips_cprmask[4];
91
92-/* True if any MIPS16 code was produced. */
93+/* 2True if any MIPS16 code was produced. */
94 static int file_ase_mips16;
95
96 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
97@@ -510,7 +510,8 @@ static int mips_32bitmode = 0;
98 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
99
100 /* True if CPU is in the Octeon family */
101-#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
102+#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
103+ || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
104
105 /* True if CPU has seq/sne and seqi/snei instructions. */
106 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
107@@ -18677,6 +18678,7 @@ static const struct mips_cpu_info mips_c
108 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
109 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
110 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
111+ { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R2, CPU_OCTEON3 },
112
113 /* RMI Xlr */
114 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
115Index: git/gas/doc/c-mips.texi
116===================================================================
117--- git.orig/gas/doc/c-mips.texi
118+++ git/gas/doc/c-mips.texi
119@@ -382,6 +382,7 @@ loongson3a,
120 octeon,
121 octeon+,
122 octeon2,
123+octeon3,
124 xlr,
125 xlp
126 @end quotation
127Index: git/gas/testsuite/gas/mips/mips.exp
128===================================================================
129--- git.orig/gas/testsuite/gas/mips/mips.exp
130+++ git/gas/testsuite/gas/mips/mips.exp
131@@ -1102,6 +1102,7 @@ if { [istarget mips*-*-vxworks*] } {
132 run_list_test_arches "octeon-ill" [mips_arch_list_matching octeon]
133 run_dump_test_arches "octeon-pref" [mips_arch_list_matching octeon]
134 run_dump_test_arches "octeon2" [mips_arch_list_matching octeon2]
135+ run_dump_test_arches "octeon3" [mips_arch_list_matching octeon3]
136
137 run_dump_test "smartmips"
138 run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32r2 \
139Index: git/gas/testsuite/gas/mips/octeon3.d
140===================================================================
141--- /dev/null
142+++ git/gas/testsuite/gas/mips/octeon3.d
143@@ -0,0 +1,20 @@
144+#objdump: -d -r --show-raw-insn
145+#name: MIPS octeon3 instructions
146+
147+.*: +file format .*mips.*
148+
149+Disassembly of section .text:
150+
151+[0-9a-f]+ <foo>:
152+.*: 71ec0008 mtm0 t3,t0
153+.*: 71a40008 mtm0 t1,a0
154+.*: 7083000c mtm1 a0,v1
155+.*: 70e1000c mtm1 a3,at
156+.*: 7022000d mtm2 at,v0
157+.*: 7083000c mtm1 a0,v1
158+.*: 70a20009 mtp0 a1,v0
159+.*: 70c40009 mtp0 a2,a0
160+.*: 7083000a mtp1 a0,v1
161+.*: 70e1000a mtp1 a3,at
162+.*: 7022000b mtp2 at,v0
163+.*: 7083000a mtp1 a0,v1
164Index: git/gas/testsuite/gas/mips/octeon3.s
165===================================================================
166--- /dev/null
167+++ git/gas/testsuite/gas/mips/octeon3.s
168@@ -0,0 +1,22 @@
169++ .text
170+ .set noreorder
171+ .set noat
172+
173+foo:
174+ mtm0 $15,$12
175+ mtm0 $13,$4
176+
177+ mtm1 $4,$3
178+ mtm1 $7,$1
179+
180+ mtm2 $1,$2
181+ mtm1 $4,$3
182+
183+ mtp0 $5,$2
184+ mtp0 $6,$4
185+
186+ mtp1 $4,$3
187+ mtp1 $7,$1
188+
189+ mtp2 $1,$2
190+ mtp1 $4,$3
191Index: git/include/opcode/mips.h
192===================================================================
193--- git.orig/include/opcode/mips.h
194+++ git/include/opcode/mips.h
195@@ -1196,6 +1196,7 @@ static const unsigned int mips_isa_table
196 #define INSN_OCTEON 0x00000800
197 #define INSN_OCTEONP 0x00000200
198 #define INSN_OCTEON2 0x00000100
199+#define INSN_OCTEON3 0x00000040
200
201 /* MIPS R5900 instruction */
202 #define INSN_5900 0x00004000
203@@ -1325,6 +1326,7 @@ static const unsigned int mips_isa_table
204 #define CPU_OCTEON 6501
205 #define CPU_OCTEONP 6601
206 #define CPU_OCTEON2 6502
207+#define CPU_OCTEON3 6503
208 #define CPU_XLR 887682 /* decimal 'XLR' */
209 #define CPU_XLP 887680 /* decimal 'XLP' */
210
211@@ -1391,6 +1393,9 @@ cpu_is_member (int cpu, unsigned int mas
212 case CPU_OCTEON2:
213 return (mask & INSN_OCTEON2) != 0;
214
215+ case CPU_OCTEON3:
216+ return (mask & INSN_OCTEON3) != 0;
217+
218 case CPU_XLR:
219 return (mask & INSN_XLR) != 0;
220
221Index: git/opcodes/mips-dis.c
222===================================================================
223--- git.orig/opcodes/mips-dis.c
224+++ git/opcodes/mips-dis.c
225@@ -649,6 +649,11 @@ const struct mips_arch_choice mips_arch_
226 ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
227 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
228
229+ { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3,
230+ ISA_MIPS64R2 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64,
231+ mips_cp0_names_numeric,
232+ NULL, 0, mips_hwr_names_numeric },
233+
234 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
235 ISA_MIPS64 | INSN_XLR, 0,
236 mips_cp0_names_xlr,
237Index: git/opcodes/mips-opc.c
238===================================================================
239--- git.orig/opcodes/mips-opc.c
240+++ git/opcodes/mips-opc.c
241@@ -316,9 +316,10 @@ decode_mips_operand (const char *p)
242 #define N5 (INSN_5400 | INSN_5500)
243 #define N54 INSN_5400
244 #define N55 INSN_5500
245-#define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
246-#define IOCTP (INSN_OCTEONP | INSN_OCTEON2)
247-#define IOCT2 INSN_OCTEON2
248+#define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
249+#define IOCTP (INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
250+#define IOCT2 (INSN_OCTEON2 | INSN_OCTEON3)
251+#define IOCT3 INSN_OCTEON3
252 #define XLR INSN_XLR
253 #define XLP INSN_XLP
254 #define IVIRT ASE_VIRT
255@@ -1505,11 +1506,17 @@ const struct mips_opcode mips_builtin_op
256 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
257 {"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 },
258 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
259+{"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
260 {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
261+{"mtm1", "s,t", 0x7000000c, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
262 {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
263+{"mtm2", "s,t", 0x7000000d, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
264 {"mtp0", "s", 0x70000009, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
265+{"mtp0", "s,t", 0x70000009, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
266 {"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
267+{"mtp1", "s,t", 0x7000000a, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
268 {"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
269+{"mtp2", "s,t", 0x7000000b, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
270 {"mtsa", "s", 0x00000029, 0xfc1fffff, RD_1, 0, EE, 0, 0 },
271 {"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_1, 0, EE, 0, 0 },
272 {"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_1, 0, EE, 0, 0 },
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-14 01:30:13 +0000