diff options
Diffstat (limited to 'meta/recipes-kernel/oprofile/oprofile/0001-Add-freescale-e500mc-support.patch')
-rw-r--r-- | meta/recipes-kernel/oprofile/oprofile/0001-Add-freescale-e500mc-support.patch | 219 |
1 files changed, 219 insertions, 0 deletions
diff --git a/meta/recipes-kernel/oprofile/oprofile/0001-Add-freescale-e500mc-support.patch b/meta/recipes-kernel/oprofile/oprofile/0001-Add-freescale-e500mc-support.patch new file mode 100644 index 0000000000..077da4bf2b --- /dev/null +++ b/meta/recipes-kernel/oprofile/oprofile/0001-Add-freescale-e500mc-support.patch | |||
@@ -0,0 +1,219 @@ | |||
1 | From ca3f796b3a7742215ed35b56fc072595174c410e Mon Sep 17 00:00:00 2001 | ||
2 | From: Ting Liu <b28495@freescale.com> | ||
3 | Date: Thu, 5 Sep 2013 07:43:55 -0500 | ||
4 | Subject: [PATCH 1/2] Add freescale e500mc support | ||
5 | |||
6 | Upstream-Status: Backport | ||
7 | |||
8 | Signed-off-by: George Stephen <Stephen.George@freescale.com> | ||
9 | Signed-off-by: Zhenhua Luo <zhenhua.luo@freescale.com> | ||
10 | Signed-off-by: Ting Liu <b28495@freescale.com> | ||
11 | --- | ||
12 | events/Makefile.am | 1 + | ||
13 | events/ppc/e500mc/events | 120 ++++++++++++++++++++++++++++++++++++++++++ | ||
14 | events/ppc/e500mc/unit_masks | 4 ++ | ||
15 | libop/op_cpu_type.c | 1 + | ||
16 | libop/op_cpu_type.h | 1 + | ||
17 | libop/op_events.c | 1 + | ||
18 | utils/ophelp.c | 1 + | ||
19 | 7 files changed, 129 insertions(+), 0 deletions(-) | ||
20 | create mode 100644 events/ppc/e500mc/events | ||
21 | create mode 100644 events/ppc/e500mc/unit_masks | ||
22 | |||
23 | diff --git a/events/Makefile.am b/events/Makefile.am | ||
24 | index be87781..e496f98 100644 | ||
25 | --- a/events/Makefile.am | ||
26 | +++ b/events/Makefile.am | ||
27 | @@ -76,6 +76,7 @@ event_files = \ | ||
28 | ppc/7450/events ppc/7450/unit_masks \ | ||
29 | ppc/e500/events ppc/e500/unit_masks \ | ||
30 | ppc/e500v2/events ppc/e500v2/unit_masks \ | ||
31 | + ppc/e500mc/events ppc/e500mc/unit_masks \ | ||
32 | ppc/e300/events ppc/e300/unit_masks \ | ||
33 | tile/tile64/events tile/tile64/unit_masks \ | ||
34 | tile/tilepro/events tile/tilepro/unit_masks \ | ||
35 | diff --git a/events/ppc/e500mc/events b/events/ppc/e500mc/events | ||
36 | new file mode 100644 | ||
37 | index 0000000..8197a7d | ||
38 | --- /dev/null | ||
39 | +++ b/events/ppc/e500mc/events | ||
40 | @@ -0,0 +1,120 @@ | ||
41 | +# e500mc Events | ||
42 | +# | ||
43 | +# Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
44 | +# | ||
45 | +event:0x1 counters:0,1,2,3 um:zero minimum:100 name:CPU_CLK : Cycles | ||
46 | +event:0x2 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_INSNS : Completed Instructions (0, 1, or 2 per cycle) | ||
47 | +event:0x3 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_OPS : Completed Micro-ops (counts 2 for load/store w/update) | ||
48 | +event:0x4 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCHES : Instruction fetches | ||
49 | +event:0x5 counters:0,1,2,3 um:zero minimum:500 name:DECODED_OPS : Micro-ops decoded | ||
50 | +event:0x8 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_BRANCHES : Branch Instructions completed | ||
51 | +event:0x9 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_LOAD_OPS : Load micro-ops completed | ||
52 | +event:0xa counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_STORE_OPS : Store micro-ops completed | ||
53 | +event:0xb counters:0,1,2,3 um:zero minimum:500 name:COMPLETION_REDIRECTS : Number of completion buffer redirects | ||
54 | +event:0xc counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_FINISHED : Branches finished | ||
55 | +event:0xd counters:0,1,2,3 um:zero minimum:500 name:TAKEN_BRANCHES_FINISHED : Taken branches finished | ||
56 | +event:0xe counters:0,1,2,3 um:zero minimum:500 name:BIFFED_BRANCHES_FINISHED : Biffed branches finished | ||
57 | +event:0xf counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch instructions mispredicted due to direction, target, or IAB prediction | ||
58 | +event:0x10 counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED_DIRECTION : Branches mispredicted due to direction prediction | ||
59 | +event:0x11 counters:0,1,2,3 um:zero minimum:500 name:BTB_HITS : Branches that hit in the BTB, or missed but are not taken | ||
60 | +event:0x12 counters:0,1,2,3 um:zero minimum:500 name:DECODE_STALLED : Cycles the instruction buffer was not empty, but 0 instructions decoded | ||
61 | +event:0x13 counters:0,1,2,3 um:zero minimum:500 name:ISSUE_STALLED : Cycles the issue buffer is not empty but 0 instructions issued | ||
62 | +event:0x14 counters:0,1,2,3 um:zero minimum:500 name:BRANCH_ISSUE_STALLED : Cycles the branch buffer is not empty but 0 instructions issued | ||
63 | +event:0x15 counters:0,1,2,3 um:zero minimum:500 name:SRS0_SCHEDULE_STALLED : Cycles SRS0 is not empty but 0 instructions scheduled | ||
64 | +event:0x16 counters:0,1,2,3 um:zero minimum:500 name:SRS1_SCHEDULE_STALLED : Cycles SRS1 is not empty but 0 instructions scheduled | ||
65 | +event:0x17 counters:0,1,2,3 um:zero minimum:500 name:VRS_SCHEDULE_STALLED : Cycles VRS is not empty but 0 instructions scheduled | ||
66 | +event:0x18 counters:0,1,2,3 um:zero minimum:500 name:LRS_SCHEDULE_STALLED : Cycles LRS is not empty but 0 instructions scheduled | ||
67 | +event:0x19 counters:0,1,2,3 um:zero minimum:500 name:BRS_SCHEDULE_STALLED : Cycles BRS is not empty but 0 instructions scheduled Load/Store, Data Cache, and dLFB Events | ||
68 | +event:0x1a counters:0,1,2,3 um:zero minimum:500 name:TOTAL_TRANSLATED : Total Ldst microops translated. | ||
69 | +event:0x1b counters:0,1,2,3 um:zero minimum:500 name:LOADS_TRANSLATED : Number of cacheable L* or EVL* microops translated. (This includes microops from load-multiple, load-update, and load-context instructions.) | ||
70 | +event:0x1c counters:0,1,2,3 um:zero minimum:500 name:STORES_TRANSLATED : Number of cacheable ST* or EVST* microops translated. (This includes microops from store-multiple, store-update, and save-context instructions.) | ||
71 | +event:0x1d counters:0,1,2,3 um:zero minimum:500 name:TOUCHES_TRANSLATED : Number of cacheable DCBT and DCBTST instructions translated (L1 only) (Does not count touches that are converted to nops i.e. exceptions, noncacheable, hid0[nopti] bit is set.) | ||
72 | +event:0x1e counters:0,1,2,3 um:zero minimum:500 name:CACHEOPS_TRANSLATED : Number of dcba, dcbf, dcbst, and dcbz instructions translated (e500 traps on dcbi) | ||
73 | +event:0x1f counters:0,1,2,3 um:zero minimum:500 name:CACHEINHIBITED_ACCESSES_TRANSLATED : Number of cache inhibited accesses translated | ||
74 | +event:0x20 counters:0,1,2,3 um:zero minimum:500 name:GUARDED_LOADS_TRANSLATED : Number of guarded loads translated | ||
75 | +event:0x21 counters:0,1,2,3 um:zero minimum:500 name:WRITETHROUGH_STORES_TRANSLATED : Number of write-through stores translated | ||
76 | +event:0x22 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES_TRANSLATED : Number of misaligned load or store accesses translated. | ||
77 | +event:0x23 counters:0,1,2,3 um:zero minimum:500 name:TOTAL_ALLOCATED_DLFB : Total allocated to dLFB | ||
78 | +event:0x24 counters:0,1,2,3 um:zero minimum:500 name:LOADS_TRANSLATED_ALLOCATED_DLFB : Loads translated and allocated to dLFB (Applies to same class of instructions as loads translated.) | ||
79 | +event:0x25 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED_ALLOCATED_DLFB : Stores completed and allocated to dLFB (Applies to same class of instructions as stores translated.) | ||
80 | +event:0x26 counters:0,1,2,3 um:zero minimum:500 name:TOUCHES_TRANSLATED_ALLOCATED_DLFB : Touches translated and allocated to dLFB (Applies to same class of instructions as touches translated.) | ||
81 | +event:0x27 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED : Number of cacheable ST* or EVST* microops completed. (Applies to the same class of instructions as stores translated.) | ||
82 | +event:0x28 counters:0,1,2,3 um:zero minimum:500 name:DL1_LOCKS : Number of cache lines locked in the dL1. (Counts a lock even if an overlock condition is encountered.) | ||
83 | +event:0x29 counters:0,1,2,3 um:zero minimum:500 name:DL1_RELOADS : This is historically used to determine dcache miss rate (along with loads/stores completed). This counts dL1 reloads for any reason. | ||
84 | +event:0x2a counters:0,1,2,3 um:zero minimum:500 name:DL1_CASTOUTS : dL1 castouts. Does not count castouts due to DCBF. | ||
85 | +event:0x2b counters:0,1,2,3 um:zero minimum:500 name:DETECTED_REPLAYS : Times detected replay condition - Load miss with dLFB full. | ||
86 | +event:0x2c counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_REPLAYS : Load miss with load queue full. | ||
87 | +event:0x2d counters:0,1,2,3 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_REPLAYS : Load guarded miss when the load is not yet at the bottom of the completion buffer. | ||
88 | +event:0x2e counters:0,1,2,3 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_REPLAYS : Translate a store when the StQ is full. | ||
89 | +event:0x2f counters:0,1,2,3 um:zero minimum:500 name:ADDRESS_COLLISION_REPLAYS : Address collision. | ||
90 | +event:0x30 counters:0,1,2,3 um:zero minimum:500 name:DMMU_MISS_REPLAYS : DMMU_MISS_REPLAYS : DMMU miss. | ||
91 | +event:0x31 counters:0,1,2,3 um:zero minimum:500 name:DMMU_BUSY_REPLAYS : DMMU_BUSY_REPLAYS : DMMU busy. | ||
92 | +event:0x32 counters:0,1,2,3 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_REPLAYS : Second part of misaligned access when first part missed in cache. | ||
93 | +event:0x33 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_DLFB_FULL_CYCLES : Cycles stalled on replay condition - Load miss with dLFB full. | ||
94 | +event:0x34 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Load miss with load queue full. | ||
95 | +event:0x35 counters:0,1,2,3 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_CYCLES : Cycles stalled on replay condition - Load guarded miss when the load is not yet at the bottom of the completion buffer. | ||
96 | +event:0x36 counters:0,1,2,3 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Translate a store when the StQ is full. | ||
97 | +event:0x37 counters:0,1,2,3 um:zero minimum:500 name:ADDRESS_COLLISION_CYCLES : Cycles stalled on replay condition - Address collision. | ||
98 | +event:0x38 counters:0,1,2,3 um:zero minimum:500 name:DMMU_MISS_CYCLES : Cycles stalled on replay condition - DMMU miss. | ||
99 | +event:0x39 counters:0,1,2,3 um:zero minimum:500 name:DMMU_BUSY_CYCLES : Cycles stalled on replay condition - DMMU busy. | ||
100 | +event:0x3a counters:0,1,2,3 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_CYCLES : Cycles stalled on replay condition - Second part of misaligned access when first part missed in cache. | ||
101 | +event:0x3b counters:0,1,2,3 um:zero minimum:500 name:IL1_LOCKS : Number of cache lines locked in the iL1. (Counts a lock even if an overlock condition is encountered.) | ||
102 | +event:0x3c counters:0,1,2,3 um:zero minimum:500 name:IL1_FETCH_RELOADS : This is historically used to determine icache miss rate (along with instructions completed) Reloads due to demand fetch. | ||
103 | +event:0x3d counters:0,1,2,3 um:zero minimum:500 name:FETCHES : Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch) | ||
104 | +event:0x3e counters:0,1,2,3 um:zero minimum:500 name:IMMU_TLB4K_RELOADS : iMMU TLB4K reloads | ||
105 | +event:0x3f counters:0,1,2,3 um:zero minimum:500 name:IMMU_VSP_RELOADS : iMMU VSP reloads | ||
106 | +event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DMMU_TLB4K_RELOADS : dMMU TLB4K reloads | ||
107 | +event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DMMU_VSP_RELOADS : dMMU VSP reloads | ||
108 | +event:0x42 counters:0,1,2,3 um:zero minimum:500 name:L2MMU_MISSES : Counts iTLB/dTLB error interrupt | ||
109 | +event:0x43 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_REQUESTS : Number of master transactions. (Number of master TSs.) | ||
110 | +event:0x44 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_I_REQUESTS : Number of master I-Side transactions. (Number of master I-Side TSs.) | ||
111 | +event:0x45 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_REQUESTS : Number of master D-Side transactions. (Number of master D-Side TSs.) | ||
112 | +event:0x46 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_CASTOUT_REQUESTS : Number of master D-Side non-program-demand castout transactions. This counts replacement pushes and snoop pushes. This does not count DCBF castouts. (Number of master D-side non-program-demand castout TSs.) | ||
113 | +event:0x48 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_REQUESTS : Number of externally generated snoop requests. (Counts snoop TSs.) | ||
114 | +event:0x49 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_HITS : Number of snoop hits on all D-side resources regardless of the cache state (modified, exclusive, or shared) | ||
115 | +event:0x4a counters:0,1,2,3 um:zero minimum:500 name:SNOOP_PUSHES : Number of snoop pushes from all D-side resources. (Counts snoop ARTRY/WOPs.) | ||
116 | +event:0x52 counters:0,1,2,3 um:zero minimum:500 name:PMC0_OVERFLOW : Counts the number of times PMC0[32] transitioned from 1 to 0. | ||
117 | +event:0x53 counters:0,1,2,3 um:zero minimum:500 name:PMC1_OVERFLOW : Counts the number of times PMC1[32] transitioned from 1 to 0. | ||
118 | +event:0x54 counters:0,1,2,3 um:zero minimum:500 name:PMC2_OVERFLOW : Counts the number of times PMC2[32] transitioned from 1 to 0. | ||
119 | +event:0x55 counters:0,1,2,3 um:zero minimum:500 name:PMC3_OVERFLOW : Counts the number of times PMC3[32] transitioned from 1 to 0. | ||
120 | +event:0x56 counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS : Number of interrupts taken | ||
121 | +event:0x57 counters:0,1,2,3 um:zero minimum:500 name:EXTERNAL_INTERRUPTS : Number of external input interrupts taken | ||
122 | +event:0x58 counters:0,1,2,3 um:zero minimum:500 name:CRITICAL_INTERRUPTS : Number of critical input interrupts taken | ||
123 | +event:0x59 counters:0,1,2,3 um:zero minimum:500 name:SC_TRAP_INTERRUPTS : Number of system call and trap interrupts | ||
124 | +event:0x5b counters:0,1,2,3 um:zero minimum:500 name:L2_LINEFILL_REQ : Number L2 Linefill requests | ||
125 | +event:0x5c counters:0,1,2,3 um:zero minimum:500 name:L2_VICTIM_SELECT : Number L2 Victim selects | ||
126 | +event:0x6e counters:0,1,2,3 um:zero minimum:500 name:L2_ACCESS : Number L2 cache accesses | ||
127 | +event:0x6f counters:0,1,2,3 um:zero minimum:500 name:L2_HIT_ACCESS : Number L2 hit cache accesses | ||
128 | +event:0x70 counters:0,1,2,3 um:zero minimum:500 name:L2_DATA_ACCESS : Number L2 data cache accesses | ||
129 | +event:0x71 counters:0,1,2,3 um:zero minimum:500 name:L2_HIT_DATA_ACCESS : Number L2 hit data cache accesses | ||
130 | +event:0x72 counters:0,1,2,3 um:zero minimum:500 name:L2_INST_ACCESS : Number L2 instruction cache accesses | ||
131 | +event:0x73 counters:0,1,2,3 um:zero minimum:500 name:L2_HIT_INST_ACCESS : Number L2 hit instruction cache accesses | ||
132 | +event:0x74 counters:0,1,2,3 um:zero minimum:500 name:L2_ALLOC : Number L2 cache allocations | ||
133 | +event:0x75 counters:0,1,2,3 um:zero minimum:500 name:L2_DATA_ALLOC : Number L2 data cache allocations | ||
134 | +event:0x76 counters:0,1,2,3 um:zero minimum:500 name:L2_DIRTY_DATA_ALLOC : Number L2 dirty data cache allocations | ||
135 | +event:0x77 counters:0,1,2,3 um:zero minimum:500 name:L2_INST_ALLOC : Number L2 instruction cache allocations | ||
136 | +event:0x78 counters:0,1,2,3 um:zero minimum:500 name:L2_UPDATE : Number L2 cache updates | ||
137 | +event:0x79 counters:0,1,2,3 um:zero minimum:500 name:L2_CLEAN_UPDATE : Number L2 cache clean updates | ||
138 | +event:0x7a counters:0,1,2,3 um:zero minimum:500 name:L2_DIRTY_UPDATE : Number L2 cache dirty updates | ||
139 | +event:0x7b counters:0,1,2,3 um:zero minimum:500 name:L2_CLEAN_REDU_UPDATE : Number L2 cache clean redundant updates | ||
140 | +event:0x7c counters:0,1,2,3 um:zero minimum:500 name:L2_DIRTY_REDU_UPDATE : Number L2 cache dirty redundant updates | ||
141 | +event:0x7d counters:0,1,2,3 um:zero minimum:500 name:L2_LOCKS : Number L2 cache locks | ||
142 | +event:0x7e counters:0,1,2,3 um:zero minimum:500 name:L2_CASTOUT : Number L2 cache castouts | ||
143 | +event:0x7f counters:0,1,2,3 um:zero minimum:500 name:L2_HIT_DATA_DIRTY : Number L2 cache data dirty hits | ||
144 | +event:0x82 counters:0,1,2,3 um:zero minimum:500 name:L2_INV_CLEAN : Number L2 cache invalidation of clean lines | ||
145 | +event:0x83 counters:0,1,2,3 um:zero minimum:500 name:L2_INV_INCOHER : Number L2 cache invalidation of incoherent lines | ||
146 | +event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L2_INV_COHER : Number L2 cache invalidation of coherent lines | ||
147 | +event:0x94 counters:0,1,2,3 um:zero minimum:500 name:DVT0 : Detection of write to DEVENT with DVT0 set | ||
148 | +event:0x95 counters:0,1,2,3 um:zero minimum:500 name:DVT1 : Detection of write to DEVENT with DVT1 set | ||
149 | +event:0x96 counters:0,1,2,3 um:zero minimum:500 name:DVT2 : Detection of write to DEVENT with DVT2 set | ||
150 | +event:0x97 counters:0,1,2,3 um:zero minimum:500 name:DVT3 : Detection of write to DEVENT with DVT3 set | ||
151 | +event:0x98 counters:0,1,2,3 um:zero minimum:500 name:DVT4 : Detection of write to DEVENT with DVT4 set | ||
152 | +event:0x99 counters:0,1,2,3 um:zero minimum:500 name:DVT5 : Detection of write to DEVENT with DVT5 set | ||
153 | +event:0x9a counters:0,1,2,3 um:zero minimum:500 name:DVT6 : Detection of write to DEVENT with DVT6 set | ||
154 | +event:0x9b counters:0,1,2,3 um:zero minimum:500 name:DVT7 : Detection of write to DEVENT with DVT7 set | ||
155 | +event:0x9c counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NEXUS_STALLED : Number of completion cycles stalled due to Nexus FIFO full | ||
156 | +event:0xb0 counters:0,1,2,3 um:zero minimum:500 name:DECORATED_LOAD : Number of decorated loads. | ||
157 | +event:0xb1 counters:0,1,2,3 um:zero minimum:500 name:DECORATED_STORE : Number of decorated stores | ||
158 | +event:0xb2 counters:0,1,2,3 um:zero minimum:500 name:LOAD_RETRY : Number of load retries | ||
159 | +event:0xb3 counters:0,1,2,3 um:zero minimum:500 name:STWCX_SUCCESS : Number of successful stwcx. instructions | ||
160 | +event:0xb4 counters:0,1,2,3 um:zero minimum:500 name:STWCX_UNSUCCESS : Number of unsuccessful stwcx. instructions | ||
161 | diff --git a/events/ppc/e500mc/unit_masks b/events/ppc/e500mc/unit_masks | ||
162 | new file mode 100644 | ||
163 | index 0000000..395c653 | ||
164 | --- /dev/null | ||
165 | +++ b/events/ppc/e500mc/unit_masks | ||
166 | @@ -0,0 +1,4 @@ | ||
167 | +# e500 possible unit masks | ||
168 | +# | ||
169 | +name:zero type:mandatory default:0x0 | ||
170 | + 0x0 No unit mask | ||
171 | diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c | ||
172 | index 89d5a92..7d50a2d 100644 | ||
173 | --- a/libop/op_cpu_type.c | ||
174 | +++ b/libop/op_cpu_type.c | ||
175 | @@ -125,6 +125,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { | ||
176 | { "AMD64 generic", "x86-64/generic", CPU_AMD64_GENERIC, 4 }, | ||
177 | { "IBM Power Architected Events V1", "ppc64/architected_events_v1", CPU_PPC64_ARCH_V1, 6 }, | ||
178 | { "ppc64 POWER8", "ppc64/power8", CPU_PPC64_POWER8, 6 }, | ||
179 | + { "e500mc", "ppc/e500mc", CPU_PPC_E500MC, 4 }, | ||
180 | }; | ||
181 | |||
182 | static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); | ||
183 | diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h | ||
184 | index aeb6bb2..10f000b 100644 | ||
185 | --- a/libop/op_cpu_type.h | ||
186 | +++ b/libop/op_cpu_type.h | ||
187 | @@ -105,6 +105,7 @@ typedef enum { | ||
188 | CPU_AMD64_GENERIC, /**< AMD64 Generic */ | ||
189 | CPU_PPC64_ARCH_V1, /** < IBM Power architected events version 1 */ | ||
190 | CPU_PPC64_POWER8, /**< ppc64 POWER8 family */ | ||
191 | + CPU_PPC_E500MC, /**< e500mc */ | ||
192 | MAX_CPU_TYPE | ||
193 | } op_cpu; | ||
194 | |||
195 | diff --git a/libop/op_events.c b/libop/op_events.c | ||
196 | index bb86833..638dc5c 100644 | ||
197 | --- a/libop/op_events.c | ||
198 | +++ b/libop/op_events.c | ||
199 | @@ -1308,6 +1308,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) | ||
200 | |||
201 | case CPU_PPC_E500: | ||
202 | case CPU_PPC_E500_2: | ||
203 | + case CPU_PPC_E500MC: | ||
204 | case CPU_PPC_E300: | ||
205 | descr->name = "CPU_CLK"; | ||
206 | break; | ||
207 | diff --git a/utils/ophelp.c b/utils/ophelp.c | ||
208 | index 1b913ca..0647360 100644 | ||
209 | --- a/utils/ophelp.c | ||
210 | +++ b/utils/ophelp.c | ||
211 | @@ -753,6 +753,7 @@ int main(int argc, char const * argv[]) | ||
212 | |||
213 | case CPU_PPC_E500: | ||
214 | case CPU_PPC_E500_2: | ||
215 | + case CPU_PPC_E500MC: | ||
216 | event_doc = | ||
217 | "See PowerPC e500 Core Complex Reference Manual\n" | ||
218 | "Chapter 7: Performance Monitor\n" | ||
219 | -- | ||