diff options
Diffstat (limited to 'meta/recipes-kernel/linux/linux-omap2-git/omap3evm')
10 files changed, 4536 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch new file mode 100644 index 0000000000..550a4f58be --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch | |||
@@ -0,0 +1,1002 @@ | |||
1 | From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> | ||
2 | To: linux-omap@vger.kernel.org | ||
3 | Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> | ||
4 | Subject: [PATCH 1/3] ARM: OMAP: SmartReflex driver, reference source and header files | ||
5 | Date: Mon, 2 Jun 2008 14:30:12 +0300 | ||
6 | |||
7 | The following patch set integrates TI's SmartReflex driver. SmartReflex is a | ||
8 | module that adjusts OMAP3 VDD1 and VDD2 operating voltages around the nominal | ||
9 | values of current operating point depending on silicon characteristics and | ||
10 | operating conditions. | ||
11 | |||
12 | The driver creates two sysfs entries into /sys/power/ named "sr_vdd1_autocomp" | ||
13 | and "sr_vdd2_autocomp" which can be used to activate SmartReflex modules 1 and | ||
14 | 2. | ||
15 | |||
16 | Use the following commands to enable SmartReflex: | ||
17 | |||
18 | echo -n 1 > /sys/power/sr_vdd1_autocomp | ||
19 | echo -n 1 > /sys/power/sr_vdd2_autocomp | ||
20 | |||
21 | To disable: | ||
22 | |||
23 | echo -n 0 > /sys/power/sr_vdd1_autocomp | ||
24 | echo -n 0 > /sys/power/sr_vdd2_autocomp | ||
25 | |||
26 | This particular patch adds the TI reference source and header files for | ||
27 | SmartReflex. Only modifications include minor styling to pass checkpatch.pl | ||
28 | test. | ||
29 | |||
30 | Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> | ||
31 | --- | ||
32 | arch/arm/mach-omap2/smartreflex.c | 815 +++++++++++++++++++++++++++++++++++++ | ||
33 | arch/arm/mach-omap2/smartreflex.h | 136 ++++++ | ||
34 | 2 files changed, 951 insertions(+), 0 deletions(-) | ||
35 | create mode 100644 arch/arm/mach-omap2/smartreflex.c | ||
36 | create mode 100644 arch/arm/mach-omap2/smartreflex.h | ||
37 | |||
38 | diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c | ||
39 | new file mode 100644 | ||
40 | index 0000000..dae7460 | ||
41 | --- /dev/null | ||
42 | +++ b/arch/arm/mach-omap2/smartreflex.c | ||
43 | @@ -0,0 +1,815 @@ | ||
44 | +/* | ||
45 | + * linux/arch/arm/mach-omap3/smartreflex.c | ||
46 | + * | ||
47 | + * OMAP34XX SmartReflex Voltage Control | ||
48 | + * | ||
49 | + * Copyright (C) 2007 Texas Instruments, Inc. | ||
50 | + * Lesly A M <x0080970@ti.com> | ||
51 | + * | ||
52 | + * This program is free software; you can redistribute it and/or modify | ||
53 | + * it under the terms of the GNU General Public License version 2 as | ||
54 | + * published by the Free Software Foundation. | ||
55 | + */ | ||
56 | + | ||
57 | + | ||
58 | +#include <linux/kernel.h> | ||
59 | +#include <linux/init.h> | ||
60 | +#include <linux/interrupt.h> | ||
61 | +#include <linux/module.h> | ||
62 | +#include <linux/delay.h> | ||
63 | +#include <linux/err.h> | ||
64 | +#include <linux/clk.h> | ||
65 | +#include <linux/sysfs.h> | ||
66 | + | ||
67 | +#include <asm/arch/prcm.h> | ||
68 | +#include <asm/arch/power_companion.h> | ||
69 | +#include <linux/io.h> | ||
70 | + | ||
71 | +#include "prcm-regs.h" | ||
72 | +#include "smartreflex.h" | ||
73 | + | ||
74 | + | ||
75 | +/* #define DEBUG_SR 1 */ | ||
76 | +#ifdef DEBUG_SR | ||
77 | +# define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__ ,\ | ||
78 | + ## args) | ||
79 | +#else | ||
80 | +# define DPRINTK(fmt, args...) | ||
81 | +#endif | ||
82 | + | ||
83 | +struct omap_sr{ | ||
84 | + int srid; | ||
85 | + int is_sr_reset; | ||
86 | + int is_autocomp_active; | ||
87 | + struct clk *fck; | ||
88 | + u32 req_opp_no; | ||
89 | + u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue; | ||
90 | + u32 senp_mod, senn_mod; | ||
91 | + u32 srbase_addr; | ||
92 | + u32 vpbase_addr; | ||
93 | +}; | ||
94 | + | ||
95 | +static struct omap_sr sr1 = { | ||
96 | + .srid = SR1, | ||
97 | + .is_sr_reset = 1, | ||
98 | + .is_autocomp_active = 0, | ||
99 | + .srbase_addr = OMAP34XX_SR1_BASE, | ||
100 | +}; | ||
101 | + | ||
102 | +static struct omap_sr sr2 = { | ||
103 | + .srid = SR2, | ||
104 | + .is_sr_reset = 1, | ||
105 | + .is_autocomp_active = 0, | ||
106 | + .srbase_addr = OMAP34XX_SR2_BASE, | ||
107 | +}; | ||
108 | + | ||
109 | +static inline void sr_write_reg(struct omap_sr *sr, int offset, u32 value) | ||
110 | +{ | ||
111 | + omap_writel(value, sr->srbase_addr + offset); | ||
112 | +} | ||
113 | + | ||
114 | +static inline void sr_modify_reg(struct omap_sr *sr, int offset, u32 mask, | ||
115 | + u32 value) | ||
116 | +{ | ||
117 | + u32 reg_val; | ||
118 | + | ||
119 | + reg_val = omap_readl(sr->srbase_addr + offset); | ||
120 | + reg_val &= ~mask; | ||
121 | + reg_val |= value; | ||
122 | + | ||
123 | + omap_writel(reg_val, sr->srbase_addr + offset); | ||
124 | +} | ||
125 | + | ||
126 | +static inline u32 sr_read_reg(struct omap_sr *sr, int offset) | ||
127 | +{ | ||
128 | + return omap_readl(sr->srbase_addr + offset); | ||
129 | +} | ||
130 | + | ||
131 | + | ||
132 | +#ifndef USE_EFUSE_VALUES | ||
133 | +static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen) | ||
134 | +{ | ||
135 | + u32 gn, rn, mul; | ||
136 | + | ||
137 | + for (gn = 0; gn < GAIN_MAXLIMIT; gn++) { | ||
138 | + mul = 1 << (gn + 8); | ||
139 | + rn = mul / sensor; | ||
140 | + if (rn < R_MAXLIMIT) { | ||
141 | + *sengain = gn; | ||
142 | + *rnsen = rn; | ||
143 | + } | ||
144 | + } | ||
145 | +} | ||
146 | +#endif | ||
147 | + | ||
148 | +static int sr_clk_enable(struct omap_sr *sr) | ||
149 | +{ | ||
150 | + if (clk_enable(sr->fck) != 0) { | ||
151 | + printk(KERN_ERR "Could not enable sr%d_fck\n", sr->srid); | ||
152 | + goto clk_enable_err; | ||
153 | + } | ||
154 | + | ||
155 | + /* set fclk- active , iclk- idle */ | ||
156 | + sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK, | ||
157 | + SR_CLKACTIVITY_IOFF_FON); | ||
158 | + | ||
159 | + return 0; | ||
160 | + | ||
161 | +clk_enable_err: | ||
162 | + return -1; | ||
163 | +} | ||
164 | + | ||
165 | +static int sr_clk_disable(struct omap_sr *sr) | ||
166 | +{ | ||
167 | + /* set fclk, iclk- idle */ | ||
168 | + sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK, | ||
169 | + SR_CLKACTIVITY_IOFF_FOFF); | ||
170 | + | ||
171 | + clk_disable(sr->fck); | ||
172 | + sr->is_sr_reset = 1; | ||
173 | + | ||
174 | + return 0; | ||
175 | +} | ||
176 | + | ||
177 | +static void sr_set_nvalues(struct omap_sr *sr) | ||
178 | +{ | ||
179 | +#ifdef USE_EFUSE_VALUES | ||
180 | + u32 n1, n2; | ||
181 | +#else | ||
182 | + u32 senpval, sennval; | ||
183 | + u32 senpgain, senngain; | ||
184 | + u32 rnsenp, rnsenn; | ||
185 | +#endif | ||
186 | + | ||
187 | + if (sr->srid == SR1) { | ||
188 | +#ifdef USE_EFUSE_VALUES | ||
189 | + /* Read values for VDD1 from EFUSE */ | ||
190 | +#else | ||
191 | + /* since E-Fuse Values are not available, calculating the | ||
192 | + * reciprocal of the SenN and SenP values for SR1 | ||
193 | + */ | ||
194 | + sr->senp_mod = 0x03; /* SenN-M5 enabled */ | ||
195 | + sr->senn_mod = 0x03; | ||
196 | + | ||
197 | + /* for OPP5 */ | ||
198 | + senpval = 0x848 + 0x330; | ||
199 | + sennval = 0xacd + 0x330; | ||
200 | + | ||
201 | + cal_reciprocal(senpval, &senpgain, &rnsenp); | ||
202 | + cal_reciprocal(sennval, &senngain, &rnsenn); | ||
203 | + | ||
204 | + sr->opp5_nvalue = | ||
205 | + ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | | ||
206 | + (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | | ||
207 | + (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | | ||
208 | + (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); | ||
209 | + | ||
210 | + /* for OPP4 */ | ||
211 | + senpval = 0x727 + 0x2a0; | ||
212 | + sennval = 0x964 + 0x2a0; | ||
213 | + | ||
214 | + cal_reciprocal(senpval, &senpgain, &rnsenp); | ||
215 | + cal_reciprocal(sennval, &senngain, &rnsenn); | ||
216 | + | ||
217 | + sr->opp4_nvalue = | ||
218 | + ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | | ||
219 | + (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | | ||
220 | + (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | | ||
221 | + (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); | ||
222 | + | ||
223 | + /* for OPP3 */ | ||
224 | + senpval = 0x655 + 0x200; | ||
225 | + sennval = 0x85b + 0x200; | ||
226 | + | ||
227 | + cal_reciprocal(senpval, &senpgain, &rnsenp); | ||
228 | + cal_reciprocal(sennval, &senngain, &rnsenn); | ||
229 | + | ||
230 | + sr->opp3_nvalue = | ||
231 | + ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | | ||
232 | + (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | | ||
233 | + (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | | ||
234 | + (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); | ||
235 | + | ||
236 | + /* for OPP2 */ | ||
237 | + senpval = 0x3be + 0x1a0; | ||
238 | + sennval = 0x506 + 0x1a0; | ||
239 | + | ||
240 | + cal_reciprocal(senpval, &senpgain, &rnsenp); | ||
241 | + cal_reciprocal(sennval, &senngain, &rnsenn); | ||
242 | + | ||
243 | + sr->opp2_nvalue = | ||
244 | + ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | | ||
245 | + (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | | ||
246 | + (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | | ||
247 | + (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); | ||
248 | + | ||
249 | + /* for OPP1 */ | ||
250 | + senpval = 0x28c + 0x100; | ||
251 | + sennval = 0x373 + 0x100; | ||
252 | + | ||
253 | + cal_reciprocal(senpval, &senpgain, &rnsenp); | ||
254 | + cal_reciprocal(sennval, &senngain, &rnsenn); | ||
255 | + | ||
256 | + sr->opp1_nvalue = | ||
257 | + ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | | ||
258 | + (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | | ||
259 | + (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | | ||
260 | + (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); | ||
261 | + | ||
262 | + sr_clk_enable(sr); | ||
263 | + sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue); | ||
264 | + sr_clk_disable(sr); | ||
265 | + | ||
266 | +#endif | ||
267 | + } else if (sr->srid == SR2) { | ||
268 | +#ifdef USE_EFUSE_VALUES | ||
269 | + /* Read values for VDD2 from EFUSE */ | ||
270 | +#else | ||
271 | + /* since E-Fuse Values are not available, calculating the | ||
272 | + * reciprocal of the SenN and SenP values for SR2 | ||
273 | + */ | ||
274 | + sr->senp_mod = 0x03; | ||
275 | + sr->senn_mod = 0x03; | ||
276 | + | ||
277 | + /* for OPP3 */ | ||
278 | + senpval = 0x579 + 0x200; | ||
279 | + sennval = 0x76f + 0x200; | ||
280 | + | ||
281 | + cal_reciprocal(senpval, &senpgain, &rnsenp); | ||
282 | + cal_reciprocal(sennval, &senngain, &rnsenn); | ||
283 | + | ||
284 | + sr->opp3_nvalue = | ||
285 | + ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | | ||
286 | + (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | | ||
287 | + (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | | ||
288 | + (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); | ||
289 | + | ||
290 | + /* for OPP2 */ | ||
291 | + senpval = 0x390 + 0x1c0; | ||
292 | + sennval = 0x4f5 + 0x1c0; | ||
293 | + | ||
294 | + cal_reciprocal(senpval, &senpgain, &rnsenp); | ||
295 | + cal_reciprocal(sennval, &senngain, &rnsenn); | ||
296 | + | ||
297 | + sr->opp2_nvalue = | ||
298 | + ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | | ||
299 | + (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | | ||
300 | + (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | | ||
301 | + (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); | ||
302 | + | ||
303 | + /* for OPP1 */ | ||
304 | + senpval = 0x25d; | ||
305 | + sennval = 0x359; | ||
306 | + | ||
307 | + cal_reciprocal(senpval, &senpgain, &rnsenp); | ||
308 | + cal_reciprocal(sennval, &senngain, &rnsenn); | ||
309 | + | ||
310 | + sr->opp1_nvalue = | ||
311 | + ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | | ||
312 | + (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | | ||
313 | + (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | | ||
314 | + (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); | ||
315 | + | ||
316 | +#endif | ||
317 | + } | ||
318 | + | ||
319 | +} | ||
320 | + | ||
321 | +static void sr_configure_vp(int srid) | ||
322 | +{ | ||
323 | + u32 vpconfig; | ||
324 | + | ||
325 | + if (srid == SR1) { | ||
326 | + vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN | ||
327 | + | PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN; | ||
328 | + | ||
329 | + PRM_VP1_CONFIG = vpconfig; | ||
330 | + PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN | | ||
331 | + PRM_VP1_VSTEPMIN_VSTEPMIN; | ||
332 | + | ||
333 | + PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX | | ||
334 | + PRM_VP1_VSTEPMAX_VSTEPMAX; | ||
335 | + | ||
336 | + PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX | | ||
337 | + PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT; | ||
338 | + | ||
339 | + PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD; | ||
340 | + PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD; | ||
341 | + | ||
342 | + } else if (srid == SR2) { | ||
343 | + vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN | ||
344 | + | PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN; | ||
345 | + | ||
346 | + PRM_VP2_CONFIG = vpconfig; | ||
347 | + PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN | | ||
348 | + PRM_VP2_VSTEPMIN_VSTEPMIN; | ||
349 | + | ||
350 | + PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX | | ||
351 | + PRM_VP2_VSTEPMAX_VSTEPMAX; | ||
352 | + | ||
353 | + PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX | | ||
354 | + PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT; | ||
355 | + | ||
356 | + PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD; | ||
357 | + PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD; | ||
358 | + | ||
359 | + } | ||
360 | +} | ||
361 | + | ||
362 | +static void sr_configure_vc(void) | ||
363 | +{ | ||
364 | + PRM_VC_SMPS_SA = | ||
365 | + (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) | | ||
366 | + (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT); | ||
367 | + | ||
368 | + PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) | | ||
369 | + (R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT); | ||
370 | + | ||
371 | + PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) | | ||
372 | + (PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) | | ||
373 | + (PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) | | ||
374 | + (PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT); | ||
375 | + | ||
376 | + PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) | | ||
377 | + (PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) | | ||
378 | + (PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) | | ||
379 | + (PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT); | ||
380 | + | ||
381 | + PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1; | ||
382 | + | ||
383 | + PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN | ||
384 | + | PRM_VC_I2C_CFG_SREN; | ||
385 | + | ||
386 | + /* Setup voltctrl and other setup times */ | ||
387 | +#ifdef CONFIG_SYSOFFMODE | ||
388 | + PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET; | ||
389 | + PRM_CLKSETUP = PRM_CLKSETUP_DURATION; | ||
390 | + PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) | | ||
391 | + (PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET); | ||
392 | + PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION; | ||
393 | + PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION; | ||
394 | +#else | ||
395 | + PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET; | ||
396 | +#endif | ||
397 | + | ||
398 | +} | ||
399 | + | ||
400 | + | ||
401 | +static void sr_configure(struct omap_sr *sr) | ||
402 | +{ | ||
403 | + u32 sys_clk, sr_clk_length = 0; | ||
404 | + u32 sr_config; | ||
405 | + u32 senp_en , senn_en; | ||
406 | + | ||
407 | + senp_en = sr->senp_mod; | ||
408 | + senn_en = sr->senn_mod; | ||
409 | + | ||
410 | + sys_clk = prcm_get_system_clock_speed(); | ||
411 | + | ||
412 | + switch (sys_clk) { | ||
413 | + case 12000: | ||
414 | + sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK; | ||
415 | + break; | ||
416 | + case 13000: | ||
417 | + sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK; | ||
418 | + break; | ||
419 | + case 19200: | ||
420 | + sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK; | ||
421 | + break; | ||
422 | + case 26000: | ||
423 | + sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK; | ||
424 | + break; | ||
425 | + case 38400: | ||
426 | + sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK; | ||
427 | + break; | ||
428 | + default : | ||
429 | + printk(KERN_ERR "Invalid sysclk value\n"); | ||
430 | + break; | ||
431 | + } | ||
432 | + | ||
433 | + DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk); | ||
434 | + if (sr->srid == SR1) { | ||
435 | + sr_config = SR1_SRCONFIG_ACCUMDATA | | ||
436 | + (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | | ||
437 | + SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN | | ||
438 | + SRCONFIG_MINMAXAVG_EN | | ||
439 | + (senn_en << SRCONFIG_SENNENABLE_SHIFT) | | ||
440 | + (senp_en << SRCONFIG_SENPENABLE_SHIFT) | | ||
441 | + SRCONFIG_DELAYCTRL; | ||
442 | + | ||
443 | + sr_write_reg(sr, SRCONFIG, sr_config); | ||
444 | + | ||
445 | + sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT | | ||
446 | + SR1_AVGWEIGHT_SENNAVGWEIGHT); | ||
447 | + | ||
448 | + sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK | | ||
449 | + SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), | ||
450 | + (SR1_ERRWEIGHT | SR1_ERRMAXLIMIT | SR1_ERRMINLIMIT)); | ||
451 | + | ||
452 | + } else if (sr->srid == SR2) { | ||
453 | + sr_config = SR2_SRCONFIG_ACCUMDATA | | ||
454 | + (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | | ||
455 | + SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN | | ||
456 | + SRCONFIG_MINMAXAVG_EN | | ||
457 | + (senn_en << SRCONFIG_SENNENABLE_SHIFT) | | ||
458 | + (senp_en << SRCONFIG_SENPENABLE_SHIFT) | | ||
459 | + SRCONFIG_DELAYCTRL; | ||
460 | + | ||
461 | + sr_write_reg(sr, SRCONFIG, sr_config); | ||
462 | + | ||
463 | + sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT | | ||
464 | + SR2_AVGWEIGHT_SENNAVGWEIGHT); | ||
465 | + | ||
466 | + sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK | | ||
467 | + SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), | ||
468 | + (SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT)); | ||
469 | + | ||
470 | + } | ||
471 | + sr->is_sr_reset = 0; | ||
472 | +} | ||
473 | + | ||
474 | +static void sr_enable(struct omap_sr *sr, u32 target_opp_no) | ||
475 | +{ | ||
476 | + u32 nvalue_reciprocal, current_nvalue; | ||
477 | + | ||
478 | + sr->req_opp_no = target_opp_no; | ||
479 | + | ||
480 | + if (sr->srid == SR1) { | ||
481 | + switch (target_opp_no) { | ||
482 | + case 5: | ||
483 | + nvalue_reciprocal = sr->opp5_nvalue; | ||
484 | + break; | ||
485 | + case 4: | ||
486 | + nvalue_reciprocal = sr->opp4_nvalue; | ||
487 | + break; | ||
488 | + case 3: | ||
489 | + nvalue_reciprocal = sr->opp3_nvalue; | ||
490 | + break; | ||
491 | + case 2: | ||
492 | + nvalue_reciprocal = sr->opp2_nvalue; | ||
493 | + break; | ||
494 | + case 1: | ||
495 | + nvalue_reciprocal = sr->opp1_nvalue; | ||
496 | + break; | ||
497 | + default: | ||
498 | + nvalue_reciprocal = sr->opp3_nvalue; | ||
499 | + break; | ||
500 | + } | ||
501 | + } else { | ||
502 | + switch (target_opp_no) { | ||
503 | + case 3: | ||
504 | + nvalue_reciprocal = sr->opp3_nvalue; | ||
505 | + break; | ||
506 | + case 2: | ||
507 | + nvalue_reciprocal = sr->opp2_nvalue; | ||
508 | + break; | ||
509 | + case 1: | ||
510 | + nvalue_reciprocal = sr->opp1_nvalue; | ||
511 | + break; | ||
512 | + default: | ||
513 | + nvalue_reciprocal = sr->opp3_nvalue; | ||
514 | + break; | ||
515 | + } | ||
516 | + } | ||
517 | + | ||
518 | + current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL); | ||
519 | + | ||
520 | + if (current_nvalue == nvalue_reciprocal) { | ||
521 | + DPRINTK("System is already at the desired voltage level\n"); | ||
522 | + return; | ||
523 | + } | ||
524 | + | ||
525 | + sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal); | ||
526 | + | ||
527 | + /* Enable the interrupt */ | ||
528 | + sr_modify_reg(sr, ERRCONFIG, | ||
529 | + (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST), | ||
530 | + (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST)); | ||
531 | + | ||
532 | + if (sr->srid == SR1) { | ||
533 | + /* Enable VP1 */ | ||
534 | + PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE; | ||
535 | + } else if (sr->srid == SR2) { | ||
536 | + /* Enable VP2 */ | ||
537 | + PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE; | ||
538 | + } | ||
539 | + | ||
540 | + /* SRCONFIG - enable SR */ | ||
541 | + sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE); | ||
542 | + | ||
543 | +} | ||
544 | + | ||
545 | +static void sr_disable(struct omap_sr *sr) | ||
546 | +{ | ||
547 | + sr->is_sr_reset = 1; | ||
548 | + | ||
549 | + /* SRCONFIG - disable SR */ | ||
550 | + sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE); | ||
551 | + | ||
552 | + if (sr->srid == SR1) { | ||
553 | + /* Enable VP1 */ | ||
554 | + PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE; | ||
555 | + } else if (sr->srid == SR2) { | ||
556 | + /* Enable VP2 */ | ||
557 | + PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE; | ||
558 | + } | ||
559 | +} | ||
560 | + | ||
561 | + | ||
562 | +void sr_start_vddautocomap(int srid, u32 target_opp_no) | ||
563 | +{ | ||
564 | + struct omap_sr *sr = NULL; | ||
565 | + | ||
566 | + if (srid == SR1) | ||
567 | + sr = &sr1; | ||
568 | + else if (srid == SR2) | ||
569 | + sr = &sr2; | ||
570 | + | ||
571 | + if (sr->is_sr_reset == 1) { | ||
572 | + sr_clk_enable(sr); | ||
573 | + sr_configure(sr); | ||
574 | + } | ||
575 | + | ||
576 | + if (sr->is_autocomp_active == 1) | ||
577 | + DPRINTK(KERN_WARNING "SR%d: VDD autocomp is already active\n", | ||
578 | + srid); | ||
579 | + | ||
580 | + sr->is_autocomp_active = 1; | ||
581 | + sr_enable(sr, target_opp_no); | ||
582 | +} | ||
583 | +EXPORT_SYMBOL(sr_start_vddautocomap); | ||
584 | + | ||
585 | +int sr_stop_vddautocomap(int srid) | ||
586 | +{ | ||
587 | + struct omap_sr *sr = NULL; | ||
588 | + | ||
589 | + if (srid == SR1) | ||
590 | + sr = &sr1; | ||
591 | + else if (srid == SR2) | ||
592 | + sr = &sr2; | ||
593 | + | ||
594 | + if (sr->is_autocomp_active == 1) { | ||
595 | + sr_disable(sr); | ||
596 | + sr_clk_disable(sr); | ||
597 | + sr->is_autocomp_active = 0; | ||
598 | + return SR_TRUE; | ||
599 | + } else { | ||
600 | + DPRINTK(KERN_WARNING "SR%d: VDD autocomp is not active\n", | ||
601 | + srid); | ||
602 | + return SR_FALSE; | ||
603 | + } | ||
604 | + | ||
605 | +} | ||
606 | +EXPORT_SYMBOL(sr_stop_vddautocomap); | ||
607 | + | ||
608 | +void enable_smartreflex(int srid) | ||
609 | +{ | ||
610 | + u32 target_opp_no = 0; | ||
611 | + struct omap_sr *sr = NULL; | ||
612 | + | ||
613 | + if (srid == SR1) | ||
614 | + sr = &sr1; | ||
615 | + else if (srid == SR2) | ||
616 | + sr = &sr2; | ||
617 | + | ||
618 | + if (sr->is_autocomp_active == 1) { | ||
619 | + if (sr->is_sr_reset == 1) { | ||
620 | + if (srid == SR1) { | ||
621 | + /* Enable SR clks */ | ||
622 | + CM_FCLKEN_WKUP |= SR1_CLK_ENABLE; | ||
623 | + target_opp_no = get_opp_no(current_vdd1_opp); | ||
624 | + | ||
625 | + } else if (srid == SR2) { | ||
626 | + /* Enable SR clks */ | ||
627 | + CM_FCLKEN_WKUP |= SR2_CLK_ENABLE; | ||
628 | + target_opp_no = get_opp_no(current_vdd2_opp); | ||
629 | + } | ||
630 | + | ||
631 | + sr_configure(sr); | ||
632 | + | ||
633 | + sr_enable(sr, target_opp_no); | ||
634 | + } | ||
635 | + } | ||
636 | +} | ||
637 | + | ||
638 | +void disable_smartreflex(int srid) | ||
639 | +{ | ||
640 | + struct omap_sr *sr = NULL; | ||
641 | + | ||
642 | + if (srid == SR1) | ||
643 | + sr = &sr1; | ||
644 | + else if (srid == SR2) | ||
645 | + sr = &sr2; | ||
646 | + | ||
647 | + if (sr->is_autocomp_active == 1) { | ||
648 | + if (srid == SR1) { | ||
649 | + /* Enable SR clk */ | ||
650 | + CM_FCLKEN_WKUP |= SR1_CLK_ENABLE; | ||
651 | + | ||
652 | + } else if (srid == SR2) { | ||
653 | + /* Enable SR clk */ | ||
654 | + CM_FCLKEN_WKUP |= SR2_CLK_ENABLE; | ||
655 | + } | ||
656 | + | ||
657 | + if (sr->is_sr_reset == 0) { | ||
658 | + | ||
659 | + sr->is_sr_reset = 1; | ||
660 | + /* SRCONFIG - disable SR */ | ||
661 | + sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, | ||
662 | + ~SRCONFIG_SRENABLE); | ||
663 | + | ||
664 | + if (sr->srid == SR1) { | ||
665 | + /* Disable SR clk */ | ||
666 | + CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE; | ||
667 | + /* Enable VP1 */ | ||
668 | + PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE; | ||
669 | + | ||
670 | + } else if (sr->srid == SR2) { | ||
671 | + /* Disable SR clk */ | ||
672 | + CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE; | ||
673 | + /* Enable VP2 */ | ||
674 | + PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE; | ||
675 | + } | ||
676 | + } | ||
677 | + } | ||
678 | +} | ||
679 | + | ||
680 | + | ||
681 | +/* Voltage Scaling using SR VCBYPASS */ | ||
682 | +int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel) | ||
683 | +{ | ||
684 | + int ret; | ||
685 | + int sr_status = 0; | ||
686 | + u32 vdd, target_opp_no; | ||
687 | + u32 vc_bypass_value; | ||
688 | + u32 reg_addr = 0; | ||
689 | + u32 loop_cnt = 0, retries_cnt = 0; | ||
690 | + | ||
691 | + vdd = get_vdd(target_opp); | ||
692 | + target_opp_no = get_opp_no(target_opp); | ||
693 | + | ||
694 | + if (vdd == PRCM_VDD1) { | ||
695 | + sr_status = sr_stop_vddautocomap(SR1); | ||
696 | + | ||
697 | + PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) | | ||
698 | + (vsel << PRM_VC_CMD_ON_SHIFT); | ||
699 | + reg_addr = R_VDD1_SR_CONTROL; | ||
700 | + | ||
701 | + } else if (vdd == PRCM_VDD2) { | ||
702 | + sr_status = sr_stop_vddautocomap(SR2); | ||
703 | + | ||
704 | + PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) | | ||
705 | + (vsel << PRM_VC_CMD_ON_SHIFT); | ||
706 | + reg_addr = R_VDD2_SR_CONTROL; | ||
707 | + } | ||
708 | + | ||
709 | + vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) | | ||
710 | + (reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) | | ||
711 | + (R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT); | ||
712 | + | ||
713 | + PRM_VC_BYPASS_VAL = vc_bypass_value; | ||
714 | + | ||
715 | + PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID; | ||
716 | + | ||
717 | + DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL); | ||
718 | + DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU); | ||
719 | + | ||
720 | + while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) { | ||
721 | + ret = loop_wait(&loop_cnt, &retries_cnt, 10); | ||
722 | + if (ret != PRCM_PASS) { | ||
723 | + printk(KERN_INFO "Loop count exceeded in check SR I2C" | ||
724 | + "write\n"); | ||
725 | + return ret; | ||
726 | + } | ||
727 | + } | ||
728 | + | ||
729 | + omap_udelay(T2_SMPS_UPDATE_DELAY); | ||
730 | + | ||
731 | + if (sr_status) { | ||
732 | + if (vdd == PRCM_VDD1) | ||
733 | + sr_start_vddautocomap(SR1, target_opp_no); | ||
734 | + else if (vdd == PRCM_VDD2) | ||
735 | + sr_start_vddautocomap(SR2, target_opp_no); | ||
736 | + } | ||
737 | + | ||
738 | + return SR_PASS; | ||
739 | +} | ||
740 | + | ||
741 | +/* Sysfs interface to select SR VDD1 auto compensation */ | ||
742 | +static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf) | ||
743 | +{ | ||
744 | + return sprintf(buf, "%d\n", sr1.is_autocomp_active); | ||
745 | +} | ||
746 | + | ||
747 | +static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys, | ||
748 | + const char *buf, size_t n) | ||
749 | +{ | ||
750 | + u32 current_vdd1opp_no; | ||
751 | + unsigned short value; | ||
752 | + | ||
753 | + if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) { | ||
754 | + printk(KERN_ERR "sr_vdd1_autocomp: Invalid value\n"); | ||
755 | + return -EINVAL; | ||
756 | + } | ||
757 | + | ||
758 | + current_vdd1opp_no = get_opp_no(current_vdd1_opp); | ||
759 | + | ||
760 | + if (value == 0) | ||
761 | + sr_stop_vddautocomap(SR1); | ||
762 | + else | ||
763 | + sr_start_vddautocomap(SR1, current_vdd1opp_no); | ||
764 | + | ||
765 | + return n; | ||
766 | +} | ||
767 | + | ||
768 | +static struct subsys_attribute sr_vdd1_autocomp = { | ||
769 | + .attr = { | ||
770 | + .name = __stringify(sr_vdd1_autocomp), | ||
771 | + .mode = 0644, | ||
772 | + }, | ||
773 | + .show = omap_sr_vdd1_autocomp_show, | ||
774 | + .store = omap_sr_vdd1_autocomp_store, | ||
775 | +}; | ||
776 | + | ||
777 | +/* Sysfs interface to select SR VDD2 auto compensation */ | ||
778 | +static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf) | ||
779 | +{ | ||
780 | + return sprintf(buf, "%d\n", sr2.is_autocomp_active); | ||
781 | +} | ||
782 | + | ||
783 | +static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys, | ||
784 | + const char *buf, size_t n) | ||
785 | +{ | ||
786 | + u32 current_vdd2opp_no; | ||
787 | + unsigned short value; | ||
788 | + | ||
789 | + if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) { | ||
790 | + printk(KERN_ERR "sr_vdd2_autocomp: Invalid value\n"); | ||
791 | + return -EINVAL; | ||
792 | + } | ||
793 | + | ||
794 | + current_vdd2opp_no = get_opp_no(current_vdd2_opp); | ||
795 | + | ||
796 | + if (value == 0) | ||
797 | + sr_stop_vddautocomap(SR2); | ||
798 | + else | ||
799 | + sr_start_vddautocomap(SR2, current_vdd2opp_no); | ||
800 | + | ||
801 | + return n; | ||
802 | +} | ||
803 | + | ||
804 | +static struct subsys_attribute sr_vdd2_autocomp = { | ||
805 | + .attr = { | ||
806 | + .name = __stringify(sr_vdd2_autocomp), | ||
807 | + .mode = 0644, | ||
808 | + }, | ||
809 | + .show = omap_sr_vdd2_autocomp_show, | ||
810 | + .store = omap_sr_vdd2_autocomp_store, | ||
811 | +}; | ||
812 | + | ||
813 | + | ||
814 | + | ||
815 | +static int __init omap3_sr_init(void) | ||
816 | +{ | ||
817 | + int ret = 0; | ||
818 | + u8 RdReg; | ||
819 | + | ||
820 | +#ifdef CONFIG_ARCH_OMAP34XX | ||
821 | + sr1.fck = clk_get(NULL, "sr1_fck"); | ||
822 | + if (IS_ERR(sr1.fck)) | ||
823 | + printk(KERN_ERR "Could not get sr1_fck\n"); | ||
824 | + | ||
825 | + sr2.fck = clk_get(NULL, "sr2_fck"); | ||
826 | + if (IS_ERR(sr2.fck)) | ||
827 | + printk(KERN_ERR "Could not get sr2_fck\n"); | ||
828 | +#endif /* #ifdef CONFIG_ARCH_OMAP34XX */ | ||
829 | + | ||
830 | + /* Call the VPConfig, VCConfig, set N Values. */ | ||
831 | + sr_set_nvalues(&sr1); | ||
832 | + sr_configure_vp(SR1); | ||
833 | + | ||
834 | + sr_set_nvalues(&sr2); | ||
835 | + sr_configure_vp(SR2); | ||
836 | + | ||
837 | + sr_configure_vc(); | ||
838 | + | ||
839 | + /* Enable SR on T2 */ | ||
840 | + ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG); | ||
841 | + RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX; | ||
842 | + ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG); | ||
843 | + | ||
844 | + | ||
845 | + printk(KERN_INFO "SmartReflex driver initialized\n"); | ||
846 | + | ||
847 | + ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp); | ||
848 | + if (ret) | ||
849 | + printk(KERN_ERR "subsys_create_file failed: %d\n", ret); | ||
850 | + | ||
851 | + ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp); | ||
852 | + if (ret) | ||
853 | + printk(KERN_ERR "subsys_create_file failed: %d\n", ret); | ||
854 | + | ||
855 | + return 0; | ||
856 | +} | ||
857 | + | ||
858 | +arch_initcall(omap3_sr_init); | ||
859 | diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h | ||
860 | new file mode 100644 | ||
861 | index 0000000..62907ef | ||
862 | --- /dev/null | ||
863 | +++ b/arch/arm/mach-omap2/smartreflex.h | ||
864 | @@ -0,0 +1,136 @@ | ||
865 | +/* | ||
866 | + * linux/arch/arm/mach-omap3/smartreflex.h | ||
867 | + * | ||
868 | + * Copyright (C) 2007 Texas Instruments, Inc. | ||
869 | + * Lesly A M <x0080970@ti.com> | ||
870 | + * | ||
871 | + * This program is free software; you can redistribute it and/or modify | ||
872 | + * it under the terms of the GNU General Public License version 2 as | ||
873 | + * published by the Free Software Foundation. | ||
874 | + */ | ||
875 | + | ||
876 | + | ||
877 | +/* SR Modules */ | ||
878 | +#define SR1 1 | ||
879 | +#define SR2 2 | ||
880 | + | ||
881 | +#define SR_FAIL 1 | ||
882 | +#define SR_PASS 0 | ||
883 | + | ||
884 | +#define SR_TRUE 1 | ||
885 | +#define SR_FALSE 0 | ||
886 | + | ||
887 | +#define GAIN_MAXLIMIT 16 | ||
888 | +#define R_MAXLIMIT 256 | ||
889 | + | ||
890 | +#define SR1_CLK_ENABLE (0x1 << 6) | ||
891 | +#define SR2_CLK_ENABLE (0x1 << 7) | ||
892 | + | ||
893 | +/* PRM_VP1_CONFIG */ | ||
894 | +#define PRM_VP1_CONFIG_ERROROFFSET (0x00 << 24) | ||
895 | +#define PRM_VP1_CONFIG_ERRORGAIN (0x20 << 16) | ||
896 | + | ||
897 | +#define PRM_VP1_CONFIG_INITVOLTAGE (0x30 << 8) /* 1.2 volt */ | ||
898 | +#define PRM_VP1_CONFIG_TIMEOUTEN (0x1 << 3) | ||
899 | +#define PRM_VP1_CONFIG_INITVDD (0x1 << 2) | ||
900 | +#define PRM_VP1_CONFIG_FORCEUPDATE (0x1 << 1) | ||
901 | +#define PRM_VP1_CONFIG_VPENABLE (0x1 << 0) | ||
902 | + | ||
903 | +/* PRM_VP1_VSTEPMIN */ | ||
904 | +#define PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN (0x01F4 << 8) | ||
905 | +#define PRM_VP1_VSTEPMIN_VSTEPMIN (0x01 << 0) | ||
906 | + | ||
907 | +/* PRM_VP1_VSTEPMAX */ | ||
908 | +#define PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX (0x01F4 << 8) | ||
909 | +#define PRM_VP1_VSTEPMAX_VSTEPMAX (0x04 << 0) | ||
910 | + | ||
911 | +/* PRM_VP1_VLIMITTO */ | ||
912 | +#define PRM_VP1_VLIMITTO_VDDMAX (0x3C << 24) | ||
913 | +#define PRM_VP1_VLIMITTO_VDDMIN (0x0 << 16) | ||
914 | +#define PRM_VP1_VLIMITTO_TIMEOUT (0xFFFF << 0) | ||
915 | + | ||
916 | +/* PRM_VP2_CONFIG */ | ||
917 | +#define PRM_VP2_CONFIG_ERROROFFSET (0x00 << 24) | ||
918 | +#define PRM_VP2_CONFIG_ERRORGAIN (0x20 << 16) | ||
919 | + | ||
920 | +#define PRM_VP2_CONFIG_INITVOLTAGE (0x30 << 8) /* 1.2 volt */ | ||
921 | +#define PRM_VP2_CONFIG_TIMEOUTEN (0x1 << 3) | ||
922 | +#define PRM_VP2_CONFIG_INITVDD (0x1 << 2) | ||
923 | +#define PRM_VP2_CONFIG_FORCEUPDATE (0x1 << 1) | ||
924 | +#define PRM_VP2_CONFIG_VPENABLE (0x1 << 0) | ||
925 | + | ||
926 | +/* PRM_VP2_VSTEPMIN */ | ||
927 | +#define PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN (0x01F4 << 8) | ||
928 | +#define PRM_VP2_VSTEPMIN_VSTEPMIN (0x01 << 0) | ||
929 | + | ||
930 | +/* PRM_VP2_VSTEPMAX */ | ||
931 | +#define PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX (0x01F4 << 8) | ||
932 | +#define PRM_VP2_VSTEPMAX_VSTEPMAX (0x04 << 0) | ||
933 | + | ||
934 | +/* PRM_VP2_VLIMITTO */ | ||
935 | +#define PRM_VP2_VLIMITTO_VDDMAX (0x2C << 24) | ||
936 | +#define PRM_VP2_VLIMITTO_VDDMIN (0x0 << 16) | ||
937 | +#define PRM_VP2_VLIMITTO_TIMEOUT (0xFFFF << 0) | ||
938 | + | ||
939 | +/* SRCONFIG */ | ||
940 | +#define SR1_SRCONFIG_ACCUMDATA (0x1F4 << 22) | ||
941 | +#define SR2_SRCONFIG_ACCUMDATA (0x1F4 << 22) | ||
942 | + | ||
943 | +#define SRCLKLENGTH_12MHZ_SYSCLK 0x3C | ||
944 | +#define SRCLKLENGTH_13MHZ_SYSCLK 0x41 | ||
945 | +#define SRCLKLENGTH_19MHZ_SYSCLK 0x60 | ||
946 | +#define SRCLKLENGTH_26MHZ_SYSCLK 0x82 | ||
947 | +#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0 | ||
948 | + | ||
949 | +#define SRCONFIG_SRCLKLENGTH_SHIFT 12 | ||
950 | +#define SRCONFIG_SENNENABLE_SHIFT 5 | ||
951 | +#define SRCONFIG_SENPENABLE_SHIFT 3 | ||
952 | + | ||
953 | +#define SRCONFIG_SRENABLE (0x01 << 11) | ||
954 | +#define SRCONFIG_SENENABLE (0x01 << 10) | ||
955 | +#define SRCONFIG_ERRGEN_EN (0x01 << 9) | ||
956 | +#define SRCONFIG_MINMAXAVG_EN (0x01 << 8) | ||
957 | + | ||
958 | +#define SRCONFIG_DELAYCTRL (0x01 << 2) | ||
959 | +#define SRCONFIG_CLKCTRL (0x00 << 0) | ||
960 | + | ||
961 | +/* AVGWEIGHT */ | ||
962 | +#define SR1_AVGWEIGHT_SENPAVGWEIGHT (0x03 << 2) | ||
963 | +#define SR1_AVGWEIGHT_SENNAVGWEIGHT (0x03 << 0) | ||
964 | + | ||
965 | +#define SR2_AVGWEIGHT_SENPAVGWEIGHT (0x01 << 2) | ||
966 | +#define SR2_AVGWEIGHT_SENNAVGWEIGHT (0x01 << 0) | ||
967 | + | ||
968 | +/* NVALUERECIPROCAL */ | ||
969 | +#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20 | ||
970 | +#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16 | ||
971 | +#define NVALUERECIPROCAL_RNSENP_SHIFT 8 | ||
972 | +#define NVALUERECIPROCAL_RNSENN_SHIFT 0 | ||
973 | + | ||
974 | +/* ERRCONFIG */ | ||
975 | +#define SR_CLKACTIVITY_MASK (0x03 << 20) | ||
976 | +#define SR_ERRWEIGHT_MASK (0x07 << 16) | ||
977 | +#define SR_ERRMAXLIMIT_MASK (0xFF << 8) | ||
978 | +#define SR_ERRMINLIMIT_MASK (0xFF << 0) | ||
979 | + | ||
980 | +#define SR_CLKACTIVITY_IOFF_FOFF (0x00 << 20) | ||
981 | +#define SR_CLKACTIVITY_IOFF_FON (0x02 << 20) | ||
982 | + | ||
983 | +#define ERRCONFIG_VPBOUNDINTEN (0x1 << 31) | ||
984 | +#define ERRCONFIG_VPBOUNDINTST (0x1 << 30) | ||
985 | + | ||
986 | +#define SR1_ERRWEIGHT (0x07 << 16) | ||
987 | +#define SR1_ERRMAXLIMIT (0x02 << 8) | ||
988 | +#define SR1_ERRMINLIMIT (0xFA << 0) | ||
989 | + | ||
990 | +#define SR2_ERRWEIGHT (0x07 << 16) | ||
991 | +#define SR2_ERRMAXLIMIT (0x02 << 8) | ||
992 | +#define SR2_ERRMINLIMIT (0xF9 << 0) | ||
993 | + | ||
994 | +extern u32 current_vdd1_opp; | ||
995 | +extern u32 current_vdd2_opp; | ||
996 | +extern struct kset power_subsys; | ||
997 | + | ||
998 | +extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay); | ||
999 | +extern void omap_udelay(u32 udelay); | ||
1000 | + | ||
1001 | -- | ||
1002 | 1.5.4.3 | ||
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch new file mode 100644 index 0000000000..6e31ead2bd --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch | |||
@@ -0,0 +1,55 @@ | |||
1 | From a1dbb6dd28e9815a307b87b8d96dcf371d6cfd58 Mon Sep 17 00:00:00 2001 | ||
2 | From: Jarkko Nikula <jarkko.nikula@nokia.com> | ||
3 | Date: Mon, 19 May 2008 13:24:41 +0300 | ||
4 | Subject: [PATCH] ASoC: OMAP: Add basic support for OMAP34xx in McBSP DAI driver | ||
5 | |||
6 | This adds support for OMAP34xx McBSP port 1 and 2. | ||
7 | |||
8 | Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com> | ||
9 | --- | ||
10 | sound/soc/omap/omap-mcbsp.c | 20 +++++++++++++++++++- | ||
11 | 1 files changed, 19 insertions(+), 1 deletions(-) | ||
12 | |||
13 | diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c | ||
14 | index 40d87e6..8e6ec9d 100644 | ||
15 | --- a/sound/soc/omap/omap-mcbsp.c | ||
16 | +++ b/sound/soc/omap/omap-mcbsp.c | ||
17 | @@ -99,6 +99,21 @@ static const unsigned long omap2420_mcbsp_port[][2] = { | ||
18 | static const int omap2420_dma_reqs[][2] = {}; | ||
19 | static const unsigned long omap2420_mcbsp_port[][2] = {}; | ||
20 | #endif | ||
21 | +#if defined(CONFIG_ARCH_OMAP34XX) | ||
22 | +static const int omap34xx_dma_reqs[][2] = { | ||
23 | + { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX }, | ||
24 | + { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX }, | ||
25 | +}; | ||
26 | +static const unsigned long omap34xx_mcbsp_port[][2] = { | ||
27 | + { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR2, | ||
28 | + OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR2 }, | ||
29 | + { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR2, | ||
30 | + OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR2 }, | ||
31 | +}; | ||
32 | +#else | ||
33 | +static const int omap34xx_dma_reqs[][2] = {}; | ||
34 | +static const unsigned long omap34xx_mcbsp_port[][2] = {}; | ||
35 | +#endif | ||
36 | |||
37 | static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream) | ||
38 | { | ||
39 | @@ -169,9 +184,12 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, | ||
40 | } else if (cpu_is_omap2420()) { | ||
41 | dma = omap2420_dma_reqs[bus_id][substream->stream]; | ||
42 | port = omap2420_mcbsp_port[bus_id][substream->stream]; | ||
43 | + } else if (cpu_is_omap343x()) { | ||
44 | + dma = omap34xx_dma_reqs[bus_id][substream->stream]; | ||
45 | + port = omap34xx_mcbsp_port[bus_id][substream->stream]; | ||
46 | } else { | ||
47 | /* | ||
48 | - * TODO: Add support for 2430 and 3430 | ||
49 | + * TODO: Add support for 2430 | ||
50 | */ | ||
51 | return -ENODEV; | ||
52 | } | ||
53 | -- | ||
54 | 1.5.5.1 | ||
55 | |||
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch new file mode 100644 index 0000000000..cdc9447b4c --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch | |||
@@ -0,0 +1,450 @@ | |||
1 | From: "Rajendra Nayak" <rnayak@ti.com> | ||
2 | To: <linux-omap@vger.kernel.org> | ||
3 | Subject: [PATCH 01/02] OMAP3 CPUidle driver | ||
4 | Date: Tue, 10 Jun 2008 12:39:00 +0530 | ||
5 | |||
6 | This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver | ||
7 | before it queries the governor for the next state. | ||
8 | |||
9 | Signed-off-by: Rajendra Nayak <rnayak@ti.com> | ||
10 | |||
11 | --- | ||
12 | arch/arm/mach-omap2/Makefile | 2 | ||
13 | arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++ | ||
14 | arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++ | ||
15 | arch/arm/mach-omap2/pm34xx.c | 5 | ||
16 | drivers/cpuidle/cpuidle.c | 10 + | ||
17 | 5 files changed, 359 insertions(+), 2 deletions(-) | ||
18 | |||
19 | Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile | ||
20 | =================================================================== | ||
21 | --- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530 | ||
22 | +++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530 | ||
23 | @@ -20,7 +20,7 @@ obj-y += pm.o | ||
24 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o | ||
25 | obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o | ||
26 | obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o | ||
27 | -obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o | ||
28 | +obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o | ||
29 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o | ||
30 | endif | ||
31 | |||
32 | Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c | ||
33 | =================================================================== | ||
34 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
35 | +++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530 | ||
36 | @@ -0,0 +1,293 @@ | ||
37 | +/* | ||
38 | + * linux/arch/arm/mach-omap2/cpuidle34xx.c | ||
39 | + * | ||
40 | + * OMAP3 CPU IDLE Routines | ||
41 | + * | ||
42 | + * Copyright (C) 2007-2008 Texas Instruments, Inc. | ||
43 | + * Rajendra Nayak <rnayak@ti.com> | ||
44 | + * | ||
45 | + * Copyright (C) 2007 Texas Instruments, Inc. | ||
46 | + * Karthik Dasu <karthik-dp@ti.com> | ||
47 | + * | ||
48 | + * Copyright (C) 2006 Nokia Corporation | ||
49 | + * Tony Lindgren <tony@atomide.com> | ||
50 | + * | ||
51 | + * Copyright (C) 2005 Texas Instruments, Inc. | ||
52 | + * Richard Woodruff <r-woodruff2@ti.com> | ||
53 | + * | ||
54 | + * This program is free software; you can redistribute it and/or modify | ||
55 | + * it under the terms of the GNU General Public License version 2 as | ||
56 | + * published by the Free Software Foundation. | ||
57 | + */ | ||
58 | + | ||
59 | +#include <linux/cpuidle.h> | ||
60 | +#include <asm/arch/pm.h> | ||
61 | +#include <asm/arch/prcm.h> | ||
62 | +#include <asm/arch/powerdomain.h> | ||
63 | +#include <asm/arch/clockdomain.h> | ||
64 | +#include <asm/arch/irqs.h> | ||
65 | +#include "cpuidle34xx.h" | ||
66 | + | ||
67 | +#ifdef CONFIG_CPU_IDLE | ||
68 | + | ||
69 | +struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; | ||
70 | +struct omap3_processor_cx current_cx_state; | ||
71 | + | ||
72 | +static int omap3_idle_bm_check(void) | ||
73 | +{ | ||
74 | + /* Check for omap3_fclks_active() here once available */ | ||
75 | + return 0; | ||
76 | +} | ||
77 | + | ||
78 | +/* omap3_enter_idle - Programs OMAP3 to enter the specified state. | ||
79 | + * returns the total time during which the system was idle. | ||
80 | + */ | ||
81 | +static int omap3_enter_idle(struct cpuidle_device *dev, | ||
82 | + struct cpuidle_state *state) | ||
83 | +{ | ||
84 | + struct omap3_processor_cx *cx = cpuidle_get_statedata(state); | ||
85 | + struct timespec ts_preidle, ts_postidle, ts_idle; | ||
86 | + struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd; | ||
87 | + int neon_pwrst; | ||
88 | + | ||
89 | + current_cx_state = *cx; | ||
90 | + | ||
91 | + if (cx->type == OMAP3_STATE_C0) { | ||
92 | + /* Do nothing for C0, not even a wfi */ | ||
93 | + return 0; | ||
94 | + } | ||
95 | + | ||
96 | + /* Used to keep track of the total time in idle */ | ||
97 | + getnstimeofday(&ts_preidle); | ||
98 | + | ||
99 | + mpu_pd = pwrdm_lookup("mpu_pwrdm"); | ||
100 | + core_pd = pwrdm_lookup("core_pwrdm"); | ||
101 | + per_pd = pwrdm_lookup("per_pwrdm"); | ||
102 | + neon_pd = pwrdm_lookup("neon_pwrdm"); | ||
103 | + | ||
104 | + /* Reset previous power state registers */ | ||
105 | + pwrdm_clear_all_prev_pwrst(mpu_pd); | ||
106 | + pwrdm_clear_all_prev_pwrst(neon_pd); | ||
107 | + pwrdm_clear_all_prev_pwrst(core_pd); | ||
108 | + pwrdm_clear_all_prev_pwrst(per_pd); | ||
109 | + | ||
110 | + if (omap_irq_pending()) | ||
111 | + return 0; | ||
112 | + | ||
113 | + neon_pwrst = pwrdm_read_pwrst(neon_pd); | ||
114 | + | ||
115 | + /* Program MPU/NEON to target state */ | ||
116 | + if (cx->mpu_state < PWRDM_POWER_ON) { | ||
117 | + if (neon_pwrst == PWRDM_POWER_ON) { | ||
118 | + if (cx->mpu_state == PWRDM_POWER_RET) | ||
119 | + pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET); | ||
120 | + else if (cx->mpu_state == PWRDM_POWER_OFF) | ||
121 | + pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF); | ||
122 | + } | ||
123 | + pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state); | ||
124 | + } | ||
125 | + | ||
126 | + /* Program CORE to target state */ | ||
127 | + if (cx->core_state < PWRDM_POWER_ON) | ||
128 | + pwrdm_set_next_pwrst(core_pd, cx->core_state); | ||
129 | + | ||
130 | + /* Execute ARM wfi */ | ||
131 | + omap_sram_idle(); | ||
132 | + | ||
133 | + /* Program MPU/NEON to ON */ | ||
134 | + if (cx->mpu_state < PWRDM_POWER_ON) { | ||
135 | + if (neon_pwrst == PWRDM_POWER_ON) | ||
136 | + pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON); | ||
137 | + pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON); | ||
138 | + } | ||
139 | + | ||
140 | + if (cx->core_state < PWRDM_POWER_ON) | ||
141 | + pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON); | ||
142 | + | ||
143 | + getnstimeofday(&ts_postidle); | ||
144 | + ts_idle = timespec_sub(ts_postidle, ts_preidle); | ||
145 | + return timespec_to_ns(&ts_idle); | ||
146 | +} | ||
147 | + | ||
148 | +/* | ||
149 | + * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM | ||
150 | + * | ||
151 | + * This function checks for all the pre-requisites needed for OMAP3 to enter | ||
152 | + * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired | ||
153 | + * C state. | ||
154 | + */ | ||
155 | +static int omap3_enter_idle_bm(struct cpuidle_device *dev, | ||
156 | + struct cpuidle_state *state) | ||
157 | +{ | ||
158 | + struct cpuidle_state *new_state = NULL; | ||
159 | + int i, j; | ||
160 | + | ||
161 | + if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { | ||
162 | + | ||
163 | + /* Find current state in list */ | ||
164 | + for (i = 0; i < OMAP3_MAX_STATES; i++) | ||
165 | + if (state == &dev->states[i]) | ||
166 | + break; | ||
167 | + BUG_ON(i == OMAP3_MAX_STATES); | ||
168 | + | ||
169 | + /* Back up to non 'CHECK_BM' state */ | ||
170 | + for (j = i - 1; j > 0; j--) { | ||
171 | + struct cpuidle_state *s = &dev->states[j]; | ||
172 | + | ||
173 | + if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) { | ||
174 | + new_state = s; | ||
175 | + break; | ||
176 | + } | ||
177 | + } | ||
178 | + | ||
179 | + pr_debug("%s: Bus activity: Entering %s (instead of %s)\n", | ||
180 | + __FUNCTION__, new_state->name, state->name); | ||
181 | + } | ||
182 | + | ||
183 | + return omap3_enter_idle(dev, new_state ? : state); | ||
184 | +} | ||
185 | + | ||
186 | +DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); | ||
187 | + | ||
188 | +/* omap3_init_power_states - Initialises the OMAP3 specific C states. | ||
189 | + * Below is the desciption of each C state. | ||
190 | + * | ||
191 | + C0 . System executing code | ||
192 | + C1 . MPU WFI + Core active | ||
193 | + C2 . MPU CSWR + Core active | ||
194 | + C3 . MPU OFF + Core active | ||
195 | + C4 . MPU CSWR + Core CSWR | ||
196 | + C5 . MPU OFF + Core CSWR | ||
197 | + C6 . MPU OFF + Core OFF | ||
198 | + */ | ||
199 | +void omap_init_power_states(void) | ||
200 | +{ | ||
201 | + /* C0 . System executing code */ | ||
202 | + omap3_power_states[0].valid = 1; | ||
203 | + omap3_power_states[0].type = OMAP3_STATE_C0; | ||
204 | + omap3_power_states[0].sleep_latency = 0; | ||
205 | + omap3_power_states[0].wakeup_latency = 0; | ||
206 | + omap3_power_states[0].threshold = 0; | ||
207 | + omap3_power_states[0].mpu_state = PWRDM_POWER_ON; | ||
208 | + omap3_power_states[0].core_state = PWRDM_POWER_ON; | ||
209 | + omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID | | ||
210 | + CPUIDLE_FLAG_SHALLOW; | ||
211 | + | ||
212 | + /* C1 . MPU WFI + Core active */ | ||
213 | + omap3_power_states[1].valid = 1; | ||
214 | + omap3_power_states[1].type = OMAP3_STATE_C1; | ||
215 | + omap3_power_states[1].sleep_latency = 10; | ||
216 | + omap3_power_states[1].wakeup_latency = 10; | ||
217 | + omap3_power_states[1].threshold = 30; | ||
218 | + omap3_power_states[1].mpu_state = PWRDM_POWER_ON; | ||
219 | + omap3_power_states[1].core_state = PWRDM_POWER_ON; | ||
220 | + omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID | | ||
221 | + CPUIDLE_FLAG_SHALLOW; | ||
222 | + | ||
223 | + /* C2 . MPU CSWR + Core active */ | ||
224 | + omap3_power_states[2].valid = 1; | ||
225 | + omap3_power_states[2].type = OMAP3_STATE_C2; | ||
226 | + omap3_power_states[2].sleep_latency = 50; | ||
227 | + omap3_power_states[2].wakeup_latency = 50; | ||
228 | + omap3_power_states[2].threshold = 300; | ||
229 | + omap3_power_states[2].mpu_state = PWRDM_POWER_RET; | ||
230 | + omap3_power_states[2].core_state = PWRDM_POWER_ON; | ||
231 | + omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID | | ||
232 | + CPUIDLE_FLAG_BALANCED; | ||
233 | + | ||
234 | + /* C3 . MPU OFF + Core active */ | ||
235 | + omap3_power_states[3].valid = 0; | ||
236 | + omap3_power_states[3].type = OMAP3_STATE_C3; | ||
237 | + omap3_power_states[3].sleep_latency = 1500; | ||
238 | + omap3_power_states[3].wakeup_latency = 1800; | ||
239 | + omap3_power_states[3].threshold = 4000; | ||
240 | + omap3_power_states[3].mpu_state = PWRDM_POWER_OFF; | ||
241 | + omap3_power_states[3].core_state = PWRDM_POWER_RET; | ||
242 | + omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID | | ||
243 | + CPUIDLE_FLAG_BALANCED; | ||
244 | + | ||
245 | + /* C4 . MPU CSWR + Core CSWR*/ | ||
246 | + omap3_power_states[4].valid = 1; | ||
247 | + omap3_power_states[4].type = OMAP3_STATE_C4; | ||
248 | + omap3_power_states[4].sleep_latency = 2500; | ||
249 | + omap3_power_states[4].wakeup_latency = 7500; | ||
250 | + omap3_power_states[4].threshold = 12000; | ||
251 | + omap3_power_states[4].mpu_state = PWRDM_POWER_RET; | ||
252 | + omap3_power_states[4].core_state = PWRDM_POWER_RET; | ||
253 | + omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID | | ||
254 | + CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM; | ||
255 | + | ||
256 | + /* C5 . MPU OFF + Core CSWR */ | ||
257 | + omap3_power_states[5].valid = 0; | ||
258 | + omap3_power_states[5].type = OMAP3_STATE_C5; | ||
259 | + omap3_power_states[5].sleep_latency = 3000; | ||
260 | + omap3_power_states[5].wakeup_latency = 8500; | ||
261 | + omap3_power_states[5].threshold = 15000; | ||
262 | + omap3_power_states[5].mpu_state = PWRDM_POWER_OFF; | ||
263 | + omap3_power_states[5].core_state = PWRDM_POWER_RET; | ||
264 | + omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID | | ||
265 | + CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM; | ||
266 | + | ||
267 | + /* C6 . MPU OFF + Core OFF */ | ||
268 | + omap3_power_states[6].valid = 0; | ||
269 | + omap3_power_states[6].type = OMAP3_STATE_C6; | ||
270 | + omap3_power_states[6].sleep_latency = 10000; | ||
271 | + omap3_power_states[6].wakeup_latency = 30000; | ||
272 | + omap3_power_states[6].threshold = 300000; | ||
273 | + omap3_power_states[6].mpu_state = PWRDM_POWER_OFF; | ||
274 | + omap3_power_states[6].core_state = PWRDM_POWER_OFF; | ||
275 | + omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID | | ||
276 | + CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM; | ||
277 | +} | ||
278 | + | ||
279 | +struct cpuidle_driver omap3_idle_driver = { | ||
280 | + .name = "omap3_idle", | ||
281 | + .owner = THIS_MODULE, | ||
282 | +}; | ||
283 | +/* | ||
284 | + * omap3_idle_init - Init routine for OMAP3 idle. | ||
285 | + * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w | ||
286 | + * with the valid set of states. | ||
287 | + */ | ||
288 | +int omap3_idle_init(void) | ||
289 | +{ | ||
290 | + int i, count = 0; | ||
291 | + struct omap3_processor_cx *cx; | ||
292 | + struct cpuidle_state *state; | ||
293 | + struct cpuidle_device *dev; | ||
294 | + | ||
295 | + omap_init_power_states(); | ||
296 | + cpuidle_register_driver(&omap3_idle_driver); | ||
297 | + | ||
298 | + dev = &per_cpu(omap3_idle_dev, smp_processor_id()); | ||
299 | + | ||
300 | + for (i = 0; i < OMAP3_MAX_STATES; i++) { | ||
301 | + cx = &omap3_power_states[i]; | ||
302 | + state = &dev->states[count]; | ||
303 | + | ||
304 | + if (!cx->valid) | ||
305 | + continue; | ||
306 | + cpuidle_set_statedata(state, cx); | ||
307 | + state->exit_latency = cx->sleep_latency + cx->wakeup_latency; | ||
308 | + state->target_residency = cx->threshold; | ||
309 | + state->flags = cx->flags; | ||
310 | + state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? | ||
311 | + omap3_enter_idle_bm : omap3_enter_idle; | ||
312 | + sprintf(state->name, "C%d", count+1); | ||
313 | + count++; | ||
314 | + } | ||
315 | + | ||
316 | + if (!count) | ||
317 | + return -EINVAL; | ||
318 | + dev->state_count = count; | ||
319 | + | ||
320 | + if (cpuidle_register_device(dev)) { | ||
321 | + printk(KERN_ERR "%s: CPUidle register device failed\n", | ||
322 | + __FUNCTION__); | ||
323 | + return -EIO; | ||
324 | + } | ||
325 | + | ||
326 | + return 0; | ||
327 | +} | ||
328 | +__initcall(omap3_idle_init); | ||
329 | +#endif /* CONFIG_CPU_IDLE */ | ||
330 | Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h | ||
331 | =================================================================== | ||
332 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
333 | +++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530 | ||
334 | @@ -0,0 +1,51 @@ | ||
335 | +/* | ||
336 | + * linux/arch/arm/mach-omap2/cpuidle34xx.h | ||
337 | + * | ||
338 | + * OMAP3 cpuidle structure definitions | ||
339 | + * | ||
340 | + * Copyright (C) 2007-2008 Texas Instruments, Inc. | ||
341 | + * Written by Rajendra Nayak <rnayak@ti.com> | ||
342 | + * | ||
343 | + * This program is free software; you can redistribute it and/or modify | ||
344 | + * it under the terms of the GNU General Public License version 2 as | ||
345 | + * published by the Free Software Foundation. | ||
346 | + * | ||
347 | + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR | ||
348 | + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED | ||
349 | + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. | ||
350 | + * | ||
351 | + * History: | ||
352 | + * | ||
353 | + */ | ||
354 | + | ||
355 | +#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX | ||
356 | +#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX | ||
357 | + | ||
358 | +#define OMAP3_MAX_STATES 7 | ||
359 | +#define OMAP3_STATE_C0 0 /* C0 - System executing code */ | ||
360 | +#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */ | ||
361 | +#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */ | ||
362 | +#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */ | ||
363 | +#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */ | ||
364 | +#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */ | ||
365 | +#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */ | ||
366 | + | ||
367 | +extern void omap_sram_idle(void); | ||
368 | +extern int omap3_irq_pending(void); | ||
369 | + | ||
370 | +struct omap3_processor_cx { | ||
371 | + u8 valid; | ||
372 | + u8 type; | ||
373 | + u32 sleep_latency; | ||
374 | + u32 wakeup_latency; | ||
375 | + u32 mpu_state; | ||
376 | + u32 core_state; | ||
377 | + u32 threshold; | ||
378 | + u32 flags; | ||
379 | +}; | ||
380 | + | ||
381 | +void omap_init_power_states(void); | ||
382 | +int omap3_idle_init(void); | ||
383 | + | ||
384 | +#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */ | ||
385 | + | ||
386 | Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c | ||
387 | =================================================================== | ||
388 | --- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530 | ||
389 | +++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530 | ||
390 | @@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle | ||
391 | return IRQ_HANDLED; | ||
392 | } | ||
393 | |||
394 | -static void omap_sram_idle(void) | ||
395 | +void omap_sram_idle(void) | ||
396 | { | ||
397 | /* Variable to tell what needs to be saved and restored | ||
398 | * in omap_sram_idle*/ | ||
399 | @@ -156,6 +156,7 @@ static void omap_sram_idle(void) | ||
400 | |||
401 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); | ||
402 | switch (mpu_next_state) { | ||
403 | + case PWRDM_POWER_ON: | ||
404 | case PWRDM_POWER_RET: | ||
405 | /* No need to save context */ | ||
406 | save_state = 0; | ||
407 | @@ -386,7 +387,9 @@ int __init omap3_pm_init(void) | ||
408 | |||
409 | prcm_setup_regs(); | ||
410 | |||
411 | +#ifndef CONFIG_CPU_IDLE | ||
412 | pm_idle = omap3_pm_idle; | ||
413 | +#endif | ||
414 | |||
415 | err1: | ||
416 | return ret; | ||
417 | Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c | ||
418 | =================================================================== | ||
419 | --- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530 | ||
420 | +++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530 | ||
421 | @@ -58,6 +58,11 @@ static void cpuidle_idle_call(void) | ||
422 | return; | ||
423 | } | ||
424 | |||
425 | +#ifdef CONFIG_ARCH_OMAP3 | ||
426 | + local_irq_disable(); | ||
427 | + local_fiq_disable(); | ||
428 | +#endif | ||
429 | + | ||
430 | /* ask the governor for the next state */ | ||
431 | next_state = cpuidle_curr_governor->select(dev); | ||
432 | if (need_resched()) | ||
433 | @@ -70,6 +75,11 @@ static void cpuidle_idle_call(void) | ||
434 | target_state->time += (unsigned long long)dev->last_residency; | ||
435 | target_state->usage++; | ||
436 | |||
437 | +#ifdef CONFIG_ARCH_OMAP3 | ||
438 | + local_irq_enable(); | ||
439 | + local_fiq_enable(); | ||
440 | +#endif | ||
441 | + | ||
442 | /* give the governor an opportunity to reflect on the outcome */ | ||
443 | if (cpuidle_curr_governor->reflect) | ||
444 | cpuidle_curr_governor->reflect(dev); | ||
445 | |||
446 | -- | ||
447 | To unsubscribe from this list: send the line "unsubscribe linux-omap" in | ||
448 | the body of a message to majordomo@vger.kernel.org | ||
449 | More majordomo info at http://vger.kernel.org/majordomo-info.html | ||
450 | |||
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch new file mode 100644 index 0000000000..17329be29b --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch | |||
@@ -0,0 +1,69 @@ | |||
1 | From 7a444ee080c5f1a62ac5042f1e7926622b3e1ce7 Mon Sep 17 00:00:00 2001 | ||
2 | From: Koen Kooi <koen@openembedded.org> | ||
3 | Date: Fri, 30 May 2008 13:43:36 +0200 | ||
4 | Subject: [PATCH] ARM: OMAP: omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver | ||
5 | |||
6 | omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver | ||
7 | * on revision A5 and earlier board the two leds can't be controlled seperately, should be fixed in rev. B and C boards. | ||
8 | |||
9 | Signed-off-by: Koen Kooi <koen@openembedded.org> | ||
10 | --- | ||
11 | arch/arm/mach-omap2/board-omap3beagle.c | 28 ++++++++++++++++++++++++++++ | ||
12 | 1 files changed, 28 insertions(+), 0 deletions(-) | ||
13 | |||
14 | diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c | ||
15 | index c992cc7..83891fc 100644 | ||
16 | --- a/arch/arm/mach-omap2/board-omap3beagle.c | ||
17 | +++ b/arch/arm/mach-omap2/board-omap3beagle.c | ||
18 | @@ -19,6 +19,7 @@ | ||
19 | #include <linux/err.h> | ||
20 | #include <linux/clk.h> | ||
21 | #include <linux/io.h> | ||
22 | +#include <linux/leds.h> | ||
23 | |||
24 | #include <asm/hardware.h> | ||
25 | #include <asm/mach-types.h> | ||
26 | @@ -72,6 +73,32 @@ static struct omap_lcd_config omap3_beagle_lcd_config __initdata = { | ||
27 | .ctrl_name = "internal", | ||
28 | }; | ||
29 | |||
30 | +struct gpio_led gpio_leds[] = { | ||
31 | + { | ||
32 | + .name = "beagleboard::led0", | ||
33 | + .default_trigger = "none", | ||
34 | + .gpio = 149, | ||
35 | + }, | ||
36 | + { | ||
37 | + .name = "beagleboard::led1", | ||
38 | + .default_trigger = "none", | ||
39 | + .gpio = 150, | ||
40 | + }, | ||
41 | +}; | ||
42 | + | ||
43 | +static struct gpio_led_platform_data gpio_led_info = { | ||
44 | + .leds = gpio_leds, | ||
45 | + .num_leds = ARRAY_SIZE(gpio_leds), | ||
46 | +}; | ||
47 | + | ||
48 | +static struct platform_device leds_gpio = { | ||
49 | + .name = "leds-gpio", | ||
50 | + .id = -1, | ||
51 | + .dev = { | ||
52 | + .platform_data = &gpio_led_info, | ||
53 | + }, | ||
54 | +}; | ||
55 | + | ||
56 | static struct omap_board_config_kernel omap3_beagle_config[] __initdata = { | ||
57 | { OMAP_TAG_UART, &omap3_beagle_uart_config }, | ||
58 | { OMAP_TAG_MMC, &omap3beagle_mmc_config }, | ||
59 | @@ -83,6 +110,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = { | ||
60 | #ifdef CONFIG_RTC_DRV_TWL4030 | ||
61 | &omap3_beagle_twl4030rtc_device, | ||
62 | #endif | ||
63 | + &leds_gpio, | ||
64 | }; | ||
65 | |||
66 | static void __init omap3_beagle_init(void) | ||
67 | -- | ||
68 | 1.5.4.3 | ||
69 | |||
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch new file mode 100644 index 0000000000..8e609395a0 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch | |||
@@ -0,0 +1,278 @@ | |||
1 | From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> | ||
2 | To: linux-omap@vger.kernel.org | ||
3 | Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> | ||
4 | Subject: [PATCH 2/3] ARM: OMAP: SmartReflex driver: added required register and bit definitions. | ||
5 | Date: Fri, 6 Jun 2008 12:49:48 +0300 | ||
6 | |||
7 | Added new register and bit definitions to enable Smartreflex driver integration. | ||
8 | Also PRM_VC_SMPS_SA bit definitions' naming was changed to match the naming of | ||
9 | other similar bit definitions. | ||
10 | |||
11 | Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> | ||
12 | --- | ||
13 | arch/arm/mach-omap2/prm-regbits-34xx.h | 27 ++++++-- | ||
14 | arch/arm/mach-omap2/smartreflex.h | 124 ++++++++++++++++++++++++++++++- | ||
15 | include/asm-arm/arch-omap/control.h | 19 +++++ | ||
16 | include/asm-arm/arch-omap/omap34xx.h | 2 + | ||
17 | 4 files changed, 163 insertions(+), 9 deletions(-) | ||
18 | |||
19 | diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h | ||
20 | index c6a7940..f82b5a7 100644 | ||
21 | --- a/arch/arm/mach-omap2/prm-regbits-34xx.h | ||
22 | +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | ||
23 | @@ -435,10 +435,10 @@ | ||
24 | /* PM_PWSTST_EMU specific bits */ | ||
25 | |||
26 | /* PRM_VC_SMPS_SA */ | ||
27 | -#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 | ||
28 | -#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) | ||
29 | -#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 | ||
30 | -#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) | ||
31 | +#define OMAP3430_SMPS_SA1_SHIFT 16 | ||
32 | +#define OMAP3430_SMPS_SA1_MASK (0x7f << 16) | ||
33 | +#define OMAP3430_SMPS_SA0_SHIFT 0 | ||
34 | +#define OMAP3430_SMPS_SA0_MASK (0x7f << 0) | ||
35 | |||
36 | /* PRM_VC_SMPS_VOL_RA */ | ||
37 | #define OMAP3430_VOLRA1_SHIFT 16 | ||
38 | @@ -452,7 +452,7 @@ | ||
39 | #define OMAP3430_CMDRA0_SHIFT 0 | ||
40 | #define OMAP3430_CMDRA0_MASK (0xff << 0) | ||
41 | |||
42 | -/* PRM_VC_CMD_VAL_0 specific bits */ | ||
43 | +/* PRM_VC_CMD_VAL */ | ||
44 | #define OMAP3430_VC_CMD_ON_SHIFT 24 | ||
45 | #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) | ||
46 | #define OMAP3430_VC_CMD_ONLP_SHIFT 16 | ||
47 | @@ -462,7 +462,17 @@ | ||
48 | #define OMAP3430_VC_CMD_OFF_SHIFT 0 | ||
49 | #define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0) | ||
50 | |||
51 | +/* PRM_VC_CMD_VAL_0 specific bits */ | ||
52 | +#define OMAP3430_VC_CMD_VAL0_ON (0x3 << 4) | ||
53 | +#define OMAP3430_VC_CMD_VAL0_ONLP (0x3 << 3) | ||
54 | +#define OMAP3430_VC_CMD_VAL0_RET (0x3 << 3) | ||
55 | +#define OMAP3430_VC_CMD_VAL0_OFF (0x3 << 3) | ||
56 | + | ||
57 | /* PRM_VC_CMD_VAL_1 specific bits */ | ||
58 | +#define OMAP3430_VC_CMD_VAL1_ON (0xB << 2) | ||
59 | +#define OMAP3430_VC_CMD_VAL1_ONLP (0x3 << 3) | ||
60 | +#define OMAP3430_VC_CMD_VAL1_RET (0x3 << 3) | ||
61 | +#define OMAP3430_VC_CMD_VAL1_OFF (0x3 << 3) | ||
62 | |||
63 | /* PRM_VC_CH_CONF */ | ||
64 | #define OMAP3430_CMD1 (1 << 20) | ||
65 | @@ -521,6 +531,13 @@ | ||
66 | #define OMAP3430_AUTO_RET (1 << 1) | ||
67 | #define OMAP3430_AUTO_SLEEP (1 << 0) | ||
68 | |||
69 | +/* Constants to define setup durations */ | ||
70 | +#define OMAP3430_CLKSETUP_DURATION 0xff | ||
71 | +#define OMAP3430_VOLTSETUP_TIME2 0xfff | ||
72 | +#define OMAP3430_VOLTSETUP_TIME1 0xfff | ||
73 | +#define OMAP3430_VOLTOFFSET_DURATION 0xff | ||
74 | +#define OMAP3430_VOLTSETUP2_DURATION 0xff | ||
75 | + | ||
76 | /* PRM_SRAM_PCHARGE */ | ||
77 | #define OMAP3430_PCHARGE_TIME_SHIFT 0 | ||
78 | #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0) | ||
79 | diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h | ||
80 | index 62907ef..2091a15 100644 | ||
81 | --- a/arch/arm/mach-omap2/smartreflex.h | ||
82 | +++ b/arch/arm/mach-omap2/smartreflex.h | ||
83 | @@ -1,5 +1,10 @@ | ||
84 | +#ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H | ||
85 | +#define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H | ||
86 | /* | ||
87 | - * linux/arch/arm/mach-omap3/smartreflex.h | ||
88 | + * linux/arch/arm/mach-omap2/smartreflex.h | ||
89 | + * | ||
90 | + * Copyright (C) 2008 Nokia Corporation | ||
91 | + * Kalle Jokiniemi | ||
92 | * | ||
93 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
94 | * Lesly A M <x0080970@ti.com> | ||
95 | @@ -9,6 +14,21 @@ | ||
96 | * published by the Free Software Foundation. | ||
97 | */ | ||
98 | |||
99 | +#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36) | ||
100 | +#define PHY_TO_OFF_PM_RECIEVER(p) (p - 0x5b) | ||
101 | +#define PHY_TO_OFF_PM_INT(p) (p - 0x2e) | ||
102 | + | ||
103 | +/* SMART REFLEX REG ADDRESS OFFSET */ | ||
104 | +#define SRCONFIG 0x00 | ||
105 | +#define SRSTATUS 0x04 | ||
106 | +#define SENVAL 0x08 | ||
107 | +#define SENMIN 0x0C | ||
108 | +#define SENMAX 0x10 | ||
109 | +#define SENAVG 0x14 | ||
110 | +#define AVGWEIGHT 0x18 | ||
111 | +#define NVALUERECIPROCAL 0x1C | ||
112 | +#define SENERROR 0x20 | ||
113 | +#define ERRCONFIG 0x24 | ||
114 | |||
115 | /* SR Modules */ | ||
116 | #define SR1 1 | ||
117 | @@ -127,10 +147,106 @@ | ||
118 | #define SR2_ERRMAXLIMIT (0x02 << 8) | ||
119 | #define SR2_ERRMINLIMIT (0xF9 << 0) | ||
120 | |||
121 | +/* T2 SMART REFLEX */ | ||
122 | +#define R_SRI2C_SLAVE_ADDR 0x12 | ||
123 | +#define R_VDD1_SR_CONTROL 0x00 | ||
124 | +#define R_VDD2_SR_CONTROL 0x01 | ||
125 | +#define T2_SMPS_UPDATE_DELAY 360 /* In uSec */ | ||
126 | + | ||
127 | +/* Vmode control */ | ||
128 | +#define R_DCDC_GLOBAL_CFG PHY_TO_OFF_PM_RECIEVER(0x61) | ||
129 | + | ||
130 | +#define R_VDD1_VSEL PHY_TO_OFF_PM_RECIEVER(0xb9) | ||
131 | +#define R_VDD1_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xba) | ||
132 | +#define R_VDD1_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xbb) | ||
133 | +#define R_VDD1_VROOF PHY_TO_OFF_PM_RECIEVER(0xbc) | ||
134 | +#define R_VDD1_STEP PHY_TO_OFF_PM_RECIEVER(0xbd) | ||
135 | + | ||
136 | +#define R_VDD2_VSEL PHY_TO_OFF_PM_RECIEVER(0xc7) | ||
137 | +#define R_VDD2_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xc8) | ||
138 | +#define R_VDD2_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xc9) | ||
139 | +#define R_VDD2_VROOF PHY_TO_OFF_PM_RECIEVER(0xca) | ||
140 | +#define R_VDD2_STEP PHY_TO_OFF_PM_RECIEVER(0xcb) | ||
141 | + | ||
142 | +/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE valuws */ | ||
143 | +#define DCDC_GLOBAL_CFG_ENABLE_SRFLX 0x08 | ||
144 | + | ||
145 | +/* VDDs*/ | ||
146 | +#define PRCM_VDD1 1 | ||
147 | +#define PRCM_VDD2 2 | ||
148 | +#define PRCM_MAX_SYSC_REGS 30 | ||
149 | + | ||
150 | +/* XXX: These should be removed/moved from here once we have a working DVFS | ||
151 | + implementation in place */ | ||
152 | +#define AT_3430 1 /*3430 ES 1.0 */ | ||
153 | +#define AT_3430_ES2 2 /*3430 ES 2.0 */ | ||
154 | + | ||
155 | +#define ID_OPP 0xE2 /*OPP*/ | ||
156 | + | ||
157 | +/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */ | ||
158 | +#define OMAP_TYPE_SHIFT 28 | ||
159 | +#define OMAP_TYPE_MASK 0xF | ||
160 | +/* OPP ID: bits: 0-4 for OPP number */ | ||
161 | +#define OPP_NO_POS 0 | ||
162 | +#define OPP_NO_MASK 0x1F | ||
163 | +/* OPP ID: bits: 5-6 for VDD */ | ||
164 | +#define VDD_NO_POS 5 | ||
165 | +#define VDD_NO_MASK 0x3 | ||
166 | +/* Other IDs: bits 20-27 for ID type */ | ||
167 | +/* These IDs have bits 25,26,27 as 1 */ | ||
168 | +#define OTHER_ID_TYPE_SHIFT 20 | ||
169 | +#define OTHER_ID_TYPE_MASK 0xFF | ||
170 | + | ||
171 | +#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT) | ||
172 | +#define ID_OPP_NO(X) ((X & OPP_NO_MASK) << OPP_NO_POS) | ||
173 | +#define ID_VDD(X) ((X & VDD_NO_MASK) << VDD_NO_POS) | ||
174 | +#define OMAP(X) ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK) | ||
175 | +#define get_opp_no(X) ((X >> OPP_NO_POS) & OPP_NO_MASK) | ||
176 | +#define get_vdd(X) ((X >> VDD_NO_POS) & VDD_NO_MASK) | ||
177 | + | ||
178 | +/* VDD1 OPPs */ | ||
179 | +#define PRCM_VDD1_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ | ||
180 | + ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1)) | ||
181 | +#define PRCM_VDD1_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ | ||
182 | + ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2)) | ||
183 | +#define PRCM_VDD1_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ | ||
184 | + ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3)) | ||
185 | +#define PRCM_VDD1_OPP4 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ | ||
186 | + ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4)) | ||
187 | +#define PRCM_VDD1_OPP5 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ | ||
188 | + ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5)) | ||
189 | +#define PRCM_NO_VDD1_OPPS 5 | ||
190 | + | ||
191 | + | ||
192 | +/* VDD2 OPPs */ | ||
193 | +#define PRCM_VDD2_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ | ||
194 | + ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1)) | ||
195 | +#define PRCM_VDD2_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ | ||
196 | + ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2)) | ||
197 | +#define PRCM_VDD2_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ | ||
198 | + ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3)) | ||
199 | +#define PRCM_NO_VDD2_OPPS 3 | ||
200 | +/* XXX: end remove/move */ | ||
201 | + | ||
202 | + | ||
203 | +/* XXX: find more appropriate place for these once DVFS is in place */ | ||
204 | extern u32 current_vdd1_opp; | ||
205 | extern u32 current_vdd2_opp; | ||
206 | -extern struct kset power_subsys; | ||
207 | |||
208 | -extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay); | ||
209 | -extern void omap_udelay(u32 udelay); | ||
210 | +/* | ||
211 | + * Smartreflex module enable/disable interface. | ||
212 | + * NOTE: if smartreflex is not enabled from sysfs, these functions will not | ||
213 | + * do anything. | ||
214 | + */ | ||
215 | +#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE) | ||
216 | +void enable_smartreflex(int srid); | ||
217 | +void disable_smartreflex(int srid); | ||
218 | +#else | ||
219 | +static inline void enable_smartreflex(int srid) {} | ||
220 | +static inline void disable_smartreflex(int srid) {} | ||
221 | +#endif | ||
222 | + | ||
223 | + | ||
224 | +#endif | ||
225 | + | ||
226 | |||
227 | diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h | ||
228 | index 12bc22a..6e64fe7 100644 | ||
229 | --- a/include/asm-arm/arch-omap/control.h | ||
230 | +++ b/include/asm-arm/arch-omap/control.h | ||
231 | @@ -138,6 +138,15 @@ | ||
232 | #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) | ||
233 | #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) | ||
234 | #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) | ||
235 | +#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) | ||
236 | +#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) | ||
237 | +#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) | ||
238 | +#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) | ||
239 | +#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) | ||
240 | +#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) | ||
241 | +#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) | ||
242 | +#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) | ||
243 | +#define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) | ||
244 | #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) | ||
245 | #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) | ||
246 | #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) | ||
247 | @@ -172,6 +181,16 @@ | ||
248 | #define OMAP2_SYSBOOT_1_MASK (1 << 1) | ||
249 | #define OMAP2_SYSBOOT_0_MASK (1 << 0) | ||
250 | |||
251 | +/* CONTROL_FUSE_SR bits */ | ||
252 | +#define OMAP343X_SR2_SENNENABLE_MASK (0x3 << 10) | ||
253 | +#define OMAP343X_SR2_SENNENABLE_SHIFT 10 | ||
254 | +#define OMAP343X_SR2_SENPENABLE_MASK (0x3 << 8) | ||
255 | +#define OMAP343X_SR2_SENPENABLE_SHIFT 8 | ||
256 | +#define OMAP343X_SR1_SENNENABLE_MASK (0x3 << 2) | ||
257 | +#define OMAP343X_SR1_SENNENABLE_SHIFT 2 | ||
258 | +#define OMAP343X_SR1_SENPENABLE_MASK (0x3 << 0) | ||
259 | +#define OMAP343X_SR1_SENPENABLE_SHIFT 0 | ||
260 | + | ||
261 | #ifndef __ASSEMBLY__ | ||
262 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
263 | extern void __iomem *omap_ctrl_base_get(void); | ||
264 | diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h | ||
265 | index 6a0459a..3667fd6 100644 | ||
266 | --- a/include/asm-arm/arch-omap/omap34xx.h | ||
267 | +++ b/include/asm-arm/arch-omap/omap34xx.h | ||
268 | @@ -54,6 +54,8 @@ | ||
269 | #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) | ||
270 | #define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000) | ||
271 | #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) | ||
272 | +#define OMAP34XX_SR1_BASE 0x480C9000 | ||
273 | +#define OMAP34XX_SR2_BASE 0x480CB000 | ||
274 | |||
275 | |||
276 | #if defined(CONFIG_ARCH_OMAP3430) | ||
277 | -- | ||
278 | 1.5.4.3 | ||
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch new file mode 100644 index 0000000000..d35fd47567 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch | |||
@@ -0,0 +1,88 @@ | |||
1 | From: "Rajendra Nayak" <rnayak@ti.com> | ||
2 | To: <linux-omap@vger.kernel.org> | ||
3 | Subject: [PATCH 02/02] Kconfig changes | ||
4 | Date: Tue, 10 Jun 2008 12:39:02 +0530 | ||
5 | |||
6 | Updates the CPUidle Kconfig | ||
7 | |||
8 | Signed-off-by: Rajendra Nayak <rnayak@ti.com> | ||
9 | |||
10 | --- | ||
11 | arch/arm/Kconfig | 10 ++++++++++ | ||
12 | drivers/cpuidle/Kconfig | 28 ++++++++++++++++++++++------ | ||
13 | 2 files changed, 32 insertions(+), 6 deletions(-) | ||
14 | |||
15 | Index: linux-omap-2.6/arch/arm/Kconfig | ||
16 | =================================================================== | ||
17 | --- linux-omap-2.6.orig/arch/arm/Kconfig 2008-06-10 11:43:10.790502713 +0530 | ||
18 | +++ linux-omap-2.6/arch/arm/Kconfig 2008-06-10 11:43:38.701604549 +0530 | ||
19 | @@ -954,6 +954,16 @@ config ATAGS_PROC | ||
20 | |||
21 | endmenu | ||
22 | |||
23 | +if (ARCH_OMAP) | ||
24 | + | ||
25 | +menu "CPUIdle" | ||
26 | + | ||
27 | +source "drivers/cpuidle/Kconfig" | ||
28 | + | ||
29 | +endmenu | ||
30 | + | ||
31 | +endif | ||
32 | + | ||
33 | if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) | ||
34 | |||
35 | menu "CPU Frequency scaling" | ||
36 | Index: linux-omap-2.6/drivers/cpuidle/Kconfig | ||
37 | =================================================================== | ||
38 | --- linux-omap-2.6.orig/drivers/cpuidle/Kconfig 2008-06-10 11:43:10.790502713 +0530 | ||
39 | +++ linux-omap-2.6/drivers/cpuidle/Kconfig 2008-06-10 12:06:36.139332151 +0530 | ||
40 | @@ -1,20 +1,36 @@ | ||
41 | +menu "CPU idle PM support" | ||
42 | |||
43 | config CPU_IDLE | ||
44 | bool "CPU idle PM support" | ||
45 | - default ACPI | ||
46 | + default n | ||
47 | help | ||
48 | CPU idle is a generic framework for supporting software-controlled | ||
49 | idle processor power management. It includes modular cross-platform | ||
50 | governors that can be swapped during runtime. | ||
51 | |||
52 | - If you're using an ACPI-enabled platform, you should say Y here. | ||
53 | + If you're using a mobile platform that supports CPU idle PM (e.g. | ||
54 | + an ACPI-capable notebook), you should say Y here. | ||
55 | + | ||
56 | +if CPU_IDLE | ||
57 | + | ||
58 | +comment "Governors" | ||
59 | |||
60 | config CPU_IDLE_GOV_LADDER | ||
61 | - bool | ||
62 | + bool "ladder" | ||
63 | depends on CPU_IDLE | ||
64 | - default y | ||
65 | + default n | ||
66 | |||
67 | config CPU_IDLE_GOV_MENU | ||
68 | - bool | ||
69 | + bool "menu" | ||
70 | depends on CPU_IDLE && NO_HZ | ||
71 | - default y | ||
72 | + default n | ||
73 | + help | ||
74 | + This cpuidle governor evaluates all available states and chooses the | ||
75 | + deepest state that meets all of the following constraints: BM activity, | ||
76 | + expected time until next timer interrupt, and last break event time | ||
77 | + delta. It is designed to minimize power consumption. Currently | ||
78 | + dynticks is required. | ||
79 | + | ||
80 | +endif # CPU_IDLE | ||
81 | + | ||
82 | +endmenu | ||
83 | |||
84 | -- | ||
85 | To unsubscribe from this list: send the line "unsubscribe linux-omap" in | ||
86 | the body of a message to majordomo@vger.kernel.org | ||
87 | More majordomo info at http://vger.kernel.org/majordomo-info.html | ||
88 | |||
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch new file mode 100644 index 0000000000..40d5790367 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch | |||
@@ -0,0 +1,1001 @@ | |||
1 | From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> | ||
2 | To: linux-omap@vger.kernel.org | ||
3 | Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> | ||
4 | Subject: [PATCH 3/3] ARM: OMAP: SmartReflex driver: integration to linux-omap | ||
5 | Date: Fri, 6 Jun 2008 12:49:49 +0300 | ||
6 | Message-Id: <1212745789-13926-3-git-send-email-ext-kalle.jokiniemi@nokia.com> | ||
7 | |||
8 | - Changed register accesses to use prm_{read,write}_mod_reg and | ||
9 | prm_{set,clear,rmw}_mod_reg_bits() functions instread of | ||
10 | "REG_X = REG_Y" type accesses. | ||
11 | |||
12 | - Changed direct register clock enables/disables to clockframework calls. | ||
13 | |||
14 | - replaced cpu-related #ifdefs with if (cpu_is_xxxx()) calls. | ||
15 | |||
16 | - Added E-fuse support: Use silicon characteristics parameters from E-fuse | ||
17 | |||
18 | - added smartreflex_disable/enable calls to pm34xx.c suspend function. | ||
19 | |||
20 | - Added "SmartReflex support" entry into Kconfig under "System type->TI OMAP | ||
21 | Implementations". It depends on ARCH_OMAP34XX and TWL4030_CORE. | ||
22 | |||
23 | - Added "SmartReflex testing support" Kconfig option for using hard coded | ||
24 | software parameters instead of E-fuse parameters. | ||
25 | |||
26 | Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> | ||
27 | --- | ||
28 | arch/arm/mach-omap2/Makefile | 3 + | ||
29 | arch/arm/mach-omap2/pm34xx.c | 9 + | ||
30 | arch/arm/mach-omap2/smartreflex.c | 531 +++++++++++++++++++++++-------------- | ||
31 | arch/arm/mach-omap2/smartreflex.h | 9 +- | ||
32 | arch/arm/plat-omap/Kconfig | 31 +++ | ||
33 | 5 files changed, 385 insertions(+), 198 deletions(-) | ||
34 | |||
35 | diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile | ||
36 | index 50c6657..f645b6e 100644 | ||
37 | --- a/arch/arm/mach-omap2/Makefile | ||
38 | +++ b/arch/arm/mach-omap2/Makefile | ||
39 | @@ -25,6 +25,9 @@ obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o | ||
40 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o | ||
41 | endif | ||
42 | |||
43 | +# SmartReflex driver | ||
44 | +obj-$(CONFIG_OMAP_SMARTREFLEX) += smartreflex.o | ||
45 | + | ||
46 | # Clock framework | ||
47 | obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o | ||
48 | obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o | ||
49 | diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c | ||
50 | index 7e775cc..3da4f47 100644 | ||
51 | --- a/arch/arm/mach-omap2/pm34xx.c | ||
52 | +++ b/arch/arm/mach-omap2/pm34xx.c | ||
53 | @@ -36,6 +36,7 @@ | ||
54 | |||
55 | #include "prm.h" | ||
56 | #include "pm.h" | ||
57 | +#include "smartreflex.h" | ||
58 | |||
59 | struct power_state { | ||
60 | struct powerdomain *pwrdm; | ||
61 | @@ -256,6 +257,10 @@ static int omap3_pm_suspend(void) | ||
62 | struct power_state *pwrst; | ||
63 | int state, ret = 0; | ||
64 | |||
65 | + /* XXX Disable smartreflex before entering suspend */ | ||
66 | + disable_smartreflex(SR1); | ||
67 | + disable_smartreflex(SR2); | ||
68 | + | ||
69 | /* Read current next_pwrsts */ | ||
70 | list_for_each_entry(pwrst, &pwrst_list, node) | ||
71 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | ||
72 | @@ -287,6 +292,10 @@ restore: | ||
73 | printk(KERN_INFO "Successfully put all powerdomains " | ||
74 | "to target state\n"); | ||
75 | |||
76 | + /* XXX Enable smartreflex after suspend */ | ||
77 | + enable_smartreflex(SR1); | ||
78 | + enable_smartreflex(SR2); | ||
79 | + | ||
80 | return ret; | ||
81 | } | ||
82 | |||
83 | diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c | ||
84 | index dae7460..0b10a5d 100644 | ||
85 | --- a/arch/arm/mach-omap2/smartreflex.c | ||
86 | +++ b/arch/arm/mach-omap2/smartreflex.c | ||
87 | @@ -3,6 +3,9 @@ | ||
88 | * | ||
89 | * OMAP34XX SmartReflex Voltage Control | ||
90 | * | ||
91 | + * Copyright (C) 2008 Nokia Corporation | ||
92 | + * Kalle Jokiniemi | ||
93 | + * | ||
94 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
95 | * Lesly A M <x0080970@ti.com> | ||
96 | * | ||
97 | @@ -20,13 +23,16 @@ | ||
98 | #include <linux/err.h> | ||
99 | #include <linux/clk.h> | ||
100 | #include <linux/sysfs.h> | ||
101 | - | ||
102 | -#include <asm/arch/prcm.h> | ||
103 | -#include <asm/arch/power_companion.h> | ||
104 | +#include <linux/kobject.h> | ||
105 | +#include <linux/i2c/twl4030.h> | ||
106 | #include <linux/io.h> | ||
107 | |||
108 | -#include "prcm-regs.h" | ||
109 | +#include <asm/arch/omap34xx.h> | ||
110 | +#include <asm/arch/control.h> | ||
111 | + | ||
112 | +#include "prm.h" | ||
113 | #include "smartreflex.h" | ||
114 | +#include "prm-regbits-34xx.h" | ||
115 | |||
116 | |||
117 | /* #define DEBUG_SR 1 */ | ||
118 | @@ -37,11 +43,16 @@ | ||
119 | # define DPRINTK(fmt, args...) | ||
120 | #endif | ||
121 | |||
122 | +/* XXX: These should be relocated where-ever the OPP implementation will be */ | ||
123 | +u32 current_vdd1_opp; | ||
124 | +u32 current_vdd2_opp; | ||
125 | + | ||
126 | struct omap_sr{ | ||
127 | int srid; | ||
128 | int is_sr_reset; | ||
129 | int is_autocomp_active; | ||
130 | struct clk *fck; | ||
131 | + u32 clk_length; | ||
132 | u32 req_opp_no; | ||
133 | u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue; | ||
134 | u32 senp_mod, senn_mod; | ||
135 | @@ -53,6 +64,7 @@ static struct omap_sr sr1 = { | ||
136 | .srid = SR1, | ||
137 | .is_sr_reset = 1, | ||
138 | .is_autocomp_active = 0, | ||
139 | + .clk_length = 0, | ||
140 | .srbase_addr = OMAP34XX_SR1_BASE, | ||
141 | }; | ||
142 | |||
143 | @@ -60,6 +72,7 @@ static struct omap_sr sr2 = { | ||
144 | .srid = SR2, | ||
145 | .is_sr_reset = 1, | ||
146 | .is_autocomp_active = 0, | ||
147 | + .clk_length = 0, | ||
148 | .srbase_addr = OMAP34XX_SR2_BASE, | ||
149 | }; | ||
150 | |||
151 | @@ -85,8 +98,6 @@ static inline u32 sr_read_reg(struct omap_sr *sr, int offset) | ||
152 | return omap_readl(sr->srbase_addr + offset); | ||
153 | } | ||
154 | |||
155 | - | ||
156 | -#ifndef USE_EFUSE_VALUES | ||
157 | static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen) | ||
158 | { | ||
159 | u32 gn, rn, mul; | ||
160 | @@ -100,7 +111,21 @@ static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen) | ||
161 | } | ||
162 | } | ||
163 | } | ||
164 | -#endif | ||
165 | + | ||
166 | +static void sr_clk_get(struct omap_sr *sr) | ||
167 | +{ | ||
168 | + if (sr->srid == SR1) { | ||
169 | + sr->fck = clk_get(NULL, "sr1_fck"); | ||
170 | + if (IS_ERR(sr->fck)) | ||
171 | + printk(KERN_ERR "Could not get sr1_fck\n"); | ||
172 | + | ||
173 | + } else if (sr->srid == SR2) { | ||
174 | + sr->fck = clk_get(NULL, "sr2_fck"); | ||
175 | + if (IS_ERR(sr->fck)) | ||
176 | + printk(KERN_ERR "Could not get sr2_fck\n"); | ||
177 | + | ||
178 | + } | ||
179 | +} | ||
180 | |||
181 | static int sr_clk_enable(struct omap_sr *sr) | ||
182 | { | ||
183 | @@ -131,22 +156,86 @@ static int sr_clk_disable(struct omap_sr *sr) | ||
184 | return 0; | ||
185 | } | ||
186 | |||
187 | -static void sr_set_nvalues(struct omap_sr *sr) | ||
188 | +static void sr_set_clk_length(struct omap_sr *sr) | ||
189 | +{ | ||
190 | + struct clk *osc_sys_ck; | ||
191 | + u32 sys_clk = 0; | ||
192 | + | ||
193 | + osc_sys_ck = clk_get(NULL, "osc_sys_ck"); | ||
194 | + sys_clk = clk_get_rate(osc_sys_ck); | ||
195 | + clk_put(osc_sys_ck); | ||
196 | + | ||
197 | + switch (sys_clk) { | ||
198 | + case 12000000: | ||
199 | + sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK; | ||
200 | + break; | ||
201 | + case 13000000: | ||
202 | + sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK; | ||
203 | + break; | ||
204 | + case 19200000: | ||
205 | + sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK; | ||
206 | + break; | ||
207 | + case 26000000: | ||
208 | + sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK; | ||
209 | + break; | ||
210 | + case 38400000: | ||
211 | + sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK; | ||
212 | + break; | ||
213 | + default : | ||
214 | + printk(KERN_ERR "Invalid sysclk value: %d\n", sys_clk); | ||
215 | + break; | ||
216 | + } | ||
217 | +} | ||
218 | + | ||
219 | +static void sr_set_efuse_nvalues(struct omap_sr *sr) | ||
220 | +{ | ||
221 | + if (sr->srid == SR1) { | ||
222 | + sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & | ||
223 | + OMAP343X_SR1_SENNENABLE_MASK) >> | ||
224 | + OMAP343X_SR1_SENNENABLE_SHIFT; | ||
225 | + | ||
226 | + sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & | ||
227 | + OMAP343X_SR1_SENPENABLE_MASK) >> | ||
228 | + OMAP343X_SR1_SENPENABLE_SHIFT; | ||
229 | + | ||
230 | + sr->opp5_nvalue = omap_ctrl_readl( | ||
231 | + OMAP343X_CONTROL_FUSE_OPP5_VDD1); | ||
232 | + sr->opp4_nvalue = omap_ctrl_readl( | ||
233 | + OMAP343X_CONTROL_FUSE_OPP4_VDD1); | ||
234 | + sr->opp3_nvalue = omap_ctrl_readl( | ||
235 | + OMAP343X_CONTROL_FUSE_OPP3_VDD1); | ||
236 | + sr->opp2_nvalue = omap_ctrl_readl( | ||
237 | + OMAP343X_CONTROL_FUSE_OPP2_VDD1); | ||
238 | + sr->opp1_nvalue = omap_ctrl_readl( | ||
239 | + OMAP343X_CONTROL_FUSE_OPP1_VDD1); | ||
240 | + } else if (sr->srid == SR2) { | ||
241 | + sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & | ||
242 | + OMAP343X_SR2_SENNENABLE_MASK) >> | ||
243 | + OMAP343X_SR2_SENNENABLE_SHIFT; | ||
244 | + | ||
245 | + sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & | ||
246 | + OMAP343X_SR2_SENPENABLE_MASK) >> | ||
247 | + OMAP343X_SR2_SENPENABLE_SHIFT; | ||
248 | + | ||
249 | + sr->opp3_nvalue = omap_ctrl_readl( | ||
250 | + OMAP343X_CONTROL_FUSE_OPP3_VDD2); | ||
251 | + sr->opp2_nvalue = omap_ctrl_readl( | ||
252 | + OMAP343X_CONTROL_FUSE_OPP2_VDD2); | ||
253 | + sr->opp1_nvalue = omap_ctrl_readl( | ||
254 | + OMAP343X_CONTROL_FUSE_OPP1_VDD2); | ||
255 | + } | ||
256 | +} | ||
257 | + | ||
258 | +/* Hard coded nvalues for testing purposes, may cause device to hang! */ | ||
259 | +static void sr_set_testing_nvalues(struct omap_sr *sr) | ||
260 | { | ||
261 | -#ifdef USE_EFUSE_VALUES | ||
262 | - u32 n1, n2; | ||
263 | -#else | ||
264 | u32 senpval, sennval; | ||
265 | u32 senpgain, senngain; | ||
266 | u32 rnsenp, rnsenn; | ||
267 | -#endif | ||
268 | |||
269 | if (sr->srid == SR1) { | ||
270 | -#ifdef USE_EFUSE_VALUES | ||
271 | - /* Read values for VDD1 from EFUSE */ | ||
272 | -#else | ||
273 | - /* since E-Fuse Values are not available, calculating the | ||
274 | - * reciprocal of the SenN and SenP values for SR1 | ||
275 | + /* Calculating the reciprocal of the SenN and SenP values | ||
276 | + * for SR1 | ||
277 | */ | ||
278 | sr->senp_mod = 0x03; /* SenN-M5 enabled */ | ||
279 | sr->senn_mod = 0x03; | ||
280 | @@ -216,15 +305,16 @@ static void sr_set_nvalues(struct omap_sr *sr) | ||
281 | (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | | ||
282 | (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); | ||
283 | |||
284 | + /* XXX The clocks are enabled in the startup and NVALUE is | ||
285 | + * set also there. Disabling this for now, but this could | ||
286 | + * be related to dynamic sleep during boot */ | ||
287 | +#if 0 | ||
288 | sr_clk_enable(sr); | ||
289 | sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue); | ||
290 | sr_clk_disable(sr); | ||
291 | - | ||
292 | #endif | ||
293 | + | ||
294 | } else if (sr->srid == SR2) { | ||
295 | -#ifdef USE_EFUSE_VALUES | ||
296 | - /* Read values for VDD2 from EFUSE */ | ||
297 | -#else | ||
298 | /* since E-Fuse Values are not available, calculating the | ||
299 | * reciprocal of the SenN and SenP values for SR2 | ||
300 | */ | ||
301 | @@ -269,134 +359,163 @@ static void sr_set_nvalues(struct omap_sr *sr) | ||
302 | (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | | ||
303 | (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | | ||
304 | (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); | ||
305 | - | ||
306 | -#endif | ||
307 | } | ||
308 | |||
309 | } | ||
310 | |||
311 | +static void sr_set_nvalues(struct omap_sr *sr) | ||
312 | +{ | ||
313 | + if (SR_TESTING_NVALUES) | ||
314 | + sr_set_testing_nvalues(sr); | ||
315 | + else | ||
316 | + sr_set_efuse_nvalues(sr); | ||
317 | +} | ||
318 | + | ||
319 | static void sr_configure_vp(int srid) | ||
320 | { | ||
321 | u32 vpconfig; | ||
322 | |||
323 | if (srid == SR1) { | ||
324 | vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN | ||
325 | - | PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN; | ||
326 | - | ||
327 | - PRM_VP1_CONFIG = vpconfig; | ||
328 | - PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN | | ||
329 | - PRM_VP1_VSTEPMIN_VSTEPMIN; | ||
330 | - | ||
331 | - PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX | | ||
332 | - PRM_VP1_VSTEPMAX_VSTEPMAX; | ||
333 | - | ||
334 | - PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX | | ||
335 | - PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT; | ||
336 | - | ||
337 | - PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD; | ||
338 | - PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD; | ||
339 | + | PRM_VP1_CONFIG_INITVOLTAGE | ||
340 | + | PRM_VP1_CONFIG_TIMEOUTEN; | ||
341 | + | ||
342 | + prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD, | ||
343 | + OMAP3_PRM_VP1_CONFIG_OFFSET); | ||
344 | + prm_write_mod_reg(PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN | | ||
345 | + PRM_VP1_VSTEPMIN_VSTEPMIN, | ||
346 | + OMAP3430_GR_MOD, | ||
347 | + OMAP3_PRM_VP1_VSTEPMIN_OFFSET); | ||
348 | + | ||
349 | + prm_write_mod_reg(PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX | | ||
350 | + PRM_VP1_VSTEPMAX_VSTEPMAX, | ||
351 | + OMAP3430_GR_MOD, | ||
352 | + OMAP3_PRM_VP1_VSTEPMAX_OFFSET); | ||
353 | + | ||
354 | + prm_write_mod_reg(PRM_VP1_VLIMITTO_VDDMAX | | ||
355 | + PRM_VP1_VLIMITTO_VDDMIN | | ||
356 | + PRM_VP1_VLIMITTO_TIMEOUT, | ||
357 | + OMAP3430_GR_MOD, | ||
358 | + OMAP3_PRM_VP1_VLIMITTO_OFFSET); | ||
359 | + | ||
360 | + /* Trigger initVDD value copy to voltage processor */ | ||
361 | + prm_set_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD, | ||
362 | + OMAP3_PRM_VP1_CONFIG_OFFSET); | ||
363 | + /* Clear initVDD copy trigger bit */ | ||
364 | + prm_clear_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD, | ||
365 | + OMAP3_PRM_VP1_CONFIG_OFFSET); | ||
366 | |||
367 | } else if (srid == SR2) { | ||
368 | vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN | ||
369 | - | PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN; | ||
370 | - | ||
371 | - PRM_VP2_CONFIG = vpconfig; | ||
372 | - PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN | | ||
373 | - PRM_VP2_VSTEPMIN_VSTEPMIN; | ||
374 | - | ||
375 | - PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX | | ||
376 | - PRM_VP2_VSTEPMAX_VSTEPMAX; | ||
377 | - | ||
378 | - PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX | | ||
379 | - PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT; | ||
380 | - | ||
381 | - PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD; | ||
382 | - PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD; | ||
383 | + | PRM_VP2_CONFIG_INITVOLTAGE | ||
384 | + | PRM_VP2_CONFIG_TIMEOUTEN; | ||
385 | + | ||
386 | + prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD, | ||
387 | + OMAP3_PRM_VP2_CONFIG_OFFSET); | ||
388 | + prm_write_mod_reg(PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN | | ||
389 | + PRM_VP2_VSTEPMIN_VSTEPMIN, | ||
390 | + OMAP3430_GR_MOD, | ||
391 | + OMAP3_PRM_VP2_VSTEPMIN_OFFSET); | ||
392 | + | ||
393 | + prm_write_mod_reg(PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX | | ||
394 | + PRM_VP2_VSTEPMAX_VSTEPMAX, | ||
395 | + OMAP3430_GR_MOD, | ||
396 | + OMAP3_PRM_VP2_VSTEPMAX_OFFSET); | ||
397 | + | ||
398 | + prm_write_mod_reg(PRM_VP2_VLIMITTO_VDDMAX | | ||
399 | + PRM_VP2_VLIMITTO_VDDMIN | | ||
400 | + PRM_VP2_VLIMITTO_TIMEOUT, | ||
401 | + OMAP3430_GR_MOD, | ||
402 | + OMAP3_PRM_VP2_VLIMITTO_OFFSET); | ||
403 | + | ||
404 | + /* Trigger initVDD value copy to voltage processor */ | ||
405 | + prm_set_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD, | ||
406 | + OMAP3_PRM_VP2_CONFIG_OFFSET); | ||
407 | + /* Reset initVDD copy trigger bit */ | ||
408 | + prm_clear_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD, | ||
409 | + OMAP3_PRM_VP2_CONFIG_OFFSET); | ||
410 | |||
411 | } | ||
412 | } | ||
413 | |||
414 | static void sr_configure_vc(void) | ||
415 | { | ||
416 | - PRM_VC_SMPS_SA = | ||
417 | - (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) | | ||
418 | - (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT); | ||
419 | - | ||
420 | - PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) | | ||
421 | - (R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT); | ||
422 | - | ||
423 | - PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) | | ||
424 | - (PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) | | ||
425 | - (PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) | | ||
426 | - (PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT); | ||
427 | - | ||
428 | - PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) | | ||
429 | - (PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) | | ||
430 | - (PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) | | ||
431 | - (PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT); | ||
432 | - | ||
433 | - PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1; | ||
434 | - | ||
435 | - PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN | ||
436 | - | PRM_VC_I2C_CFG_SREN; | ||
437 | + prm_write_mod_reg((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) | | ||
438 | + (R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT), | ||
439 | + OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET); | ||
440 | + | ||
441 | + prm_write_mod_reg((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) | | ||
442 | + (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT), | ||
443 | + OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET); | ||
444 | + | ||
445 | + prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON << | ||
446 | + OMAP3430_VC_CMD_ON_SHIFT) | | ||
447 | + (OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) | | ||
448 | + (OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) | | ||
449 | + (OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT), | ||
450 | + OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET); | ||
451 | + | ||
452 | + prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON << | ||
453 | + OMAP3430_VC_CMD_ON_SHIFT) | | ||
454 | + (OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) | | ||
455 | + (OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) | | ||
456 | + (OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT), | ||
457 | + OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET); | ||
458 | + | ||
459 | + prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1, | ||
460 | + OMAP3430_GR_MOD, | ||
461 | + OMAP3_PRM_VC_CH_CONF_OFFSET); | ||
462 | + | ||
463 | + prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN, | ||
464 | + OMAP3430_GR_MOD, | ||
465 | + OMAP3_PRM_VC_I2C_CFG_OFFSET); | ||
466 | |||
467 | /* Setup voltctrl and other setup times */ | ||
468 | + /* XXX CONFIG_SYSOFFMODE has not been implemented yet */ | ||
469 | #ifdef CONFIG_SYSOFFMODE | ||
470 | - PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET; | ||
471 | - PRM_CLKSETUP = PRM_CLKSETUP_DURATION; | ||
472 | - PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) | | ||
473 | - (PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET); | ||
474 | - PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION; | ||
475 | - PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION; | ||
476 | + prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET, | ||
477 | + OMAP3430_GR_MOD, | ||
478 | + OMAP3_PRM_VOLTCTRL_OFFSET); | ||
479 | + | ||
480 | + prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD, | ||
481 | + OMAP3_PRM_CLKSETUP_OFFSET); | ||
482 | + prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 << | ||
483 | + OMAP3430_VOLTSETUP_TIME2_OFFSET) | | ||
484 | + (OMAP3430_VOLTSETUP_TIME1 << | ||
485 | + OMAP3430_VOLTSETUP_TIME1_OFFSET), | ||
486 | + OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET); | ||
487 | + | ||
488 | + prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD, | ||
489 | + OMAP3_PRM_VOLTOFFSET_OFFSET); | ||
490 | + prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD, | ||
491 | + OMAP3_PRM_VOLTSETUP2_OFFSET); | ||
492 | #else | ||
493 | - PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET; | ||
494 | + prm_set_mod_reg_bits(OMAP3430_AUTO_RET, OMAP3430_GR_MOD, | ||
495 | + OMAP3_PRM_VOLTCTRL_OFFSET); | ||
496 | #endif | ||
497 | |||
498 | } | ||
499 | |||
500 | - | ||
501 | static void sr_configure(struct omap_sr *sr) | ||
502 | { | ||
503 | - u32 sys_clk, sr_clk_length = 0; | ||
504 | u32 sr_config; | ||
505 | u32 senp_en , senn_en; | ||
506 | |||
507 | + if (sr->clk_length == 0) | ||
508 | + sr_set_clk_length(sr); | ||
509 | + | ||
510 | senp_en = sr->senp_mod; | ||
511 | senn_en = sr->senn_mod; | ||
512 | - | ||
513 | - sys_clk = prcm_get_system_clock_speed(); | ||
514 | - | ||
515 | - switch (sys_clk) { | ||
516 | - case 12000: | ||
517 | - sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK; | ||
518 | - break; | ||
519 | - case 13000: | ||
520 | - sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK; | ||
521 | - break; | ||
522 | - case 19200: | ||
523 | - sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK; | ||
524 | - break; | ||
525 | - case 26000: | ||
526 | - sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK; | ||
527 | - break; | ||
528 | - case 38400: | ||
529 | - sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK; | ||
530 | - break; | ||
531 | - default : | ||
532 | - printk(KERN_ERR "Invalid sysclk value\n"); | ||
533 | - break; | ||
534 | - } | ||
535 | - | ||
536 | - DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk); | ||
537 | if (sr->srid == SR1) { | ||
538 | sr_config = SR1_SRCONFIG_ACCUMDATA | | ||
539 | - (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | | ||
540 | + (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | | ||
541 | SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN | | ||
542 | SRCONFIG_MINMAXAVG_EN | | ||
543 | (senn_en << SRCONFIG_SENNENABLE_SHIFT) | | ||
544 | (senp_en << SRCONFIG_SENPENABLE_SHIFT) | | ||
545 | SRCONFIG_DELAYCTRL; | ||
546 | - | ||
547 | + DPRINTK(KERN_DEBUG "setting SRCONFIG1 to 0x%08lx\n", | ||
548 | + (unsigned long int) sr_config); | ||
549 | sr_write_reg(sr, SRCONFIG, sr_config); | ||
550 | |||
551 | sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT | | ||
552 | @@ -408,18 +527,18 @@ static void sr_configure(struct omap_sr *sr) | ||
553 | |||
554 | } else if (sr->srid == SR2) { | ||
555 | sr_config = SR2_SRCONFIG_ACCUMDATA | | ||
556 | - (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | | ||
557 | + (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | | ||
558 | SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN | | ||
559 | SRCONFIG_MINMAXAVG_EN | | ||
560 | (senn_en << SRCONFIG_SENNENABLE_SHIFT) | | ||
561 | (senp_en << SRCONFIG_SENPENABLE_SHIFT) | | ||
562 | SRCONFIG_DELAYCTRL; | ||
563 | |||
564 | + DPRINTK(KERN_DEBUG "setting SRCONFIG2 to 0x%08lx\n", | ||
565 | + (unsigned long int) sr_config); | ||
566 | sr_write_reg(sr, SRCONFIG, sr_config); | ||
567 | - | ||
568 | sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT | | ||
569 | SR2_AVGWEIGHT_SENNAVGWEIGHT); | ||
570 | - | ||
571 | sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK | | ||
572 | SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), | ||
573 | (SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT)); | ||
574 | @@ -428,9 +547,9 @@ static void sr_configure(struct omap_sr *sr) | ||
575 | sr->is_sr_reset = 0; | ||
576 | } | ||
577 | |||
578 | -static void sr_enable(struct omap_sr *sr, u32 target_opp_no) | ||
579 | +static int sr_enable(struct omap_sr *sr, u32 target_opp_no) | ||
580 | { | ||
581 | - u32 nvalue_reciprocal, current_nvalue; | ||
582 | + u32 nvalue_reciprocal; | ||
583 | |||
584 | sr->req_opp_no = target_opp_no; | ||
585 | |||
586 | @@ -472,11 +591,10 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no) | ||
587 | } | ||
588 | } | ||
589 | |||
590 | - current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL); | ||
591 | - | ||
592 | - if (current_nvalue == nvalue_reciprocal) { | ||
593 | - DPRINTK("System is already at the desired voltage level\n"); | ||
594 | - return; | ||
595 | + if (nvalue_reciprocal == 0) { | ||
596 | + printk(KERN_NOTICE "OPP%d doesn't support SmartReflex\n", | ||
597 | + target_opp_no); | ||
598 | + return SR_FALSE; | ||
599 | } | ||
600 | |||
601 | sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal); | ||
602 | @@ -485,18 +603,19 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no) | ||
603 | sr_modify_reg(sr, ERRCONFIG, | ||
604 | (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST), | ||
605 | (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST)); | ||
606 | - | ||
607 | if (sr->srid == SR1) { | ||
608 | /* Enable VP1 */ | ||
609 | - PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE; | ||
610 | + prm_set_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD, | ||
611 | + OMAP3_PRM_VP1_CONFIG_OFFSET); | ||
612 | } else if (sr->srid == SR2) { | ||
613 | /* Enable VP2 */ | ||
614 | - PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE; | ||
615 | + prm_set_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD, | ||
616 | + OMAP3_PRM_VP2_CONFIG_OFFSET); | ||
617 | } | ||
618 | |||
619 | /* SRCONFIG - enable SR */ | ||
620 | sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE); | ||
621 | - | ||
622 | + return SR_TRUE; | ||
623 | } | ||
624 | |||
625 | static void sr_disable(struct omap_sr *sr) | ||
626 | @@ -507,11 +626,13 @@ static void sr_disable(struct omap_sr *sr) | ||
627 | sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE); | ||
628 | |||
629 | if (sr->srid == SR1) { | ||
630 | - /* Enable VP1 */ | ||
631 | - PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE; | ||
632 | + /* Disable VP1 */ | ||
633 | + prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD, | ||
634 | + OMAP3_PRM_VP1_CONFIG_OFFSET); | ||
635 | } else if (sr->srid == SR2) { | ||
636 | - /* Enable VP2 */ | ||
637 | - PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE; | ||
638 | + /* Disable VP2 */ | ||
639 | + prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD, | ||
640 | + OMAP3_PRM_VP2_CONFIG_OFFSET); | ||
641 | } | ||
642 | } | ||
643 | |||
644 | @@ -535,7 +656,12 @@ void sr_start_vddautocomap(int srid, u32 target_opp_no) | ||
645 | srid); | ||
646 | |||
647 | sr->is_autocomp_active = 1; | ||
648 | - sr_enable(sr, target_opp_no); | ||
649 | + if (!sr_enable(sr, target_opp_no)) { | ||
650 | + printk(KERN_WARNING "SR%d: VDD autocomp not activated\n", srid); | ||
651 | + sr->is_autocomp_active = 0; | ||
652 | + if (sr->is_sr_reset == 1) | ||
653 | + sr_clk_disable(sr); | ||
654 | + } | ||
655 | } | ||
656 | EXPORT_SYMBOL(sr_start_vddautocomap); | ||
657 | |||
658 | @@ -574,20 +700,18 @@ void enable_smartreflex(int srid) | ||
659 | |||
660 | if (sr->is_autocomp_active == 1) { | ||
661 | if (sr->is_sr_reset == 1) { | ||
662 | - if (srid == SR1) { | ||
663 | - /* Enable SR clks */ | ||
664 | - CM_FCLKEN_WKUP |= SR1_CLK_ENABLE; | ||
665 | - target_opp_no = get_opp_no(current_vdd1_opp); | ||
666 | + /* Enable SR clks */ | ||
667 | + sr_clk_enable(sr); | ||
668 | |||
669 | - } else if (srid == SR2) { | ||
670 | - /* Enable SR clks */ | ||
671 | - CM_FCLKEN_WKUP |= SR2_CLK_ENABLE; | ||
672 | + if (srid == SR1) | ||
673 | + target_opp_no = get_opp_no(current_vdd1_opp); | ||
674 | + else if (srid == SR2) | ||
675 | target_opp_no = get_opp_no(current_vdd2_opp); | ||
676 | - } | ||
677 | |||
678 | sr_configure(sr); | ||
679 | |||
680 | - sr_enable(sr, target_opp_no); | ||
681 | + if (!sr_enable(sr, target_opp_no)) | ||
682 | + sr_clk_disable(sr); | ||
683 | } | ||
684 | } | ||
685 | } | ||
686 | @@ -602,15 +726,6 @@ void disable_smartreflex(int srid) | ||
687 | sr = &sr2; | ||
688 | |||
689 | if (sr->is_autocomp_active == 1) { | ||
690 | - if (srid == SR1) { | ||
691 | - /* Enable SR clk */ | ||
692 | - CM_FCLKEN_WKUP |= SR1_CLK_ENABLE; | ||
693 | - | ||
694 | - } else if (srid == SR2) { | ||
695 | - /* Enable SR clk */ | ||
696 | - CM_FCLKEN_WKUP |= SR2_CLK_ENABLE; | ||
697 | - } | ||
698 | - | ||
699 | if (sr->is_sr_reset == 0) { | ||
700 | |||
701 | sr->is_sr_reset = 1; | ||
702 | @@ -618,17 +733,18 @@ void disable_smartreflex(int srid) | ||
703 | sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, | ||
704 | ~SRCONFIG_SRENABLE); | ||
705 | |||
706 | + /* Disable SR clk */ | ||
707 | + sr_clk_disable(sr); | ||
708 | if (sr->srid == SR1) { | ||
709 | - /* Disable SR clk */ | ||
710 | - CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE; | ||
711 | - /* Enable VP1 */ | ||
712 | - PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE; | ||
713 | - | ||
714 | + /* Disable VP1 */ | ||
715 | + prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, | ||
716 | + OMAP3430_GR_MOD, | ||
717 | + OMAP3_PRM_VP1_CONFIG_OFFSET); | ||
718 | } else if (sr->srid == SR2) { | ||
719 | - /* Disable SR clk */ | ||
720 | - CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE; | ||
721 | - /* Enable VP2 */ | ||
722 | - PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE; | ||
723 | + /* Disable VP2 */ | ||
724 | + prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, | ||
725 | + OMAP3430_GR_MOD, | ||
726 | + OMAP3_PRM_VP2_CONFIG_OFFSET); | ||
727 | } | ||
728 | } | ||
729 | } | ||
730 | @@ -638,7 +754,6 @@ void disable_smartreflex(int srid) | ||
731 | /* Voltage Scaling using SR VCBYPASS */ | ||
732 | int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel) | ||
733 | { | ||
734 | - int ret; | ||
735 | int sr_status = 0; | ||
736 | u32 vdd, target_opp_no; | ||
737 | u32 vc_bypass_value; | ||
738 | @@ -651,39 +766,53 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel) | ||
739 | if (vdd == PRCM_VDD1) { | ||
740 | sr_status = sr_stop_vddautocomap(SR1); | ||
741 | |||
742 | - PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) | | ||
743 | - (vsel << PRM_VC_CMD_ON_SHIFT); | ||
744 | + prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK, | ||
745 | + (vsel << OMAP3430_VC_CMD_ON_SHIFT), | ||
746 | + OMAP3430_GR_MOD, | ||
747 | + OMAP3_PRM_VC_CMD_VAL_0_OFFSET); | ||
748 | reg_addr = R_VDD1_SR_CONTROL; | ||
749 | |||
750 | } else if (vdd == PRCM_VDD2) { | ||
751 | sr_status = sr_stop_vddautocomap(SR2); | ||
752 | |||
753 | - PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) | | ||
754 | - (vsel << PRM_VC_CMD_ON_SHIFT); | ||
755 | + prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK, | ||
756 | + (vsel << OMAP3430_VC_CMD_ON_SHIFT), | ||
757 | + OMAP3430_GR_MOD, | ||
758 | + OMAP3_PRM_VC_CMD_VAL_1_OFFSET); | ||
759 | reg_addr = R_VDD2_SR_CONTROL; | ||
760 | } | ||
761 | |||
762 | - vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) | | ||
763 | - (reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) | | ||
764 | - (R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT); | ||
765 | + vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) | | ||
766 | + (reg_addr << OMAP3430_REGADDR_SHIFT) | | ||
767 | + (R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT); | ||
768 | |||
769 | - PRM_VC_BYPASS_VAL = vc_bypass_value; | ||
770 | + prm_write_mod_reg(vc_bypass_value, OMAP3430_GR_MOD, | ||
771 | + OMAP3_PRM_VC_BYPASS_VAL_OFFSET); | ||
772 | |||
773 | - PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID; | ||
774 | + vc_bypass_value = prm_set_mod_reg_bits(OMAP3430_VALID, OMAP3430_GR_MOD, | ||
775 | + OMAP3_PRM_VC_BYPASS_VAL_OFFSET); | ||
776 | |||
777 | - DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL); | ||
778 | - DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU); | ||
779 | + DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, vc_bypass_value); | ||
780 | + DPRINTK("PRM_IRQST_MPU %X\n", prm_read_mod_reg(OCP_MOD, | ||
781 | + OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); | ||
782 | |||
783 | - while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) { | ||
784 | - ret = loop_wait(&loop_cnt, &retries_cnt, 10); | ||
785 | - if (ret != PRCM_PASS) { | ||
786 | + while ((vc_bypass_value & OMAP3430_VALID) != 0x0) { | ||
787 | + loop_cnt++; | ||
788 | + if (retries_cnt > 10) { | ||
789 | printk(KERN_INFO "Loop count exceeded in check SR I2C" | ||
790 | "write\n"); | ||
791 | - return ret; | ||
792 | + return SR_FAIL; | ||
793 | + } | ||
794 | + if (loop_cnt > 50) { | ||
795 | + retries_cnt++; | ||
796 | + loop_cnt = 0; | ||
797 | + udelay(10); | ||
798 | } | ||
799 | + vc_bypass_value = prm_read_mod_reg(OMAP3430_GR_MOD, | ||
800 | + OMAP3_PRM_VC_BYPASS_VAL_OFFSET); | ||
801 | } | ||
802 | |||
803 | - omap_udelay(T2_SMPS_UPDATE_DELAY); | ||
804 | + udelay(T2_SMPS_UPDATE_DELAY); | ||
805 | |||
806 | if (sr_status) { | ||
807 | if (vdd == PRCM_VDD1) | ||
808 | @@ -696,13 +825,15 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel) | ||
809 | } | ||
810 | |||
811 | /* Sysfs interface to select SR VDD1 auto compensation */ | ||
812 | -static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf) | ||
813 | +static ssize_t omap_sr_vdd1_autocomp_show(struct kobject *kobj, | ||
814 | + struct kobj_attribute *attr, char *buf) | ||
815 | { | ||
816 | return sprintf(buf, "%d\n", sr1.is_autocomp_active); | ||
817 | } | ||
818 | |||
819 | -static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys, | ||
820 | - const char *buf, size_t n) | ||
821 | +static ssize_t omap_sr_vdd1_autocomp_store(struct kobject *kobj, | ||
822 | + struct kobj_attribute *attr, | ||
823 | + const char *buf, size_t n) | ||
824 | { | ||
825 | u32 current_vdd1opp_no; | ||
826 | unsigned short value; | ||
827 | @@ -722,7 +853,7 @@ static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys, | ||
828 | return n; | ||
829 | } | ||
830 | |||
831 | -static struct subsys_attribute sr_vdd1_autocomp = { | ||
832 | +static struct kobj_attribute sr_vdd1_autocomp = { | ||
833 | .attr = { | ||
834 | .name = __stringify(sr_vdd1_autocomp), | ||
835 | .mode = 0644, | ||
836 | @@ -732,13 +863,15 @@ static struct subsys_attribute sr_vdd1_autocomp = { | ||
837 | }; | ||
838 | |||
839 | /* Sysfs interface to select SR VDD2 auto compensation */ | ||
840 | -static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf) | ||
841 | +static ssize_t omap_sr_vdd2_autocomp_show(struct kobject *kobj, | ||
842 | + struct kobj_attribute *attr, char *buf) | ||
843 | { | ||
844 | return sprintf(buf, "%d\n", sr2.is_autocomp_active); | ||
845 | } | ||
846 | |||
847 | -static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys, | ||
848 | - const char *buf, size_t n) | ||
849 | +static ssize_t omap_sr_vdd2_autocomp_store(struct kobject *kobj, | ||
850 | + struct kobj_attribute *attr, | ||
851 | + const char *buf, size_t n) | ||
852 | { | ||
853 | u32 current_vdd2opp_no; | ||
854 | unsigned short value; | ||
855 | @@ -758,7 +891,7 @@ static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys, | ||
856 | return n; | ||
857 | } | ||
858 | |||
859 | -static struct subsys_attribute sr_vdd2_autocomp = { | ||
860 | +static struct kobj_attribute sr_vdd2_autocomp = { | ||
861 | .attr = { | ||
862 | .name = __stringify(sr_vdd2_autocomp), | ||
863 | .mode = 0644, | ||
864 | @@ -774,15 +907,19 @@ static int __init omap3_sr_init(void) | ||
865 | int ret = 0; | ||
866 | u8 RdReg; | ||
867 | |||
868 | -#ifdef CONFIG_ARCH_OMAP34XX | ||
869 | - sr1.fck = clk_get(NULL, "sr1_fck"); | ||
870 | - if (IS_ERR(sr1.fck)) | ||
871 | - printk(KERN_ERR "Could not get sr1_fck\n"); | ||
872 | - | ||
873 | - sr2.fck = clk_get(NULL, "sr2_fck"); | ||
874 | - if (IS_ERR(sr2.fck)) | ||
875 | - printk(KERN_ERR "Could not get sr2_fck\n"); | ||
876 | -#endif /* #ifdef CONFIG_ARCH_OMAP34XX */ | ||
877 | + if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) { | ||
878 | + current_vdd1_opp = PRCM_VDD1_OPP3; | ||
879 | + current_vdd2_opp = PRCM_VDD2_OPP3; | ||
880 | + } else { | ||
881 | + current_vdd1_opp = PRCM_VDD1_OPP1; | ||
882 | + current_vdd2_opp = PRCM_VDD1_OPP1; | ||
883 | + } | ||
884 | + if (cpu_is_omap34xx()) { | ||
885 | + sr_clk_get(&sr1); | ||
886 | + sr_clk_get(&sr2); | ||
887 | + } | ||
888 | + sr_set_clk_length(&sr1); | ||
889 | + sr_set_clk_length(&sr2); | ||
890 | |||
891 | /* Call the VPConfig, VCConfig, set N Values. */ | ||
892 | sr_set_nvalues(&sr1); | ||
893 | @@ -794,22 +931,24 @@ static int __init omap3_sr_init(void) | ||
894 | sr_configure_vc(); | ||
895 | |||
896 | /* Enable SR on T2 */ | ||
897 | - ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG); | ||
898 | - RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX; | ||
899 | - ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG); | ||
900 | + ret = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &RdReg, | ||
901 | + R_DCDC_GLOBAL_CFG); | ||
902 | |||
903 | + RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX; | ||
904 | + ret |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, RdReg, | ||
905 | + R_DCDC_GLOBAL_CFG); | ||
906 | |||
907 | printk(KERN_INFO "SmartReflex driver initialized\n"); | ||
908 | |||
909 | - ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp); | ||
910 | + ret = sysfs_create_file(power_kobj, &sr_vdd1_autocomp.attr); | ||
911 | if (ret) | ||
912 | - printk(KERN_ERR "subsys_create_file failed: %d\n", ret); | ||
913 | + printk(KERN_ERR "sysfs_create_file failed: %d\n", ret); | ||
914 | |||
915 | - ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp); | ||
916 | + ret = sysfs_create_file(power_kobj, &sr_vdd2_autocomp.attr); | ||
917 | if (ret) | ||
918 | - printk(KERN_ERR "subsys_create_file failed: %d\n", ret); | ||
919 | + printk(KERN_ERR "sysfs_create_file failed: %d\n", ret); | ||
920 | |||
921 | return 0; | ||
922 | } | ||
923 | |||
924 | -arch_initcall(omap3_sr_init); | ||
925 | +late_initcall(omap3_sr_init); | ||
926 | diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h | ||
927 | index 2091a15..194429e 100644 | ||
928 | --- a/arch/arm/mach-omap2/smartreflex.h | ||
929 | +++ b/arch/arm/mach-omap2/smartreflex.h | ||
930 | @@ -233,12 +233,18 @@ | ||
931 | extern u32 current_vdd1_opp; | ||
932 | extern u32 current_vdd2_opp; | ||
933 | |||
934 | +#ifdef CONFIG_OMAP_SMARTREFLEX_TESTING | ||
935 | +#define SR_TESTING_NVALUES 1 | ||
936 | +#else | ||
937 | +#define SR_TESTING_NVALUES 0 | ||
938 | +#endif | ||
939 | + | ||
940 | /* | ||
941 | * Smartreflex module enable/disable interface. | ||
942 | * NOTE: if smartreflex is not enabled from sysfs, these functions will not | ||
943 | * do anything. | ||
944 | */ | ||
945 | -#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE) | ||
946 | +#ifdef CONFIG_OMAP_SMARTREFLEX | ||
947 | void enable_smartreflex(int srid); | ||
948 | void disable_smartreflex(int srid); | ||
949 | #else | ||
950 | @@ -246,7 +252,6 @@ static inline void enable_smartreflex(int srid) {} | ||
951 | static inline void disable_smartreflex(int srid) {} | ||
952 | #endif | ||
953 | |||
954 | - | ||
955 | #endif | ||
956 | |||
957 | |||
958 | diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig | ||
959 | index b085b07..960c13f 100644 | ||
960 | --- a/arch/arm/plat-omap/Kconfig | ||
961 | +++ b/arch/arm/plat-omap/Kconfig | ||
962 | @@ -56,6 +56,37 @@ config OMAP_DEBUG_CLOCKDOMAIN | ||
963 | for every clockdomain register write. However, the | ||
964 | extra detail costs some memory. | ||
965 | |||
966 | +config OMAP_SMARTREFLEX | ||
967 | + bool "SmartReflex support" | ||
968 | + depends on ARCH_OMAP34XX && TWL4030_CORE | ||
969 | + help | ||
970 | + Say Y if you want to enable SmartReflex. | ||
971 | + | ||
972 | + SmartReflex can perform continuous dynamic voltage | ||
973 | + scaling around the nominal operating point voltage | ||
974 | + according to silicon characteristics and operating | ||
975 | + conditions. Enabling SmartReflex reduces power | ||
976 | + consumption. | ||
977 | + | ||
978 | + Please note, that by default SmartReflex is only | ||
979 | + initialized. To enable the automatic voltage | ||
980 | + compensation for VDD1 and VDD2, user must write 1 to | ||
981 | + /sys/power/sr_vddX_autocomp, where X is 1 or 2. | ||
982 | + | ||
983 | +config OMAP_SMARTREFLEX_TESTING | ||
984 | + bool "Smartreflex testing support" | ||
985 | + depends on OMAP_SMARTREFLEX | ||
986 | + default n | ||
987 | + help | ||
988 | + Say Y if you want to enable SmartReflex testing with SW hardcoded | ||
989 | + NVALUES intead of E-fuse NVALUES set in factory silicon testing. | ||
990 | + | ||
991 | + In some devices the E-fuse values have not been set, even though | ||
992 | + SmartReflex modules are included. Using these hardcoded values set | ||
993 | + in software, one can test the SmartReflex features without E-fuse. | ||
994 | + | ||
995 | + WARNING: Enabling this option may cause your device to hang! | ||
996 | + | ||
997 | config OMAP_RESET_CLOCKS | ||
998 | bool "Reset unused clocks during boot" | ||
999 | depends on ARCH_OMAP | ||
1000 | -- | ||
1001 | 1.5.4.3 | ||
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/defconfig b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/defconfig new file mode 100644 index 0000000000..f74cef90ee --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/defconfig | |||
@@ -0,0 +1,1567 @@ | |||
1 | # | ||
2 | # Automatically generated make config: don't edit | ||
3 | # Linux kernel version: 2.6.26-rc3-omap1 | ||
4 | # Wed May 21 07:38:41 2008 | ||
5 | # | ||
6 | CONFIG_ARM=y | ||
7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
8 | CONFIG_GENERIC_GPIO=y | ||
9 | CONFIG_GENERIC_TIME=y | ||
10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
11 | CONFIG_MMU=y | ||
12 | # CONFIG_NO_IOPORT is not set | ||
13 | CONFIG_GENERIC_HARDIRQS=y | ||
14 | CONFIG_STACKTRACE_SUPPORT=y | ||
15 | CONFIG_LOCKDEP_SUPPORT=y | ||
16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
22 | CONFIG_GENERIC_HWEIGHT=y | ||
23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
24 | CONFIG_ARCH_SUPPORTS_AOUT=y | ||
25 | CONFIG_ZONE_DMA=y | ||
26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
28 | |||
29 | # | ||
30 | # General setup | ||
31 | # | ||
32 | CONFIG_EXPERIMENTAL=y | ||
33 | CONFIG_BROKEN_ON_SMP=y | ||
34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
35 | CONFIG_LOCALVERSION="" | ||
36 | CONFIG_LOCALVERSION_AUTO=y | ||
37 | CONFIG_SWAP=y | ||
38 | CONFIG_SYSVIPC=y | ||
39 | CONFIG_SYSVIPC_SYSCTL=y | ||
40 | # CONFIG_POSIX_MQUEUE is not set | ||
41 | CONFIG_BSD_PROCESS_ACCT=y | ||
42 | # CONFIG_BSD_PROCESS_ACCT_V3 is not set | ||
43 | # CONFIG_TASKSTATS is not set | ||
44 | # CONFIG_AUDIT is not set | ||
45 | # CONFIG_IKCONFIG is not set | ||
46 | CONFIG_LOG_BUF_SHIFT=14 | ||
47 | # CONFIG_CGROUPS is not set | ||
48 | CONFIG_GROUP_SCHED=y | ||
49 | CONFIG_FAIR_GROUP_SCHED=y | ||
50 | # CONFIG_RT_GROUP_SCHED is not set | ||
51 | CONFIG_USER_SCHED=y | ||
52 | # CONFIG_CGROUP_SCHED is not set | ||
53 | CONFIG_SYSFS_DEPRECATED=y | ||
54 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
55 | # CONFIG_RELAY is not set | ||
56 | # CONFIG_NAMESPACES is not set | ||
57 | CONFIG_BLK_DEV_INITRD=y | ||
58 | CONFIG_INITRAMFS_SOURCE="" | ||
59 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
60 | CONFIG_SYSCTL=y | ||
61 | CONFIG_EMBEDDED=y | ||
62 | CONFIG_UID16=y | ||
63 | # CONFIG_SYSCTL_SYSCALL is not set | ||
64 | CONFIG_KALLSYMS=y | ||
65 | # CONFIG_KALLSYMS_ALL is not set | ||
66 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
67 | CONFIG_HOTPLUG=y | ||
68 | CONFIG_PRINTK=y | ||
69 | CONFIG_BUG=y | ||
70 | CONFIG_ELF_CORE=y | ||
71 | CONFIG_COMPAT_BRK=y | ||
72 | CONFIG_BASE_FULL=y | ||
73 | CONFIG_FUTEX=y | ||
74 | CONFIG_ANON_INODES=y | ||
75 | CONFIG_EPOLL=y | ||
76 | CONFIG_SIGNALFD=y | ||
77 | CONFIG_TIMERFD=y | ||
78 | CONFIG_EVENTFD=y | ||
79 | CONFIG_SHMEM=y | ||
80 | CONFIG_VM_EVENT_COUNTERS=y | ||
81 | CONFIG_SLAB=y | ||
82 | # CONFIG_SLUB is not set | ||
83 | # CONFIG_SLOB is not set | ||
84 | # CONFIG_PROFILING is not set | ||
85 | # CONFIG_MARKERS is not set | ||
86 | CONFIG_HAVE_OPROFILE=y | ||
87 | # CONFIG_KPROBES is not set | ||
88 | CONFIG_HAVE_KPROBES=y | ||
89 | CONFIG_HAVE_KRETPROBES=y | ||
90 | # CONFIG_HAVE_DMA_ATTRS is not set | ||
91 | CONFIG_PROC_PAGE_MONITOR=y | ||
92 | CONFIG_SLABINFO=y | ||
93 | CONFIG_RT_MUTEXES=y | ||
94 | # CONFIG_TINY_SHMEM is not set | ||
95 | CONFIG_BASE_SMALL=0 | ||
96 | CONFIG_MODULES=y | ||
97 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
98 | CONFIG_MODULE_UNLOAD=y | ||
99 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
100 | CONFIG_MODVERSIONS=y | ||
101 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
102 | CONFIG_KMOD=y | ||
103 | CONFIG_BLOCK=y | ||
104 | CONFIG_LBD=y | ||
105 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
106 | CONFIG_LSF=y | ||
107 | # CONFIG_BLK_DEV_BSG is not set | ||
108 | |||
109 | # | ||
110 | # IO Schedulers | ||
111 | # | ||
112 | CONFIG_IOSCHED_NOOP=y | ||
113 | CONFIG_IOSCHED_AS=y | ||
114 | CONFIG_IOSCHED_DEADLINE=y | ||
115 | # CONFIG_IOSCHED_CFQ is not set | ||
116 | CONFIG_DEFAULT_AS=y | ||
117 | # CONFIG_DEFAULT_DEADLINE is not set | ||
118 | # CONFIG_DEFAULT_CFQ is not set | ||
119 | # CONFIG_DEFAULT_NOOP is not set | ||
120 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
121 | CONFIG_CLASSIC_RCU=y | ||
122 | |||
123 | # | ||
124 | # System Type | ||
125 | # | ||
126 | # CONFIG_ARCH_AAEC2000 is not set | ||
127 | # CONFIG_ARCH_INTEGRATOR is not set | ||
128 | # CONFIG_ARCH_REALVIEW is not set | ||
129 | # CONFIG_ARCH_VERSATILE is not set | ||
130 | # CONFIG_ARCH_AT91 is not set | ||
131 | # CONFIG_ARCH_CLPS7500 is not set | ||
132 | # CONFIG_ARCH_CLPS711X is not set | ||
133 | # CONFIG_ARCH_CO285 is not set | ||
134 | # CONFIG_ARCH_EBSA110 is not set | ||
135 | # CONFIG_ARCH_EP93XX is not set | ||
136 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
137 | # CONFIG_ARCH_NETX is not set | ||
138 | # CONFIG_ARCH_H720X is not set | ||
139 | # CONFIG_ARCH_IMX is not set | ||
140 | # CONFIG_ARCH_IOP13XX is not set | ||
141 | # CONFIG_ARCH_IOP32X is not set | ||
142 | # CONFIG_ARCH_IOP33X is not set | ||
143 | # CONFIG_ARCH_IXP23XX is not set | ||
144 | # CONFIG_ARCH_IXP2000 is not set | ||
145 | # CONFIG_ARCH_IXP4XX is not set | ||
146 | # CONFIG_ARCH_L7200 is not set | ||
147 | # CONFIG_ARCH_KS8695 is not set | ||
148 | # CONFIG_ARCH_NS9XXX is not set | ||
149 | # CONFIG_ARCH_MXC is not set | ||
150 | # CONFIG_ARCH_ORION5X is not set | ||
151 | # CONFIG_ARCH_PNX4008 is not set | ||
152 | # CONFIG_ARCH_PXA is not set | ||
153 | # CONFIG_ARCH_RPC is not set | ||
154 | # CONFIG_ARCH_SA1100 is not set | ||
155 | # CONFIG_ARCH_S3C2410 is not set | ||
156 | # CONFIG_ARCH_SHARK is not set | ||
157 | # CONFIG_ARCH_LH7A40X is not set | ||
158 | # CONFIG_ARCH_DAVINCI is not set | ||
159 | CONFIG_ARCH_OMAP=y | ||
160 | # CONFIG_ARCH_MSM7X00A is not set | ||
161 | |||
162 | # | ||
163 | # TI OMAP Implementations | ||
164 | # | ||
165 | CONFIG_ARCH_OMAP_OTG=y | ||
166 | # CONFIG_ARCH_OMAP1 is not set | ||
167 | # CONFIG_ARCH_OMAP2 is not set | ||
168 | CONFIG_ARCH_OMAP3=y | ||
169 | |||
170 | # | ||
171 | # OMAP Feature Selections | ||
172 | # | ||
173 | CONFIG_OMAP_DEBUG_SRAM_PATCH=y | ||
174 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set | ||
175 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set | ||
176 | # CONFIG_OMAP_RESET_CLOCKS is not set | ||
177 | CONFIG_OMAP_BOOT_TAG=y | ||
178 | CONFIG_OMAP_BOOT_REASON=y | ||
179 | # CONFIG_OMAP_COMPONENT_VERSION is not set | ||
180 | # CONFIG_OMAP_GPIO_SWITCH is not set | ||
181 | # CONFIG_OMAP_MUX is not set | ||
182 | CONFIG_OMAP_MCBSP=y | ||
183 | # CONFIG_OMAP_MMU_FWK is not set | ||
184 | # CONFIG_OMAP_MBOX_FWK is not set | ||
185 | # CONFIG_OMAP_MPU_TIMER is not set | ||
186 | CONFIG_OMAP_32K_TIMER=y | ||
187 | CONFIG_OMAP_32K_TIMER_HZ=128 | ||
188 | CONFIG_OMAP_DM_TIMER=y | ||
189 | # CONFIG_OMAP_LL_DEBUG_UART1 is not set | ||
190 | # CONFIG_OMAP_LL_DEBUG_UART2 is not set | ||
191 | CONFIG_OMAP_LL_DEBUG_UART3=y | ||
192 | CONFIG_ARCH_OMAP34XX=y | ||
193 | CONFIG_ARCH_OMAP3430=y | ||
194 | |||
195 | # | ||
196 | # OMAP Board Type | ||
197 | # | ||
198 | # CONFIG_MACH_OMAP_LDP is not set | ||
199 | # CONFIG_MACH_OMAP_3430SDP is not set | ||
200 | CONFIG_MACH_OMAP3EVM=y | ||
201 | # CONFIG_MACH_OMAP3_BEAGLE is not set | ||
202 | |||
203 | # | ||
204 | # Boot options | ||
205 | # | ||
206 | |||
207 | # | ||
208 | # Power management | ||
209 | # | ||
210 | |||
211 | # | ||
212 | # Processor Type | ||
213 | # | ||
214 | CONFIG_CPU_32=y | ||
215 | CONFIG_CPU_32v6K=y | ||
216 | CONFIG_CPU_V7=y | ||
217 | CONFIG_CPU_32v7=y | ||
218 | CONFIG_CPU_ABRT_EV7=y | ||
219 | CONFIG_CPU_PABRT_IFAR=y | ||
220 | CONFIG_CPU_CACHE_V7=y | ||
221 | CONFIG_CPU_CACHE_VIPT=y | ||
222 | CONFIG_CPU_COPY_V6=y | ||
223 | CONFIG_CPU_TLB_V7=y | ||
224 | CONFIG_CPU_HAS_ASID=y | ||
225 | CONFIG_CPU_CP15=y | ||
226 | CONFIG_CPU_CP15_MMU=y | ||
227 | |||
228 | # | ||
229 | # Processor Features | ||
230 | # | ||
231 | CONFIG_ARM_THUMB=y | ||
232 | # CONFIG_ARM_THUMBEE is not set | ||
233 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
234 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
235 | # CONFIG_CPU_LOCKDOWN_TO_64K_L2 is not set | ||
236 | # CONFIG_CPU_LOCKDOWN_TO_128K_L2 is not set | ||
237 | CONFIG_CPU_LOCKDOWN_TO_256K_L2=y | ||
238 | # CONFIG_CPU_L2CACHE_DISABLE is not set | ||
239 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
240 | CONFIG_HAS_TLS_REG=y | ||
241 | # CONFIG_OUTER_CACHE is not set | ||
242 | |||
243 | # | ||
244 | # Bus support | ||
245 | # | ||
246 | # CONFIG_PCI_SYSCALL is not set | ||
247 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
248 | # CONFIG_PCCARD is not set | ||
249 | |||
250 | # | ||
251 | # Kernel Features | ||
252 | # | ||
253 | # CONFIG_TICK_ONESHOT is not set | ||
254 | # CONFIG_NO_HZ is not set | ||
255 | # CONFIG_HIGH_RES_TIMERS is not set | ||
256 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
257 | # CONFIG_PREEMPT is not set | ||
258 | CONFIG_HZ=128 | ||
259 | CONFIG_AEABI=y | ||
260 | CONFIG_OABI_COMPAT=y | ||
261 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
262 | CONFIG_SELECT_MEMORY_MODEL=y | ||
263 | CONFIG_FLATMEM_MANUAL=y | ||
264 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
265 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
266 | CONFIG_FLATMEM=y | ||
267 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
268 | # CONFIG_SPARSEMEM_STATIC is not set | ||
269 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
270 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
271 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
272 | # CONFIG_RESOURCES_64BIT is not set | ||
273 | CONFIG_ZONE_DMA_FLAG=1 | ||
274 | CONFIG_BOUNCE=y | ||
275 | CONFIG_VIRT_TO_BUS=y | ||
276 | # CONFIG_LEDS is not set | ||
277 | CONFIG_ALIGNMENT_TRAP=y | ||
278 | |||
279 | # | ||
280 | # Boot options | ||
281 | # | ||
282 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
283 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
284 | CONFIG_CMDLINE=" quiet " | ||
285 | # CONFIG_XIP_KERNEL is not set | ||
286 | # CONFIG_KEXEC is not set | ||
287 | |||
288 | # | ||
289 | # CPU Frequency scaling | ||
290 | # | ||
291 | # CONFIG_CPU_FREQ is not set | ||
292 | |||
293 | # | ||
294 | # Floating point emulation | ||
295 | # | ||
296 | |||
297 | # | ||
298 | # At least one emulation must be selected | ||
299 | # | ||
300 | CONFIG_FPE_NWFPE=y | ||
301 | # CONFIG_FPE_NWFPE_XP is not set | ||
302 | # CONFIG_FPE_FASTFPE is not set | ||
303 | CONFIG_VFP=y | ||
304 | CONFIG_VFPv3=y | ||
305 | # CONFIG_NEON is not set | ||
306 | |||
307 | # | ||
308 | # Userspace binary formats | ||
309 | # | ||
310 | CONFIG_BINFMT_ELF=y | ||
311 | # CONFIG_BINFMT_AOUT is not set | ||
312 | CONFIG_BINFMT_MISC=y | ||
313 | |||
314 | # | ||
315 | # Power management options | ||
316 | # | ||
317 | CONFIG_PM=y | ||
318 | # CONFIG_PM_DEBUG is not set | ||
319 | CONFIG_PM_SLEEP=y | ||
320 | CONFIG_SUSPEND=y | ||
321 | CONFIG_SUSPEND_FREEZER=y | ||
322 | # CONFIG_APM_EMULATION is not set | ||
323 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
324 | |||
325 | # | ||
326 | # Networking | ||
327 | # | ||
328 | CONFIG_NET=y | ||
329 | |||
330 | # | ||
331 | # Networking options | ||
332 | # | ||
333 | CONFIG_PACKET=y | ||
334 | CONFIG_PACKET_MMAP=y | ||
335 | CONFIG_UNIX=y | ||
336 | CONFIG_XFRM=y | ||
337 | # CONFIG_XFRM_USER is not set | ||
338 | # CONFIG_XFRM_SUB_POLICY is not set | ||
339 | # CONFIG_XFRM_MIGRATE is not set | ||
340 | # CONFIG_XFRM_STATISTICS is not set | ||
341 | # CONFIG_NET_KEY is not set | ||
342 | CONFIG_INET=y | ||
343 | # CONFIG_IP_MULTICAST is not set | ||
344 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
345 | CONFIG_IP_FIB_HASH=y | ||
346 | # CONFIG_IP_PNP is not set | ||
347 | # CONFIG_NET_IPIP is not set | ||
348 | # CONFIG_NET_IPGRE is not set | ||
349 | # CONFIG_ARPD is not set | ||
350 | # CONFIG_SYN_COOKIES is not set | ||
351 | # CONFIG_INET_AH is not set | ||
352 | # CONFIG_INET_ESP is not set | ||
353 | # CONFIG_INET_IPCOMP is not set | ||
354 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
355 | CONFIG_INET_TUNNEL=m | ||
356 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
357 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
358 | CONFIG_INET_XFRM_MODE_BEET=y | ||
359 | # CONFIG_INET_LRO is not set | ||
360 | CONFIG_INET_DIAG=y | ||
361 | CONFIG_INET_TCP_DIAG=y | ||
362 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
363 | CONFIG_TCP_CONG_CUBIC=y | ||
364 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
365 | # CONFIG_TCP_MD5SIG is not set | ||
366 | CONFIG_IPV6=m | ||
367 | # CONFIG_IPV6_PRIVACY is not set | ||
368 | # CONFIG_IPV6_ROUTER_PREF is not set | ||
369 | # CONFIG_IPV6_OPTIMISTIC_DAD is not set | ||
370 | # CONFIG_INET6_AH is not set | ||
371 | # CONFIG_INET6_ESP is not set | ||
372 | # CONFIG_INET6_IPCOMP is not set | ||
373 | # CONFIG_IPV6_MIP6 is not set | ||
374 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
375 | # CONFIG_INET6_TUNNEL is not set | ||
376 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m | ||
377 | CONFIG_INET6_XFRM_MODE_TUNNEL=m | ||
378 | CONFIG_INET6_XFRM_MODE_BEET=m | ||
379 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | ||
380 | CONFIG_IPV6_SIT=m | ||
381 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
382 | # CONFIG_IPV6_TUNNEL is not set | ||
383 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | ||
384 | # CONFIG_IPV6_MROUTE is not set | ||
385 | # CONFIG_NETWORK_SECMARK is not set | ||
386 | # CONFIG_NETFILTER is not set | ||
387 | # CONFIG_IP_DCCP is not set | ||
388 | # CONFIG_IP_SCTP is not set | ||
389 | # CONFIG_TIPC is not set | ||
390 | # CONFIG_ATM is not set | ||
391 | CONFIG_BRIDGE=m | ||
392 | CONFIG_VLAN_8021Q=m | ||
393 | # CONFIG_DECNET is not set | ||
394 | CONFIG_LLC=m | ||
395 | # CONFIG_LLC2 is not set | ||
396 | # CONFIG_IPX is not set | ||
397 | # CONFIG_ATALK is not set | ||
398 | # CONFIG_X25 is not set | ||
399 | # CONFIG_LAPB is not set | ||
400 | # CONFIG_ECONET is not set | ||
401 | # CONFIG_WAN_ROUTER is not set | ||
402 | # CONFIG_NET_SCHED is not set | ||
403 | CONFIG_NET_SCH_FIFO=y | ||
404 | |||
405 | # | ||
406 | # Network testing | ||
407 | # | ||
408 | # CONFIG_NET_PKTGEN is not set | ||
409 | # CONFIG_HAMRADIO is not set | ||
410 | # CONFIG_CAN is not set | ||
411 | # CONFIG_IRDA is not set | ||
412 | CONFIG_BT=m | ||
413 | CONFIG_BT_L2CAP=m | ||
414 | CONFIG_BT_SCO=m | ||
415 | CONFIG_BT_RFCOMM=m | ||
416 | CONFIG_BT_RFCOMM_TTY=y | ||
417 | CONFIG_BT_BNEP=m | ||
418 | CONFIG_BT_BNEP_MC_FILTER=y | ||
419 | CONFIG_BT_BNEP_PROTO_FILTER=y | ||
420 | CONFIG_BT_HIDP=m | ||
421 | |||
422 | # | ||
423 | # Bluetooth device drivers | ||
424 | # | ||
425 | # CONFIG_BT_HCIUSB is not set | ||
426 | # CONFIG_BT_HCIBTUSB is not set | ||
427 | CONFIG_BT_HCIBTSDIO=m | ||
428 | # CONFIG_BT_HCIUART is not set | ||
429 | # CONFIG_BT_HCIBCM203X is not set | ||
430 | # CONFIG_BT_HCIBPA10X is not set | ||
431 | # CONFIG_BT_HCIBFUSB is not set | ||
432 | # CONFIG_BT_HCIBRF6150 is not set | ||
433 | # CONFIG_BT_HCIH4P is not set | ||
434 | # CONFIG_BT_HCIVHCI is not set | ||
435 | # CONFIG_AF_RXRPC is not set | ||
436 | |||
437 | # | ||
438 | # Wireless | ||
439 | # | ||
440 | CONFIG_CFG80211=m | ||
441 | CONFIG_NL80211=y | ||
442 | CONFIG_WIRELESS_EXT=y | ||
443 | CONFIG_MAC80211=m | ||
444 | |||
445 | # | ||
446 | # Rate control algorithm selection | ||
447 | # | ||
448 | CONFIG_MAC80211_RC_DEFAULT_PID=y | ||
449 | # CONFIG_MAC80211_RC_DEFAULT_NONE is not set | ||
450 | |||
451 | # | ||
452 | # Selecting 'y' for an algorithm will | ||
453 | # | ||
454 | |||
455 | # | ||
456 | # build the algorithm into mac80211. | ||
457 | # | ||
458 | CONFIG_MAC80211_RC_DEFAULT="pid" | ||
459 | CONFIG_MAC80211_RC_PID=y | ||
460 | # CONFIG_MAC80211_MESH is not set | ||
461 | # CONFIG_MAC80211_LEDS is not set | ||
462 | # CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set | ||
463 | # CONFIG_MAC80211_DEBUG is not set | ||
464 | CONFIG_IEEE80211=m | ||
465 | # CONFIG_IEEE80211_DEBUG is not set | ||
466 | CONFIG_IEEE80211_CRYPT_WEP=m | ||
467 | # CONFIG_IEEE80211_CRYPT_CCMP is not set | ||
468 | # CONFIG_IEEE80211_CRYPT_TKIP is not set | ||
469 | # CONFIG_RFKILL is not set | ||
470 | # CONFIG_NET_9P is not set | ||
471 | |||
472 | # | ||
473 | # Device Drivers | ||
474 | # | ||
475 | |||
476 | # | ||
477 | # Generic Driver Options | ||
478 | # | ||
479 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
480 | CONFIG_STANDALONE=y | ||
481 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
482 | CONFIG_FW_LOADER=y | ||
483 | # CONFIG_DEBUG_DRIVER is not set | ||
484 | # CONFIG_DEBUG_DEVRES is not set | ||
485 | # CONFIG_SYS_HYPERVISOR is not set | ||
486 | # CONFIG_CONNECTOR is not set | ||
487 | CONFIG_MTD=y | ||
488 | # CONFIG_MTD_DEBUG is not set | ||
489 | CONFIG_MTD_CONCAT=y | ||
490 | CONFIG_MTD_PARTITIONS=y | ||
491 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
492 | CONFIG_MTD_CMDLINE_PARTS=y | ||
493 | # CONFIG_MTD_AFS_PARTS is not set | ||
494 | # CONFIG_MTD_AR7_PARTS is not set | ||
495 | |||
496 | # | ||
497 | # User Modules And Translation Layers | ||
498 | # | ||
499 | CONFIG_MTD_CHAR=y | ||
500 | CONFIG_MTD_BLKDEVS=y | ||
501 | CONFIG_MTD_BLOCK=y | ||
502 | # CONFIG_FTL is not set | ||
503 | # CONFIG_NFTL is not set | ||
504 | # CONFIG_INFTL is not set | ||
505 | # CONFIG_RFD_FTL is not set | ||
506 | # CONFIG_SSFDC is not set | ||
507 | # CONFIG_MTD_OOPS is not set | ||
508 | |||
509 | # | ||
510 | # RAM/ROM/Flash chip drivers | ||
511 | # | ||
512 | CONFIG_MTD_CFI=y | ||
513 | # CONFIG_MTD_JEDECPROBE is not set | ||
514 | CONFIG_MTD_GEN_PROBE=y | ||
515 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
516 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
517 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
518 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
519 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
520 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
521 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
522 | CONFIG_MTD_CFI_I1=y | ||
523 | CONFIG_MTD_CFI_I2=y | ||
524 | # CONFIG_MTD_CFI_I4 is not set | ||
525 | # CONFIG_MTD_CFI_I8 is not set | ||
526 | CONFIG_MTD_CFI_INTELEXT=y | ||
527 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
528 | # CONFIG_MTD_CFI_STAA is not set | ||
529 | CONFIG_MTD_CFI_UTIL=y | ||
530 | # CONFIG_MTD_RAM is not set | ||
531 | # CONFIG_MTD_ROM is not set | ||
532 | # CONFIG_MTD_ABSENT is not set | ||
533 | |||
534 | # | ||
535 | # Mapping drivers for chip access | ||
536 | # | ||
537 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
538 | # CONFIG_MTD_PHYSMAP is not set | ||
539 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
540 | CONFIG_MTD_OMAP_NOR=y | ||
541 | # CONFIG_MTD_PLATRAM is not set | ||
542 | |||
543 | # | ||
544 | # Self-contained MTD device drivers | ||
545 | # | ||
546 | # CONFIG_MTD_DATAFLASH is not set | ||
547 | # CONFIG_MTD_M25P80 is not set | ||
548 | # CONFIG_MTD_SLRAM is not set | ||
549 | # CONFIG_MTD_PHRAM is not set | ||
550 | # CONFIG_MTD_MTDRAM is not set | ||
551 | # CONFIG_MTD_BLOCK2MTD is not set | ||
552 | |||
553 | # | ||
554 | # Disk-On-Chip Device Drivers | ||
555 | # | ||
556 | # CONFIG_MTD_DOC2000 is not set | ||
557 | # CONFIG_MTD_DOC2001 is not set | ||
558 | # CONFIG_MTD_DOC2001PLUS is not set | ||
559 | # CONFIG_MTD_NAND is not set | ||
560 | CONFIG_MTD_ONENAND=y | ||
561 | CONFIG_MTD_ONENAND_VERIFY_WRITE=y | ||
562 | # CONFIG_MTD_ONENAND_GENERIC is not set | ||
563 | CONFIG_MTD_ONENAND_OMAP2=y | ||
564 | # CONFIG_MTD_ONENAND_OTP is not set | ||
565 | # CONFIG_MTD_ONENAND_2X_PROGRAM is not set | ||
566 | # CONFIG_MTD_ONENAND_SIM is not set | ||
567 | |||
568 | # | ||
569 | # UBI - Unsorted block images | ||
570 | # | ||
571 | # CONFIG_MTD_UBI is not set | ||
572 | # CONFIG_PARPORT is not set | ||
573 | CONFIG_BLK_DEV=y | ||
574 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
575 | CONFIG_BLK_DEV_LOOP=y | ||
576 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
577 | # CONFIG_BLK_DEV_NBD is not set | ||
578 | # CONFIG_BLK_DEV_UB is not set | ||
579 | CONFIG_BLK_DEV_RAM=y | ||
580 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
581 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
582 | # CONFIG_BLK_DEV_XIP is not set | ||
583 | # CONFIG_CDROM_PKTCDVD is not set | ||
584 | # CONFIG_ATA_OVER_ETH is not set | ||
585 | CONFIG_MISC_DEVICES=y | ||
586 | CONFIG_EEPROM_93CX6=m | ||
587 | # CONFIG_OMAP_STI is not set | ||
588 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
589 | CONFIG_HAVE_IDE=y | ||
590 | # CONFIG_IDE is not set | ||
591 | |||
592 | # | ||
593 | # SCSI device support | ||
594 | # | ||
595 | # CONFIG_RAID_ATTRS is not set | ||
596 | # CONFIG_SCSI is not set | ||
597 | # CONFIG_SCSI_DMA is not set | ||
598 | # CONFIG_SCSI_NETLINK is not set | ||
599 | # CONFIG_ATA is not set | ||
600 | # CONFIG_MD is not set | ||
601 | CONFIG_NETDEVICES=y | ||
602 | CONFIG_NETDEVICES_MULTIQUEUE=y | ||
603 | # CONFIG_DUMMY is not set | ||
604 | # CONFIG_BONDING is not set | ||
605 | # CONFIG_MACVLAN is not set | ||
606 | # CONFIG_EQUALIZER is not set | ||
607 | # CONFIG_TUN is not set | ||
608 | # CONFIG_VETH is not set | ||
609 | # CONFIG_PHYLIB is not set | ||
610 | CONFIG_NET_ETHERNET=y | ||
611 | CONFIG_MII=y | ||
612 | # CONFIG_AX88796 is not set | ||
613 | # CONFIG_SMC91X is not set | ||
614 | # CONFIG_DM9000 is not set | ||
615 | # CONFIG_ENC28J60 is not set | ||
616 | CONFIG_SMC911X=y | ||
617 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
618 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
619 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
620 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
621 | # CONFIG_B44 is not set | ||
622 | # CONFIG_NETDEV_1000 is not set | ||
623 | # CONFIG_NETDEV_10000 is not set | ||
624 | |||
625 | # | ||
626 | # Wireless LAN | ||
627 | # | ||
628 | # CONFIG_WLAN_PRE80211 is not set | ||
629 | CONFIG_WLAN_80211=y | ||
630 | CONFIG_LIBERTAS=m | ||
631 | # CONFIG_LIBERTAS_USB is not set | ||
632 | CONFIG_LIBERTAS_SDIO=m | ||
633 | # CONFIG_LIBERTAS_DEBUG is not set | ||
634 | # CONFIG_USB_ZD1201 is not set | ||
635 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
636 | # CONFIG_RTL8187 is not set | ||
637 | CONFIG_P54_COMMON=m | ||
638 | # CONFIG_P54_USB is not set | ||
639 | # CONFIG_IWLWIFI_LEDS is not set | ||
640 | CONFIG_HOSTAP=m | ||
641 | CONFIG_HOSTAP_FIRMWARE=y | ||
642 | CONFIG_HOSTAP_FIRMWARE_NVRAM=y | ||
643 | # CONFIG_B43 is not set | ||
644 | # CONFIG_B43LEGACY is not set | ||
645 | # CONFIG_ZD1211RW is not set | ||
646 | # CONFIG_RT2X00 is not set | ||
647 | |||
648 | # | ||
649 | # USB Network Adapters | ||
650 | # | ||
651 | CONFIG_USB_CATC=m | ||
652 | CONFIG_USB_KAWETH=m | ||
653 | CONFIG_USB_PEGASUS=m | ||
654 | CONFIG_USB_RTL8150=m | ||
655 | CONFIG_USB_USBNET=m | ||
656 | CONFIG_USB_NET_AX8817X=m | ||
657 | CONFIG_USB_NET_CDCETHER=m | ||
658 | CONFIG_USB_NET_DM9601=m | ||
659 | CONFIG_USB_NET_GL620A=m | ||
660 | CONFIG_USB_NET_NET1080=m | ||
661 | CONFIG_USB_NET_PLUSB=m | ||
662 | CONFIG_USB_NET_MCS7830=m | ||
663 | CONFIG_USB_NET_RNDIS_HOST=m | ||
664 | CONFIG_USB_NET_CDC_SUBSET=m | ||
665 | CONFIG_USB_ALI_M5632=y | ||
666 | CONFIG_USB_AN2720=y | ||
667 | CONFIG_USB_BELKIN=y | ||
668 | CONFIG_USB_ARMLINUX=y | ||
669 | CONFIG_USB_EPSON2888=y | ||
670 | CONFIG_USB_KC2190=y | ||
671 | CONFIG_USB_NET_ZAURUS=m | ||
672 | # CONFIG_WAN is not set | ||
673 | CONFIG_PPP=m | ||
674 | CONFIG_PPP_MULTILINK=y | ||
675 | CONFIG_PPP_FILTER=y | ||
676 | CONFIG_PPP_ASYNC=m | ||
677 | CONFIG_PPP_SYNC_TTY=m | ||
678 | CONFIG_PPP_DEFLATE=m | ||
679 | CONFIG_PPP_BSDCOMP=m | ||
680 | CONFIG_PPP_MPPE=m | ||
681 | CONFIG_PPPOE=m | ||
682 | CONFIG_PPPOL2TP=m | ||
683 | # CONFIG_SLIP is not set | ||
684 | CONFIG_SLHC=m | ||
685 | # CONFIG_NETCONSOLE is not set | ||
686 | # CONFIG_NETPOLL is not set | ||
687 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
688 | # CONFIG_ISDN is not set | ||
689 | |||
690 | # | ||
691 | # Input device support | ||
692 | # | ||
693 | CONFIG_INPUT=y | ||
694 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
695 | # CONFIG_INPUT_POLLDEV is not set | ||
696 | |||
697 | # | ||
698 | # Userland interfaces | ||
699 | # | ||
700 | # CONFIG_INPUT_MOUSEDEV is not set | ||
701 | # CONFIG_INPUT_JOYDEV is not set | ||
702 | CONFIG_INPUT_EVDEV=y | ||
703 | CONFIG_INPUT_EVBUG=y | ||
704 | |||
705 | # | ||
706 | # Input Device Drivers | ||
707 | # | ||
708 | CONFIG_INPUT_KEYBOARD=y | ||
709 | # CONFIG_KEYBOARD_ATKBD is not set | ||
710 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
711 | # CONFIG_KEYBOARD_LKKBD is not set | ||
712 | # CONFIG_KEYBOARD_XTKBD is not set | ||
713 | # CONFIG_KEYBOARD_NEWTON is not set | ||
714 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
715 | # CONFIG_KEYBOARD_LM8323 is not set | ||
716 | # CONFIG_KEYBOARD_GPIO is not set | ||
717 | # CONFIG_INPUT_MOUSE is not set | ||
718 | # CONFIG_INPUT_JOYSTICK is not set | ||
719 | # CONFIG_INPUT_TABLET is not set | ||
720 | CONFIG_INPUT_TOUCHSCREEN=y | ||
721 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
722 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
723 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
724 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
725 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
726 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
727 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
728 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
729 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
730 | # CONFIG_TOUCHSCREEN_TSC2005 is not set | ||
731 | # CONFIG_TOUCHSCREEN_TSC2102 is not set | ||
732 | # CONFIG_TOUCHSCREEN_TSC210X is not set | ||
733 | # CONFIG_TOUCHSCREEN_UCB1400 is not set | ||
734 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
735 | # CONFIG_INPUT_MISC is not set | ||
736 | |||
737 | # | ||
738 | # Hardware I/O ports | ||
739 | # | ||
740 | # CONFIG_SERIO is not set | ||
741 | # CONFIG_GAMEPORT is not set | ||
742 | |||
743 | # | ||
744 | # Character devices | ||
745 | # | ||
746 | CONFIG_VT=y | ||
747 | CONFIG_VT_CONSOLE=y | ||
748 | CONFIG_HW_CONSOLE=y | ||
749 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
750 | CONFIG_DEVKMEM=y | ||
751 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
752 | |||
753 | # | ||
754 | # Serial drivers | ||
755 | # | ||
756 | CONFIG_SERIAL_8250=y | ||
757 | CONFIG_SERIAL_8250_CONSOLE=y | ||
758 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
759 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
760 | CONFIG_SERIAL_8250_EXTENDED=y | ||
761 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
762 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
763 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
764 | CONFIG_SERIAL_8250_RSA=y | ||
765 | |||
766 | # | ||
767 | # Non-8250 serial port support | ||
768 | # | ||
769 | CONFIG_SERIAL_CORE=y | ||
770 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
771 | CONFIG_UNIX98_PTYS=y | ||
772 | # CONFIG_LEGACY_PTYS is not set | ||
773 | # CONFIG_IPMI_HANDLER is not set | ||
774 | CONFIG_HW_RANDOM=y | ||
775 | # CONFIG_NVRAM is not set | ||
776 | # CONFIG_R3964 is not set | ||
777 | # CONFIG_RAW_DRIVER is not set | ||
778 | # CONFIG_TCG_TPM is not set | ||
779 | CONFIG_I2C=y | ||
780 | CONFIG_I2C_BOARDINFO=y | ||
781 | CONFIG_I2C_CHARDEV=y | ||
782 | |||
783 | # | ||
784 | # I2C Hardware Bus support | ||
785 | # | ||
786 | # CONFIG_I2C_GPIO is not set | ||
787 | # CONFIG_I2C_OCORES is not set | ||
788 | CONFIG_I2C_OMAP=y | ||
789 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
790 | # CONFIG_I2C_SIMTEC is not set | ||
791 | # CONFIG_I2C_TAOS_EVM is not set | ||
792 | # CONFIG_I2C_STUB is not set | ||
793 | # CONFIG_I2C_TINY_USB is not set | ||
794 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
795 | |||
796 | # | ||
797 | # Miscellaneous I2C Chip support | ||
798 | # | ||
799 | # CONFIG_DS1682 is not set | ||
800 | # CONFIG_SENSORS_EEPROM is not set | ||
801 | # CONFIG_SENSORS_PCF8574 is not set | ||
802 | # CONFIG_PCF8575 is not set | ||
803 | # CONFIG_SENSORS_PCF8591 is not set | ||
804 | # CONFIG_ISP1301_OMAP is not set | ||
805 | # CONFIG_TPS65010 is not set | ||
806 | # CONFIG_SENSORS_TLV320AIC23 is not set | ||
807 | CONFIG_TWL4030_CORE=y | ||
808 | CONFIG_TWL4030_GPIO=y | ||
809 | # CONFIG_TWL4030_MADC is not set | ||
810 | CONFIG_TWL4030_USB=y | ||
811 | CONFIG_TWL4030_USB_HS_ULPI=y | ||
812 | # CONFIG_TWL4030_PWRBUTTON is not set | ||
813 | # CONFIG_TWL4030_POWEROFF is not set | ||
814 | # CONFIG_SENSORS_MAX6875 is not set | ||
815 | # CONFIG_SENSORS_TSL2550 is not set | ||
816 | # CONFIG_LP5521 is not set | ||
817 | # CONFIG_I2C_DEBUG_CORE is not set | ||
818 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
819 | # CONFIG_I2C_DEBUG_BUS is not set | ||
820 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
821 | CONFIG_SPI=y | ||
822 | CONFIG_SPI_DEBUG=y | ||
823 | CONFIG_SPI_MASTER=y | ||
824 | |||
825 | # | ||
826 | # SPI Master Controller Drivers | ||
827 | # | ||
828 | # CONFIG_SPI_BITBANG is not set | ||
829 | CONFIG_SPI_OMAP24XX=y | ||
830 | |||
831 | # | ||
832 | # SPI Protocol Masters | ||
833 | # | ||
834 | # CONFIG_SPI_AT25 is not set | ||
835 | # CONFIG_SPI_TSC2101 is not set | ||
836 | # CONFIG_SPI_TSC2102 is not set | ||
837 | # CONFIG_SPI_TSC210X is not set | ||
838 | # CONFIG_SPI_TSC2301 is not set | ||
839 | # CONFIG_SPI_SPIDEV is not set | ||
840 | # CONFIG_SPI_TLE62X0 is not set | ||
841 | CONFIG_HAVE_GPIO_LIB=y | ||
842 | |||
843 | # | ||
844 | # GPIO Support | ||
845 | # | ||
846 | # CONFIG_DEBUG_GPIO is not set | ||
847 | |||
848 | # | ||
849 | # I2C GPIO expanders: | ||
850 | # | ||
851 | # CONFIG_GPIO_PCA953X is not set | ||
852 | # CONFIG_GPIO_PCF857X is not set | ||
853 | |||
854 | # | ||
855 | # SPI GPIO expanders: | ||
856 | # | ||
857 | # CONFIG_GPIO_MCP23S08 is not set | ||
858 | # CONFIG_W1 is not set | ||
859 | # CONFIG_POWER_SUPPLY is not set | ||
860 | # CONFIG_HWMON is not set | ||
861 | CONFIG_WATCHDOG=y | ||
862 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
863 | |||
864 | # | ||
865 | # Watchdog Device Drivers | ||
866 | # | ||
867 | # CONFIG_SOFT_WATCHDOG is not set | ||
868 | CONFIG_OMAP_WATCHDOG=y | ||
869 | |||
870 | # | ||
871 | # USB-based Watchdog Cards | ||
872 | # | ||
873 | # CONFIG_USBPCWATCHDOG is not set | ||
874 | |||
875 | # | ||
876 | # Sonics Silicon Backplane | ||
877 | # | ||
878 | CONFIG_SSB_POSSIBLE=y | ||
879 | # CONFIG_SSB is not set | ||
880 | |||
881 | # | ||
882 | # Multifunction device drivers | ||
883 | # | ||
884 | # CONFIG_MFD_SM501 is not set | ||
885 | # CONFIG_MFD_ASIC3 is not set | ||
886 | # CONFIG_HTC_EGPIO is not set | ||
887 | # CONFIG_HTC_PASIC3 is not set | ||
888 | |||
889 | # | ||
890 | # Multimedia devices | ||
891 | # | ||
892 | |||
893 | # | ||
894 | # Multimedia core support | ||
895 | # | ||
896 | # CONFIG_VIDEO_DEV is not set | ||
897 | # CONFIG_DVB_CORE is not set | ||
898 | # CONFIG_VIDEO_MEDIA is not set | ||
899 | |||
900 | # | ||
901 | # Multimedia drivers | ||
902 | # | ||
903 | CONFIG_DAB=y | ||
904 | # CONFIG_USB_DABUSB is not set | ||
905 | |||
906 | # | ||
907 | # Graphics support | ||
908 | # | ||
909 | # CONFIG_VGASTATE is not set | ||
910 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
911 | CONFIG_FB=y | ||
912 | CONFIG_FIRMWARE_EDID=y | ||
913 | # CONFIG_FB_DDC is not set | ||
914 | CONFIG_FB_CFB_FILLRECT=y | ||
915 | CONFIG_FB_CFB_COPYAREA=y | ||
916 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
917 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
918 | # CONFIG_FB_SYS_FILLRECT is not set | ||
919 | # CONFIG_FB_SYS_COPYAREA is not set | ||
920 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
921 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
922 | # CONFIG_FB_SYS_FOPS is not set | ||
923 | # CONFIG_FB_SVGALIB is not set | ||
924 | # CONFIG_FB_MACMODES is not set | ||
925 | # CONFIG_FB_BACKLIGHT is not set | ||
926 | CONFIG_FB_MODE_HELPERS=y | ||
927 | CONFIG_FB_TILEBLITTING=y | ||
928 | |||
929 | # | ||
930 | # Frame buffer hardware drivers | ||
931 | # | ||
932 | # CONFIG_FB_S1D13XXX is not set | ||
933 | # CONFIG_FB_VIRTUAL is not set | ||
934 | CONFIG_FB_OMAP=y | ||
935 | # CONFIG_FB_OMAP_LCDC_EXTERNAL is not set | ||
936 | # CONFIG_FB_OMAP_BOOTLOADER_INIT is not set | ||
937 | CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2 | ||
938 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
939 | |||
940 | # | ||
941 | # Display device support | ||
942 | # | ||
943 | # CONFIG_DISPLAY_SUPPORT is not set | ||
944 | |||
945 | # | ||
946 | # Console display driver support | ||
947 | # | ||
948 | # CONFIG_VGA_CONSOLE is not set | ||
949 | CONFIG_DUMMY_CONSOLE=y | ||
950 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
951 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
952 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | ||
953 | # CONFIG_FONTS is not set | ||
954 | CONFIG_FONT_8x8=y | ||
955 | CONFIG_FONT_8x16=y | ||
956 | # CONFIG_LOGO is not set | ||
957 | |||
958 | # | ||
959 | # Sound | ||
960 | # | ||
961 | CONFIG_SOUND=y | ||
962 | |||
963 | # | ||
964 | # Advanced Linux Sound Architecture | ||
965 | # | ||
966 | CONFIG_SND=y | ||
967 | CONFIG_SND_TIMER=y | ||
968 | CONFIG_SND_PCM=y | ||
969 | # CONFIG_SND_SEQUENCER is not set | ||
970 | CONFIG_SND_OSSEMUL=y | ||
971 | # CONFIG_SND_MIXER_OSS is not set | ||
972 | CONFIG_SND_PCM_OSS=y | ||
973 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
974 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
975 | CONFIG_SND_SUPPORT_OLD_API=y | ||
976 | CONFIG_SND_VERBOSE_PROCFS=y | ||
977 | CONFIG_SND_VERBOSE_PRINTK=y | ||
978 | CONFIG_SND_DEBUG=y | ||
979 | CONFIG_SND_DEBUG_DETECT=y | ||
980 | CONFIG_SND_PCM_XRUN_DEBUG=y | ||
981 | |||
982 | # | ||
983 | # Generic devices | ||
984 | # | ||
985 | # CONFIG_SND_DUMMY is not set | ||
986 | # CONFIG_SND_MTPAV is not set | ||
987 | # CONFIG_SND_SERIAL_U16550 is not set | ||
988 | # CONFIG_SND_MPU401 is not set | ||
989 | |||
990 | # | ||
991 | # ALSA ARM devices | ||
992 | # | ||
993 | # CONFIG_SND_OMAP_AIC23 is not set | ||
994 | # CONFIG_SND_OMAP_TSC2101 is not set | ||
995 | # CONFIG_SND_SX1 is not set | ||
996 | # CONFIG_SND_OMAP_TSC2102 is not set | ||
997 | # CONFIG_SND_OMAP24XX_EAC is not set | ||
998 | |||
999 | # | ||
1000 | # SPI devices | ||
1001 | # | ||
1002 | |||
1003 | # | ||
1004 | # USB devices | ||
1005 | # | ||
1006 | # CONFIG_SND_USB_AUDIO is not set | ||
1007 | # CONFIG_SND_USB_CAIAQ is not set | ||
1008 | |||
1009 | # | ||
1010 | # System on Chip audio support | ||
1011 | # | ||
1012 | CONFIG_SND_SOC=y | ||
1013 | |||
1014 | # | ||
1015 | # ALSA SoC audio for Freescale SOCs | ||
1016 | # | ||
1017 | |||
1018 | # | ||
1019 | # SoC Audio for the Texas Instruments OMAP | ||
1020 | # | ||
1021 | CONFIG_SND_OMAP_SOC=y | ||
1022 | CONFIG_SND_OMAP_SOC_MCBSP=y | ||
1023 | CONFIG_SND_OMAP_SOC_OMAP3EVM=y | ||
1024 | CONFIG_SND_SOC_TWL4030=y | ||
1025 | |||
1026 | # | ||
1027 | # Open Sound System | ||
1028 | # | ||
1029 | CONFIG_SOUND_PRIME=y | ||
1030 | # CONFIG_SOUND_MSNDCLAS is not set | ||
1031 | # CONFIG_SOUND_MSNDPIN is not set | ||
1032 | CONFIG_HID_SUPPORT=y | ||
1033 | CONFIG_HID=y | ||
1034 | # CONFIG_HID_DEBUG is not set | ||
1035 | # CONFIG_HIDRAW is not set | ||
1036 | |||
1037 | # | ||
1038 | # USB Input Devices | ||
1039 | # | ||
1040 | CONFIG_USB_HID=y | ||
1041 | # CONFIG_USB_HIDINPUT_POWERBOOK is not set | ||
1042 | # CONFIG_HID_FF is not set | ||
1043 | # CONFIG_USB_HIDDEV is not set | ||
1044 | CONFIG_USB_SUPPORT=y | ||
1045 | CONFIG_USB_ARCH_HAS_HCD=y | ||
1046 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
1047 | CONFIG_USB_ARCH_HAS_EHCI=y | ||
1048 | CONFIG_USB=y | ||
1049 | # CONFIG_USB_DEBUG is not set | ||
1050 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
1051 | |||
1052 | # | ||
1053 | # Miscellaneous USB options | ||
1054 | # | ||
1055 | CONFIG_USB_DEVICEFS=y | ||
1056 | CONFIG_USB_DEVICE_CLASS=y | ||
1057 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
1058 | # CONFIG_USB_SUSPEND is not set | ||
1059 | # CONFIG_USB_OTG is not set | ||
1060 | # CONFIG_USB_OTG_WHITELIST is not set | ||
1061 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
1062 | |||
1063 | # | ||
1064 | # USB Host Controller Drivers | ||
1065 | # | ||
1066 | # CONFIG_USB_C67X00_HCD is not set | ||
1067 | CONFIG_USB_EHCI_HCD=y | ||
1068 | CONFIG_OMAP_EHCI_PHY_MODE=y | ||
1069 | # CONFIG_OMAP_EHCI_TLL_MODE is not set | ||
1070 | # CONFIG_USB_EHCI_ROOT_HUB_TT is not set | ||
1071 | # CONFIG_USB_EHCI_TT_NEWSCHED is not set | ||
1072 | CONFIG_USB_ISP116X_HCD=y | ||
1073 | # CONFIG_USB_ISP1760_HCD is not set | ||
1074 | CONFIG_USB_OHCI_HCD=y | ||
1075 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
1076 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
1077 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
1078 | CONFIG_USB_SL811_HCD=y | ||
1079 | CONFIG_USB_R8A66597_HCD=y | ||
1080 | CONFIG_USB_MUSB_HDRC=m | ||
1081 | CONFIG_USB_MUSB_SOC=y | ||
1082 | |||
1083 | # | ||
1084 | # OMAP 343x high speed USB support | ||
1085 | # | ||
1086 | CONFIG_USB_MUSB_HOST=y | ||
1087 | # CONFIG_USB_MUSB_PERIPHERAL is not set | ||
1088 | # CONFIG_USB_MUSB_OTG is not set | ||
1089 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
1090 | CONFIG_USB_MUSB_HDRC_HCD=y | ||
1091 | # CONFIG_MUSB_PIO_ONLY is not set | ||
1092 | CONFIG_USB_INVENTRA_DMA=y | ||
1093 | # CONFIG_USB_TI_CPPI_DMA is not set | ||
1094 | CONFIG_USB_MUSB_LOGLEVEL=0 | ||
1095 | |||
1096 | # | ||
1097 | # USB Device Class drivers | ||
1098 | # | ||
1099 | # CONFIG_USB_ACM is not set | ||
1100 | # CONFIG_USB_PRINTER is not set | ||
1101 | |||
1102 | # | ||
1103 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
1104 | # | ||
1105 | |||
1106 | # | ||
1107 | # may also be needed; see USB_STORAGE Help for more information | ||
1108 | # | ||
1109 | # CONFIG_USB_LIBUSUAL is not set | ||
1110 | |||
1111 | # | ||
1112 | # USB Imaging devices | ||
1113 | # | ||
1114 | # CONFIG_USB_MDC800 is not set | ||
1115 | CONFIG_USB_MON=y | ||
1116 | |||
1117 | # | ||
1118 | # USB port drivers | ||
1119 | # | ||
1120 | # CONFIG_USB_SERIAL is not set | ||
1121 | |||
1122 | # | ||
1123 | # USB Miscellaneous drivers | ||
1124 | # | ||
1125 | # CONFIG_USB_EMI62 is not set | ||
1126 | # CONFIG_USB_EMI26 is not set | ||
1127 | # CONFIG_USB_ADUTUX is not set | ||
1128 | # CONFIG_USB_AUERSWALD is not set | ||
1129 | # CONFIG_USB_RIO500 is not set | ||
1130 | # CONFIG_USB_LEGOTOWER is not set | ||
1131 | # CONFIG_USB_LCD is not set | ||
1132 | # CONFIG_USB_BERRY_CHARGE is not set | ||
1133 | # CONFIG_USB_LED is not set | ||
1134 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
1135 | # CONFIG_USB_CYTHERM is not set | ||
1136 | # CONFIG_USB_PHIDGET is not set | ||
1137 | # CONFIG_USB_IDMOUSE is not set | ||
1138 | # CONFIG_USB_FTDI_ELAN is not set | ||
1139 | # CONFIG_USB_APPLEDISPLAY is not set | ||
1140 | # CONFIG_USB_SISUSBVGA is not set | ||
1141 | # CONFIG_USB_LD is not set | ||
1142 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
1143 | # CONFIG_USB_IOWARRIOR is not set | ||
1144 | # CONFIG_USB_TEST is not set | ||
1145 | CONFIG_USB_GADGET=m | ||
1146 | # CONFIG_USB_GADGET_DEBUG is not set | ||
1147 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
1148 | CONFIG_USB_GADGET_SELECTED=y | ||
1149 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
1150 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
1151 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
1152 | # CONFIG_USB_GADGET_NET2280 is not set | ||
1153 | # CONFIG_USB_GADGET_PXA2XX is not set | ||
1154 | # CONFIG_USB_GADGET_M66592 is not set | ||
1155 | # CONFIG_USB_GADGET_PXA27X is not set | ||
1156 | # CONFIG_USB_GADGET_GOKU is not set | ||
1157 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
1158 | CONFIG_USB_GADGET_OMAP=y | ||
1159 | CONFIG_USB_OMAP=m | ||
1160 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
1161 | # CONFIG_USB_GADGET_AT91 is not set | ||
1162 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
1163 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
1164 | # CONFIG_USB_ZERO is not set | ||
1165 | CONFIG_USB_ETH=m | ||
1166 | CONFIG_USB_ETH_RNDIS=y | ||
1167 | CONFIG_USB_GADGETFS=m | ||
1168 | CONFIG_USB_FILE_STORAGE=m | ||
1169 | # CONFIG_USB_FILE_STORAGE_TEST is not set | ||
1170 | CONFIG_USB_G_SERIAL=m | ||
1171 | # CONFIG_USB_MIDI_GADGET is not set | ||
1172 | CONFIG_USB_G_PRINTER=m | ||
1173 | CONFIG_MMC=y | ||
1174 | # CONFIG_MMC_DEBUG is not set | ||
1175 | CONFIG_MMC_UNSAFE_RESUME=y | ||
1176 | |||
1177 | # | ||
1178 | # MMC/SD Card Drivers | ||
1179 | # | ||
1180 | CONFIG_MMC_BLOCK=y | ||
1181 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
1182 | CONFIG_SDIO_UART=m | ||
1183 | |||
1184 | # | ||
1185 | # MMC/SD Host Controller Drivers | ||
1186 | # | ||
1187 | CONFIG_MMC_OMAP_HS=y | ||
1188 | # CONFIG_MMC_SPI is not set | ||
1189 | # CONFIG_NEW_LEDS is not set | ||
1190 | CONFIG_RTC_LIB=y | ||
1191 | CONFIG_RTC_CLASS=y | ||
1192 | CONFIG_RTC_HCTOSYS=y | ||
1193 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
1194 | # CONFIG_RTC_DEBUG is not set | ||
1195 | |||
1196 | # | ||
1197 | # RTC interfaces | ||
1198 | # | ||
1199 | CONFIG_RTC_INTF_SYSFS=y | ||
1200 | CONFIG_RTC_INTF_PROC=y | ||
1201 | CONFIG_RTC_INTF_DEV=y | ||
1202 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
1203 | # CONFIG_RTC_DRV_TEST is not set | ||
1204 | |||
1205 | # | ||
1206 | # I2C RTC drivers | ||
1207 | # | ||
1208 | # CONFIG_RTC_DRV_DS1307 is not set | ||
1209 | # CONFIG_RTC_DRV_DS1374 is not set | ||
1210 | # CONFIG_RTC_DRV_DS1672 is not set | ||
1211 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
1212 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
1213 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
1214 | # CONFIG_RTC_DRV_X1205 is not set | ||
1215 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
1216 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
1217 | # CONFIG_RTC_DRV_M41T80 is not set | ||
1218 | CONFIG_RTC_DRV_TWL4030=y | ||
1219 | # CONFIG_RTC_DRV_S35390A is not set | ||
1220 | |||
1221 | # | ||
1222 | # SPI RTC drivers | ||
1223 | # | ||
1224 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
1225 | # CONFIG_RTC_DRV_R9701 is not set | ||
1226 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
1227 | |||
1228 | # | ||
1229 | # Platform RTC drivers | ||
1230 | # | ||
1231 | # CONFIG_RTC_DRV_CMOS is not set | ||
1232 | # CONFIG_RTC_DRV_DS1511 is not set | ||
1233 | # CONFIG_RTC_DRV_DS1553 is not set | ||
1234 | # CONFIG_RTC_DRV_DS1742 is not set | ||
1235 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
1236 | # CONFIG_RTC_DRV_M48T86 is not set | ||
1237 | # CONFIG_RTC_DRV_M48T59 is not set | ||
1238 | # CONFIG_RTC_DRV_V3020 is not set | ||
1239 | |||
1240 | # | ||
1241 | # on-CPU RTC drivers | ||
1242 | # | ||
1243 | # CONFIG_UIO is not set | ||
1244 | |||
1245 | # | ||
1246 | # CBUS support | ||
1247 | # | ||
1248 | # CONFIG_CBUS is not set | ||
1249 | |||
1250 | # | ||
1251 | # File systems | ||
1252 | # | ||
1253 | CONFIG_EXT2_FS=y | ||
1254 | # CONFIG_EXT2_FS_XATTR is not set | ||
1255 | # CONFIG_EXT2_FS_XIP is not set | ||
1256 | CONFIG_EXT3_FS=y | ||
1257 | # CONFIG_EXT3_FS_XATTR is not set | ||
1258 | # CONFIG_EXT4DEV_FS is not set | ||
1259 | CONFIG_JBD=y | ||
1260 | # CONFIG_REISERFS_FS is not set | ||
1261 | # CONFIG_JFS_FS is not set | ||
1262 | # CONFIG_FS_POSIX_ACL is not set | ||
1263 | CONFIG_XFS_FS=m | ||
1264 | CONFIG_XFS_QUOTA=y | ||
1265 | # CONFIG_XFS_POSIX_ACL is not set | ||
1266 | # CONFIG_XFS_RT is not set | ||
1267 | # CONFIG_XFS_DEBUG is not set | ||
1268 | # CONFIG_GFS2_FS is not set | ||
1269 | # CONFIG_OCFS2_FS is not set | ||
1270 | CONFIG_DNOTIFY=y | ||
1271 | CONFIG_INOTIFY=y | ||
1272 | CONFIG_INOTIFY_USER=y | ||
1273 | CONFIG_QUOTA=y | ||
1274 | # CONFIG_QUOTA_NETLINK_INTERFACE is not set | ||
1275 | CONFIG_PRINT_QUOTA_WARNING=y | ||
1276 | # CONFIG_QFMT_V1 is not set | ||
1277 | CONFIG_QFMT_V2=y | ||
1278 | CONFIG_QUOTACTL=y | ||
1279 | # CONFIG_AUTOFS_FS is not set | ||
1280 | # CONFIG_AUTOFS4_FS is not set | ||
1281 | # CONFIG_FUSE_FS is not set | ||
1282 | |||
1283 | # | ||
1284 | # CD-ROM/DVD Filesystems | ||
1285 | # | ||
1286 | CONFIG_ISO9660_FS=m | ||
1287 | CONFIG_JOLIET=y | ||
1288 | CONFIG_ZISOFS=y | ||
1289 | CONFIG_UDF_FS=m | ||
1290 | CONFIG_UDF_NLS=y | ||
1291 | |||
1292 | # | ||
1293 | # DOS/FAT/NT Filesystems | ||
1294 | # | ||
1295 | CONFIG_FAT_FS=y | ||
1296 | CONFIG_MSDOS_FS=y | ||
1297 | CONFIG_VFAT_FS=y | ||
1298 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
1299 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
1300 | CONFIG_NTFS_FS=m | ||
1301 | # CONFIG_NTFS_DEBUG is not set | ||
1302 | # CONFIG_NTFS_RW is not set | ||
1303 | |||
1304 | # | ||
1305 | # Pseudo filesystems | ||
1306 | # | ||
1307 | CONFIG_PROC_FS=y | ||
1308 | CONFIG_PROC_SYSCTL=y | ||
1309 | CONFIG_SYSFS=y | ||
1310 | CONFIG_TMPFS=y | ||
1311 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
1312 | # CONFIG_HUGETLB_PAGE is not set | ||
1313 | # CONFIG_CONFIGFS_FS is not set | ||
1314 | |||
1315 | # | ||
1316 | # Miscellaneous filesystems | ||
1317 | # | ||
1318 | # CONFIG_ADFS_FS is not set | ||
1319 | # CONFIG_AFFS_FS is not set | ||
1320 | # CONFIG_HFS_FS is not set | ||
1321 | CONFIG_HFSPLUS_FS=m | ||
1322 | # CONFIG_BEFS_FS is not set | ||
1323 | # CONFIG_BFS_FS is not set | ||
1324 | # CONFIG_EFS_FS is not set | ||
1325 | CONFIG_JFFS2_FS=y | ||
1326 | CONFIG_JFFS2_FS_DEBUG=0 | ||
1327 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
1328 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
1329 | CONFIG_JFFS2_SUMMARY=y | ||
1330 | # CONFIG_JFFS2_FS_XATTR is not set | ||
1331 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
1332 | CONFIG_JFFS2_ZLIB=y | ||
1333 | # CONFIG_JFFS2_LZO is not set | ||
1334 | CONFIG_JFFS2_RTIME=y | ||
1335 | # CONFIG_JFFS2_RUBIN is not set | ||
1336 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
1337 | CONFIG_JFFS2_CMODE_PRIORITY=y | ||
1338 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
1339 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | ||
1340 | CONFIG_CRAMFS=m | ||
1341 | # CONFIG_VXFS_FS is not set | ||
1342 | # CONFIG_MINIX_FS is not set | ||
1343 | # CONFIG_HPFS_FS is not set | ||
1344 | # CONFIG_QNX4FS_FS is not set | ||
1345 | # CONFIG_ROMFS_FS is not set | ||
1346 | # CONFIG_SYSV_FS is not set | ||
1347 | # CONFIG_UFS_FS is not set | ||
1348 | CONFIG_NETWORK_FILESYSTEMS=y | ||
1349 | # CONFIG_NFS_FS is not set | ||
1350 | # CONFIG_NFSD is not set | ||
1351 | # CONFIG_SMB_FS is not set | ||
1352 | # CONFIG_CIFS is not set | ||
1353 | # CONFIG_NCP_FS is not set | ||
1354 | # CONFIG_CODA_FS is not set | ||
1355 | # CONFIG_AFS_FS is not set | ||
1356 | |||
1357 | # | ||
1358 | # Partition Types | ||
1359 | # | ||
1360 | CONFIG_PARTITION_ADVANCED=y | ||
1361 | # CONFIG_ACORN_PARTITION is not set | ||
1362 | # CONFIG_OSF_PARTITION is not set | ||
1363 | # CONFIG_AMIGA_PARTITION is not set | ||
1364 | # CONFIG_ATARI_PARTITION is not set | ||
1365 | CONFIG_MAC_PARTITION=y | ||
1366 | CONFIG_MSDOS_PARTITION=y | ||
1367 | CONFIG_BSD_DISKLABEL=y | ||
1368 | # CONFIG_MINIX_SUBPARTITION is not set | ||
1369 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
1370 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
1371 | # CONFIG_LDM_PARTITION is not set | ||
1372 | # CONFIG_SGI_PARTITION is not set | ||
1373 | # CONFIG_ULTRIX_PARTITION is not set | ||
1374 | # CONFIG_SUN_PARTITION is not set | ||
1375 | # CONFIG_KARMA_PARTITION is not set | ||
1376 | # CONFIG_EFI_PARTITION is not set | ||
1377 | # CONFIG_SYSV68_PARTITION is not set | ||
1378 | CONFIG_NLS=y | ||
1379 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
1380 | CONFIG_NLS_CODEPAGE_437=y | ||
1381 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
1382 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
1383 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
1384 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
1385 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
1386 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
1387 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
1388 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
1389 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
1390 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
1391 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
1392 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
1393 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
1394 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
1395 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
1396 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
1397 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
1398 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
1399 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
1400 | # CONFIG_NLS_ISO8859_8 is not set | ||
1401 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
1402 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
1403 | # CONFIG_NLS_ASCII is not set | ||
1404 | # CONFIG_NLS_ISO8859_1 is not set | ||
1405 | # CONFIG_NLS_ISO8859_2 is not set | ||
1406 | # CONFIG_NLS_ISO8859_3 is not set | ||
1407 | # CONFIG_NLS_ISO8859_4 is not set | ||
1408 | # CONFIG_NLS_ISO8859_5 is not set | ||
1409 | # CONFIG_NLS_ISO8859_6 is not set | ||
1410 | # CONFIG_NLS_ISO8859_7 is not set | ||
1411 | # CONFIG_NLS_ISO8859_9 is not set | ||
1412 | # CONFIG_NLS_ISO8859_13 is not set | ||
1413 | # CONFIG_NLS_ISO8859_14 is not set | ||
1414 | # CONFIG_NLS_ISO8859_15 is not set | ||
1415 | # CONFIG_NLS_KOI8_R is not set | ||
1416 | # CONFIG_NLS_KOI8_U is not set | ||
1417 | CONFIG_NLS_UTF8=m | ||
1418 | # CONFIG_DLM is not set | ||
1419 | |||
1420 | # | ||
1421 | # Kernel hacking | ||
1422 | # | ||
1423 | # CONFIG_PRINTK_TIME is not set | ||
1424 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
1425 | CONFIG_ENABLE_MUST_CHECK=y | ||
1426 | CONFIG_FRAME_WARN=1024 | ||
1427 | CONFIG_MAGIC_SYSRQ=y | ||
1428 | # CONFIG_UNUSED_SYMBOLS is not set | ||
1429 | # CONFIG_DEBUG_FS is not set | ||
1430 | # CONFIG_HEADERS_CHECK is not set | ||
1431 | CONFIG_DEBUG_KERNEL=y | ||
1432 | # CONFIG_DEBUG_SHIRQ is not set | ||
1433 | CONFIG_DETECT_SOFTLOCKUP=y | ||
1434 | CONFIG_SCHED_DEBUG=y | ||
1435 | # CONFIG_SCHEDSTATS is not set | ||
1436 | # CONFIG_TIMER_STATS is not set | ||
1437 | # CONFIG_DEBUG_OBJECTS is not set | ||
1438 | # CONFIG_DEBUG_SLAB is not set | ||
1439 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
1440 | # CONFIG_RT_MUTEX_TESTER is not set | ||
1441 | # CONFIG_DEBUG_SPINLOCK is not set | ||
1442 | CONFIG_DEBUG_MUTEXES=y | ||
1443 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
1444 | # CONFIG_PROVE_LOCKING is not set | ||
1445 | # CONFIG_LOCK_STAT is not set | ||
1446 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
1447 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
1448 | # CONFIG_DEBUG_KOBJECT is not set | ||
1449 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
1450 | CONFIG_DEBUG_INFO=y | ||
1451 | # CONFIG_DEBUG_VM is not set | ||
1452 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
1453 | # CONFIG_DEBUG_LIST is not set | ||
1454 | # CONFIG_DEBUG_SG is not set | ||
1455 | CONFIG_FRAME_POINTER=y | ||
1456 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
1457 | # CONFIG_RCU_TORTURE_TEST is not set | ||
1458 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
1459 | # CONFIG_FAULT_INJECTION is not set | ||
1460 | # CONFIG_SAMPLES is not set | ||
1461 | # CONFIG_DEBUG_USER is not set | ||
1462 | # CONFIG_DEBUG_ERRORS is not set | ||
1463 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
1464 | CONFIG_DEBUG_LL=y | ||
1465 | # CONFIG_DEBUG_ICEDCC is not set | ||
1466 | |||
1467 | # | ||
1468 | # Security options | ||
1469 | # | ||
1470 | # CONFIG_KEYS is not set | ||
1471 | # CONFIG_SECURITY is not set | ||
1472 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
1473 | CONFIG_CRYPTO=y | ||
1474 | |||
1475 | # | ||
1476 | # Crypto core or helper | ||
1477 | # | ||
1478 | CONFIG_CRYPTO_ALGAPI=y | ||
1479 | CONFIG_CRYPTO_BLKCIPHER=y | ||
1480 | CONFIG_CRYPTO_MANAGER=y | ||
1481 | # CONFIG_CRYPTO_GF128MUL is not set | ||
1482 | # CONFIG_CRYPTO_NULL is not set | ||
1483 | # CONFIG_CRYPTO_CRYPTD is not set | ||
1484 | # CONFIG_CRYPTO_AUTHENC is not set | ||
1485 | # CONFIG_CRYPTO_TEST is not set | ||
1486 | |||
1487 | # | ||
1488 | # Authenticated Encryption with Associated Data | ||
1489 | # | ||
1490 | # CONFIG_CRYPTO_CCM is not set | ||
1491 | # CONFIG_CRYPTO_GCM is not set | ||
1492 | # CONFIG_CRYPTO_SEQIV is not set | ||
1493 | |||
1494 | # | ||
1495 | # Block modes | ||
1496 | # | ||
1497 | CONFIG_CRYPTO_CBC=y | ||
1498 | # CONFIG_CRYPTO_CTR is not set | ||
1499 | # CONFIG_CRYPTO_CTS is not set | ||
1500 | CONFIG_CRYPTO_ECB=m | ||
1501 | # CONFIG_CRYPTO_LRW is not set | ||
1502 | CONFIG_CRYPTO_PCBC=m | ||
1503 | # CONFIG_CRYPTO_XTS is not set | ||
1504 | |||
1505 | # | ||
1506 | # Hash modes | ||
1507 | # | ||
1508 | # CONFIG_CRYPTO_HMAC is not set | ||
1509 | # CONFIG_CRYPTO_XCBC is not set | ||
1510 | |||
1511 | # | ||
1512 | # Digest | ||
1513 | # | ||
1514 | # CONFIG_CRYPTO_CRC32C is not set | ||
1515 | # CONFIG_CRYPTO_MD4 is not set | ||
1516 | CONFIG_CRYPTO_MD5=y | ||
1517 | CONFIG_CRYPTO_MICHAEL_MIC=m | ||
1518 | CONFIG_CRYPTO_SHA1=m | ||
1519 | # CONFIG_CRYPTO_SHA256 is not set | ||
1520 | # CONFIG_CRYPTO_SHA512 is not set | ||
1521 | # CONFIG_CRYPTO_TGR192 is not set | ||
1522 | # CONFIG_CRYPTO_WP512 is not set | ||
1523 | |||
1524 | # | ||
1525 | # Ciphers | ||
1526 | # | ||
1527 | CONFIG_CRYPTO_AES=m | ||
1528 | # CONFIG_CRYPTO_ANUBIS is not set | ||
1529 | CONFIG_CRYPTO_ARC4=m | ||
1530 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
1531 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
1532 | # CONFIG_CRYPTO_CAST5 is not set | ||
1533 | # CONFIG_CRYPTO_CAST6 is not set | ||
1534 | CONFIG_CRYPTO_DES=y | ||
1535 | # CONFIG_CRYPTO_FCRYPT is not set | ||
1536 | # CONFIG_CRYPTO_KHAZAD is not set | ||
1537 | # CONFIG_CRYPTO_SALSA20 is not set | ||
1538 | # CONFIG_CRYPTO_SEED is not set | ||
1539 | # CONFIG_CRYPTO_SERPENT is not set | ||
1540 | # CONFIG_CRYPTO_TEA is not set | ||
1541 | # CONFIG_CRYPTO_TWOFISH is not set | ||
1542 | |||
1543 | # | ||
1544 | # Compression | ||
1545 | # | ||
1546 | # CONFIG_CRYPTO_DEFLATE is not set | ||
1547 | # CONFIG_CRYPTO_LZO is not set | ||
1548 | CONFIG_CRYPTO_HW=y | ||
1549 | |||
1550 | # | ||
1551 | # Library routines | ||
1552 | # | ||
1553 | CONFIG_BITREVERSE=y | ||
1554 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | ||
1555 | # CONFIG_GENERIC_FIND_NEXT_BIT is not set | ||
1556 | CONFIG_CRC_CCITT=y | ||
1557 | # CONFIG_CRC16 is not set | ||
1558 | CONFIG_CRC_ITU_T=m | ||
1559 | CONFIG_CRC32=y | ||
1560 | # CONFIG_CRC7 is not set | ||
1561 | CONFIG_LIBCRC32C=y | ||
1562 | CONFIG_ZLIB_INFLATE=y | ||
1563 | CONFIG_ZLIB_DEFLATE=y | ||
1564 | CONFIG_PLIST=y | ||
1565 | CONFIG_HAS_IOMEM=y | ||
1566 | CONFIG_HAS_IOPORT=y | ||
1567 | CONFIG_HAS_DMA=y | ||
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-empty-flash-warnings.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-empty-flash-warnings.patch new file mode 100644 index 0000000000..ab344b0449 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-empty-flash-warnings.patch | |||
@@ -0,0 +1,15 @@ | |||
1 | diff --git a/fs/jffs2/scan.c b/fs/jffs2/scan.c | ||
2 | index 1d437de..33b3feb 100644 | ||
3 | --- a/fs/jffs2/scan.c | ||
4 | +++ b/fs/jffs2/scan.c | ||
5 | @@ -647,8 +647,8 @@ scan_more: | ||
6 | inbuf_ofs = ofs - buf_ofs; | ||
7 | while (inbuf_ofs < scan_end) { | ||
8 | if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) { | ||
9 | - printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n", | ||
10 | - empty_start, ofs); | ||
11 | +// printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n", | ||
12 | +// empty_start, ofs); | ||
13 | if ((err = jffs2_scan_dirty_space(c, jeb, ofs-empty_start))) | ||
14 | return err; | ||
15 | goto scan_more; | ||
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-harry-potter.diff b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-harry-potter.diff new file mode 100644 index 0000000000..2bb20ab9c0 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-harry-potter.diff | |||
@@ -0,0 +1,11 @@ | |||
1 | --- /tmp/Makefile 2008-04-24 14:36:20.509598016 +0200 | ||
2 | +++ git/arch/arm/Makefile 2008-04-24 14:36:31.949546584 +0200 | ||
3 | @@ -47,7 +47,7 @@ | ||
4 | # Note that GCC does not numerically define an architecture version | ||
5 | # macro, but instead defines a whole series of macros which makes | ||
6 | # testing for a specific architecture or later rather impossible. | ||
7 | -arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a) | ||
8 | +arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a) | ||
9 | arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6) | ||
10 | # Only override the compiler option if ARMv6. The ARMv6K extensions are | ||
11 | # always available in ARMv7 | ||