10 files changed, 4536 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch
new file mode 100644
index 0000000000..550a4f58be
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch
@@ -0,0 +1,1002 @@
+From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+To: linux-omap@vger.kernel.org
+Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+Subject: [PATCH 1/3] ARM: OMAP: SmartReflex driver, reference source and header files
+Date:   Mon,  2 Jun 2008 14:30:12 +0300
+The following patch set integrates TI's SmartReflex driver. SmartReflex is a
+module that adjusts OMAP3 VDD1 and VDD2 operating voltages around the nominal
+values of current operating point depending on silicon characteristics and
+operating conditions.
+The driver creates two sysfs entries into /sys/power/ named "sr_vdd1_autocomp"
+and "sr_vdd2_autocomp" which can be used to activate SmartReflex modules 1 and
+2.
+Use the following commands to enable SmartReflex:
+echo -n 1 > /sys/power/sr_vdd1_autocomp
+echo -n 1 > /sys/power/sr_vdd2_autocomp
+To disable:
+echo -n 0 > /sys/power/sr_vdd1_autocomp
+echo -n 0 > /sys/power/sr_vdd2_autocomp
+This particular patch adds the TI reference source and header files for
+SmartReflex. Only modifications include minor styling to pass checkpatch.pl
+test.
+Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+---
+ arch/arm/mach-omap2/smartreflex.c |  815 +++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/smartreflex.h |  136 ++++++
+ 2 files changed, 951 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/smartreflex.c
+ create mode 100644 arch/arm/mach-omap2/smartreflex.h
+diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
+new file mode 100644
+index 0000000..dae7460
+--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.c
+@@ -0,0 +1,815 @@
+/*
+ * linux/arch/arm/mach-omap3/smartreflex.c
+ *
+ * OMAP34XX SmartReflex Voltage Control
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysfs.h>
+
+#include <asm/arch/prcm.h>
+#include <asm/arch/power_companion.h>
+#include <linux/io.h>
+
+#include "prcm-regs.h"
+#include "smartreflex.h"
+
+
+/* #define DEBUG_SR 1 */
+#ifdef DEBUG_SR
+#  define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__ ,\
+                                                                       ## args)
+#else
+#  define DPRINTK(fmt, args...)
+#endif
+
+struct omap_sr{
+       int srid;
+       int is_sr_reset;
+       int is_autocomp_active;
+       struct clk *fck;
+       u32 req_opp_no;
+       u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue;
+       u32 senp_mod, senn_mod;
+       u32 srbase_addr;
+       u32 vpbase_addr;
+};
+
+static struct omap_sr sr1 = {
+       .srid = SR1,
+       .is_sr_reset = 1,
+       .is_autocomp_active = 0,
+       .srbase_addr = OMAP34XX_SR1_BASE,
+};
+
+static struct omap_sr sr2 = {
+       .srid = SR2,
+       .is_sr_reset = 1,
+       .is_autocomp_active = 0,
+       .srbase_addr = OMAP34XX_SR2_BASE,
+};
+
+static inline void sr_write_reg(struct omap_sr *sr, int offset, u32 value)
+{
+       omap_writel(value, sr->srbase_addr + offset);
+}
+
+static inline void sr_modify_reg(struct omap_sr *sr, int offset, u32 mask,
+                                                               u32 value)
+{
+       u32 reg_val;
+
+       reg_val = omap_readl(sr->srbase_addr + offset);
+       reg_val &= ~mask;
+       reg_val |= value;
+
+       omap_writel(reg_val, sr->srbase_addr + offset);
+}
+
+static inline u32 sr_read_reg(struct omap_sr *sr, int offset)
+{
+       return omap_readl(sr->srbase_addr + offset);
+}
+
+
+#ifndef USE_EFUSE_VALUES
+static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
+{
+       u32 gn, rn, mul;
+
+       for (gn = 0; gn < GAIN_MAXLIMIT; gn++) {
+               mul = 1 << (gn + 8);
+               rn = mul / sensor;
+               if (rn < R_MAXLIMIT) {
+                       *sengain = gn;
+                       *rnsen = rn;
+               }
+       }
+}
+#endif
+
+static int sr_clk_enable(struct omap_sr *sr)
+{
+       if (clk_enable(sr->fck) != 0) {
+               printk(KERN_ERR "Could not enable sr%d_fck\n", sr->srid);
+               goto clk_enable_err;
+       }
+
+       /* set fclk- active , iclk- idle */
+       sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
+                                               SR_CLKACTIVITY_IOFF_FON);
+
+       return 0;
+
+clk_enable_err:
+       return -1;
+}
+
+static int sr_clk_disable(struct omap_sr *sr)
+{
+       /* set fclk, iclk- idle */
+       sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
+                                               SR_CLKACTIVITY_IOFF_FOFF);
+
+       clk_disable(sr->fck);
+       sr->is_sr_reset = 1;
+
+       return 0;
+}
+
+static void sr_set_nvalues(struct omap_sr *sr)
+{
+#ifdef USE_EFUSE_VALUES
+       u32 n1, n2;
+#else
+       u32 senpval, sennval;
+       u32 senpgain, senngain;
+       u32 rnsenp, rnsenn;
+#endif
+
+       if (sr->srid == SR1) {
+#ifdef USE_EFUSE_VALUES
+               /* Read values for VDD1 from EFUSE */
+#else
+               /* since E-Fuse Values are not available, calculating the
+                * reciprocal of the SenN and SenP values for SR1
+                */
+               sr->senp_mod = 0x03;        /* SenN-M5 enabled */
+               sr->senn_mod = 0x03;
+
+               /* for OPP5 */
+               senpval = 0x848 + 0x330;
+               sennval = 0xacd + 0x330;
+
+               cal_reciprocal(senpval, &senpgain, &rnsenp);
+               cal_reciprocal(sennval, &senngain, &rnsenn);
+
+               sr->opp5_nvalue =
+                               ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+                               (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+                               (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+                               (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+               /* for OPP4 */
+               senpval = 0x727 + 0x2a0;
+               sennval = 0x964 + 0x2a0;
+
+               cal_reciprocal(senpval, &senpgain, &rnsenp);
+               cal_reciprocal(sennval, &senngain, &rnsenn);
+
+               sr->opp4_nvalue =
+                               ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+                               (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+                               (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+                               (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+               /* for OPP3 */
+               senpval = 0x655 + 0x200;
+               sennval = 0x85b + 0x200;
+
+               cal_reciprocal(senpval, &senpgain, &rnsenp);
+               cal_reciprocal(sennval, &senngain, &rnsenn);
+
+               sr->opp3_nvalue =
+                               ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+                               (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+                               (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+                               (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+               /* for OPP2 */
+               senpval = 0x3be + 0x1a0;
+               sennval = 0x506 + 0x1a0;
+
+               cal_reciprocal(senpval, &senpgain, &rnsenp);
+               cal_reciprocal(sennval, &senngain, &rnsenn);
+
+               sr->opp2_nvalue =
+                               ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+                               (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+                               (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+                               (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+               /* for OPP1 */
+               senpval = 0x28c + 0x100;
+               sennval = 0x373 + 0x100;
+
+               cal_reciprocal(senpval, &senpgain, &rnsenp);
+               cal_reciprocal(sennval, &senngain, &rnsenn);
+
+               sr->opp1_nvalue =
+                               ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+                               (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+                               (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+                               (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+               sr_clk_enable(sr);
+               sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue);
+               sr_clk_disable(sr);
+
+#endif
+       } else if (sr->srid == SR2) {
+#ifdef USE_EFUSE_VALUES
+               /* Read values for VDD2 from EFUSE */
+#else
+               /* since E-Fuse Values are not available, calculating the
+                * reciprocal of the SenN and SenP values for SR2
+                */
+               sr->senp_mod = 0x03;
+               sr->senn_mod = 0x03;
+
+               /* for OPP3 */
+               senpval = 0x579 + 0x200;
+               sennval = 0x76f + 0x200;
+
+               cal_reciprocal(senpval, &senpgain, &rnsenp);
+               cal_reciprocal(sennval, &senngain, &rnsenn);
+
+               sr->opp3_nvalue =
+                               ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+                               (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+                               (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+                               (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+               /* for OPP2 */
+               senpval = 0x390 + 0x1c0;
+               sennval = 0x4f5 + 0x1c0;
+
+               cal_reciprocal(senpval, &senpgain, &rnsenp);
+               cal_reciprocal(sennval, &senngain, &rnsenn);
+
+               sr->opp2_nvalue =
+                               ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+                               (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+                               (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+                               (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+               /* for OPP1 */
+               senpval = 0x25d;
+               sennval = 0x359;
+
+               cal_reciprocal(senpval, &senpgain, &rnsenp);
+               cal_reciprocal(sennval, &senngain, &rnsenn);
+
+               sr->opp1_nvalue =
+                               ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+                               (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+                               (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+                               (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+#endif
+       }
+
+}
+
+static void sr_configure_vp(int srid)
+{
+       u32 vpconfig;
+
+       if (srid == SR1) {
+               vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN
+                       | PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN;
+
+               PRM_VP1_CONFIG = vpconfig;
+               PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
+                                               PRM_VP1_VSTEPMIN_VSTEPMIN;
+
+               PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
+                                               PRM_VP1_VSTEPMAX_VSTEPMAX;
+
+               PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX |
+                       PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT;
+
+               PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD;
+               PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD;
+
+       } else if (srid == SR2) {
+               vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN
+                       | PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN;
+
+               PRM_VP2_CONFIG = vpconfig;
+               PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
+                                               PRM_VP2_VSTEPMIN_VSTEPMIN;
+
+               PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
+                                               PRM_VP2_VSTEPMAX_VSTEPMAX;
+
+               PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX |
+                       PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT;
+
+               PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD;
+               PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD;
+
+       }
+}
+
+static void sr_configure_vc(void)
+{
+       PRM_VC_SMPS_SA =
+               (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) |
+               (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT);
+
+       PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) |
+                               (R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT);
+
+       PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) |
+                       (PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
+                       (PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) |
+                       (PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT);
+
+       PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) |
+                       (PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
+                       (PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) |
+                       (PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT);
+
+       PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1;
+
+       PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN
+                                                       | PRM_VC_I2C_CFG_SREN;
+
+       /* Setup voltctrl and other setup times */
+#ifdef CONFIG_SYSOFFMODE
+       PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET;
+       PRM_CLKSETUP = PRM_CLKSETUP_DURATION;
+       PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) |
+                       (PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET);
+       PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION;
+       PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION;
+#else
+       PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET;
+#endif
+
+}
+
+
+static void sr_configure(struct omap_sr *sr)
+{
+       u32 sys_clk, sr_clk_length = 0;
+       u32 sr_config;
+       u32 senp_en , senn_en;
+
+       senp_en = sr->senp_mod;
+       senn_en = sr->senn_mod;
+
+       sys_clk = prcm_get_system_clock_speed();
+
+       switch (sys_clk) {
+       case 12000:
+               sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+               break;
+       case 13000:
+               sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+               break;
+       case 19200:
+               sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+               break;
+       case 26000:
+               sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+               break;
+       case 38400:
+               sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+               break;
+       default :
+               printk(KERN_ERR "Invalid sysclk value\n");
+               break;
+       }
+
+       DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk);
+       if (sr->srid == SR1) {
+               sr_config = SR1_SRCONFIG_ACCUMDATA |
+                       (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+                       SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+                       SRCONFIG_MINMAXAVG_EN |
+                       (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
+                       (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
+                       SRCONFIG_DELAYCTRL;
+
+               sr_write_reg(sr, SRCONFIG, sr_config);
+
+               sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
+                                       SR1_AVGWEIGHT_SENNAVGWEIGHT);
+
+               sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
+                       SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+                       (SR1_ERRWEIGHT | SR1_ERRMAXLIMIT | SR1_ERRMINLIMIT));
+
+       } else if (sr->srid == SR2) {
+               sr_config = SR2_SRCONFIG_ACCUMDATA |
+                       (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+                       SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+                       SRCONFIG_MINMAXAVG_EN |
+                       (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
+                       (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
+                       SRCONFIG_DELAYCTRL;
+
+               sr_write_reg(sr, SRCONFIG, sr_config);
+
+               sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
+                                       SR2_AVGWEIGHT_SENNAVGWEIGHT);
+
+               sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
+                       SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+                       (SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
+
+       }
+       sr->is_sr_reset = 0;
+}
+
+static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
+{
+       u32 nvalue_reciprocal, current_nvalue;
+
+       sr->req_opp_no = target_opp_no;
+
+       if (sr->srid == SR1) {
+               switch (target_opp_no) {
+               case 5:
+                       nvalue_reciprocal = sr->opp5_nvalue;
+                       break;
+               case 4:
+                       nvalue_reciprocal = sr->opp4_nvalue;
+                       break;
+               case 3:
+                       nvalue_reciprocal = sr->opp3_nvalue;
+                       break;
+               case 2:
+                       nvalue_reciprocal = sr->opp2_nvalue;
+                       break;
+               case 1:
+                       nvalue_reciprocal = sr->opp1_nvalue;
+                       break;
+               default:
+                       nvalue_reciprocal = sr->opp3_nvalue;
+                       break;
+               }
+       } else {
+               switch (target_opp_no) {
+               case 3:
+                       nvalue_reciprocal = sr->opp3_nvalue;
+                       break;
+               case 2:
+                       nvalue_reciprocal = sr->opp2_nvalue;
+                       break;
+               case 1:
+                       nvalue_reciprocal = sr->opp1_nvalue;
+                       break;
+               default:
+                       nvalue_reciprocal = sr->opp3_nvalue;
+                       break;
+               }
+       }
+
+       current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL);
+
+       if (current_nvalue == nvalue_reciprocal) {
+               DPRINTK("System is already at the desired voltage level\n");
+               return;
+       }
+
+       sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
+
+       /* Enable the interrupt */
+       sr_modify_reg(sr, ERRCONFIG,
+                       (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
+                       (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
+
+       if (sr->srid == SR1) {
+               /* Enable VP1 */
+               PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE;
+       } else if (sr->srid == SR2) {
+               /* Enable VP2 */
+               PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE;
+       }
+
+       /* SRCONFIG - enable SR */
+       sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
+
+}
+
+static void sr_disable(struct omap_sr *sr)
+{
+       sr->is_sr_reset = 1;
+
+       /* SRCONFIG - disable SR */
+       sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE);
+
+       if (sr->srid == SR1) {
+               /* Enable VP1 */
+               PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
+       } else if (sr->srid == SR2) {
+               /* Enable VP2 */
+               PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
+       }
+}
+
+
+void sr_start_vddautocomap(int srid, u32 target_opp_no)
+{
+       struct omap_sr *sr = NULL;
+
+       if (srid == SR1)
+               sr = &sr1;
+       else if (srid == SR2)
+               sr = &sr2;
+
+       if (sr->is_sr_reset == 1) {
+               sr_clk_enable(sr);
+               sr_configure(sr);
+       }
+
+       if (sr->is_autocomp_active == 1)
+               DPRINTK(KERN_WARNING "SR%d: VDD autocomp is already active\n",
+                                                                       srid);
+
+       sr->is_autocomp_active = 1;
+       sr_enable(sr, target_opp_no);
+}
+EXPORT_SYMBOL(sr_start_vddautocomap);
+
+int sr_stop_vddautocomap(int srid)
+{
+       struct omap_sr *sr = NULL;
+
+       if (srid == SR1)
+               sr = &sr1;
+       else if (srid == SR2)
+               sr = &sr2;
+
+       if (sr->is_autocomp_active == 1) {
+               sr_disable(sr);
+               sr_clk_disable(sr);
+               sr->is_autocomp_active = 0;
+               return SR_TRUE;
+       } else {
+               DPRINTK(KERN_WARNING "SR%d: VDD autocomp is not active\n",
+                                                               srid);
+               return SR_FALSE;
+       }
+
+}
+EXPORT_SYMBOL(sr_stop_vddautocomap);
+
+void enable_smartreflex(int srid)
+{
+       u32 target_opp_no = 0;
+       struct omap_sr *sr = NULL;
+
+       if (srid == SR1)
+               sr = &sr1;
+       else if (srid == SR2)
+               sr = &sr2;
+
+       if (sr->is_autocomp_active == 1) {
+               if (sr->is_sr_reset == 1) {
+                       if (srid == SR1) {
+                               /* Enable SR clks */
+                               CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
+                               target_opp_no = get_opp_no(current_vdd1_opp);
+
+                       } else if (srid == SR2) {
+                               /* Enable SR clks */
+                               CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
+                               target_opp_no = get_opp_no(current_vdd2_opp);
+                       }
+
+                       sr_configure(sr);
+
+                       sr_enable(sr, target_opp_no);
+               }
+       }
+}
+
+void disable_smartreflex(int srid)
+{
+       struct omap_sr *sr = NULL;
+
+       if (srid == SR1)
+               sr = &sr1;
+       else if (srid == SR2)
+               sr = &sr2;
+
+       if (sr->is_autocomp_active == 1) {
+               if (srid == SR1) {
+                       /* Enable SR clk */
+                       CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
+
+               } else if (srid == SR2) {
+                       /* Enable SR clk */
+                       CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
+               }
+
+               if (sr->is_sr_reset == 0) {
+
+                       sr->is_sr_reset = 1;
+                       /* SRCONFIG - disable SR */
+                       sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+                                                       ~SRCONFIG_SRENABLE);
+
+                       if (sr->srid == SR1) {
+                               /* Disable SR clk */
+                               CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE;
+                               /* Enable VP1 */
+                               PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
+
+                       } else if (sr->srid == SR2) {
+                               /* Disable SR clk */
+                               CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE;
+                               /* Enable VP2 */
+                               PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
+                       }
+               }
+       }
+}
+
+
+/* Voltage Scaling using SR VCBYPASS */
+int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
+{
+       int ret;
+       int sr_status = 0;
+       u32 vdd, target_opp_no;
+       u32 vc_bypass_value;
+       u32 reg_addr = 0;
+       u32 loop_cnt = 0, retries_cnt = 0;
+
+       vdd = get_vdd(target_opp);
+       target_opp_no = get_opp_no(target_opp);
+
+       if (vdd == PRCM_VDD1) {
+               sr_status = sr_stop_vddautocomap(SR1);
+
+               PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) |
+                                               (vsel << PRM_VC_CMD_ON_SHIFT);
+               reg_addr = R_VDD1_SR_CONTROL;
+
+       } else if (vdd == PRCM_VDD2) {
+               sr_status = sr_stop_vddautocomap(SR2);
+
+               PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) |
+                                               (vsel << PRM_VC_CMD_ON_SHIFT);
+               reg_addr = R_VDD2_SR_CONTROL;
+       }
+
+       vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) |
+                       (reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) |
+                       (R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT);
+
+       PRM_VC_BYPASS_VAL = vc_bypass_value;
+
+       PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID;
+
+       DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL);
+       DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU);
+
+       while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) {
+               ret = loop_wait(&loop_cnt, &retries_cnt, 10);
+               if (ret != PRCM_PASS) {
+                       printk(KERN_INFO "Loop count exceeded in check SR I2C"
+                                                               "write\n");
+                       return ret;
+               }
+       }
+
+       omap_udelay(T2_SMPS_UPDATE_DELAY);
+
+       if (sr_status) {
+               if (vdd == PRCM_VDD1)
+                       sr_start_vddautocomap(SR1, target_opp_no);
+               else if (vdd == PRCM_VDD2)
+                       sr_start_vddautocomap(SR2, target_opp_no);
+       }
+
+       return SR_PASS;
+}
+
+/* Sysfs interface to select SR VDD1 auto compensation */
+static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf)
+{
+       return sprintf(buf, "%d\n", sr1.is_autocomp_active);
+}
+
+static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
+                               const char *buf, size_t n)
+{
+       u32 current_vdd1opp_no;
+       unsigned short value;
+
+       if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
+               printk(KERN_ERR "sr_vdd1_autocomp: Invalid value\n");
+               return -EINVAL;
+       }
+
+       current_vdd1opp_no = get_opp_no(current_vdd1_opp);
+
+       if (value == 0)
+               sr_stop_vddautocomap(SR1);
+       else
+               sr_start_vddautocomap(SR1, current_vdd1opp_no);
+
+       return n;
+}
+
+static struct subsys_attribute sr_vdd1_autocomp = {
+       .attr = {
+       .name = __stringify(sr_vdd1_autocomp),
+       .mode = 0644,
+       },
+       .show = omap_sr_vdd1_autocomp_show,
+       .store = omap_sr_vdd1_autocomp_store,
+};
+
+/* Sysfs interface to select SR VDD2 auto compensation */
+static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf)
+{
+       return sprintf(buf, "%d\n", sr2.is_autocomp_active);
+}
+
+static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
+                               const char *buf, size_t n)
+{
+       u32 current_vdd2opp_no;
+       unsigned short value;
+
+       if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
+               printk(KERN_ERR "sr_vdd2_autocomp: Invalid value\n");
+               return -EINVAL;
+       }
+
+       current_vdd2opp_no = get_opp_no(current_vdd2_opp);
+
+       if (value == 0)
+               sr_stop_vddautocomap(SR2);
+       else
+               sr_start_vddautocomap(SR2, current_vdd2opp_no);
+
+       return n;
+}
+
+static struct subsys_attribute sr_vdd2_autocomp = {
+       .attr = {
+       .name = __stringify(sr_vdd2_autocomp),
+       .mode = 0644,
+       },
+       .show = omap_sr_vdd2_autocomp_show,
+       .store = omap_sr_vdd2_autocomp_store,
+};
+
+
+
+static int __init omap3_sr_init(void)
+{
+       int ret = 0;
+       u8 RdReg;
+
+#ifdef CONFIG_ARCH_OMAP34XX
+       sr1.fck = clk_get(NULL, "sr1_fck");
+       if (IS_ERR(sr1.fck))
+               printk(KERN_ERR "Could not get sr1_fck\n");
+
+       sr2.fck = clk_get(NULL, "sr2_fck");
+       if (IS_ERR(sr2.fck))
+               printk(KERN_ERR "Could not get sr2_fck\n");
+#endif /* #ifdef CONFIG_ARCH_OMAP34XX */
+
+       /* Call the VPConfig, VCConfig, set N Values. */
+       sr_set_nvalues(&sr1);
+       sr_configure_vp(SR1);
+
+       sr_set_nvalues(&sr2);
+       sr_configure_vp(SR2);
+
+       sr_configure_vc();
+
+       /* Enable SR on T2 */
+       ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG);
+       RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
+       ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG);
+
+
+       printk(KERN_INFO "SmartReflex driver initialized\n");
+
+       ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp);
+       if (ret)
+               printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
+
+       ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp);
+       if (ret)
+               printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
+
+       return 0;
+}
+
+arch_initcall(omap3_sr_init);
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+new file mode 100644
+index 0000000..62907ef
+--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -0,0 +1,136 @@
+/*
+ * linux/arch/arm/mach-omap3/smartreflex.h
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* SR Modules */
+#define SR1            1
+#define SR2            2
+
+#define SR_FAIL                1
+#define SR_PASS                0
+
+#define SR_TRUE                1
+#define SR_FALSE       0
+
+#define GAIN_MAXLIMIT  16
+#define R_MAXLIMIT     256
+
+#define SR1_CLK_ENABLE (0x1 << 6)
+#define SR2_CLK_ENABLE (0x1 << 7)
+
+/* PRM_VP1_CONFIG */
+#define PRM_VP1_CONFIG_ERROROFFSET     (0x00 << 24)
+#define PRM_VP1_CONFIG_ERRORGAIN       (0x20 << 16)
+
+#define PRM_VP1_CONFIG_INITVOLTAGE     (0x30 << 8) /* 1.2 volt */
+#define PRM_VP1_CONFIG_TIMEOUTEN       (0x1 << 3)
+#define PRM_VP1_CONFIG_INITVDD         (0x1 << 2)
+#define PRM_VP1_CONFIG_FORCEUPDATE     (0x1 << 1)
+#define PRM_VP1_CONFIG_VPENABLE                (0x1 << 0)
+
+/* PRM_VP1_VSTEPMIN */
+#define PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN       (0x01F4 << 8)
+#define PRM_VP1_VSTEPMIN_VSTEPMIN              (0x01 << 0)
+
+/* PRM_VP1_VSTEPMAX */
+#define PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX       (0x01F4 << 8)
+#define PRM_VP1_VSTEPMAX_VSTEPMAX              (0x04 << 0)
+
+/* PRM_VP1_VLIMITTO */
+#define PRM_VP1_VLIMITTO_VDDMAX                (0x3C << 24)
+#define PRM_VP1_VLIMITTO_VDDMIN                (0x0 << 16)
+#define PRM_VP1_VLIMITTO_TIMEOUT       (0xFFFF << 0)
+
+/* PRM_VP2_CONFIG */
+#define PRM_VP2_CONFIG_ERROROFFSET     (0x00 << 24)
+#define PRM_VP2_CONFIG_ERRORGAIN       (0x20 << 16)
+
+#define PRM_VP2_CONFIG_INITVOLTAGE     (0x30 << 8) /* 1.2 volt */
+#define PRM_VP2_CONFIG_TIMEOUTEN       (0x1 << 3)
+#define PRM_VP2_CONFIG_INITVDD         (0x1 << 2)
+#define PRM_VP2_CONFIG_FORCEUPDATE     (0x1 << 1)
+#define PRM_VP2_CONFIG_VPENABLE                (0x1 << 0)
+
+/* PRM_VP2_VSTEPMIN */
+#define PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN       (0x01F4 << 8)
+#define PRM_VP2_VSTEPMIN_VSTEPMIN              (0x01 << 0)
+
+/* PRM_VP2_VSTEPMAX */
+#define PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX       (0x01F4 << 8)
+#define PRM_VP2_VSTEPMAX_VSTEPMAX              (0x04 << 0)
+
+/* PRM_VP2_VLIMITTO */
+#define PRM_VP2_VLIMITTO_VDDMAX                (0x2C << 24)
+#define PRM_VP2_VLIMITTO_VDDMIN                (0x0 << 16)
+#define PRM_VP2_VLIMITTO_TIMEOUT       (0xFFFF << 0)
+
+/* SRCONFIG */
+#define SR1_SRCONFIG_ACCUMDATA         (0x1F4 << 22)
+#define SR2_SRCONFIG_ACCUMDATA         (0x1F4 << 22)
+
+#define SRCLKLENGTH_12MHZ_SYSCLK       0x3C
+#define SRCLKLENGTH_13MHZ_SYSCLK       0x41
+#define SRCLKLENGTH_19MHZ_SYSCLK       0x60
+#define SRCLKLENGTH_26MHZ_SYSCLK       0x82
+#define SRCLKLENGTH_38MHZ_SYSCLK       0xC0
+
+#define SRCONFIG_SRCLKLENGTH_SHIFT     12
+#define SRCONFIG_SENNENABLE_SHIFT      5
+#define SRCONFIG_SENPENABLE_SHIFT      3
+
+#define SRCONFIG_SRENABLE              (0x01 << 11)
+#define SRCONFIG_SENENABLE             (0x01 << 10)
+#define SRCONFIG_ERRGEN_EN             (0x01 << 9)
+#define SRCONFIG_MINMAXAVG_EN          (0x01 << 8)
+
+#define SRCONFIG_DELAYCTRL             (0x01 << 2)
+#define SRCONFIG_CLKCTRL               (0x00 << 0)
+
+/* AVGWEIGHT */
+#define SR1_AVGWEIGHT_SENPAVGWEIGHT    (0x03 << 2)
+#define SR1_AVGWEIGHT_SENNAVGWEIGHT    (0x03 << 0)
+
+#define SR2_AVGWEIGHT_SENPAVGWEIGHT    (0x01 << 2)
+#define SR2_AVGWEIGHT_SENNAVGWEIGHT    (0x01 << 0)
+
+/* NVALUERECIPROCAL */
+#define NVALUERECIPROCAL_SENPGAIN_SHIFT        20
+#define NVALUERECIPROCAL_SENNGAIN_SHIFT        16
+#define NVALUERECIPROCAL_RNSENP_SHIFT  8
+#define NVALUERECIPROCAL_RNSENN_SHIFT  0
+
+/* ERRCONFIG */
+#define SR_CLKACTIVITY_MASK            (0x03 << 20)
+#define SR_ERRWEIGHT_MASK              (0x07 << 16)
+#define SR_ERRMAXLIMIT_MASK            (0xFF << 8)
+#define SR_ERRMINLIMIT_MASK            (0xFF << 0)
+
+#define SR_CLKACTIVITY_IOFF_FOFF       (0x00 << 20)
+#define SR_CLKACTIVITY_IOFF_FON                (0x02 << 20)
+
+#define ERRCONFIG_VPBOUNDINTEN         (0x1 << 31)
+#define ERRCONFIG_VPBOUNDINTST         (0x1 << 30)
+
+#define SR1_ERRWEIGHT                  (0x07 << 16)
+#define SR1_ERRMAXLIMIT                        (0x02 << 8)
+#define SR1_ERRMINLIMIT                        (0xFA << 0)
+
+#define SR2_ERRWEIGHT                  (0x07 << 16)
+#define SR2_ERRMAXLIMIT                        (0x02 << 8)
+#define SR2_ERRMINLIMIT                        (0xF9 << 0)
+
+extern u32 current_vdd1_opp;
+extern u32 current_vdd2_opp;
+extern struct kset power_subsys;
+
+extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
+extern void omap_udelay(u32 udelay);
+
+-- 
+1.5.4.3
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch
new file mode 100644
index 0000000000..6e31ead2bd
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch
@@ -0,0 +1,55 @@
+From a1dbb6dd28e9815a307b87b8d96dcf371d6cfd58 Mon Sep 17 00:00:00 2001
+From: Jarkko Nikula <jarkko.nikula@nokia.com>
+Date: Mon, 19 May 2008 13:24:41 +0300
+Subject: [PATCH] ASoC: OMAP: Add basic support for OMAP34xx in McBSP DAI driver
+This adds support for OMAP34xx McBSP port 1 and 2.
+Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com>
+---
+ sound/soc/omap/omap-mcbsp.c |   20 +++++++++++++++++++-
+ 1 files changed, 19 insertions(+), 1 deletions(-)
+diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
+index 40d87e6..8e6ec9d 100644
+--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
+@@ -99,6 +99,21 @@ static const unsigned long omap2420_mcbsp_port[][2] = {
+ static const int omap2420_dma_reqs[][2] = {};
+ static const unsigned long omap2420_mcbsp_port[][2] = {};
+ #endif
+#if defined(CONFIG_ARCH_OMAP34XX)
+static const int omap34xx_dma_reqs[][2] = {
+       { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
+       { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
+};
+static const unsigned long omap34xx_mcbsp_port[][2] = {
+       { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR2,
+         OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR2 },
+       { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR2,
+         OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR2 },
+};
+#else
+static const int omap34xx_dma_reqs[][2] = {};
+static const unsigned long omap34xx_mcbsp_port[][2] = {};
+#endif
+ 
+ static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream)
+ {
+@@ -169,9 +184,12 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
+        } else if (cpu_is_omap2420()) {
+                dma = omap2420_dma_reqs[bus_id][substream->stream];
+                port = omap2420_mcbsp_port[bus_id][substream->stream];
+       } else if (cpu_is_omap343x()) {
+               dma = omap34xx_dma_reqs[bus_id][substream->stream];
+               port = omap34xx_mcbsp_port[bus_id][substream->stream];
+        } else {
+                /*
+-                * TODO: Add support for 2430 and 3430
+                * TODO: Add support for 2430
+                 */
+                return -ENODEV;
+        }
+-- 
+1.5.5.1
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch
new file mode 100644
index 0000000000..cdc9447b4c
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch
@@ -0,0 +1,450 @@
+From: "Rajendra Nayak" <rnayak@ti.com>
+To: <linux-omap@vger.kernel.org>
+Subject: [PATCH 01/02] OMAP3 CPUidle driver
+Date:   Tue, 10 Jun 2008 12:39:00 +0530
+This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver
+before it queries the governor for the next state.
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>   
+---
+ arch/arm/mach-omap2/Makefile      |    2 
+ arch/arm/mach-omap2/cpuidle34xx.c |  293 ++++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/cpuidle34xx.h |   51 ++++++
+ arch/arm/mach-omap2/pm34xx.c      |    5 
+ drivers/cpuidle/cpuidle.c         |   10 +
+ 5 files changed, 359 insertions(+), 2 deletions(-)
+Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile
+===================================================================
+--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile    2008-06-09 20:15:33.855303920 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530
+@@ -20,7 +20,7 @@ obj-y                                 += pm.o
+ obj-$(CONFIG_ARCH_OMAP2)               += pm24xx.o
+ obj-$(CONFIG_ARCH_OMAP2420)            += sleep242x.o
+ obj-$(CONFIG_ARCH_OMAP2430)            += sleep243x.o
+-obj-$(CONFIG_ARCH_OMAP3)               += pm34xx.o sleep34xx.o
+obj-$(CONFIG_ARCH_OMAP3)               += pm34xx.o sleep34xx.o cpuidle34xx.o
+ obj-$(CONFIG_PM_DEBUG)                 += pm-debug.o
+ endif
+ 
+Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c
+===================================================================
+--- /dev/null   1970-01-01 00:00:00.000000000 +0000
+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c    2008-06-10 11:41:27.644820323 +0530
+@@ -0,0 +1,293 @@
+/*
+ * linux/arch/arm/mach-omap2/cpuidle34xx.c
+ *
+ * OMAP3 CPU IDLE Routines
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Karthik Dasu <karthik-dp@ti.com>
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ * Tony Lindgren <tony@atomide.com>
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/cpuidle.h>
+#include <asm/arch/pm.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/powerdomain.h>
+#include <asm/arch/clockdomain.h>
+#include <asm/arch/irqs.h>
+#include "cpuidle34xx.h"
+
+#ifdef CONFIG_CPU_IDLE
+
+struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
+struct omap3_processor_cx current_cx_state;
+
+static int omap3_idle_bm_check(void)
+{
+       /* Check for omap3_fclks_active() here once available */
+       return 0;
+}
+
+/* omap3_enter_idle - Programs OMAP3 to enter the specified state.
+ * returns the total time during which the system was idle.
+ */
+static int omap3_enter_idle(struct cpuidle_device *dev,
+                       struct cpuidle_state *state)
+{
+       struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
+       struct timespec ts_preidle, ts_postidle, ts_idle;
+       struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;
+       int neon_pwrst;
+
+       current_cx_state = *cx;
+
+       if (cx->type == OMAP3_STATE_C0) {
+               /* Do nothing for C0, not even a wfi */
+               return 0;
+       }
+
+       /* Used to keep track of the total time in idle */
+       getnstimeofday(&ts_preidle);
+
+       mpu_pd = pwrdm_lookup("mpu_pwrdm");
+       core_pd = pwrdm_lookup("core_pwrdm");
+       per_pd = pwrdm_lookup("per_pwrdm");
+       neon_pd = pwrdm_lookup("neon_pwrdm");
+
+       /* Reset previous power state registers */
+       pwrdm_clear_all_prev_pwrst(mpu_pd);
+       pwrdm_clear_all_prev_pwrst(neon_pd);
+       pwrdm_clear_all_prev_pwrst(core_pd);
+       pwrdm_clear_all_prev_pwrst(per_pd);
+
+       if (omap_irq_pending())
+               return 0;
+
+       neon_pwrst = pwrdm_read_pwrst(neon_pd);
+
+       /* Program MPU/NEON to target state */
+       if (cx->mpu_state < PWRDM_POWER_ON) {
+               if (neon_pwrst == PWRDM_POWER_ON) {
+                        if (cx->mpu_state == PWRDM_POWER_RET)
+                                pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
+                        else if (cx->mpu_state == PWRDM_POWER_OFF)
+                                pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);
+               }
+               pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
+       }
+
+       /* Program CORE to target state */
+       if (cx->core_state < PWRDM_POWER_ON)
+               pwrdm_set_next_pwrst(core_pd, cx->core_state);
+
+       /* Execute ARM wfi */
+       omap_sram_idle();
+
+       /* Program MPU/NEON to ON */
+       if (cx->mpu_state < PWRDM_POWER_ON) {
+               if (neon_pwrst == PWRDM_POWER_ON)
+                       pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);
+               pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);
+       }
+
+       if (cx->core_state < PWRDM_POWER_ON)
+               pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);
+
+       getnstimeofday(&ts_postidle);
+       ts_idle = timespec_sub(ts_postidle, ts_preidle);
+       return timespec_to_ns(&ts_idle);
+}
+
+/*
+ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM
+ *
+ * This function checks for all the pre-requisites needed for OMAP3 to enter
+ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired
+ * C state.
+ */
+static int omap3_enter_idle_bm(struct cpuidle_device *dev,
+                              struct cpuidle_state *state)
+{
+       struct cpuidle_state *new_state = NULL;
+       int i, j;
+
+       if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
+
+               /* Find current state in list */
+               for (i = 0; i < OMAP3_MAX_STATES; i++)
+                       if (state == &dev->states[i])
+                               break;
+               BUG_ON(i == OMAP3_MAX_STATES);
+
+               /* Back up to non 'CHECK_BM' state */
+               for (j = i - 1;  j > 0; j--) {
+                       struct cpuidle_state *s = &dev->states[j];
+
+                       if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) {
+                               new_state = s;
+                               break;
+                       }
+               }
+
+               pr_debug("%s: Bus activity: Entering %s (instead of %s)\n",
+                       __FUNCTION__, new_state->name, state->name);
+       }
+
+       return omap3_enter_idle(dev, new_state ? : state);
+}
+
+DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
+
+/* omap3_init_power_states - Initialises the OMAP3 specific C states.
+ * Below is the desciption of each C state.
+ *
+       C0 . System executing code
+       C1 . MPU WFI + Core active
+       C2 . MPU CSWR + Core active
+       C3 . MPU OFF + Core active
+       C4 . MPU CSWR + Core CSWR
+       C5 . MPU OFF + Core CSWR
+       C6 . MPU OFF + Core OFF
+ */
+void omap_init_power_states(void)
+{
+       /* C0 . System executing code */
+       omap3_power_states[0].valid = 1;
+       omap3_power_states[0].type = OMAP3_STATE_C0;
+       omap3_power_states[0].sleep_latency = 0;
+       omap3_power_states[0].wakeup_latency = 0;
+       omap3_power_states[0].threshold = 0;
+       omap3_power_states[0].mpu_state = PWRDM_POWER_ON;
+       omap3_power_states[0].core_state = PWRDM_POWER_ON;
+       omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID |
+                               CPUIDLE_FLAG_SHALLOW;
+
+       /* C1 . MPU WFI + Core active */
+       omap3_power_states[1].valid = 1;
+       omap3_power_states[1].type = OMAP3_STATE_C1;
+       omap3_power_states[1].sleep_latency = 10;
+       omap3_power_states[1].wakeup_latency = 10;
+       omap3_power_states[1].threshold = 30;
+       omap3_power_states[1].mpu_state = PWRDM_POWER_ON;
+       omap3_power_states[1].core_state = PWRDM_POWER_ON;
+       omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID |
+                               CPUIDLE_FLAG_SHALLOW;
+
+       /* C2 . MPU CSWR + Core active */
+       omap3_power_states[2].valid = 1;
+       omap3_power_states[2].type = OMAP3_STATE_C2;
+       omap3_power_states[2].sleep_latency = 50;
+       omap3_power_states[2].wakeup_latency = 50;
+       omap3_power_states[2].threshold = 300;
+       omap3_power_states[2].mpu_state = PWRDM_POWER_RET;
+       omap3_power_states[2].core_state = PWRDM_POWER_ON;
+       omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID |
+                               CPUIDLE_FLAG_BALANCED;
+
+       /* C3 . MPU OFF + Core active */
+       omap3_power_states[3].valid = 0;
+       omap3_power_states[3].type = OMAP3_STATE_C3;
+       omap3_power_states[3].sleep_latency = 1500;
+       omap3_power_states[3].wakeup_latency = 1800;
+       omap3_power_states[3].threshold = 4000;
+       omap3_power_states[3].mpu_state = PWRDM_POWER_OFF;
+       omap3_power_states[3].core_state = PWRDM_POWER_RET;
+       omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID |
+                               CPUIDLE_FLAG_BALANCED;
+
+       /* C4 . MPU CSWR + Core CSWR*/
+       omap3_power_states[4].valid = 1;
+       omap3_power_states[4].type = OMAP3_STATE_C4;
+       omap3_power_states[4].sleep_latency = 2500;
+       omap3_power_states[4].wakeup_latency = 7500;
+       omap3_power_states[4].threshold = 12000;
+       omap3_power_states[4].mpu_state = PWRDM_POWER_RET;
+       omap3_power_states[4].core_state = PWRDM_POWER_RET;
+       omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID |
+                       CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
+
+       /* C5 . MPU OFF + Core CSWR */
+       omap3_power_states[5].valid = 0;
+       omap3_power_states[5].type = OMAP3_STATE_C5;
+       omap3_power_states[5].sleep_latency = 3000;
+       omap3_power_states[5].wakeup_latency = 8500;
+       omap3_power_states[5].threshold = 15000;
+       omap3_power_states[5].mpu_state = PWRDM_POWER_OFF;
+       omap3_power_states[5].core_state = PWRDM_POWER_RET;
+       omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID |
+                       CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
+
+       /* C6 . MPU OFF + Core OFF */
+       omap3_power_states[6].valid = 0;
+       omap3_power_states[6].type = OMAP3_STATE_C6;
+       omap3_power_states[6].sleep_latency = 10000;
+       omap3_power_states[6].wakeup_latency = 30000;
+       omap3_power_states[6].threshold = 300000;
+       omap3_power_states[6].mpu_state = PWRDM_POWER_OFF;
+       omap3_power_states[6].core_state = PWRDM_POWER_OFF;
+       omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID |
+                       CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM;
+}
+
+struct cpuidle_driver omap3_idle_driver = {
+       .name =         "omap3_idle",
+       .owner =        THIS_MODULE,
+};
+/*
+ * omap3_idle_init - Init routine for OMAP3 idle.
+ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w
+ * with the valid set of states.
+ */
+int omap3_idle_init(void)
+{
+       int i, count = 0;
+       struct omap3_processor_cx *cx;
+       struct cpuidle_state *state;
+       struct cpuidle_device *dev;
+
+       omap_init_power_states();
+       cpuidle_register_driver(&omap3_idle_driver);
+
+       dev = &per_cpu(omap3_idle_dev, smp_processor_id());
+
+       for (i = 0; i < OMAP3_MAX_STATES; i++) {
+               cx = &omap3_power_states[i];
+               state = &dev->states[count];
+
+               if (!cx->valid)
+                       continue;
+               cpuidle_set_statedata(state, cx);
+               state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
+               state->target_residency = cx->threshold;
+               state->flags = cx->flags;
+               state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
+                       omap3_enter_idle_bm : omap3_enter_idle;
+               sprintf(state->name, "C%d", count+1);
+               count++;
+       }
+
+       if (!count)
+               return -EINVAL;
+       dev->state_count = count;
+
+       if (cpuidle_register_device(dev)) {
+               printk(KERN_ERR "%s: CPUidle register device failed\n",
+                      __FUNCTION__);
+               return -EIO;
+       }
+
+       return 0;
+}
+__initcall(omap3_idle_init);
+#endif /* CONFIG_CPU_IDLE */
+Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h
+===================================================================
+--- /dev/null   1970-01-01 00:00:00.000000000 +0000
+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h    2008-06-09 20:15:39.569121361 +0530
+@@ -0,0 +1,51 @@
+/*
+ * linux/arch/arm/mach-omap2/cpuidle34xx.h
+ *
+ * OMAP3 cpuidle structure definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Written by Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * History:
+ *
+ */
+
+#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
+#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
+
+#define OMAP3_MAX_STATES 7
+#define OMAP3_STATE_C0 0 /* C0 - System executing code */
+#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */
+#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */
+#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */
+#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */
+#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
+#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */
+
+extern void omap_sram_idle(void);
+extern int omap3_irq_pending(void);
+
+struct omap3_processor_cx {
+       u8 valid;
+       u8 type;
+       u32 sleep_latency;
+       u32 wakeup_latency;
+       u32 mpu_state;
+       u32 core_state;
+       u32 threshold;
+       u32 flags;
+};
+
+void omap_init_power_states(void);
+int omap3_idle_init(void);
+
+#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */
+
+Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c
+===================================================================
+--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c    2008-06-09 20:15:33.855303920 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530
+@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle
+        return IRQ_HANDLED;
+ }
+ 
+-static void omap_sram_idle(void)
+void omap_sram_idle(void)
+ {
+        /* Variable to tell what needs to be saved and restored
+         * in omap_sram_idle*/
+@@ -156,6 +156,7 @@ static void omap_sram_idle(void)
+ 
+        mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
+        switch (mpu_next_state) {
+       case PWRDM_POWER_ON:
+        case PWRDM_POWER_RET:
+                /* No need to save context */
+                save_state = 0;
+@@ -386,7 +387,9 @@ int __init omap3_pm_init(void)
+ 
+        prcm_setup_regs();
+ 
+#ifndef CONFIG_CPU_IDLE
+        pm_idle = omap3_pm_idle;
+#endif
+ 
+ err1:
+        return ret;
+Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c
+===================================================================
+--- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c       2008-06-09 20:15:33.856303888 +0530
+++ linux-omap-2.6/drivers/cpuidle/cpuidle.c    2008-06-09 20:15:39.570121329 +0530
+@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void)
+                return;
+        }
+ 
+#ifdef CONFIG_ARCH_OMAP3
+       local_irq_disable();
+       local_fiq_disable();
+#endif
+
+        /* ask the governor for the next state */
+        next_state = cpuidle_curr_governor->select(dev);
+        if (need_resched())
+@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void)
+        target_state->time += (unsigned long long)dev->last_residency;
+        target_state->usage++;
+ 
+#ifdef CONFIG_ARCH_OMAP3
+       local_irq_enable();
+       local_fiq_enable();
+#endif
+
+        /* give the governor an opportunity to reflect on the outcome */
+        if (cpuidle_curr_governor->reflect)
+                cpuidle_curr_governor->reflect(dev);
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch
new file mode 100644
index 0000000000..17329be29b
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch
@@ -0,0 +1,69 @@
+From 7a444ee080c5f1a62ac5042f1e7926622b3e1ce7 Mon Sep 17 00:00:00 2001
+From: Koen Kooi <koen@openembedded.org>
+Date: Fri, 30 May 2008 13:43:36 +0200
+Subject: [PATCH] ARM: OMAP: omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver
+omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver
+ * on revision A5 and earlier board the two leds can't be controlled seperately, should be fixed in rev. B and C boards.
+Signed-off-by: Koen Kooi <koen@openembedded.org>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |   28 ++++++++++++++++++++++++++++
+ 1 files changed, 28 insertions(+), 0 deletions(-)
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index c992cc7..83891fc 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -19,6 +19,7 @@
+ #include <linux/err.h>
+ #include <linux/clk.h>
+ #include <linux/io.h>
+#include <linux/leds.h>
+ 
+ #include <asm/hardware.h>
+ #include <asm/mach-types.h>
+@@ -72,6 +73,32 @@ static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
+        .ctrl_name      = "internal",
+ };
+ 
+struct gpio_led gpio_leds[] = {
+       {
+               .name = "beagleboard::led0",
+               .default_trigger = "none",
+               .gpio = 149,
+       },
+       {
+               .name = "beagleboard::led1",
+               .default_trigger = "none",
+               .gpio = 150,
+       },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+       .leds = gpio_leds,
+       .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+       .name = "leds-gpio",
+       .id   = -1,
+       .dev  = {
+               .platform_data = &gpio_led_info,
+       },
+};
+
+ static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
+        { OMAP_TAG_UART,        &omap3_beagle_uart_config },
+        { OMAP_TAG_MMC,         &omap3beagle_mmc_config },
+@@ -83,6 +110,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
+ #ifdef CONFIG_RTC_DRV_TWL4030
+        &omap3_beagle_twl4030rtc_device,
+ #endif
+       &leds_gpio,
+ };
+ 
+ static void __init omap3_beagle_init(void)
+-- 
+1.5.4.3
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch
new file mode 100644
index 0000000000..8e609395a0
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch
@@ -0,0 +1,278 @@
+From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+To: linux-omap@vger.kernel.org
+Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+Subject: [PATCH 2/3] ARM: OMAP: SmartReflex driver: added required register and bit definitions.
+Date:   Fri,  6 Jun 2008 12:49:48 +0300
+Added new register and bit definitions to enable Smartreflex driver integration.
+Also PRM_VC_SMPS_SA bit definitions' naming was changed to match the naming of
+other similar bit definitions.
+Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+---
+ arch/arm/mach-omap2/prm-regbits-34xx.h |   27 ++++++--
+ arch/arm/mach-omap2/smartreflex.h      |  124 ++++++++++++++++++++++++++++++-
+ include/asm-arm/arch-omap/control.h    |   19 +++++
+ include/asm-arm/arch-omap/omap34xx.h   |    2 +
+ 4 files changed, 163 insertions(+), 9 deletions(-)
+diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
+index c6a7940..f82b5a7 100644
+--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
+@@ -435,10 +435,10 @@
+ /* PM_PWSTST_EMU specific bits */
+ 
+ /* PRM_VC_SMPS_SA */
+-#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT              16
+-#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK               (0x7f << 16)
+-#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT              0
+-#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK               (0x7f << 0)
+#define OMAP3430_SMPS_SA1_SHIFT                                16
+#define OMAP3430_SMPS_SA1_MASK                         (0x7f << 16)
+#define OMAP3430_SMPS_SA0_SHIFT                                0
+#define OMAP3430_SMPS_SA0_MASK                         (0x7f << 0)
+ 
+ /* PRM_VC_SMPS_VOL_RA */
+ #define OMAP3430_VOLRA1_SHIFT                          16
+@@ -452,7 +452,7 @@
+ #define OMAP3430_CMDRA0_SHIFT                          0
+ #define OMAP3430_CMDRA0_MASK                           (0xff << 0)
+ 
+-/* PRM_VC_CMD_VAL_0 specific bits */
+/* PRM_VC_CMD_VAL */
+ #define OMAP3430_VC_CMD_ON_SHIFT                       24
+ #define OMAP3430_VC_CMD_ON_MASK                                (0xFF << 24)
+ #define OMAP3430_VC_CMD_ONLP_SHIFT                     16
+@@ -462,7 +462,17 @@
+ #define OMAP3430_VC_CMD_OFF_SHIFT                      0
+ #define OMAP3430_VC_CMD_OFF_MASK                       (0xFF << 0)
+ 
+/* PRM_VC_CMD_VAL_0 specific bits */
+#define OMAP3430_VC_CMD_VAL0_ON                                (0x3 << 4)
+#define OMAP3430_VC_CMD_VAL0_ONLP                      (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL0_RET                       (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL0_OFF                       (0x3 << 3)
+
+ /* PRM_VC_CMD_VAL_1 specific bits */
+#define OMAP3430_VC_CMD_VAL1_ON                                (0xB << 2)
+#define OMAP3430_VC_CMD_VAL1_ONLP                      (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL1_RET                       (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL1_OFF                       (0x3 << 3)
+ 
+ /* PRM_VC_CH_CONF */
+ #define OMAP3430_CMD1                                  (1 << 20)
+@@ -521,6 +531,13 @@
+ #define OMAP3430_AUTO_RET                              (1 << 1)
+ #define OMAP3430_AUTO_SLEEP                            (1 << 0)
+ 
+/* Constants to define setup durations */
+#define OMAP3430_CLKSETUP_DURATION                     0xff
+#define OMAP3430_VOLTSETUP_TIME2                       0xfff
+#define OMAP3430_VOLTSETUP_TIME1                       0xfff
+#define OMAP3430_VOLTOFFSET_DURATION                   0xff
+#define OMAP3430_VOLTSETUP2_DURATION                   0xff
+
+ /* PRM_SRAM_PCHARGE */
+ #define OMAP3430_PCHARGE_TIME_SHIFT                    0
+ #define OMAP3430_PCHARGE_TIME_MASK                     (0xff << 0)
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+index 62907ef..2091a15 100644
+--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -1,5 +1,10 @@
+#ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
+#define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
+ /*
+- * linux/arch/arm/mach-omap3/smartreflex.h
+ * linux/arch/arm/mach-omap2/smartreflex.h
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+  *
+  * Copyright (C) 2007 Texas Instruments, Inc.
+  * Lesly A M <x0080970@ti.com>
+@@ -9,6 +14,21 @@
+  * published by the Free Software Foundation.
+  */
+ 
+#define PHY_TO_OFF_PM_MASTER(p)                (p - 0x36)
+#define PHY_TO_OFF_PM_RECIEVER(p)      (p - 0x5b)
+#define PHY_TO_OFF_PM_INT(p)           (p - 0x2e)
+
+/* SMART REFLEX REG ADDRESS OFFSET */
+#define SRCONFIG       0x00
+#define SRSTATUS       0x04
+#define SENVAL         0x08
+#define SENMIN         0x0C
+#define SENMAX         0x10
+#define SENAVG         0x14
+#define AVGWEIGHT      0x18
+#define NVALUERECIPROCAL       0x1C
+#define SENERROR       0x20
+#define ERRCONFIG      0x24
+ 
+ /* SR Modules */
+ #define SR1            1
+@@ -127,10 +147,106 @@
+ #define SR2_ERRMAXLIMIT                        (0x02 << 8)
+ #define SR2_ERRMINLIMIT                        (0xF9 << 0)
+ 
+/* T2 SMART REFLEX */
+#define R_SRI2C_SLAVE_ADDR             0x12
+#define R_VDD1_SR_CONTROL              0x00
+#define R_VDD2_SR_CONTROL              0x01
+#define T2_SMPS_UPDATE_DELAY           360     /* In uSec */
+
+/* Vmode control */
+#define R_DCDC_GLOBAL_CFG      PHY_TO_OFF_PM_RECIEVER(0x61)
+
+#define R_VDD1_VSEL            PHY_TO_OFF_PM_RECIEVER(0xb9)
+#define R_VDD1_VMODE_CFG       PHY_TO_OFF_PM_RECIEVER(0xba)
+#define R_VDD1_VFLOOR          PHY_TO_OFF_PM_RECIEVER(0xbb)
+#define R_VDD1_VROOF           PHY_TO_OFF_PM_RECIEVER(0xbc)
+#define R_VDD1_STEP            PHY_TO_OFF_PM_RECIEVER(0xbd)
+
+#define R_VDD2_VSEL            PHY_TO_OFF_PM_RECIEVER(0xc7)
+#define R_VDD2_VMODE_CFG       PHY_TO_OFF_PM_RECIEVER(0xc8)
+#define R_VDD2_VFLOOR          PHY_TO_OFF_PM_RECIEVER(0xc9)
+#define R_VDD2_VROOF           PHY_TO_OFF_PM_RECIEVER(0xca)
+#define R_VDD2_STEP            PHY_TO_OFF_PM_RECIEVER(0xcb)
+
+/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE valuws */
+#define DCDC_GLOBAL_CFG_ENABLE_SRFLX   0x08
+
+/* VDDs*/
+#define PRCM_VDD1      1
+#define PRCM_VDD2      2
+#define PRCM_MAX_SYSC_REGS 30
+
+/* XXX: These should be removed/moved from here once we have a working DVFS
+   implementation in place */
+#define AT_3430                1       /*3430 ES 1.0 */
+#define AT_3430_ES2    2       /*3430 ES 2.0 */
+
+#define ID_OPP                 0xE2    /*OPP*/
+
+/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */
+#define OMAP_TYPE_SHIFT                28
+#define OMAP_TYPE_MASK         0xF
+/* OPP ID: bits: 0-4 for OPP number */
+#define OPP_NO_POS             0
+#define OPP_NO_MASK            0x1F
+/* OPP ID: bits: 5-6 for VDD */
+#define VDD_NO_POS             5
+#define VDD_NO_MASK            0x3
+/* Other IDs: bits 20-27 for ID type */
+/* These IDs have bits 25,26,27 as 1 */
+#define OTHER_ID_TYPE_SHIFT            20
+#define OTHER_ID_TYPE_MASK             0xFF
+
+#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT)
+#define ID_OPP_NO(X)    ((X & OPP_NO_MASK) << OPP_NO_POS)
+#define ID_VDD(X)       ((X & VDD_NO_MASK) << VDD_NO_POS)
+#define OMAP(X)                 ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK)
+#define get_opp_no(X)   ((X >> OPP_NO_POS) & OPP_NO_MASK)
+#define get_vdd(X)      ((X >> VDD_NO_POS) & VDD_NO_MASK)
+
+/* VDD1 OPPs */
+#define PRCM_VDD1_OPP1         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+                                       ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1))
+#define PRCM_VDD1_OPP2         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+                                       ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2))
+#define PRCM_VDD1_OPP3         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+                                       ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3))
+#define PRCM_VDD1_OPP4         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+                                       ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4))
+#define PRCM_VDD1_OPP5         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+                                       ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5))
+#define PRCM_NO_VDD1_OPPS      5
+
+
+/* VDD2 OPPs */
+#define PRCM_VDD2_OPP1         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+                                       ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1))
+#define PRCM_VDD2_OPP2         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+                                       ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2))
+#define PRCM_VDD2_OPP3         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+                                       ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3))
+#define PRCM_NO_VDD2_OPPS      3
+/* XXX: end remove/move */
+
+
+/* XXX: find more appropriate place for these once DVFS is in place */
+ extern u32 current_vdd1_opp;
+ extern u32 current_vdd2_opp;
+-extern struct kset power_subsys;
+ 
+-extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
+-extern void omap_udelay(u32 udelay);
+/*
+ * Smartreflex module enable/disable interface.
+ * NOTE: if smartreflex is not enabled from sysfs, these functions will not
+ * do anything.
+ */
+#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE)
+void enable_smartreflex(int srid);
+void disable_smartreflex(int srid);
+#else
+static inline void enable_smartreflex(int srid) {}
+static inline void disable_smartreflex(int srid) {}
+#endif
+
+
+#endif
+
+ 
+diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
+index 12bc22a..6e64fe7 100644
+--- a/include/asm-arm/arch-omap/control.h
+++ b/include/asm-arm/arch-omap/control.h
+@@ -138,6 +138,15 @@
+ #define OMAP343X_CONTROL_TEST_KEY_11   (OMAP2_CONTROL_GENERAL + 0x00f4)
+ #define OMAP343X_CONTROL_TEST_KEY_12   (OMAP2_CONTROL_GENERAL + 0x00f8)
+ #define OMAP343X_CONTROL_TEST_KEY_13   (OMAP2_CONTROL_GENERAL + 0x00fc)
+#define OMAP343X_CONTROL_FUSE_OPP1_VDD1        (OMAP2_CONTROL_GENERAL + 0x0110)
+#define OMAP343X_CONTROL_FUSE_OPP2_VDD1        (OMAP2_CONTROL_GENERAL + 0x0114)
+#define OMAP343X_CONTROL_FUSE_OPP3_VDD1        (OMAP2_CONTROL_GENERAL + 0x0118)
+#define OMAP343X_CONTROL_FUSE_OPP4_VDD1        (OMAP2_CONTROL_GENERAL + 0x011c)
+#define OMAP343X_CONTROL_FUSE_OPP5_VDD1        (OMAP2_CONTROL_GENERAL + 0x0120)
+#define OMAP343X_CONTROL_FUSE_OPP1_VDD2        (OMAP2_CONTROL_GENERAL + 0x0124)
+#define OMAP343X_CONTROL_FUSE_OPP2_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
+#define OMAP343X_CONTROL_FUSE_OPP3_VDD2        (OMAP2_CONTROL_GENERAL + 0x012c)
+#define OMAP343X_CONTROL_FUSE_SR       (OMAP2_CONTROL_GENERAL + 0x0130)
+ #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
+ #define OMAP343X_CONTROL_IVA2_BOOTMOD  (OMAP2_CONTROL_GENERAL + 0x0194)
+ #define OMAP343X_CONTROL_TEMP_SENSOR   (OMAP2_CONTROL_GENERAL + 0x02b4)
+@@ -172,6 +181,16 @@
+ #define OMAP2_SYSBOOT_1_MASK           (1 << 1)
+ #define OMAP2_SYSBOOT_0_MASK           (1 << 0)
+ 
+/* CONTROL_FUSE_SR bits */
+#define OMAP343X_SR2_SENNENABLE_MASK   (0x3 << 10)
+#define OMAP343X_SR2_SENNENABLE_SHIFT  10
+#define OMAP343X_SR2_SENPENABLE_MASK   (0x3 << 8)
+#define OMAP343X_SR2_SENPENABLE_SHIFT  8
+#define OMAP343X_SR1_SENNENABLE_MASK   (0x3 << 2)
+#define OMAP343X_SR1_SENNENABLE_SHIFT  2
+#define OMAP343X_SR1_SENPENABLE_MASK   (0x3 << 0)
+#define OMAP343X_SR1_SENPENABLE_SHIFT  0
+
+ #ifndef __ASSEMBLY__
+ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+ extern void __iomem *omap_ctrl_base_get(void);
+diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
+index 6a0459a..3667fd6 100644
+--- a/include/asm-arm/arch-omap/omap34xx.h
+++ b/include/asm-arm/arch-omap/omap34xx.h
+@@ -54,6 +54,8 @@
+ #define OMAP34XX_HSUSB_OTG_BASE        (L4_34XX_BASE + 0xAB000)
+ #define OMAP34XX_HSUSB_HOST_BASE       (L4_34XX_BASE + 0x64000)
+ #define OMAP34XX_USBTLL_BASE   (L4_34XX_BASE + 0x62000)
+#define OMAP34XX_SR1_BASE      0x480C9000
+#define OMAP34XX_SR2_BASE      0x480CB000
+ 
+ 
+ #if defined(CONFIG_ARCH_OMAP3430)
+-- 
+1.5.4.3
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch
new file mode 100644
index 0000000000..d35fd47567
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch
@@ -0,0 +1,88 @@
+From: "Rajendra Nayak" <rnayak@ti.com>
+To: <linux-omap@vger.kernel.org>
+Subject: [PATCH 02/02] Kconfig changes
+Date:   Tue, 10 Jun 2008 12:39:02 +0530
+Updates the CPUidle Kconfig
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>   
+---
+ arch/arm/Kconfig        |   10 ++++++++++
+ drivers/cpuidle/Kconfig |   28 ++++++++++++++++++++++------
+ 2 files changed, 32 insertions(+), 6 deletions(-)
+Index: linux-omap-2.6/arch/arm/Kconfig
+===================================================================
+--- linux-omap-2.6.orig/arch/arm/Kconfig        2008-06-10 11:43:10.790502713 +0530
+++ linux-omap-2.6/arch/arm/Kconfig     2008-06-10 11:43:38.701604549 +0530
+@@ -954,6 +954,16 @@ config ATAGS_PROC
+ 
+ endmenu
+ 
+if (ARCH_OMAP)
+
+menu "CPUIdle"
+
+source "drivers/cpuidle/Kconfig"
+
+endmenu
+
+endif
+
+ if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
+ 
+ menu "CPU Frequency scaling"
+Index: linux-omap-2.6/drivers/cpuidle/Kconfig
+===================================================================
+--- linux-omap-2.6.orig/drivers/cpuidle/Kconfig 2008-06-10 11:43:10.790502713 +0530
+++ linux-omap-2.6/drivers/cpuidle/Kconfig      2008-06-10 12:06:36.139332151 +0530
+@@ -1,20 +1,36 @@
+menu "CPU idle PM support"
+ 
+ config CPU_IDLE
+        bool "CPU idle PM support"
+-       default ACPI
+       default n
+        help
+          CPU idle is a generic framework for supporting software-controlled
+          idle processor power management.  It includes modular cross-platform
+          governors that can be swapped during runtime.
+ 
+-         If you're using an ACPI-enabled platform, you should say Y here.
+         If you're using a mobile platform that supports CPU idle PM (e.g.
+         an ACPI-capable notebook), you should say Y here.
+
+if CPU_IDLE
+
+comment "Governors"
+ 
+ config CPU_IDLE_GOV_LADDER
+-       bool
+       bool "ladder"
+        depends on CPU_IDLE
+-       default y
+       default n
+ 
+ config CPU_IDLE_GOV_MENU
+-       bool
+       bool "menu"
+        depends on CPU_IDLE && NO_HZ
+-       default y
+       default n
+        help
+         This cpuidle governor evaluates all available states and chooses the
+         deepest state that meets all of the following constraints: BM activity,
+         expected time until next timer interrupt, and last break event time
+         delta.  It is designed to minimize power consumption.  Currently
+         dynticks is required.
+
+endif   # CPU_IDLE
+
+endmenu
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch
new file mode 100644
index 0000000000..40d5790367
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch
@@ -0,0 +1,1001 @@
+From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+To: linux-omap@vger.kernel.org
+Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+Subject: [PATCH 3/3] ARM: OMAP: SmartReflex driver: integration to linux-omap
+Date:   Fri,  6 Jun 2008 12:49:49 +0300
+Message-Id: <1212745789-13926-3-git-send-email-ext-kalle.jokiniemi@nokia.com>
+- Changed register accesses to use prm_{read,write}_mod_reg and
+  prm_{set,clear,rmw}_mod_reg_bits() functions instread of
+  "REG_X = REG_Y" type accesses.
+- Changed direct register clock enables/disables to clockframework calls.
+- replaced cpu-related #ifdefs with if (cpu_is_xxxx()) calls.
+- Added E-fuse support: Use silicon characteristics parameters from E-fuse
+- added smartreflex_disable/enable calls to pm34xx.c suspend function.
+- Added "SmartReflex support" entry into Kconfig under "System type->TI OMAP
+  Implementations". It depends on ARCH_OMAP34XX and TWL4030_CORE.
+- Added "SmartReflex testing support" Kconfig option for using hard coded
+  software parameters instead of E-fuse parameters.
+Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+---
+ arch/arm/mach-omap2/Makefile      |    3 +
+ arch/arm/mach-omap2/pm34xx.c      |    9 +
+ arch/arm/mach-omap2/smartreflex.c |  531 +++++++++++++++++++++++--------------
+ arch/arm/mach-omap2/smartreflex.h |    9 +-
+ arch/arm/plat-omap/Kconfig        |   31 +++
+ 5 files changed, 385 insertions(+), 198 deletions(-)
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 50c6657..f645b6e 100644
+--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
+@@ -25,6 +25,9 @@ obj-$(CONFIG_ARCH_OMAP3)              += pm34xx.o sleep34xx.o
+ obj-$(CONFIG_PM_DEBUG)                 += pm-debug.o
+ endif
+ 
+# SmartReflex driver
+obj-$(CONFIG_OMAP_SMARTREFLEX)         += smartreflex.o
+
+ # Clock framework
+ obj-$(CONFIG_ARCH_OMAP2)               += clock24xx.o
+ obj-$(CONFIG_ARCH_OMAP3)               += clock34xx.o
+diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
+index 7e775cc..3da4f47 100644
+--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
+@@ -36,6 +36,7 @@
+ 
+ #include "prm.h"
+ #include "pm.h"
+#include "smartreflex.h"
+ 
+ struct power_state {
+        struct powerdomain *pwrdm;
+@@ -256,6 +257,10 @@ static int omap3_pm_suspend(void)
+        struct power_state *pwrst;
+        int state, ret = 0;
+ 
+       /* XXX Disable smartreflex before entering suspend */
+       disable_smartreflex(SR1);
+       disable_smartreflex(SR2);
+
+        /* Read current next_pwrsts */
+        list_for_each_entry(pwrst, &pwrst_list, node)
+                pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
+@@ -287,6 +292,10 @@ restore:
+                printk(KERN_INFO "Successfully put all powerdomains "
+                       "to target state\n");
+ 
+       /* XXX Enable smartreflex after suspend */
+       enable_smartreflex(SR1);
+       enable_smartreflex(SR2);
+
+        return ret;
+ }
+ 
+diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
+index dae7460..0b10a5d 100644
+--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
+@@ -3,6 +3,9 @@
+  *
+  * OMAP34XX SmartReflex Voltage Control
+  *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+  * Copyright (C) 2007 Texas Instruments, Inc.
+  * Lesly A M <x0080970@ti.com>
+  *
+@@ -20,13 +23,16 @@
+ #include <linux/err.h>
+ #include <linux/clk.h>
+ #include <linux/sysfs.h>
+-
+-#include <asm/arch/prcm.h>
+-#include <asm/arch/power_companion.h>
+#include <linux/kobject.h>
+#include <linux/i2c/twl4030.h>
+ #include <linux/io.h>
+ 
+-#include "prcm-regs.h"
+#include <asm/arch/omap34xx.h>
+#include <asm/arch/control.h>
+
+#include "prm.h"
+ #include "smartreflex.h"
+#include "prm-regbits-34xx.h"
+ 
+ 
+ /* #define DEBUG_SR 1 */
+@@ -37,11 +43,16 @@
+ #  define DPRINTK(fmt, args...)
+ #endif
+ 
+/* XXX: These should be relocated where-ever the OPP implementation will be */
+u32 current_vdd1_opp;
+u32 current_vdd2_opp;
+
+ struct omap_sr{
+        int srid;
+        int is_sr_reset;
+        int is_autocomp_active;
+        struct clk *fck;
+       u32 clk_length;
+        u32 req_opp_no;
+        u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue;
+        u32 senp_mod, senn_mod;
+@@ -53,6 +64,7 @@ static struct omap_sr sr1 = {
+        .srid = SR1,
+        .is_sr_reset = 1,
+        .is_autocomp_active = 0,
+       .clk_length = 0,
+        .srbase_addr = OMAP34XX_SR1_BASE,
+ };
+ 
+@@ -60,6 +72,7 @@ static struct omap_sr sr2 = {
+        .srid = SR2,
+        .is_sr_reset = 1,
+        .is_autocomp_active = 0,
+       .clk_length = 0,
+        .srbase_addr = OMAP34XX_SR2_BASE,
+ };
+ 
+@@ -85,8 +98,6 @@ static inline u32 sr_read_reg(struct omap_sr *sr, int offset)
+        return omap_readl(sr->srbase_addr + offset);
+ }
+ 
+-
+-#ifndef USE_EFUSE_VALUES
+ static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
+ {
+        u32 gn, rn, mul;
+@@ -100,7 +111,21 @@ static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
+                }
+        }
+ }
+-#endif
+
+static void sr_clk_get(struct omap_sr *sr)
+{
+       if (sr->srid == SR1) {
+               sr->fck = clk_get(NULL, "sr1_fck");
+               if (IS_ERR(sr->fck))
+                       printk(KERN_ERR "Could not get sr1_fck\n");
+
+       } else if (sr->srid == SR2) {
+               sr->fck = clk_get(NULL, "sr2_fck");
+               if (IS_ERR(sr->fck))
+                       printk(KERN_ERR "Could not get sr2_fck\n");
+
+       }
+}
+ 
+ static int sr_clk_enable(struct omap_sr *sr)
+ {
+@@ -131,22 +156,86 @@ static int sr_clk_disable(struct omap_sr *sr)
+        return 0;
+ }
+ 
+-static void sr_set_nvalues(struct omap_sr *sr)
+static void sr_set_clk_length(struct omap_sr *sr)
+{
+       struct clk *osc_sys_ck;
+       u32 sys_clk = 0;
+
+       osc_sys_ck = clk_get(NULL, "osc_sys_ck");
+       sys_clk = clk_get_rate(osc_sys_ck);
+       clk_put(osc_sys_ck);
+
+       switch (sys_clk) {
+       case 12000000:
+               sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+               break;
+       case 13000000:
+               sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+               break;
+       case 19200000:
+               sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+               break;
+       case 26000000:
+               sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+               break;
+       case 38400000:
+               sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+               break;
+       default :
+               printk(KERN_ERR "Invalid sysclk value: %d\n", sys_clk);
+               break;
+       }
+}
+
+static void sr_set_efuse_nvalues(struct omap_sr *sr)
+{
+       if (sr->srid == SR1) {
+               sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+                                       OMAP343X_SR1_SENNENABLE_MASK) >>
+                                       OMAP343X_SR1_SENNENABLE_SHIFT;
+
+               sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+                                       OMAP343X_SR1_SENPENABLE_MASK) >>
+                                       OMAP343X_SR1_SENPENABLE_SHIFT;
+
+               sr->opp5_nvalue = omap_ctrl_readl(
+                                       OMAP343X_CONTROL_FUSE_OPP5_VDD1);
+               sr->opp4_nvalue = omap_ctrl_readl(
+                                       OMAP343X_CONTROL_FUSE_OPP4_VDD1);
+               sr->opp3_nvalue = omap_ctrl_readl(
+                                       OMAP343X_CONTROL_FUSE_OPP3_VDD1);
+               sr->opp2_nvalue = omap_ctrl_readl(
+                                       OMAP343X_CONTROL_FUSE_OPP2_VDD1);
+               sr->opp1_nvalue = omap_ctrl_readl(
+                                       OMAP343X_CONTROL_FUSE_OPP1_VDD1);
+       } else if (sr->srid == SR2) {
+               sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+                                       OMAP343X_SR2_SENNENABLE_MASK) >>
+                                       OMAP343X_SR2_SENNENABLE_SHIFT;
+
+               sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+                                       OMAP343X_SR2_SENPENABLE_MASK) >>
+                                       OMAP343X_SR2_SENPENABLE_SHIFT;
+
+               sr->opp3_nvalue = omap_ctrl_readl(
+                                       OMAP343X_CONTROL_FUSE_OPP3_VDD2);
+               sr->opp2_nvalue = omap_ctrl_readl(
+                                       OMAP343X_CONTROL_FUSE_OPP2_VDD2);
+               sr->opp1_nvalue = omap_ctrl_readl(
+                                       OMAP343X_CONTROL_FUSE_OPP1_VDD2);
+       }
+}
+
+/* Hard coded nvalues for testing purposes, may cause device to hang! */
+static void sr_set_testing_nvalues(struct omap_sr *sr)
+ {
+-#ifdef USE_EFUSE_VALUES
+-       u32 n1, n2;
+-#else
+        u32 senpval, sennval;
+        u32 senpgain, senngain;
+        u32 rnsenp, rnsenn;
+-#endif
+ 
+        if (sr->srid == SR1) {
+-#ifdef USE_EFUSE_VALUES
+-               /* Read values for VDD1 from EFUSE */
+-#else
+-               /* since E-Fuse Values are not available, calculating the
+-                * reciprocal of the SenN and SenP values for SR1
+               /* Calculating the reciprocal of the SenN and SenP values
+                * for SR1
+                 */
+                sr->senp_mod = 0x03;        /* SenN-M5 enabled */
+                sr->senn_mod = 0x03;
+@@ -216,15 +305,16 @@ static void sr_set_nvalues(struct omap_sr *sr)
+                                (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+                                (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+ 
+               /* XXX The clocks are enabled in the startup and NVALUE is
+                * set also there. Disabling this for now, but this could
+                * be related to dynamic sleep during boot */
+#if 0
+                sr_clk_enable(sr);
+                sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue);
+                sr_clk_disable(sr);
+-
+ #endif
+
+        } else if (sr->srid == SR2) {
+-#ifdef USE_EFUSE_VALUES
+-               /* Read values for VDD2 from EFUSE */
+-#else
+                /* since E-Fuse Values are not available, calculating the
+                 * reciprocal of the SenN and SenP values for SR2
+                 */
+@@ -269,134 +359,163 @@ static void sr_set_nvalues(struct omap_sr *sr)
+                                (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+                                (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+                                (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+-
+-#endif
+        }
+ 
+ }
+ 
+static void sr_set_nvalues(struct omap_sr *sr)
+{
+       if (SR_TESTING_NVALUES)
+               sr_set_testing_nvalues(sr);
+       else
+               sr_set_efuse_nvalues(sr);
+}
+
+ static void sr_configure_vp(int srid)
+ {
+        u32 vpconfig;
+ 
+        if (srid == SR1) {
+                vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN
+-                       | PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN;
+-
+-               PRM_VP1_CONFIG = vpconfig;
+-               PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
+-                                               PRM_VP1_VSTEPMIN_VSTEPMIN;
+-
+-               PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
+-                                               PRM_VP1_VSTEPMAX_VSTEPMAX;
+-
+-               PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX |
+-                       PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT;
+-
+-               PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD;
+-               PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD;
+                                       | PRM_VP1_CONFIG_INITVOLTAGE
+                                       | PRM_VP1_CONFIG_TIMEOUTEN;
+
+               prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP1_CONFIG_OFFSET);
+               prm_write_mod_reg(PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
+                                       PRM_VP1_VSTEPMIN_VSTEPMIN,
+                                       OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP1_VSTEPMIN_OFFSET);
+
+               prm_write_mod_reg(PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
+                                       PRM_VP1_VSTEPMAX_VSTEPMAX,
+                                       OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP1_VSTEPMAX_OFFSET);
+
+               prm_write_mod_reg(PRM_VP1_VLIMITTO_VDDMAX |
+                                       PRM_VP1_VLIMITTO_VDDMIN |
+                                       PRM_VP1_VLIMITTO_TIMEOUT,
+                                       OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP1_VLIMITTO_OFFSET);
+
+               /* Trigger initVDD value copy to voltage processor */
+               prm_set_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP1_CONFIG_OFFSET);
+               /* Clear initVDD copy trigger bit */
+               prm_clear_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP1_CONFIG_OFFSET);
+ 
+        } else if (srid == SR2) {
+                vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN
+-                       | PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN;
+-
+-               PRM_VP2_CONFIG = vpconfig;
+-               PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
+-                                               PRM_VP2_VSTEPMIN_VSTEPMIN;
+-
+-               PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
+-                                               PRM_VP2_VSTEPMAX_VSTEPMAX;
+-
+-               PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX |
+-                       PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT;
+-
+-               PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD;
+-               PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD;
+                                       | PRM_VP2_CONFIG_INITVOLTAGE
+                                       | PRM_VP2_CONFIG_TIMEOUTEN;
+
+               prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP2_CONFIG_OFFSET);
+               prm_write_mod_reg(PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
+                                       PRM_VP2_VSTEPMIN_VSTEPMIN,
+                                       OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP2_VSTEPMIN_OFFSET);
+
+               prm_write_mod_reg(PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
+                                       PRM_VP2_VSTEPMAX_VSTEPMAX,
+                                       OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP2_VSTEPMAX_OFFSET);
+
+               prm_write_mod_reg(PRM_VP2_VLIMITTO_VDDMAX |
+                                       PRM_VP2_VLIMITTO_VDDMIN |
+                                       PRM_VP2_VLIMITTO_TIMEOUT,
+                                       OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP2_VLIMITTO_OFFSET);
+
+               /* Trigger initVDD value copy to voltage processor */
+               prm_set_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP2_CONFIG_OFFSET);
+               /* Reset initVDD copy trigger bit */
+               prm_clear_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP2_CONFIG_OFFSET);
+ 
+        }
+ }
+ 
+ static void sr_configure_vc(void)
+ {
+-       PRM_VC_SMPS_SA =
+-               (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) |
+-               (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT);
+-
+-       PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) |
+-                               (R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT);
+-
+-       PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) |
+-                       (PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
+-                       (PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) |
+-                       (PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT);
+-
+-       PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) |
+-                       (PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
+-                       (PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) |
+-                       (PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT);
+-
+-       PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1;
+-
+-       PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN
+-                                                       | PRM_VC_I2C_CFG_SREN;
+       prm_write_mod_reg((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) |
+                       (R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT),
+                       OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
+
+       prm_write_mod_reg((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) |
+                       (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
+                       OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
+
+       prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON <<
+               OMAP3430_VC_CMD_ON_SHIFT) |
+               (OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
+               (OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) |
+               (OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
+               OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
+
+       prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON <<
+               OMAP3430_VC_CMD_ON_SHIFT) |
+               (OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
+               (OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) |
+               (OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
+               OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
+
+       prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
+                               OMAP3430_GR_MOD,
+                               OMAP3_PRM_VC_CH_CONF_OFFSET);
+
+       prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
+                               OMAP3430_GR_MOD,
+                               OMAP3_PRM_VC_I2C_CFG_OFFSET);
+ 
+        /* Setup voltctrl and other setup times */
+       /* XXX CONFIG_SYSOFFMODE has not been implemented yet */
+ #ifdef CONFIG_SYSOFFMODE
+-       PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET;
+-       PRM_CLKSETUP = PRM_CLKSETUP_DURATION;
+-       PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) |
+-                       (PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET);
+-       PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION;
+-       PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION;
+       prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET,
+                       OMAP3430_GR_MOD,
+                       OMAP3_PRM_VOLTCTRL_OFFSET);
+
+       prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
+                       OMAP3_PRM_CLKSETUP_OFFSET);
+       prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 <<
+                       OMAP3430_VOLTSETUP_TIME2_OFFSET) |
+                       (OMAP3430_VOLTSETUP_TIME1 <<
+                       OMAP3430_VOLTSETUP_TIME1_OFFSET),
+                       OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
+
+       prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
+                       OMAP3_PRM_VOLTOFFSET_OFFSET);
+       prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
+                       OMAP3_PRM_VOLTSETUP2_OFFSET);
+ #else
+-       PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET;
+       prm_set_mod_reg_bits(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
+                       OMAP3_PRM_VOLTCTRL_OFFSET);
+ #endif
+ 
+ }
+ 
+-
+ static void sr_configure(struct omap_sr *sr)
+ {
+-       u32 sys_clk, sr_clk_length = 0;
+        u32 sr_config;
+        u32 senp_en , senn_en;
+ 
+       if (sr->clk_length == 0)
+               sr_set_clk_length(sr);
+
+        senp_en = sr->senp_mod;
+        senn_en = sr->senn_mod;
+-
+-       sys_clk = prcm_get_system_clock_speed();
+-
+-       switch (sys_clk) {
+-       case 12000:
+-               sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+-               break;
+-       case 13000:
+-               sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+-               break;
+-       case 19200:
+-               sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+-               break;
+-       case 26000:
+-               sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+-               break;
+-       case 38400:
+-               sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+-               break;
+-       default :
+-               printk(KERN_ERR "Invalid sysclk value\n");
+-               break;
+-       }
+-
+-       DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk);
+        if (sr->srid == SR1) {
+                sr_config = SR1_SRCONFIG_ACCUMDATA |
+-                       (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+                       (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+                        SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+                        SRCONFIG_MINMAXAVG_EN |
+                        (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
+                        (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
+                        SRCONFIG_DELAYCTRL;
+-
+               DPRINTK(KERN_DEBUG "setting SRCONFIG1 to 0x%08lx\n",
+                                               (unsigned long int) sr_config);
+                sr_write_reg(sr, SRCONFIG, sr_config);
+ 
+                sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
+@@ -408,18 +527,18 @@ static void sr_configure(struct omap_sr *sr)
+ 
+        } else if (sr->srid == SR2) {
+                sr_config = SR2_SRCONFIG_ACCUMDATA |
+-                       (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+                       (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+                        SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+                        SRCONFIG_MINMAXAVG_EN |
+                        (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
+                        (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
+                        SRCONFIG_DELAYCTRL;
+ 
+               DPRINTK(KERN_DEBUG "setting SRCONFIG2 to 0x%08lx\n",
+                                               (unsigned long int) sr_config);
+                sr_write_reg(sr, SRCONFIG, sr_config);
+-
+                sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
+                                        SR2_AVGWEIGHT_SENNAVGWEIGHT);
+-
+                sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
+                        SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+                        (SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
+@@ -428,9 +547,9 @@ static void sr_configure(struct omap_sr *sr)
+        sr->is_sr_reset = 0;
+ }
+ 
+-static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
+static int sr_enable(struct omap_sr *sr, u32 target_opp_no)
+ {
+-       u32 nvalue_reciprocal, current_nvalue;
+       u32 nvalue_reciprocal;
+ 
+        sr->req_opp_no = target_opp_no;
+ 
+@@ -472,11 +591,10 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
+                }
+        }
+ 
+-       current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL);
+-
+-       if (current_nvalue == nvalue_reciprocal) {
+-               DPRINTK("System is already at the desired voltage level\n");
+-               return;
+       if (nvalue_reciprocal == 0) {
+               printk(KERN_NOTICE "OPP%d doesn't support SmartReflex\n",
+                                                               target_opp_no);
+               return SR_FALSE;
+        }
+ 
+        sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
+@@ -485,18 +603,19 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
+        sr_modify_reg(sr, ERRCONFIG,
+                        (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
+                        (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
+-
+        if (sr->srid == SR1) {
+                /* Enable VP1 */
+-               PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE;
+               prm_set_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD,
+                               OMAP3_PRM_VP1_CONFIG_OFFSET);
+        } else if (sr->srid == SR2) {
+                /* Enable VP2 */
+-               PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE;
+               prm_set_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD,
+                               OMAP3_PRM_VP2_CONFIG_OFFSET);
+        }
+ 
+        /* SRCONFIG - enable SR */
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
+-
+       return SR_TRUE;
+ }
+ 
+ static void sr_disable(struct omap_sr *sr)
+@@ -507,11 +626,13 @@ static void sr_disable(struct omap_sr *sr)
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE);
+ 
+        if (sr->srid == SR1) {
+-               /* Enable VP1 */
+-               PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
+               /* Disable VP1 */
+               prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP1_CONFIG_OFFSET);
+        } else if (sr->srid == SR2) {
+-               /* Enable VP2 */
+-               PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
+               /* Disable VP2 */
+               prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VP2_CONFIG_OFFSET);
+        }
+ }
+ 
+@@ -535,7 +656,12 @@ void sr_start_vddautocomap(int srid, u32 target_opp_no)
+                                                                        srid);
+ 
+        sr->is_autocomp_active = 1;
+-       sr_enable(sr, target_opp_no);
+       if (!sr_enable(sr, target_opp_no)) {
+               printk(KERN_WARNING "SR%d: VDD autocomp not activated\n", srid);
+               sr->is_autocomp_active = 0;
+               if (sr->is_sr_reset == 1)
+                       sr_clk_disable(sr);
+       }
+ }
+ EXPORT_SYMBOL(sr_start_vddautocomap);
+ 
+@@ -574,20 +700,18 @@ void enable_smartreflex(int srid)
+ 
+        if (sr->is_autocomp_active == 1) {
+                if (sr->is_sr_reset == 1) {
+-                       if (srid == SR1) {
+-                               /* Enable SR clks */
+-                               CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
+-                               target_opp_no = get_opp_no(current_vdd1_opp);
+                       /* Enable SR clks */
+                       sr_clk_enable(sr);
+ 
+-                       } else if (srid == SR2) {
+-                               /* Enable SR clks */
+-                               CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
+                       if (srid == SR1)
+                               target_opp_no = get_opp_no(current_vdd1_opp);
+                       else if (srid == SR2)
+                                target_opp_no = get_opp_no(current_vdd2_opp);
+-                       }
+ 
+                        sr_configure(sr);
+ 
+-                       sr_enable(sr, target_opp_no);
+                       if (!sr_enable(sr, target_opp_no))
+                               sr_clk_disable(sr);
+                }
+        }
+ }
+@@ -602,15 +726,6 @@ void disable_smartreflex(int srid)
+                sr = &sr2;
+ 
+        if (sr->is_autocomp_active == 1) {
+-               if (srid == SR1) {
+-                       /* Enable SR clk */
+-                       CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
+-
+-               } else if (srid == SR2) {
+-                       /* Enable SR clk */
+-                       CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
+-               }
+-
+                if (sr->is_sr_reset == 0) {
+ 
+                        sr->is_sr_reset = 1;
+@@ -618,17 +733,18 @@ void disable_smartreflex(int srid)
+                        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+                                                        ~SRCONFIG_SRENABLE);
+ 
+                       /* Disable SR clk */
+                       sr_clk_disable(sr);
+                        if (sr->srid == SR1) {
+-                               /* Disable SR clk */
+-                               CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE;
+-                               /* Enable VP1 */
+-                               PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
+-
+                               /* Disable VP1 */
+                               prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE,
+                                               OMAP3430_GR_MOD,
+                                               OMAP3_PRM_VP1_CONFIG_OFFSET);
+                        } else if (sr->srid == SR2) {
+-                               /* Disable SR clk */
+-                               CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE;
+-                               /* Enable VP2 */
+-                               PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
+                               /* Disable VP2 */
+                               prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE,
+                                               OMAP3430_GR_MOD,
+                                               OMAP3_PRM_VP2_CONFIG_OFFSET);
+                        }
+                }
+        }
+@@ -638,7 +754,6 @@ void disable_smartreflex(int srid)
+ /* Voltage Scaling using SR VCBYPASS */
+ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
+ {
+-       int ret;
+        int sr_status = 0;
+        u32 vdd, target_opp_no;
+        u32 vc_bypass_value;
+@@ -651,39 +766,53 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
+        if (vdd == PRCM_VDD1) {
+                sr_status = sr_stop_vddautocomap(SR1);
+ 
+-               PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) |
+-                                               (vsel << PRM_VC_CMD_ON_SHIFT);
+               prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
+                                       (vsel << OMAP3430_VC_CMD_ON_SHIFT),
+                                       OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
+                reg_addr = R_VDD1_SR_CONTROL;
+ 
+        } else if (vdd == PRCM_VDD2) {
+                sr_status = sr_stop_vddautocomap(SR2);
+ 
+-               PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) |
+-                                               (vsel << PRM_VC_CMD_ON_SHIFT);
+               prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
+                                       (vsel << OMAP3430_VC_CMD_ON_SHIFT),
+                                       OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
+                reg_addr = R_VDD2_SR_CONTROL;
+        }
+ 
+-       vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) |
+-                       (reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) |
+-                       (R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT);
+       vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) |
+                       (reg_addr << OMAP3430_REGADDR_SHIFT) |
+                       (R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT);
+ 
+-       PRM_VC_BYPASS_VAL = vc_bypass_value;
+       prm_write_mod_reg(vc_bypass_value, OMAP3430_GR_MOD,
+                       OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
+ 
+-       PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID;
+       vc_bypass_value = prm_set_mod_reg_bits(OMAP3430_VALID, OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
+ 
+-       DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL);
+-       DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU);
+       DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, vc_bypass_value);
+       DPRINTK("PRM_IRQST_MPU %X\n", prm_read_mod_reg(OCP_MOD,
+                                       OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
+ 
+-       while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) {
+-               ret = loop_wait(&loop_cnt, &retries_cnt, 10);
+-               if (ret != PRCM_PASS) {
+       while ((vc_bypass_value & OMAP3430_VALID) != 0x0) {
+               loop_cnt++;
+               if (retries_cnt > 10) {
+                        printk(KERN_INFO "Loop count exceeded in check SR I2C"
+                                                                "write\n");
+-                       return ret;
+                       return SR_FAIL;
+               }
+               if (loop_cnt > 50) {
+                       retries_cnt++;
+                       loop_cnt = 0;
+                       udelay(10);
+                }
+               vc_bypass_value = prm_read_mod_reg(OMAP3430_GR_MOD,
+                                       OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
+        }
+ 
+-       omap_udelay(T2_SMPS_UPDATE_DELAY);
+       udelay(T2_SMPS_UPDATE_DELAY);
+ 
+        if (sr_status) {
+                if (vdd == PRCM_VDD1)
+@@ -696,13 +825,15 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
+ }
+ 
+ /* Sysfs interface to select SR VDD1 auto compensation */
+-static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf)
+static ssize_t omap_sr_vdd1_autocomp_show(struct kobject *kobj,
+                                       struct kobj_attribute *attr, char *buf)
+ {
+        return sprintf(buf, "%d\n", sr1.is_autocomp_active);
+ }
+ 
+-static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
+-                               const char *buf, size_t n)
+static ssize_t omap_sr_vdd1_autocomp_store(struct kobject *kobj,
+                                       struct kobj_attribute *attr,
+                                       const char *buf, size_t n)
+ {
+        u32 current_vdd1opp_no;
+        unsigned short value;
+@@ -722,7 +853,7 @@ static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
+        return n;
+ }
+ 
+-static struct subsys_attribute sr_vdd1_autocomp = {
+static struct kobj_attribute sr_vdd1_autocomp = {
+        .attr = {
+        .name = __stringify(sr_vdd1_autocomp),
+        .mode = 0644,
+@@ -732,13 +863,15 @@ static struct subsys_attribute sr_vdd1_autocomp = {
+ };
+ 
+ /* Sysfs interface to select SR VDD2 auto compensation */
+-static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf)
+static ssize_t omap_sr_vdd2_autocomp_show(struct kobject *kobj,
+                                       struct kobj_attribute *attr, char *buf)
+ {
+        return sprintf(buf, "%d\n", sr2.is_autocomp_active);
+ }
+ 
+-static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
+-                               const char *buf, size_t n)
+static ssize_t omap_sr_vdd2_autocomp_store(struct kobject *kobj,
+                                       struct kobj_attribute *attr,
+                                       const char *buf, size_t n)
+ {
+        u32 current_vdd2opp_no;
+        unsigned short value;
+@@ -758,7 +891,7 @@ static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
+        return n;
+ }
+ 
+-static struct subsys_attribute sr_vdd2_autocomp = {
+static struct kobj_attribute sr_vdd2_autocomp = {
+        .attr = {
+        .name = __stringify(sr_vdd2_autocomp),
+        .mode = 0644,
+@@ -774,15 +907,19 @@ static int __init omap3_sr_init(void)
+        int ret = 0;
+        u8 RdReg;
+ 
+-#ifdef CONFIG_ARCH_OMAP34XX
+-       sr1.fck = clk_get(NULL, "sr1_fck");
+-       if (IS_ERR(sr1.fck))
+-               printk(KERN_ERR "Could not get sr1_fck\n");
+-
+-       sr2.fck = clk_get(NULL, "sr2_fck");
+-       if (IS_ERR(sr2.fck))
+-               printk(KERN_ERR "Could not get sr2_fck\n");
+-#endif /* #ifdef CONFIG_ARCH_OMAP34XX */
+       if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+               current_vdd1_opp = PRCM_VDD1_OPP3;
+               current_vdd2_opp = PRCM_VDD2_OPP3;
+       } else {
+               current_vdd1_opp = PRCM_VDD1_OPP1;
+               current_vdd2_opp = PRCM_VDD1_OPP1;
+       }
+       if (cpu_is_omap34xx()) {
+               sr_clk_get(&sr1);
+               sr_clk_get(&sr2);
+       }
+       sr_set_clk_length(&sr1);
+       sr_set_clk_length(&sr2);
+ 
+        /* Call the VPConfig, VCConfig, set N Values. */
+        sr_set_nvalues(&sr1);
+@@ -794,22 +931,24 @@ static int __init omap3_sr_init(void)
+        sr_configure_vc();
+ 
+        /* Enable SR on T2 */
+-       ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG);
+-       RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
+-       ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG);
+       ret = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &RdReg,
+                                       R_DCDC_GLOBAL_CFG);
+ 
+       RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
+       ret |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, RdReg,
+                                       R_DCDC_GLOBAL_CFG);
+ 
+        printk(KERN_INFO "SmartReflex driver initialized\n");
+ 
+-       ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp);
+       ret = sysfs_create_file(power_kobj, &sr_vdd1_autocomp.attr);
+        if (ret)
+-               printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
+               printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);
+ 
+-       ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp);
+       ret = sysfs_create_file(power_kobj, &sr_vdd2_autocomp.attr);
+        if (ret)
+-               printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
+               printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);
+ 
+        return 0;
+ }
+ 
+-arch_initcall(omap3_sr_init);
+late_initcall(omap3_sr_init);
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+index 2091a15..194429e 100644
+--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -233,12 +233,18 @@
+ extern u32 current_vdd1_opp;
+ extern u32 current_vdd2_opp;
+ 
+#ifdef CONFIG_OMAP_SMARTREFLEX_TESTING
+#define SR_TESTING_NVALUES     1
+#else
+#define SR_TESTING_NVALUES     0
+#endif
+
+ /*
+  * Smartreflex module enable/disable interface.
+  * NOTE: if smartreflex is not enabled from sysfs, these functions will not
+  * do anything.
+  */
+-#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE)
+#ifdef CONFIG_OMAP_SMARTREFLEX
+ void enable_smartreflex(int srid);
+ void disable_smartreflex(int srid);
+ #else
+@@ -246,7 +252,6 @@ static inline void enable_smartreflex(int srid) {}
+ static inline void disable_smartreflex(int srid) {}
+ #endif
+ 
+-
+ #endif
+ 
+ 
+diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
+index b085b07..960c13f 100644
+--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
+@@ -56,6 +56,37 @@ config OMAP_DEBUG_CLOCKDOMAIN
+          for every clockdomain register write.  However, the
+          extra detail costs some memory.
+ 
+config OMAP_SMARTREFLEX
+       bool "SmartReflex support"
+       depends on ARCH_OMAP34XX && TWL4030_CORE
+       help
+         Say Y if you want to enable SmartReflex.
+
+         SmartReflex can perform continuous dynamic voltage
+         scaling around the nominal operating point voltage
+         according to silicon characteristics and operating
+         conditions. Enabling SmartReflex reduces power
+         consumption.
+
+         Please note, that by default SmartReflex is only
+         initialized. To enable the automatic voltage
+         compensation for VDD1 and VDD2, user must write 1 to
+         /sys/power/sr_vddX_autocomp, where X is 1 or 2.
+
+config OMAP_SMARTREFLEX_TESTING
+       bool "Smartreflex testing support"
+       depends on OMAP_SMARTREFLEX
+       default n
+       help
+         Say Y if you want to enable SmartReflex testing with SW hardcoded
+         NVALUES intead of E-fuse NVALUES set in factory silicon testing.
+
+         In some devices the E-fuse values have not been set, even though
+         SmartReflex modules are included. Using these hardcoded values set
+         in software, one can test the SmartReflex features without E-fuse.
+
+         WARNING: Enabling this option may cause your device to hang!
+
+ config OMAP_RESET_CLOCKS
+        bool "Reset unused clocks during boot"
+        depends on ARCH_OMAP
+-- 
+1.5.4.3
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/defconfig b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/defconfig
new file mode 100644
index 0000000000..f74cef90ee
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/defconfig
@@ -0,0 +1,1567 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc3-omap1
+# Wed May 21 07:38:41 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LSF=y
+# CONFIG_BLK_DEV_BSG is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM7X00A is not set
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+#
+# OMAP Feature Selections
+#
+CONFIG_OMAP_DEBUG_SRAM_PATCH=y
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_BOOT_TAG=y
+CONFIG_OMAP_BOOT_REASON=y
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+CONFIG_MACH_OMAP3EVM=y
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+#
+# Boot options
+#
+#
+# Power management
+#
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_LOCKDOWN_TO_64K_L2 is not set
+# CONFIG_CPU_LOCKDOWN_TO_128K_L2 is not set
+CONFIG_CPU_LOCKDOWN_TO_256K_L2=y
+# CONFIG_CPU_L2CACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" quiet "
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_NEON is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+#
+# Networking
+#
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=m
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_SCH_FIFO=y
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIUSB is not set
+# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIBTSDIO=m
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIBRF6150 is not set
+# CONFIG_BT_HCIH4P is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+CONFIG_NL80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=m
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_NONE is not set
+#
+# Selecting 'y' for an algorithm will
+#
+#
+# build the algorithm into mac80211.
+#
+CONFIG_MAC80211_RC_DEFAULT="pid"
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set
+# CONFIG_MAC80211_DEBUG is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+CONFIG_MTD_ONENAND=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_93CX6=m
+# CONFIG_OMAP_STI is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_NETDEVICES_MULTIQUEUE=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+CONFIG_SMC911X=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+# CONFIG_LIBERTAS_USB is not set
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+CONFIG_P54_COMMON=m
+# CONFIG_P54_USB is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2102 is not set
+# CONFIG_TOUCHSCREEN_TSC210X is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_ISP1301_OMAP is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_TLV320AIC23 is not set
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_GPIO=y
+# CONFIG_TWL4030_MADC is not set
+CONFIG_TWL4030_USB=y
+CONFIG_TWL4030_USB_HS_ULPI=y
+# CONFIG_TWL4030_PWRBUTTON is not set
+# CONFIG_TWL4030_POWEROFF is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_LP5521 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_MASTER=y
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_OMAP24XX=y
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TSC2101 is not set
+# CONFIG_SPI_TSC2102 is not set
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_HAVE_GPIO_LIB=y
+#
+# GPIO Support
+#
+# CONFIG_DEBUG_GPIO is not set
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+#
+# Multimedia devices
+#
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+#
+# Multimedia drivers
+#
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_FB_OMAP=y
+# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+#
+# Sound
+#
+CONFIG_SOUND=y
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+# CONFIG_SND_MIXER_OSS is not set
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_DEBUG_DETECT=y
+CONFIG_SND_PCM_XRUN_DEBUG=y
+#
+# Generic devices
+#
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+#
+# ALSA ARM devices
+#
+# CONFIG_SND_OMAP_AIC23 is not set
+# CONFIG_SND_OMAP_TSC2101 is not set
+# CONFIG_SND_SX1 is not set
+# CONFIG_SND_OMAP_TSC2102 is not set
+# CONFIG_SND_OMAP24XX_EAC is not set
+#
+# SPI devices
+#
+#
+# USB devices
+#
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+#
+# System on Chip audio support
+#
+CONFIG_SND_SOC=y
+#
+# ALSA SoC audio for Freescale SOCs
+#
+#
+# SoC Audio for the Texas Instruments OMAP
+#
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_OMAP_SOC_MCBSP=y
+CONFIG_SND_OMAP_SOC_OMAP3EVM=y
+CONFIG_SND_SOC_TWL4030=y
+#
+# Open Sound System
+#
+CONFIG_SOUND_PRIME=y
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_OMAP_EHCI_PHY_MODE=y
+# CONFIG_OMAP_EHCI_TLL_MODE is not set
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_ISP116X_HCD=y
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SL811_HCD=y
+CONFIG_USB_R8A66597_HCD=y
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_SOC=y
+#
+# OMAP 343x high speed USB support
+#
+CONFIG_USB_MUSB_HOST=y
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+CONFIG_USB_MUSB_LOGLEVEL=0
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_LIBUSUAL is not set
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+CONFIG_USB_MON=y
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+CONFIG_USB_GADGET_OMAP=y
+CONFIG_USB_OMAP=m
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_G_PRINTER=m
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=m
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
+# CONFIG_UIO is not set
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_XFS_FS=m
+CONFIG_XFS_QUOTA=y
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=m
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-empty-flash-warnings.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-empty-flash-warnings.patch
new file mode 100644
index 0000000000..ab344b0449
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-empty-flash-warnings.patch
@@ -0,0 +1,15 @@
+diff --git a/fs/jffs2/scan.c b/fs/jffs2/scan.c
+index 1d437de..33b3feb 100644
+--- a/fs/jffs2/scan.c
+++ b/fs/jffs2/scan.c
+@@ -647,8 +647,8 @@ scan_more:
+                        inbuf_ofs = ofs - buf_ofs;
+                        while (inbuf_ofs < scan_end) {
+                                if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) {
+-                                       printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n",
+-                                              empty_start, ofs);
+//                                     printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n",
+//                                            empty_start, ofs);
+                                        if ((err = jffs2_scan_dirty_space(c, jeb, ofs-empty_start)))
+                                                return err;
+                                        goto scan_more;
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-harry-potter.diff b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-harry-potter.diff
new file mode 100644
index 0000000000..2bb20ab9c0
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-harry-potter.diff
@@ -0,0 +1,11 @@
+--- /tmp/Makefile       2008-04-24 14:36:20.509598016 +0200
+++ git/arch/arm/Makefile       2008-04-24 14:36:31.949546584 +0200
+@@ -47,7 +47,7 @@
+ # Note that GCC does not numerically define an architecture version
+ # macro, but instead defines a whole series of macros which makes
+ # testing for a specific architecture or later rather impossible.
+-arch-$(CONFIG_CPU_32v7)                :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a)
+arch-$(CONFIG_CPU_32v7)                :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
+ arch-$(CONFIG_CPU_32v6)                :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
+ # Only override the compiler option if ARMv6. The ARMv6K extensions are
+ # always available in ARMv7