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-rw-r--r--meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch278
1 files changed, 278 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch
new file mode 100644
index 0000000000..8e609395a0
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch
@@ -0,0 +1,278 @@
1From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
2To: linux-omap@vger.kernel.org
3Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
4Subject: [PATCH 2/3] ARM: OMAP: SmartReflex driver: added required register and bit definitions.
5Date: Fri, 6 Jun 2008 12:49:48 +0300
6
7Added new register and bit definitions to enable Smartreflex driver integration.
8Also PRM_VC_SMPS_SA bit definitions' naming was changed to match the naming of
9other similar bit definitions.
10
11Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
12---
13 arch/arm/mach-omap2/prm-regbits-34xx.h | 27 ++++++--
14 arch/arm/mach-omap2/smartreflex.h | 124 ++++++++++++++++++++++++++++++-
15 include/asm-arm/arch-omap/control.h | 19 +++++
16 include/asm-arm/arch-omap/omap34xx.h | 2 +
17 4 files changed, 163 insertions(+), 9 deletions(-)
18
19diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
20index c6a7940..f82b5a7 100644
21--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
22+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
23@@ -435,10 +435,10 @@
24 /* PM_PWSTST_EMU specific bits */
25
26 /* PRM_VC_SMPS_SA */
27-#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
28-#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
29-#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
30-#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
31+#define OMAP3430_SMPS_SA1_SHIFT 16
32+#define OMAP3430_SMPS_SA1_MASK (0x7f << 16)
33+#define OMAP3430_SMPS_SA0_SHIFT 0
34+#define OMAP3430_SMPS_SA0_MASK (0x7f << 0)
35
36 /* PRM_VC_SMPS_VOL_RA */
37 #define OMAP3430_VOLRA1_SHIFT 16
38@@ -452,7 +452,7 @@
39 #define OMAP3430_CMDRA0_SHIFT 0
40 #define OMAP3430_CMDRA0_MASK (0xff << 0)
41
42-/* PRM_VC_CMD_VAL_0 specific bits */
43+/* PRM_VC_CMD_VAL */
44 #define OMAP3430_VC_CMD_ON_SHIFT 24
45 #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24)
46 #define OMAP3430_VC_CMD_ONLP_SHIFT 16
47@@ -462,7 +462,17 @@
48 #define OMAP3430_VC_CMD_OFF_SHIFT 0
49 #define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0)
50
51+/* PRM_VC_CMD_VAL_0 specific bits */
52+#define OMAP3430_VC_CMD_VAL0_ON (0x3 << 4)
53+#define OMAP3430_VC_CMD_VAL0_ONLP (0x3 << 3)
54+#define OMAP3430_VC_CMD_VAL0_RET (0x3 << 3)
55+#define OMAP3430_VC_CMD_VAL0_OFF (0x3 << 3)
56+
57 /* PRM_VC_CMD_VAL_1 specific bits */
58+#define OMAP3430_VC_CMD_VAL1_ON (0xB << 2)
59+#define OMAP3430_VC_CMD_VAL1_ONLP (0x3 << 3)
60+#define OMAP3430_VC_CMD_VAL1_RET (0x3 << 3)
61+#define OMAP3430_VC_CMD_VAL1_OFF (0x3 << 3)
62
63 /* PRM_VC_CH_CONF */
64 #define OMAP3430_CMD1 (1 << 20)
65@@ -521,6 +531,13 @@
66 #define OMAP3430_AUTO_RET (1 << 1)
67 #define OMAP3430_AUTO_SLEEP (1 << 0)
68
69+/* Constants to define setup durations */
70+#define OMAP3430_CLKSETUP_DURATION 0xff
71+#define OMAP3430_VOLTSETUP_TIME2 0xfff
72+#define OMAP3430_VOLTSETUP_TIME1 0xfff
73+#define OMAP3430_VOLTOFFSET_DURATION 0xff
74+#define OMAP3430_VOLTSETUP2_DURATION 0xff
75+
76 /* PRM_SRAM_PCHARGE */
77 #define OMAP3430_PCHARGE_TIME_SHIFT 0
78 #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
79diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
80index 62907ef..2091a15 100644
81--- a/arch/arm/mach-omap2/smartreflex.h
82+++ b/arch/arm/mach-omap2/smartreflex.h
83@@ -1,5 +1,10 @@
84+#ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
85+#define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
86 /*
87- * linux/arch/arm/mach-omap3/smartreflex.h
88+ * linux/arch/arm/mach-omap2/smartreflex.h
89+ *
90+ * Copyright (C) 2008 Nokia Corporation
91+ * Kalle Jokiniemi
92 *
93 * Copyright (C) 2007 Texas Instruments, Inc.
94 * Lesly A M <x0080970@ti.com>
95@@ -9,6 +14,21 @@
96 * published by the Free Software Foundation.
97 */
98
99+#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
100+#define PHY_TO_OFF_PM_RECIEVER(p) (p - 0x5b)
101+#define PHY_TO_OFF_PM_INT(p) (p - 0x2e)
102+
103+/* SMART REFLEX REG ADDRESS OFFSET */
104+#define SRCONFIG 0x00
105+#define SRSTATUS 0x04
106+#define SENVAL 0x08
107+#define SENMIN 0x0C
108+#define SENMAX 0x10
109+#define SENAVG 0x14
110+#define AVGWEIGHT 0x18
111+#define NVALUERECIPROCAL 0x1C
112+#define SENERROR 0x20
113+#define ERRCONFIG 0x24
114
115 /* SR Modules */
116 #define SR1 1
117@@ -127,10 +147,106 @@
118 #define SR2_ERRMAXLIMIT (0x02 << 8)
119 #define SR2_ERRMINLIMIT (0xF9 << 0)
120
121+/* T2 SMART REFLEX */
122+#define R_SRI2C_SLAVE_ADDR 0x12
123+#define R_VDD1_SR_CONTROL 0x00
124+#define R_VDD2_SR_CONTROL 0x01
125+#define T2_SMPS_UPDATE_DELAY 360 /* In uSec */
126+
127+/* Vmode control */
128+#define R_DCDC_GLOBAL_CFG PHY_TO_OFF_PM_RECIEVER(0x61)
129+
130+#define R_VDD1_VSEL PHY_TO_OFF_PM_RECIEVER(0xb9)
131+#define R_VDD1_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xba)
132+#define R_VDD1_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xbb)
133+#define R_VDD1_VROOF PHY_TO_OFF_PM_RECIEVER(0xbc)
134+#define R_VDD1_STEP PHY_TO_OFF_PM_RECIEVER(0xbd)
135+
136+#define R_VDD2_VSEL PHY_TO_OFF_PM_RECIEVER(0xc7)
137+#define R_VDD2_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xc8)
138+#define R_VDD2_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xc9)
139+#define R_VDD2_VROOF PHY_TO_OFF_PM_RECIEVER(0xca)
140+#define R_VDD2_STEP PHY_TO_OFF_PM_RECIEVER(0xcb)
141+
142+/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE valuws */
143+#define DCDC_GLOBAL_CFG_ENABLE_SRFLX 0x08
144+
145+/* VDDs*/
146+#define PRCM_VDD1 1
147+#define PRCM_VDD2 2
148+#define PRCM_MAX_SYSC_REGS 30
149+
150+/* XXX: These should be removed/moved from here once we have a working DVFS
151+ implementation in place */
152+#define AT_3430 1 /*3430 ES 1.0 */
153+#define AT_3430_ES2 2 /*3430 ES 2.0 */
154+
155+#define ID_OPP 0xE2 /*OPP*/
156+
157+/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */
158+#define OMAP_TYPE_SHIFT 28
159+#define OMAP_TYPE_MASK 0xF
160+/* OPP ID: bits: 0-4 for OPP number */
161+#define OPP_NO_POS 0
162+#define OPP_NO_MASK 0x1F
163+/* OPP ID: bits: 5-6 for VDD */
164+#define VDD_NO_POS 5
165+#define VDD_NO_MASK 0x3
166+/* Other IDs: bits 20-27 for ID type */
167+/* These IDs have bits 25,26,27 as 1 */
168+#define OTHER_ID_TYPE_SHIFT 20
169+#define OTHER_ID_TYPE_MASK 0xFF
170+
171+#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT)
172+#define ID_OPP_NO(X) ((X & OPP_NO_MASK) << OPP_NO_POS)
173+#define ID_VDD(X) ((X & VDD_NO_MASK) << VDD_NO_POS)
174+#define OMAP(X) ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK)
175+#define get_opp_no(X) ((X >> OPP_NO_POS) & OPP_NO_MASK)
176+#define get_vdd(X) ((X >> VDD_NO_POS) & VDD_NO_MASK)
177+
178+/* VDD1 OPPs */
179+#define PRCM_VDD1_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
180+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1))
181+#define PRCM_VDD1_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
182+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2))
183+#define PRCM_VDD1_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
184+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3))
185+#define PRCM_VDD1_OPP4 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
186+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4))
187+#define PRCM_VDD1_OPP5 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
188+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5))
189+#define PRCM_NO_VDD1_OPPS 5
190+
191+
192+/* VDD2 OPPs */
193+#define PRCM_VDD2_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
194+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1))
195+#define PRCM_VDD2_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
196+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2))
197+#define PRCM_VDD2_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
198+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3))
199+#define PRCM_NO_VDD2_OPPS 3
200+/* XXX: end remove/move */
201+
202+
203+/* XXX: find more appropriate place for these once DVFS is in place */
204 extern u32 current_vdd1_opp;
205 extern u32 current_vdd2_opp;
206-extern struct kset power_subsys;
207
208-extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
209-extern void omap_udelay(u32 udelay);
210+/*
211+ * Smartreflex module enable/disable interface.
212+ * NOTE: if smartreflex is not enabled from sysfs, these functions will not
213+ * do anything.
214+ */
215+#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE)
216+void enable_smartreflex(int srid);
217+void disable_smartreflex(int srid);
218+#else
219+static inline void enable_smartreflex(int srid) {}
220+static inline void disable_smartreflex(int srid) {}
221+#endif
222+
223+
224+#endif
225+
226
227diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
228index 12bc22a..6e64fe7 100644
229--- a/include/asm-arm/arch-omap/control.h
230+++ b/include/asm-arm/arch-omap/control.h
231@@ -138,6 +138,15 @@
232 #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
233 #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
234 #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
235+#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
236+#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
237+#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
238+#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
239+#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
240+#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
241+#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
242+#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
243+#define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130)
244 #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
245 #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
246 #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4)
247@@ -172,6 +181,16 @@
248 #define OMAP2_SYSBOOT_1_MASK (1 << 1)
249 #define OMAP2_SYSBOOT_0_MASK (1 << 0)
250
251+/* CONTROL_FUSE_SR bits */
252+#define OMAP343X_SR2_SENNENABLE_MASK (0x3 << 10)
253+#define OMAP343X_SR2_SENNENABLE_SHIFT 10
254+#define OMAP343X_SR2_SENPENABLE_MASK (0x3 << 8)
255+#define OMAP343X_SR2_SENPENABLE_SHIFT 8
256+#define OMAP343X_SR1_SENNENABLE_MASK (0x3 << 2)
257+#define OMAP343X_SR1_SENNENABLE_SHIFT 2
258+#define OMAP343X_SR1_SENPENABLE_MASK (0x3 << 0)
259+#define OMAP343X_SR1_SENPENABLE_SHIFT 0
260+
261 #ifndef __ASSEMBLY__
262 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
263 extern void __iomem *omap_ctrl_base_get(void);
264diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
265index 6a0459a..3667fd6 100644
266--- a/include/asm-arm/arch-omap/omap34xx.h
267+++ b/include/asm-arm/arch-omap/omap34xx.h
268@@ -54,6 +54,8 @@
269 #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
270 #define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
271 #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
272+#define OMAP34XX_SR1_BASE 0x480C9000
273+#define OMAP34XX_SR2_BASE 0x480CB000
274
275
276 #if defined(CONFIG_ARCH_OMAP3430)
277--
2781.5.4.3
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-04-27 10:29:32 +0000