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-rw-r--r--meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch450
1 files changed, 450 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch
new file mode 100644
index 0000000000..cdc9447b4c
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch
@@ -0,0 +1,450 @@
1From: "Rajendra Nayak" <rnayak@ti.com>
2To: <linux-omap@vger.kernel.org>
3Subject: [PATCH 01/02] OMAP3 CPUidle driver
4Date: Tue, 10 Jun 2008 12:39:00 +0530
5
6This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver
7before it queries the governor for the next state.
8
9Signed-off-by: Rajendra Nayak <rnayak@ti.com>
10
11---
12 arch/arm/mach-omap2/Makefile | 2
13 arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++
14 arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++
15 arch/arm/mach-omap2/pm34xx.c | 5
16 drivers/cpuidle/cpuidle.c | 10 +
17 5 files changed, 359 insertions(+), 2 deletions(-)
18
19Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile
20===================================================================
21--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530
22+++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530
23@@ -20,7 +20,7 @@ obj-y += pm.o
24 obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
25 obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o
26 obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o
27-obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
28+obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o
29 obj-$(CONFIG_PM_DEBUG) += pm-debug.o
30 endif
31
32Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c
33===================================================================
34--- /dev/null 1970-01-01 00:00:00.000000000 +0000
35+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530
36@@ -0,0 +1,293 @@
37+/*
38+ * linux/arch/arm/mach-omap2/cpuidle34xx.c
39+ *
40+ * OMAP3 CPU IDLE Routines
41+ *
42+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
43+ * Rajendra Nayak <rnayak@ti.com>
44+ *
45+ * Copyright (C) 2007 Texas Instruments, Inc.
46+ * Karthik Dasu <karthik-dp@ti.com>
47+ *
48+ * Copyright (C) 2006 Nokia Corporation
49+ * Tony Lindgren <tony@atomide.com>
50+ *
51+ * Copyright (C) 2005 Texas Instruments, Inc.
52+ * Richard Woodruff <r-woodruff2@ti.com>
53+ *
54+ * This program is free software; you can redistribute it and/or modify
55+ * it under the terms of the GNU General Public License version 2 as
56+ * published by the Free Software Foundation.
57+ */
58+
59+#include <linux/cpuidle.h>
60+#include <asm/arch/pm.h>
61+#include <asm/arch/prcm.h>
62+#include <asm/arch/powerdomain.h>
63+#include <asm/arch/clockdomain.h>
64+#include <asm/arch/irqs.h>
65+#include "cpuidle34xx.h"
66+
67+#ifdef CONFIG_CPU_IDLE
68+
69+struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
70+struct omap3_processor_cx current_cx_state;
71+
72+static int omap3_idle_bm_check(void)
73+{
74+ /* Check for omap3_fclks_active() here once available */
75+ return 0;
76+}
77+
78+/* omap3_enter_idle - Programs OMAP3 to enter the specified state.
79+ * returns the total time during which the system was idle.
80+ */
81+static int omap3_enter_idle(struct cpuidle_device *dev,
82+ struct cpuidle_state *state)
83+{
84+ struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
85+ struct timespec ts_preidle, ts_postidle, ts_idle;
86+ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;
87+ int neon_pwrst;
88+
89+ current_cx_state = *cx;
90+
91+ if (cx->type == OMAP3_STATE_C0) {
92+ /* Do nothing for C0, not even a wfi */
93+ return 0;
94+ }
95+
96+ /* Used to keep track of the total time in idle */
97+ getnstimeofday(&ts_preidle);
98+
99+ mpu_pd = pwrdm_lookup("mpu_pwrdm");
100+ core_pd = pwrdm_lookup("core_pwrdm");
101+ per_pd = pwrdm_lookup("per_pwrdm");
102+ neon_pd = pwrdm_lookup("neon_pwrdm");
103+
104+ /* Reset previous power state registers */
105+ pwrdm_clear_all_prev_pwrst(mpu_pd);
106+ pwrdm_clear_all_prev_pwrst(neon_pd);
107+ pwrdm_clear_all_prev_pwrst(core_pd);
108+ pwrdm_clear_all_prev_pwrst(per_pd);
109+
110+ if (omap_irq_pending())
111+ return 0;
112+
113+ neon_pwrst = pwrdm_read_pwrst(neon_pd);
114+
115+ /* Program MPU/NEON to target state */
116+ if (cx->mpu_state < PWRDM_POWER_ON) {
117+ if (neon_pwrst == PWRDM_POWER_ON) {
118+ if (cx->mpu_state == PWRDM_POWER_RET)
119+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
120+ else if (cx->mpu_state == PWRDM_POWER_OFF)
121+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);
122+ }
123+ pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
124+ }
125+
126+ /* Program CORE to target state */
127+ if (cx->core_state < PWRDM_POWER_ON)
128+ pwrdm_set_next_pwrst(core_pd, cx->core_state);
129+
130+ /* Execute ARM wfi */
131+ omap_sram_idle();
132+
133+ /* Program MPU/NEON to ON */
134+ if (cx->mpu_state < PWRDM_POWER_ON) {
135+ if (neon_pwrst == PWRDM_POWER_ON)
136+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);
137+ pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);
138+ }
139+
140+ if (cx->core_state < PWRDM_POWER_ON)
141+ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);
142+
143+ getnstimeofday(&ts_postidle);
144+ ts_idle = timespec_sub(ts_postidle, ts_preidle);
145+ return timespec_to_ns(&ts_idle);
146+}
147+
148+/*
149+ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM
150+ *
151+ * This function checks for all the pre-requisites needed for OMAP3 to enter
152+ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired
153+ * C state.
154+ */
155+static int omap3_enter_idle_bm(struct cpuidle_device *dev,
156+ struct cpuidle_state *state)
157+{
158+ struct cpuidle_state *new_state = NULL;
159+ int i, j;
160+
161+ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
162+
163+ /* Find current state in list */
164+ for (i = 0; i < OMAP3_MAX_STATES; i++)
165+ if (state == &dev->states[i])
166+ break;
167+ BUG_ON(i == OMAP3_MAX_STATES);
168+
169+ /* Back up to non 'CHECK_BM' state */
170+ for (j = i - 1; j > 0; j--) {
171+ struct cpuidle_state *s = &dev->states[j];
172+
173+ if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) {
174+ new_state = s;
175+ break;
176+ }
177+ }
178+
179+ pr_debug("%s: Bus activity: Entering %s (instead of %s)\n",
180+ __FUNCTION__, new_state->name, state->name);
181+ }
182+
183+ return omap3_enter_idle(dev, new_state ? : state);
184+}
185+
186+DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
187+
188+/* omap3_init_power_states - Initialises the OMAP3 specific C states.
189+ * Below is the desciption of each C state.
190+ *
191+ C0 . System executing code
192+ C1 . MPU WFI + Core active
193+ C2 . MPU CSWR + Core active
194+ C3 . MPU OFF + Core active
195+ C4 . MPU CSWR + Core CSWR
196+ C5 . MPU OFF + Core CSWR
197+ C6 . MPU OFF + Core OFF
198+ */
199+void omap_init_power_states(void)
200+{
201+ /* C0 . System executing code */
202+ omap3_power_states[0].valid = 1;
203+ omap3_power_states[0].type = OMAP3_STATE_C0;
204+ omap3_power_states[0].sleep_latency = 0;
205+ omap3_power_states[0].wakeup_latency = 0;
206+ omap3_power_states[0].threshold = 0;
207+ omap3_power_states[0].mpu_state = PWRDM_POWER_ON;
208+ omap3_power_states[0].core_state = PWRDM_POWER_ON;
209+ omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID |
210+ CPUIDLE_FLAG_SHALLOW;
211+
212+ /* C1 . MPU WFI + Core active */
213+ omap3_power_states[1].valid = 1;
214+ omap3_power_states[1].type = OMAP3_STATE_C1;
215+ omap3_power_states[1].sleep_latency = 10;
216+ omap3_power_states[1].wakeup_latency = 10;
217+ omap3_power_states[1].threshold = 30;
218+ omap3_power_states[1].mpu_state = PWRDM_POWER_ON;
219+ omap3_power_states[1].core_state = PWRDM_POWER_ON;
220+ omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID |
221+ CPUIDLE_FLAG_SHALLOW;
222+
223+ /* C2 . MPU CSWR + Core active */
224+ omap3_power_states[2].valid = 1;
225+ omap3_power_states[2].type = OMAP3_STATE_C2;
226+ omap3_power_states[2].sleep_latency = 50;
227+ omap3_power_states[2].wakeup_latency = 50;
228+ omap3_power_states[2].threshold = 300;
229+ omap3_power_states[2].mpu_state = PWRDM_POWER_RET;
230+ omap3_power_states[2].core_state = PWRDM_POWER_ON;
231+ omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID |
232+ CPUIDLE_FLAG_BALANCED;
233+
234+ /* C3 . MPU OFF + Core active */
235+ omap3_power_states[3].valid = 0;
236+ omap3_power_states[3].type = OMAP3_STATE_C3;
237+ omap3_power_states[3].sleep_latency = 1500;
238+ omap3_power_states[3].wakeup_latency = 1800;
239+ omap3_power_states[3].threshold = 4000;
240+ omap3_power_states[3].mpu_state = PWRDM_POWER_OFF;
241+ omap3_power_states[3].core_state = PWRDM_POWER_RET;
242+ omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID |
243+ CPUIDLE_FLAG_BALANCED;
244+
245+ /* C4 . MPU CSWR + Core CSWR*/
246+ omap3_power_states[4].valid = 1;
247+ omap3_power_states[4].type = OMAP3_STATE_C4;
248+ omap3_power_states[4].sleep_latency = 2500;
249+ omap3_power_states[4].wakeup_latency = 7500;
250+ omap3_power_states[4].threshold = 12000;
251+ omap3_power_states[4].mpu_state = PWRDM_POWER_RET;
252+ omap3_power_states[4].core_state = PWRDM_POWER_RET;
253+ omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID |
254+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
255+
256+ /* C5 . MPU OFF + Core CSWR */
257+ omap3_power_states[5].valid = 0;
258+ omap3_power_states[5].type = OMAP3_STATE_C5;
259+ omap3_power_states[5].sleep_latency = 3000;
260+ omap3_power_states[5].wakeup_latency = 8500;
261+ omap3_power_states[5].threshold = 15000;
262+ omap3_power_states[5].mpu_state = PWRDM_POWER_OFF;
263+ omap3_power_states[5].core_state = PWRDM_POWER_RET;
264+ omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID |
265+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
266+
267+ /* C6 . MPU OFF + Core OFF */
268+ omap3_power_states[6].valid = 0;
269+ omap3_power_states[6].type = OMAP3_STATE_C6;
270+ omap3_power_states[6].sleep_latency = 10000;
271+ omap3_power_states[6].wakeup_latency = 30000;
272+ omap3_power_states[6].threshold = 300000;
273+ omap3_power_states[6].mpu_state = PWRDM_POWER_OFF;
274+ omap3_power_states[6].core_state = PWRDM_POWER_OFF;
275+ omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID |
276+ CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM;
277+}
278+
279+struct cpuidle_driver omap3_idle_driver = {
280+ .name = "omap3_idle",
281+ .owner = THIS_MODULE,
282+};
283+/*
284+ * omap3_idle_init - Init routine for OMAP3 idle.
285+ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w
286+ * with the valid set of states.
287+ */
288+int omap3_idle_init(void)
289+{
290+ int i, count = 0;
291+ struct omap3_processor_cx *cx;
292+ struct cpuidle_state *state;
293+ struct cpuidle_device *dev;
294+
295+ omap_init_power_states();
296+ cpuidle_register_driver(&omap3_idle_driver);
297+
298+ dev = &per_cpu(omap3_idle_dev, smp_processor_id());
299+
300+ for (i = 0; i < OMAP3_MAX_STATES; i++) {
301+ cx = &omap3_power_states[i];
302+ state = &dev->states[count];
303+
304+ if (!cx->valid)
305+ continue;
306+ cpuidle_set_statedata(state, cx);
307+ state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
308+ state->target_residency = cx->threshold;
309+ state->flags = cx->flags;
310+ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
311+ omap3_enter_idle_bm : omap3_enter_idle;
312+ sprintf(state->name, "C%d", count+1);
313+ count++;
314+ }
315+
316+ if (!count)
317+ return -EINVAL;
318+ dev->state_count = count;
319+
320+ if (cpuidle_register_device(dev)) {
321+ printk(KERN_ERR "%s: CPUidle register device failed\n",
322+ __FUNCTION__);
323+ return -EIO;
324+ }
325+
326+ return 0;
327+}
328+__initcall(omap3_idle_init);
329+#endif /* CONFIG_CPU_IDLE */
330Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h
331===================================================================
332--- /dev/null 1970-01-01 00:00:00.000000000 +0000
333+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530
334@@ -0,0 +1,51 @@
335+/*
336+ * linux/arch/arm/mach-omap2/cpuidle34xx.h
337+ *
338+ * OMAP3 cpuidle structure definitions
339+ *
340+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
341+ * Written by Rajendra Nayak <rnayak@ti.com>
342+ *
343+ * This program is free software; you can redistribute it and/or modify
344+ * it under the terms of the GNU General Public License version 2 as
345+ * published by the Free Software Foundation.
346+ *
347+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
348+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
349+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
350+ *
351+ * History:
352+ *
353+ */
354+
355+#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
356+#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
357+
358+#define OMAP3_MAX_STATES 7
359+#define OMAP3_STATE_C0 0 /* C0 - System executing code */
360+#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */
361+#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */
362+#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */
363+#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */
364+#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
365+#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */
366+
367+extern void omap_sram_idle(void);
368+extern int omap3_irq_pending(void);
369+
370+struct omap3_processor_cx {
371+ u8 valid;
372+ u8 type;
373+ u32 sleep_latency;
374+ u32 wakeup_latency;
375+ u32 mpu_state;
376+ u32 core_state;
377+ u32 threshold;
378+ u32 flags;
379+};
380+
381+void omap_init_power_states(void);
382+int omap3_idle_init(void);
383+
384+#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */
385+
386Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c
387===================================================================
388--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530
389+++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530
390@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle
391 return IRQ_HANDLED;
392 }
393
394-static void omap_sram_idle(void)
395+void omap_sram_idle(void)
396 {
397 /* Variable to tell what needs to be saved and restored
398 * in omap_sram_idle*/
399@@ -156,6 +156,7 @@ static void omap_sram_idle(void)
400
401 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
402 switch (mpu_next_state) {
403+ case PWRDM_POWER_ON:
404 case PWRDM_POWER_RET:
405 /* No need to save context */
406 save_state = 0;
407@@ -386,7 +387,9 @@ int __init omap3_pm_init(void)
408
409 prcm_setup_regs();
410
411+#ifndef CONFIG_CPU_IDLE
412 pm_idle = omap3_pm_idle;
413+#endif
414
415 err1:
416 return ret;
417Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c
418===================================================================
419--- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530
420+++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530
421@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void)
422 return;
423 }
424
425+#ifdef CONFIG_ARCH_OMAP3
426+ local_irq_disable();
427+ local_fiq_disable();
428+#endif
429+
430 /* ask the governor for the next state */
431 next_state = cpuidle_curr_governor->select(dev);
432 if (need_resched())
433@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void)
434 target_state->time += (unsigned long long)dev->last_residency;
435 target_state->usage++;
436
437+#ifdef CONFIG_ARCH_OMAP3
438+ local_irq_enable();
439+ local_fiq_enable();
440+#endif
441+
442 /* give the governor an opportunity to reflect on the outcome */
443 if (cpuidle_curr_governor->reflect)
444 cpuidle_curr_governor->reflect(dev);
445
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