diff options
Diffstat (limited to 'meta/recipes-kernel/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch')
-rw-r--r-- | meta/recipes-kernel/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch | 114 |
1 files changed, 114 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch new file mode 100644 index 0000000000..25e5aad9c9 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch | |||
@@ -0,0 +1,114 @@ | |||
1 | From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008 | ||
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29 | Date: Tue, 24 Jun 2008 01:12:35 -0600 (MDT) | ||
30 | From: Paul Walmsley <paul@pwsan.com> | ||
31 | To: linux-omap@vger.kernel.org | ||
32 | Subject: [PATCH] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4 | ||
33 | Message-ID: <alpine.DEB.1.00.0806240111320.9741@utopia.booyaka.com> | ||
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46 | |||
47 | |||
48 | OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and | ||
49 | DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this | ||
50 | into the OMAP3 clock framework. | ||
51 | |||
52 | Signed-off-by: Paul Walmsley <paul@pwsan.com> | ||
53 | --- | ||
54 | |||
55 | arch/arm/mach-omap2/clock34xx.h | 20 ++++++++++++++++---- | ||
56 | 1 files changed, 16 insertions(+), 4 deletions(-) | ||
57 | |||
58 | diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h | ||
59 | index b4dceea..9605744 100644 | ||
60 | --- a/arch/arm/mach-omap2/clock34xx.h | ||
61 | +++ b/arch/arm/mach-omap2/clock34xx.h | ||
62 | @@ -1029,8 +1029,15 @@ static struct clk corex2_fck = { | ||
63 | |||
64 | /* DPLL power domain clock controls */ | ||
65 | |||
66 | -static const struct clksel div2_core_clksel[] = { | ||
67 | - { .parent = &core_ck, .rates = div2_rates }, | ||
68 | +static const struct clksel_rate div4_rates[] = { | ||
69 | + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
70 | + { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
71 | + { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
72 | + { .div = 0 } | ||
73 | +}; | ||
74 | + | ||
75 | +static const struct clksel div4_core_clksel[] = { | ||
76 | + { .parent = &core_ck, .rates = div4_rates }, | ||
77 | { .parent = NULL } | ||
78 | }; | ||
79 | |||
80 | @@ -1044,7 +1051,7 @@ static struct clk dpll1_fck = { | ||
81 | .init = &omap2_init_clksel_parent, | ||
82 | .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
83 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, | ||
84 | - .clksel = div2_core_clksel, | ||
85 | + .clksel = div4_core_clksel, | ||
86 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
87 | PARENT_CONTROLS_CLOCK, | ||
88 | .recalc = &omap2_clksel_recalc, | ||
89 | @@ -1119,7 +1126,7 @@ static struct clk dpll2_fck = { | ||
90 | .init = &omap2_init_clksel_parent, | ||
91 | .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
92 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, | ||
93 | - .clksel = div2_core_clksel, | ||
94 | + .clksel = div4_core_clksel, | ||
95 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
96 | PARENT_CONTROLS_CLOCK, | ||
97 | .recalc = &omap2_clksel_recalc, | ||
98 | @@ -1155,6 +1162,11 @@ static struct clk iva2_ck = { | ||
99 | |||
100 | /* Common interface clocks */ | ||
101 | |||
102 | +static const struct clksel div2_core_clksel[] = { | ||
103 | + { .parent = &core_ck, .rates = div2_rates }, | ||
104 | + { .parent = NULL } | ||
105 | +}; | ||
106 | + | ||
107 | static struct clk l3_ick = { | ||
108 | .name = "l3_ick", | ||
109 | .parent = &core_ck, | ||
110 | -- | ||
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