diff options
Diffstat (limited to 'meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks3.diff')
-rw-r--r-- | meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks3.diff | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks3.diff b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks3.diff new file mode 100644 index 0000000000..f8407fc2d5 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/mru-clocks3.diff | |||
@@ -0,0 +1,94 @@ | |||
1 | From: Mans Rullgard <mans@mansr.com> | ||
2 | Date: Wed, 23 Jul 2008 08:40:07 +0000 (+0100) | ||
3 | Subject: ARM: OMAP: Set DSS1_ALWON_FCLK to a multiple of the pixel clock | ||
4 | X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=01ee28c50701caa94739e764c3dae9298edd8216 | ||
5 | |||
6 | ARM: OMAP: Set DSS1_ALWON_FCLK to a multiple of the pixel clock | ||
7 | |||
8 | This sets the DSS1_ALWON_FCLK clock as close as possible to a | ||
9 | multiple of the requested pixel clock, while keeping it below | ||
10 | the 173MHz limit. | ||
11 | |||
12 | Due to of the structure of the clock tree, dss1_alwon_fck cannot | ||
13 | be set directly, and we must use dpll4_m4_ck instead. | ||
14 | |||
15 | Signed-off-by: Mans Rullgard <mans@mansr.com> | ||
16 | --- | ||
17 | |||
18 | diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c | ||
19 | index fd06ca2..e0e8528 100644 | ||
20 | --- a/drivers/video/omap/dispc.c | ||
21 | +++ b/drivers/video/omap/dispc.c | ||
22 | @@ -176,6 +176,7 @@ static struct { | ||
23 | |||
24 | struct clk *dss_ick, *dss1_fck; | ||
25 | struct clk *dss_54m_fck; | ||
26 | + struct clk *dpll4_m4_ck; | ||
27 | |||
28 | enum omapfb_update_mode update_mode; | ||
29 | struct omapfb_device *fbdev; | ||
30 | @@ -738,21 +739,34 @@ static void setup_color_conv_coef(void) | ||
31 | MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range); | ||
32 | } | ||
33 | |||
34 | -#define MAX_FCK_LCD 173000000 | ||
35 | +#define MAX_FCK 173000000 | ||
36 | |||
37 | static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div) | ||
38 | { | ||
39 | + unsigned long prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck)); | ||
40 | + unsigned long pcd_min = is_tft? 2: 3; | ||
41 | + unsigned long fck_div; | ||
42 | unsigned long fck, lck; | ||
43 | |||
44 | pck = max(1, pck); | ||
45 | + | ||
46 | + if (pck * pcd_min > MAX_FCK) { | ||
47 | + dev_warn(dispc.fbdev->dev, "pixclock %d kHz too high.\n", | ||
48 | + pck / 1000); | ||
49 | + pck = MAX_FCK / pcd_min; | ||
50 | + } | ||
51 | + | ||
52 | + fck = pck * 2; | ||
53 | + fck_div = (prate + pck) / fck; | ||
54 | + if (fck_div > 16) | ||
55 | + fck_div /= (fck_div + 15) / 16; | ||
56 | + if (fck_div < 1) | ||
57 | + fck_div = 1; | ||
58 | + clk_set_rate(dispc.dpll4_m4_ck, prate / fck_div); | ||
59 | fck = clk_get_rate(dispc.dss1_fck); | ||
60 | - *lck_div = (fck + MAX_FCK_LCD - 1) / MAX_FCK_LCD; | ||
61 | - lck = fck / *lck_div; | ||
62 | - *pck_div = (lck + pck - 1) / pck; | ||
63 | - if (is_tft) | ||
64 | - *pck_div = max(2, *pck_div); | ||
65 | - else | ||
66 | - *pck_div = max(3, *pck_div); | ||
67 | + | ||
68 | + *lck_div = 1; | ||
69 | + *pck_div = (fck + pck - 1) / pck; | ||
70 | if (*pck_div > 255) { | ||
71 | *pck_div = 255; | ||
72 | lck = pck * *pck_div; | ||
73 | @@ -914,11 +928,21 @@ static int get_dss_clocks(void) | ||
74 | return PTR_ERR(dispc.dss_54m_fck); | ||
75 | } | ||
76 | |||
77 | + if (IS_ERR((dispc.dpll4_m4_ck = | ||
78 | + clk_get(dispc.fbdev->dev, "dpll4_m4_ck")))) { | ||
79 | + dev_err(dispc.fbdev->dev, "can't get dpll4_m4_ck"); | ||
80 | + clk_put(dispc.dss_ick); | ||
81 | + clk_put(dispc.dss1_fck); | ||
82 | + clk_put(dispc.dss_54m_fck); | ||
83 | + return PTR_ERR(dispc.dss_54m_fck); | ||
84 | + } | ||
85 | + | ||
86 | return 0; | ||
87 | } | ||
88 | |||
89 | static void put_dss_clocks(void) | ||
90 | { | ||
91 | + clk_put(dispc.dpll4_m4_ck); | ||
92 | clk_put(dispc.dss_54m_fck); | ||
93 | clk_put(dispc.dss1_fck); | ||
94 | clk_put(dispc.dss_ick); | ||