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-rw-r--r--meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-08.patch278
1 files changed, 278 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-08.patch b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-08.patch
new file mode 100644
index 0000000000..9af25a762d
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap2-git/beagleboard/TWL4030-08.patch
@@ -0,0 +1,278 @@
1TWL4030: use symbolic ISR/IMR register names during twl_init_irq()
2
3From: Paul Walmsley <paul@pwsan.com>
4
5twl_init_irq() uses a bunch of magic numbers as register indices; this
6has already led to several errors, fixed earlier in this patch series.
7Now use descriptive macros instead of magic numbers. This patch should
8not change kernel behavior.
9
10Signed-off-by: Paul Walmsley <paul@pwsan.com>
11---
12
13 drivers/i2c/chips/twl4030-core.c | 188 +++++++++++++++++++-------------------
14 1 files changed, 96 insertions(+), 92 deletions(-)
15
16diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
17index 99cc143..38c227a 100644
18--- a/drivers/i2c/chips/twl4030-core.c
19+++ b/drivers/i2c/chips/twl4030-core.c
20@@ -40,6 +40,9 @@
21
22 #include <linux/i2c.h>
23 #include <linux/i2c/twl4030.h>
24+#include <linux/i2c/twl4030-gpio.h>
25+#include <linux/i2c/twl4030-madc.h>
26+#include <linux/i2c/twl4030-pwrirq.h>
27 #include <linux/slab.h>
28 #include <linux/clk.h>
29 #include <linux/device.h>
30@@ -114,6 +117,23 @@
31 #define TWL4030_BASEADD_RTC 0x001C
32 #define TWL4030_BASEADD_SECURED_REG 0x0000
33
34+/* TWL4030 BCI registers */
35+#define TWL4030_INTERRUPTS_BCIIMR1A 0x2
36+#define TWL4030_INTERRUPTS_BCIIMR2A 0x3
37+#define TWL4030_INTERRUPTS_BCIIMR1B 0x6
38+#define TWL4030_INTERRUPTS_BCIIMR2B 0x7
39+#define TWL4030_INTERRUPTS_BCIISR1A 0x0
40+#define TWL4030_INTERRUPTS_BCIISR2A 0x1
41+#define TWL4030_INTERRUPTS_BCIISR1B 0x4
42+#define TWL4030_INTERRUPTS_BCIISR2B 0x5
43+
44+/* TWL4030 keypad registers */
45+#define TWL4030_KEYPAD_KEYP_IMR1 0x12
46+#define TWL4030_KEYPAD_KEYP_IMR2 0x14
47+#define TWL4030_KEYPAD_KEYP_ISR1 0x11
48+#define TWL4030_KEYPAD_KEYP_ISR2 0x13
49+
50+
51 /* Triton Core internal information (END) */
52
53 /* Few power values */
54@@ -133,12 +153,10 @@
55 /* on I2C-1 for 2430SDP */
56 #define CONFIG_I2C_TWL4030_ID 1
57
58-/* SIH_CTRL registers */
59-#define TWL4030_INT_PWR_SIH_CTRL 0x07
60+/* SIH_CTRL registers that aren't defined elsewhere */
61 #define TWL4030_INTERRUPTS_BCISIHCTRL 0x0d
62 #define TWL4030_MADC_MADC_SIH_CTRL 0x67
63 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
64-#define TWL4030_GPIO_GPIO_SIH_CTRL 0x2d
65
66 #define TWL4030_SIH_CTRL_COR_MASK (1 << 2)
67
68@@ -776,135 +794,121 @@ static void twl_init_irq(void)
69 * handlers present.
70 */
71
72-
73- /* PWR_IMR1 */
74- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, 0x1) < 0);
75-
76- /* PWR_IMR2 */
77- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, 0x3) < 0);
78-
79- /* Clear off any other pending interrupts on power */
80+ /* Mask INT (PWR) interrupts at TWL4030 */
81+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff,
82+ TWL4030_INT_PWR_IMR1) < 0);
83+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff,
84+ TWL4030_INT_PWR_IMR2) < 0);
85
86 /* Are PWR interrupt status bits cleared by reads or writes? */
87 cor = twl4030_read_cor_bit(TWL4030_MODULE_INT,
88 TWL4030_INT_PWR_SIH_CTRL);
89 WARN_ON(cor < 0);
90
91- /* PWR_ISR1 */
92- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x00, cor) < 0);
93-
94- /* PWR_ISR2 */
95- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x02, cor) < 0);
96+ /* Clear TWL4030 INT (PWR) ISRs */
97+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT,
98+ TWL4030_INT_PWR_ISR1, cor) < 0);
99+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT,
100+ TWL4030_INT_PWR_ISR2, cor) < 0);
101
102 /* Slave address 0x4A */
103
104- /* BCIIMR1A */
105- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x2) < 0);
106-
107- /* BCIIMR2A */
108- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x3) < 0);
109-
110- /* BCIIMR2A */
111- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x6) < 0);
112-
113- /* BCIIMR2B */
114- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x7) < 0);
115+ /* Mask BCI interrupts at TWL4030 */
116+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
117+ TWL4030_INTERRUPTS_BCIIMR1A) < 0);
118+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
119+ TWL4030_INTERRUPTS_BCIIMR2A) < 0);
120+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
121+ TWL4030_INTERRUPTS_BCIIMR1B) < 0);
122+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
123+ TWL4030_INTERRUPTS_BCIIMR2B) < 0);
124
125 /* Are BCI interrupt status bits cleared by reads or writes? */
126 cor = twl4030_read_cor_bit(TWL4030_MODULE_INTERRUPTS,
127 TWL4030_INTERRUPTS_BCISIHCTRL);
128 WARN_ON(cor < 0);
129
130- /* BCIISR1A */
131- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x0, cor) < 0);
132-
133- /* BCIISR2A */
134- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x1, cor) < 0);
135-
136- /* BCIISR1B */
137- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x4, cor) < 0);
138-
139- /* BCIISR2B */
140- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x5, cor) < 0);
141+ /* Clear TWL4030 BCI ISRs */
142+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
143+ TWL4030_INTERRUPTS_BCIISR1A, cor) < 0);
144+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
145+ TWL4030_INTERRUPTS_BCIISR2A, cor) < 0);
146+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
147+ TWL4030_INTERRUPTS_BCIISR1B, cor) < 0);
148+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
149+ TWL4030_INTERRUPTS_BCIISR2B, cor) < 0);
150
151 /* MAD C */
152- /* MADC_IMR1 */
153- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, 0x62) < 0);
154-
155- /* MADC_IMR2 */
156- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, 0x64) < 0);
157+ /* Mask MADC interrupts at TWL4030 */
158+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff,
159+ TWL4030_MADC_IMR1) < 0);
160+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff,
161+ TWL4030_MADC_IMR2) < 0);
162
163 /* Are MADC interrupt status bits cleared by reads or writes? */
164 cor = twl4030_read_cor_bit(TWL4030_MODULE_MADC,
165 TWL4030_MADC_MADC_SIH_CTRL);
166 WARN_ON(cor < 0);
167
168- /* MADC_ISR1 */
169- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x61, cor) < 0);
170-
171- /* MADC_ISR2 */
172- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x63, cor) < 0);
173+ /* Clear TWL4030 MADC ISRs */
174+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC,
175+ TWL4030_MADC_ISR1, cor) < 0);
176+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC,
177+ TWL4030_MADC_ISR2, cor) < 0);
178
179 /* key Pad */
180- /* KEYPAD - IMR1 */
181- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, 0x12) < 0);
182+ /* Mask keypad interrupts at TWL4030 */
183+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff,
184+ TWL4030_KEYPAD_KEYP_IMR1) < 0);
185+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff,
186+ TWL4030_KEYPAD_KEYP_IMR2) < 0);
187
188 /* Are keypad interrupt status bits cleared by reads or writes? */
189 cor = twl4030_read_cor_bit(TWL4030_MODULE_KEYPAD,
190 TWL4030_KEYPAD_KEYP_SIH_CTRL);
191 WARN_ON(cor < 0);
192
193- /* KEYPAD - ISR1 */
194+ /* Clear TWL4030 keypad ISRs */
195 /* XXX does this still need to be done twice for some reason? */
196- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x11, cor) < 0);
197-
198- /* KEYPAD - IMR2 */
199- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, 0x14) < 0);
200-
201- /* KEYPAD - ISR2 */
202- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x13, cor) < 0);
203+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD,
204+ TWL4030_KEYPAD_KEYP_ISR1, cor) < 0);
205+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD,
206+ TWL4030_KEYPAD_KEYP_ISR2, cor) < 0);
207
208 /* Slave address 0x49 */
209- /* GPIO_IMR1A */
210- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1c) < 0);
211-
212- /* GPIO_IMR2A */
213- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1d) < 0);
214-
215- /* GPIO_IMR3A */
216- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1e) < 0);
217-
218- /* GPIO_IMR1B */
219- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x22) < 0);
220
221- /* GPIO_IMR2B */
222- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x23) < 0);
223-
224- /* GPIO_IMR3B */
225- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x24) < 0);
226+ /* Mask GPIO interrupts at TWL4030 */
227+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
228+ REG_GPIO_IMR1A) < 0);
229+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
230+ REG_GPIO_IMR2A) < 0);
231+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
232+ REG_GPIO_IMR3A) < 0);
233+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
234+ REG_GPIO_IMR1B) < 0);
235+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
236+ REG_GPIO_IMR2B) < 0);
237+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
238+ REG_GPIO_IMR3B) < 0);
239
240 /* Are GPIO interrupt status bits cleared by reads or writes? */
241 cor = twl4030_read_cor_bit(TWL4030_MODULE_GPIO,
242- TWL4030_GPIO_GPIO_SIH_CTRL);
243+ REG_GPIO_SIH_CTRL);
244 WARN_ON(cor < 0);
245
246- /* GPIO_ISR1A */
247- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x19, cor) < 0);
248-
249- /* GPIO_ISR2A */
250- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1a, cor) < 0);
251-
252- /* GPIO_ISR3A */
253- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1b, cor) < 0);
254-
255- /* GPIO_ISR1B */
256- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1f, cor) < 0);
257-
258- /* GPIO_ISR2B */
259- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x20, cor) < 0);
260-
261- /* GPIO_ISR3B */
262- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x21, cor) < 0);
263+ /* Clear TWL4030 GPIO ISRs */
264+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR1A,
265+ cor) < 0);
266+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR2A,
267+ cor) < 0);
268+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR3A,
269+ cor) < 0);
270+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR1B,
271+ cor) < 0);
272+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR2B,
273+ cor) < 0);
274+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR3B,
275+ cor) < 0);
276
277 /* install an irq handler for each of the PIH modules */
278 for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) {
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-04-27 07:38:28 +0000