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-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/isp/omap3camera/0001-omap3isp-Add-ISP-main-driver-and-register-definitio.patch4625
1 files changed, 4625 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/omap3camera/0001-omap3isp-Add-ISP-main-driver-and-register-definitio.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/omap3camera/0001-omap3isp-Add-ISP-main-driver-and-register-definitio.patch
new file mode 100644
index 0000000000..e6e07d8afc
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/omap3camera/0001-omap3isp-Add-ISP-main-driver-and-register-definitio.patch
@@ -0,0 +1,4625 @@
1From 77c99cd863b906c803c3dec08753c19bf9b67882 Mon Sep 17 00:00:00 2001
2From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
3Date: Tue, 10 Mar 2009 10:49:02 +0200
4Subject: [PATCH] omap3isp: Add ISP main driver and register definitions
5
6TODO:
7
8- Release resoures in isp_probe() if something fails.
9
10- Implement a sensible generic interface so that the ISP can offer a
11 v4l2_subdev (like the v4l2-int-device slaves) interface towards the
12 camera driver.
13
14- Handle CSI1 and CSI2 error cases (currently unhandled?).
15
16- Fix H3A / HIST interrupt enabling / disabling.
17
18- Clean up the private ioctls.
19
20- Handle SBL overflows somehow.
21
22Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
23---
24 drivers/media/video/Makefile | 2 +
25 drivers/media/video/isp/Makefile | 12 +
26 drivers/media/video/isp/isp.c | 2547 ++++++++++++++++++++++++++++++++++++++
27 drivers/media/video/isp/isp.h | 318 +++++
28 drivers/media/video/isp/ispreg.h | 1674 +++++++++++++++++++++++++
29 5 files changed, 4553 insertions(+), 0 deletions(-)
30 create mode 100644 drivers/media/video/isp/Makefile
31 create mode 100644 drivers/media/video/isp/isp.c
32 create mode 100644 drivers/media/video/isp/isp.h
33 create mode 100644 drivers/media/video/isp/ispreg.h
34
35diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
36index 72f6d03..e654270 100644
37--- a/drivers/media/video/Makefile
38+++ b/drivers/media/video/Makefile
39@@ -106,6 +106,8 @@ obj-$(CONFIG_VIDEO_CX2341X) += cx2341x.o
40 obj-$(CONFIG_VIDEO_CAFE_CCIC) += cafe_ccic.o
41 obj-$(CONFIG_VIDEO_OV7670) += ov7670.o
42
43+obj-y += isp/
44+
45 obj-$(CONFIG_VIDEO_TCM825X) += tcm825x.o
46
47 obj-$(CONFIG_USB_DABUSB) += dabusb.o
48diff --git a/drivers/media/video/isp/Makefile b/drivers/media/video/isp/Makefile
49new file mode 100644
50index 0000000..f14d617
51--- /dev/null
52+++ b/drivers/media/video/isp/Makefile
53@@ -0,0 +1,12 @@
54+# Makefile for OMAP3 ISP driver
55+
56+ifdef CONFIG_ARCH_OMAP3410
57+isp-mod-objs += \
58+ isp.o ispccdc.o
59+else
60+isp-mod-objs += \
61+ isp.o ispccdc.o ispmmu.o \
62+ isppreview.o ispresizer.o isph3a.o isphist.o isp_af.o ispcsi2.o
63+endif
64+
65+obj-$(CONFIG_VIDEO_OMAP3) += isp-mod.o
66diff --git a/drivers/media/video/isp/isp.c b/drivers/media/video/isp/isp.c
67new file mode 100644
68index 0000000..54c839b
69--- /dev/null
70+++ b/drivers/media/video/isp/isp.c
71@@ -0,0 +1,2547 @@
72+/*
73+ * isp.c
74+ *
75+ * Driver Library for ISP Control module in TI's OMAP3 Camera ISP
76+ * ISP interface and IRQ related APIs are defined here.
77+ *
78+ * Copyright (C) 2009 Texas Instruments.
79+ * Copyright (C) 2009 Nokia.
80+ *
81+ * Contributors:
82+ * Sameer Venkatraman <sameerv@ti.com>
83+ * Mohit Jalori <mjalori@ti.com>
84+ * Sergio Aguirre <saaguirre@ti.com>
85+ * Sakari Ailus <sakari.ailus@nokia.com>
86+ * Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
87+ * Toni Leinonen <toni.leinonen@nokia.com>
88+ *
89+ * This package is free software; you can redistribute it and/or modify
90+ * it under the terms of the GNU General Public License version 2 as
91+ * published by the Free Software Foundation.
92+ *
93+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
94+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
95+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
96+ */
97+
98+#include <asm/cacheflush.h>
99+
100+#include <linux/delay.h>
101+#include <linux/interrupt.h>
102+#include <linux/clk.h>
103+#include <linux/dma-mapping.h>
104+#include <linux/vmalloc.h>
105+#include <linux/platform_device.h>
106+
107+#include "isp.h"
108+#include "ispmmu.h"
109+#include "ispreg.h"
110+#include "ispccdc.h"
111+#include "isph3a.h"
112+#include "isphist.h"
113+#include "isp_af.h"
114+#include "isppreview.h"
115+#include "ispresizer.h"
116+#include "ispcsi2.h"
117+
118+static struct isp_device *omap3isp;
119+
120+static int isp_try_size(struct v4l2_pix_format *pix_input,
121+ struct v4l2_pix_format *pix_output);
122+
123+static void isp_save_ctx(void);
124+
125+static void isp_restore_ctx(void);
126+
127+static void isp_buf_init(void);
128+
129+/* List of image formats supported via OMAP ISP */
130+const static struct v4l2_fmtdesc isp_formats[] = {
131+ {
132+ .description = "UYVY, packed",
133+ .pixelformat = V4L2_PIX_FMT_UYVY,
134+ },
135+ {
136+ .description = "YUYV (YUV 4:2:2), packed",
137+ .pixelformat = V4L2_PIX_FMT_YUYV,
138+ },
139+ {
140+ .description = "Bayer10 (GrR/BGb)",
141+ .pixelformat = V4L2_PIX_FMT_SGRBG10,
142+ },
143+};
144+
145+/* ISP Crop capabilities */
146+static struct v4l2_rect ispcroprect;
147+static struct v4l2_rect cur_rect;
148+
149+/**
150+ * struct vcontrol - Video control structure.
151+ * @qc: V4L2 Query control structure.
152+ * @current_value: Current value of the control.
153+ */
154+static struct vcontrol {
155+ struct v4l2_queryctrl qc;
156+ int current_value;
157+} video_control[] = {
158+ {
159+ {
160+ .id = V4L2_CID_BRIGHTNESS,
161+ .type = V4L2_CTRL_TYPE_INTEGER,
162+ .name = "Brightness",
163+ .minimum = ISPPRV_BRIGHT_LOW,
164+ .maximum = ISPPRV_BRIGHT_HIGH,
165+ .step = ISPPRV_BRIGHT_STEP,
166+ .default_value = ISPPRV_BRIGHT_DEF,
167+ },
168+ .current_value = ISPPRV_BRIGHT_DEF,
169+ },
170+ {
171+ {
172+ .id = V4L2_CID_CONTRAST,
173+ .type = V4L2_CTRL_TYPE_INTEGER,
174+ .name = "Contrast",
175+ .minimum = ISPPRV_CONTRAST_LOW,
176+ .maximum = ISPPRV_CONTRAST_HIGH,
177+ .step = ISPPRV_CONTRAST_STEP,
178+ .default_value = ISPPRV_CONTRAST_DEF,
179+ },
180+ .current_value = ISPPRV_CONTRAST_DEF,
181+ },
182+ {
183+ {
184+ .id = V4L2_CID_COLORFX,
185+ .type = V4L2_CTRL_TYPE_MENU,
186+ .name = "Color Effects",
187+ .minimum = V4L2_COLORFX_NONE,
188+ .maximum = V4L2_COLORFX_SEPIA,
189+ .step = 1,
190+ .default_value = V4L2_COLORFX_NONE,
191+ },
192+ .current_value = V4L2_COLORFX_NONE,
193+ }
194+};
195+
196+static struct v4l2_querymenu video_menu[] = {
197+ {
198+ .id = V4L2_CID_COLORFX,
199+ .index = 0,
200+ .name = "None",
201+ },
202+ {
203+ .id = V4L2_CID_COLORFX,
204+ .index = 1,
205+ .name = "B&W",
206+ },
207+ {
208+ .id = V4L2_CID_COLORFX,
209+ .index = 2,
210+ .name = "Sepia",
211+ },
212+};
213+
214+struct isp_buf {
215+ dma_addr_t isp_addr;
216+ void (*complete)(struct videobuf_buffer *vb, void *priv);
217+ struct videobuf_buffer *vb;
218+ void *priv;
219+ u32 vb_state;
220+};
221+
222+#define ISP_BUFS_IS_FULL(bufs) \
223+ (((bufs)->queue + 1) % NUM_BUFS == (bufs)->done)
224+#define ISP_BUFS_IS_EMPTY(bufs) ((bufs)->queue == (bufs)->done)
225+#define ISP_BUFS_IS_LAST(bufs) \
226+ ((bufs)->queue == ((bufs)->done + 1) % NUM_BUFS)
227+#define ISP_BUFS_QUEUED(bufs) \
228+ ((((bufs)->done - (bufs)->queue + NUM_BUFS)) % NUM_BUFS)
229+#define ISP_BUF_DONE(bufs) ((bufs)->buf + (bufs)->done)
230+#define ISP_BUF_NEXT_DONE(bufs) \
231+ ((bufs)->buf + ((bufs)->done + 1) % NUM_BUFS)
232+#define ISP_BUF_QUEUE(bufs) ((bufs)->buf + (bufs)->queue)
233+#define ISP_BUF_MARK_DONE(bufs) \
234+ (bufs)->done = ((bufs)->done + 1) % NUM_BUFS;
235+#define ISP_BUF_MARK_QUEUED(bufs) \
236+ (bufs)->queue = ((bufs)->queue + 1) % NUM_BUFS;
237+
238+struct isp_bufs {
239+ dma_addr_t isp_addr_capture[VIDEO_MAX_FRAME];
240+ spinlock_t lock; /* For handling current buffer */
241+ /* queue full: (ispsg.queue + 1) % NUM_BUFS == ispsg.done
242+ queue empty: ispsg.queue == ispsg.done */
243+ struct isp_buf buf[NUM_BUFS];
244+ /* Next slot to queue a buffer. */
245+ int queue;
246+ /* Buffer that is being processed. */
247+ int done;
248+ /* Wait for this many hs_vs before anything else. */
249+ int wait_hs_vs;
250+};
251+
252+/**
253+ * struct ispirq - Structure for containing callbacks to be called in ISP ISR.
254+ * @isp_callbk: Array which stores callback functions, indexed by the type of
255+ * callback (8 possible types).
256+ * @isp_callbk_arg1: Pointer to array containing pointers to the first argument
257+ * to be passed to the requested callback function.
258+ * @isp_callbk_arg2: Pointer to array containing pointers to the second
259+ * argument to be passed to the requested callback function.
260+ *
261+ * This structure is used to contain all the callback functions related for
262+ * each callback type (CBK_CCDC_VD0, CBK_CCDC_VD1, CBK_PREV_DONE,
263+ * CBK_RESZ_DONE, CBK_MMU_ERR, CBK_H3A_AWB_DONE, CBK_HIST_DONE, CBK_HS_VS,
264+ * CBK_LSC_ISR).
265+ */
266+struct isp_irq {
267+ isp_callback_t isp_callbk[CBK_END];
268+ isp_vbq_callback_ptr isp_callbk_arg1[CBK_END];
269+ void *isp_callbk_arg2[CBK_END];
270+};
271+
272+/**
273+ * struct ispmodule - Structure for storing ISP sub-module information.
274+ * @isp_pipeline: Bit mask for submodules enabled within the ISP.
275+ * @applyCrop: Flag to do a crop operation when video buffer queue ISR is done
276+ * @pix: Structure containing the format and layout of the output image.
277+ * @ccdc_input_width: ISP CCDC module input image width.
278+ * @ccdc_input_height: ISP CCDC module input image height.
279+ * @ccdc_output_width: ISP CCDC module output image width.
280+ * @ccdc_output_height: ISP CCDC module output image height.
281+ * @preview_input_width: ISP Preview module input image width.
282+ * @preview_input_height: ISP Preview module input image height.
283+ * @preview_output_width: ISP Preview module output image width.
284+ * @preview_output_height: ISP Preview module output image height.
285+ * @resizer_input_width: ISP Resizer module input image width.
286+ * @resizer_input_height: ISP Resizer module input image height.
287+ * @resizer_output_width: ISP Resizer module output image width.
288+ * @resizer_output_height: ISP Resizer module output image height.
289+ */
290+struct isp_module {
291+ unsigned int isp_pipeline;
292+ int applyCrop;
293+ struct v4l2_pix_format pix;
294+ unsigned int ccdc_input_width;
295+ unsigned int ccdc_input_height;
296+ unsigned int ccdc_output_width;
297+ unsigned int ccdc_output_height;
298+ unsigned int preview_input_width;
299+ unsigned int preview_input_height;
300+ unsigned int preview_output_width;
301+ unsigned int preview_output_height;
302+ unsigned int resizer_input_width;
303+ unsigned int resizer_input_height;
304+ unsigned int resizer_output_width;
305+ unsigned int resizer_output_height;
306+};
307+
308+#define RAW_CAPTURE(isp) \
309+ (!((isp)->module.isp_pipeline & OMAP_ISP_PREVIEW))
310+
311+/**
312+ * struct isp - Structure for storing ISP Control module information
313+ * @lock: Spinlock to sync between isr and processes.
314+ * @isp_mutex: Semaphore used to get access to the ISP.
315+ * @ref_count: Reference counter.
316+ * @cam_ick: Pointer to ISP Interface clock.
317+ * @cam_fck: Pointer to ISP Functional clock.
318+ *
319+ * This structure is used to store the OMAP ISP Control Information.
320+ */
321+static struct isp {
322+ spinlock_t lock; /* For handling registered ISP callbacks */
323+ struct mutex isp_mutex; /* For handling ref_count field */
324+ int ref_count;
325+ struct clk *cam_ick;
326+ struct clk *cam_mclk;
327+ struct clk *csi2_fck;
328+ struct isp_interface_config *config;
329+ dma_addr_t tmp_buf;
330+ size_t tmp_buf_size;
331+ unsigned long tmp_buf_offset;
332+ struct isp_bufs bufs;
333+ struct isp_irq irq;
334+ struct isp_module module;
335+} isp_obj;
336+
337+/* Structure for saving/restoring ISP module registers */
338+static struct isp_reg isp_reg_list[] = {
339+ {OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0},
340+ {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_GRESET_LENGTH, 0},
341+ {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_PSTRB_REPLAY, 0},
342+ {OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0},
343+ {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0},
344+ {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_FRAME, 0},
345+ {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_PSTRB_DELAY, 0},
346+ {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_STRB_DELAY, 0},
347+ {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_SHUT_DELAY, 0},
348+ {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_PSTRB_LENGTH, 0},
349+ {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_STRB_LENGTH, 0},
350+ {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_SHUT_LENGTH, 0},
351+ {OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF_SYSCONFIG, 0},
352+ {OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF_IRQENABLE, 0},
353+ {OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF0_CTRL, 0},
354+ {OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF1_CTRL, 0},
355+ {OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF0_START, 0},
356+ {OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF1_START, 0},
357+ {OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF0_END, 0},
358+ {OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF1_END, 0},
359+ {OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF0_WINDOWSIZE, 0},
360+ {OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF1_WINDOWSIZE, 0},
361+ {OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF0_THRESHOLD, 0},
362+ {OMAP3_ISP_IOMEM_CBUFF, ISP_CBUFF1_THRESHOLD, 0},
363+ {0, ISP_TOK_TERM, 0}
364+};
365+
366+u32 isp_reg_readl(enum isp_mem_resources isp_mmio_range, u32 reg_offset)
367+{
368+ return __raw_readl(omap3isp->mmio_base[isp_mmio_range] + reg_offset);
369+}
370+EXPORT_SYMBOL(isp_reg_readl);
371+
372+void isp_reg_writel(u32 reg_value, enum isp_mem_resources isp_mmio_range,
373+ u32 reg_offset)
374+{
375+ __raw_writel(reg_value,
376+ omap3isp->mmio_base[isp_mmio_range] + reg_offset);
377+}
378+EXPORT_SYMBOL(isp_reg_writel);
379+
380+/*
381+ *
382+ * V4L2 Handling
383+ *
384+ */
385+
386+/**
387+ * find_vctrl - Returns the index of the ctrl array of the requested ctrl ID.
388+ * @id: Requested control ID.
389+ *
390+ * Returns 0 if successful, -EINVAL if not found, or -EDOM if its out of
391+ * domain.
392+ **/
393+static int find_vctrl(int id)
394+{
395+ int i;
396+
397+ if (id < V4L2_CID_BASE)
398+ return -EDOM;
399+
400+ for (i = (ARRAY_SIZE(video_control) - 1); i >= 0; i--)
401+ if (video_control[i].qc.id == id)
402+ break;
403+
404+ if (i < 0)
405+ i = -EINVAL;
406+
407+ return i;
408+}
409+
410+static int find_next_vctrl(int id)
411+{
412+ int i;
413+ u32 best = (u32)-1;
414+
415+ for (i = 0; i < ARRAY_SIZE(video_control); i++) {
416+ if (video_control[i].qc.id > id &&
417+ (best == (u32)-1 ||
418+ video_control[i].qc.id <
419+ video_control[best].qc.id)) {
420+ best = i;
421+ }
422+ }
423+
424+ if (best == (u32)-1)
425+ return -EINVAL;
426+
427+ return best;
428+}
429+
430+/**
431+ * find_vmenu - Returns index of the menu array of the requested ctrl option.
432+ * @id: Requested control ID.
433+ * @index: Requested menu option index.
434+ *
435+ * Returns 0 if successful, -EINVAL if not found, or -EDOM if its out of
436+ * domain.
437+ **/
438+static int find_vmenu(int id, int index)
439+{
440+ int i;
441+
442+ if (id < V4L2_CID_BASE)
443+ return -EDOM;
444+
445+ for (i = (ARRAY_SIZE(video_menu) - 1); i >= 0; i--) {
446+ if (video_menu[i].id != id || video_menu[i].index != index)
447+ continue;
448+ return i;
449+ }
450+
451+ return -EINVAL;
452+}
453+
454+/**
455+ * isp_release_resources - Free ISP submodules
456+ **/
457+static void isp_release_resources(void)
458+{
459+ if (isp_obj.module.isp_pipeline & OMAP_ISP_CCDC)
460+ ispccdc_free();
461+
462+ if (isp_obj.module.isp_pipeline & OMAP_ISP_PREVIEW)
463+ isppreview_free();
464+
465+ if (isp_obj.module.isp_pipeline & OMAP_ISP_RESIZER)
466+ ispresizer_free();
467+ return;
468+}
469+
470+static int isp_wait(int (*busy)(void), int wait_for_busy, int max_wait)
471+{
472+ int wait = 0;
473+
474+ if (max_wait == 0)
475+ max_wait = 10000; /* 10 ms */
476+
477+ while ((wait_for_busy && !busy())
478+ || (!wait_for_busy && busy())) {
479+ rmb();
480+ udelay(1);
481+ wait++;
482+ if (wait > max_wait) {
483+ printk(KERN_ALERT "%s: wait is too much\n", __func__);
484+ return -EBUSY;
485+ }
486+ }
487+ DPRINTK_ISPCTRL(KERN_ALERT "%s: wait %d\n", __func__, wait);
488+
489+ return 0;
490+}
491+
492+static int ispccdc_sbl_wait_idle(int max_wait)
493+{
494+ return isp_wait(ispccdc_sbl_busy, 0, max_wait);
495+}
496+
497+static void isp_enable_interrupts(int is_raw)
498+{
499+ isp_reg_writel(-1, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
500+ isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
501+ IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ |
502+ IRQ0ENABLE_HS_VS_IRQ |
503+ IRQ0ENABLE_CCDC_VD0_IRQ |
504+ IRQ0ENABLE_CCDC_VD1_IRQ);
505+
506+ if (is_raw)
507+ return;
508+
509+ isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
510+ IRQ0ENABLE_PRV_DONE_IRQ |
511+ IRQ0ENABLE_RSZ_DONE_IRQ);
512+
513+ return;
514+}
515+
516+static void isp_disable_interrupts(void)
517+{
518+ isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
519+ ~(IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ |
520+ IRQ0ENABLE_HS_VS_IRQ |
521+ IRQ0ENABLE_CCDC_VD0_IRQ |
522+ IRQ0ENABLE_CCDC_VD1_IRQ |
523+ IRQ0ENABLE_PRV_DONE_IRQ |
524+ IRQ0ENABLE_RSZ_DONE_IRQ));
525+}
526+
527+/**
528+ * isp_set_callback - Sets the callback for the ISP module done events.
529+ * @type: Type of the event for which callback is requested.
530+ * @callback: Method to be called as callback in the ISR context.
531+ * @arg1: First argument to be passed when callback is called in ISR.
532+ * @arg2: Second argument to be passed when callback is called in ISR.
533+ *
534+ * This function sets a callback function for a done event in the ISP
535+ * module, and enables the corresponding interrupt.
536+ **/
537+int isp_set_callback(enum isp_callback_type type, isp_callback_t callback,
538+ isp_vbq_callback_ptr arg1,
539+ void *arg2)
540+{
541+ unsigned long irqflags = 0;
542+
543+ if (callback == NULL) {
544+ DPRINTK_ISPCTRL("ISP_ERR : Null Callback\n");
545+ return -EINVAL;
546+ }
547+
548+ spin_lock_irqsave(&isp_obj.lock, irqflags);
549+ isp_obj.irq.isp_callbk[type] = callback;
550+ isp_obj.irq.isp_callbk_arg1[type] = arg1;
551+ isp_obj.irq.isp_callbk_arg2[type] = arg2;
552+ spin_unlock_irqrestore(&isp_obj.lock, irqflags);
553+
554+ switch (type) {
555+ case CBK_H3A_AWB_DONE:
556+ isp_reg_writel(IRQ0ENABLE_H3A_AWB_DONE_IRQ,
557+ OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
558+ isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
559+ IRQ0ENABLE_H3A_AWB_DONE_IRQ);
560+ break;
561+ case CBK_H3A_AF_DONE:
562+ isp_reg_writel(IRQ0ENABLE_H3A_AF_DONE_IRQ,
563+ OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
564+ isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
565+ IRQ0ENABLE_H3A_AF_DONE_IRQ);
566+ break;
567+ case CBK_HIST_DONE:
568+ isp_reg_writel(IRQ0ENABLE_HIST_DONE_IRQ,
569+ OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
570+ isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
571+ IRQ0ENABLE_HIST_DONE_IRQ);
572+ break;
573+ case CBK_PREV_DONE:
574+ isp_reg_writel(IRQ0ENABLE_PRV_DONE_IRQ,
575+ OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
576+ isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
577+ IRQ0ENABLE_PRV_DONE_IRQ);
578+ break;
579+ default:
580+ break;
581+ }
582+
583+ return 0;
584+}
585+EXPORT_SYMBOL(isp_set_callback);
586+
587+/**
588+ * isp_unset_callback - Clears the callback for the ISP module done events.
589+ * @type: Type of the event for which callback to be cleared.
590+ *
591+ * This function clears a callback function for a done event in the ISP
592+ * module, and disables the corresponding interrupt.
593+ **/
594+int isp_unset_callback(enum isp_callback_type type)
595+{
596+ unsigned long irqflags = 0;
597+
598+ spin_lock_irqsave(&isp_obj.lock, irqflags);
599+ isp_obj.irq.isp_callbk[type] = NULL;
600+ isp_obj.irq.isp_callbk_arg1[type] = NULL;
601+ isp_obj.irq.isp_callbk_arg2[type] = NULL;
602+ spin_unlock_irqrestore(&isp_obj.lock, irqflags);
603+
604+ switch (type) {
605+ case CBK_H3A_AWB_DONE:
606+ isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
607+ ~IRQ0ENABLE_H3A_AWB_DONE_IRQ);
608+ break;
609+ case CBK_H3A_AF_DONE:
610+ isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
611+ ~IRQ0ENABLE_H3A_AF_DONE_IRQ);
612+ break;
613+ case CBK_HIST_DONE:
614+ isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
615+ ~IRQ0ENABLE_HIST_DONE_IRQ);
616+ break;
617+ case CBK_CSIA:
618+ isp_csi2_irq_set(0);
619+ break;
620+ case CBK_CSIB:
621+ isp_reg_writel(IRQ0ENABLE_CSIB_IRQ, OMAP3_ISP_IOMEM_MAIN,
622+ ISP_IRQ0STATUS);
623+ isp_reg_or(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
624+ IRQ0ENABLE_CSIB_IRQ);
625+ break;
626+ case CBK_PREV_DONE:
627+ isp_reg_and(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE,
628+ ~IRQ0ENABLE_PRV_DONE_IRQ);
629+ break;
630+ default:
631+ break;
632+ }
633+
634+ return 0;
635+}
636+EXPORT_SYMBOL(isp_unset_callback);
637+
638+/**
639+ * isp_set_xclk - Configures the specified cam_xclk to the desired frequency.
640+ * @xclk: Desired frequency of the clock in Hz.
641+ * @xclksel: XCLK to configure (0 = A, 1 = B).
642+ *
643+ * Configures the specified MCLK divisor in the ISP timing control register
644+ * (TCTRL_CTRL) to generate the desired xclk clock value.
645+ *
646+ * Divisor = CM_CAM_MCLK_HZ / xclk
647+ *
648+ * Returns the final frequency that is actually being generated
649+ **/
650+u32 isp_set_xclk(u32 xclk, u8 xclksel)
651+{
652+ u32 divisor;
653+ u32 currentxclk;
654+
655+ if (xclk >= CM_CAM_MCLK_HZ) {
656+ divisor = ISPTCTRL_CTRL_DIV_BYPASS;
657+ currentxclk = CM_CAM_MCLK_HZ;
658+ } else if (xclk >= 2) {
659+ divisor = CM_CAM_MCLK_HZ / xclk;
660+ if (divisor >= ISPTCTRL_CTRL_DIV_BYPASS)
661+ divisor = ISPTCTRL_CTRL_DIV_BYPASS - 1;
662+ currentxclk = CM_CAM_MCLK_HZ / divisor;
663+ } else {
664+ divisor = xclk;
665+ currentxclk = 0;
666+ }
667+
668+ switch (xclksel) {
669+ case 0:
670+ isp_reg_and_or(OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
671+ ~ISPTCTRL_CTRL_DIVA_MASK,
672+ divisor << ISPTCTRL_CTRL_DIVA_SHIFT);
673+ DPRINTK_ISPCTRL("isp_set_xclk(): cam_xclka set to %d Hz\n",
674+ currentxclk);
675+ break;
676+ case 1:
677+ isp_reg_and_or(OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
678+ ~ISPTCTRL_CTRL_DIVB_MASK,
679+ divisor << ISPTCTRL_CTRL_DIVB_SHIFT);
680+ DPRINTK_ISPCTRL("isp_set_xclk(): cam_xclkb set to %d Hz\n",
681+ currentxclk);
682+ break;
683+ default:
684+ DPRINTK_ISPCTRL("ISP_ERR: isp_set_xclk(): Invalid requested "
685+ "xclk. Must be 0 (A) or 1 (B)."
686+ "\n");
687+ return -EINVAL;
688+ }
689+
690+ return currentxclk;
691+}
692+EXPORT_SYMBOL(isp_set_xclk);
693+
694+/**
695+ * isp_power_settings - Sysconfig settings, for Power Management.
696+ * @isp_sysconfig: Structure containing the power settings for ISP to configure
697+ *
698+ * Sets the power settings for the ISP, and SBL bus.
699+ **/
700+static void isp_power_settings(int idle)
701+{
702+ if (idle) {
703+ isp_reg_writel(ISP_SYSCONFIG_AUTOIDLE |
704+ (ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY <<
705+ ISP_SYSCONFIG_MIDLEMODE_SHIFT),
706+ OMAP3_ISP_IOMEM_MAIN,
707+ ISP_SYSCONFIG);
708+ if (omap_rev() == OMAP3430_REV_ES1_0) {
709+ isp_reg_writel(ISPCSI1_AUTOIDLE |
710+ (ISPCSI1_MIDLEMODE_SMARTSTANDBY <<
711+ ISPCSI1_MIDLEMODE_SHIFT),
712+ OMAP3_ISP_IOMEM_CSI2A,
713+ ISP_CSIA_SYSCONFIG);
714+ isp_reg_writel(ISPCSI1_AUTOIDLE |
715+ (ISPCSI1_MIDLEMODE_SMARTSTANDBY <<
716+ ISPCSI1_MIDLEMODE_SHIFT),
717+ OMAP3_ISP_IOMEM_CCP2,
718+ ISP_CSIB_SYSCONFIG);
719+ }
720+ isp_reg_writel(ISPCTRL_SBL_AUTOIDLE, OMAP3_ISP_IOMEM_MAIN,
721+ ISP_CTRL);
722+
723+ } else {
724+ isp_reg_writel(ISP_SYSCONFIG_AUTOIDLE |
725+ (ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY <<
726+ ISP_SYSCONFIG_MIDLEMODE_SHIFT),
727+ OMAP3_ISP_IOMEM_MAIN,
728+ ISP_SYSCONFIG);
729+ if (omap_rev() == OMAP3430_REV_ES1_0) {
730+ isp_reg_writel(ISPCSI1_AUTOIDLE |
731+ (ISPCSI1_MIDLEMODE_FORCESTANDBY <<
732+ ISPCSI1_MIDLEMODE_SHIFT),
733+ OMAP3_ISP_IOMEM_CSI2A,
734+ ISP_CSIA_SYSCONFIG);
735+
736+ isp_reg_writel(ISPCSI1_AUTOIDLE |
737+ (ISPCSI1_MIDLEMODE_FORCESTANDBY <<
738+ ISPCSI1_MIDLEMODE_SHIFT),
739+ OMAP3_ISP_IOMEM_CCP2,
740+ ISP_CSIB_SYSCONFIG);
741+ }
742+
743+ isp_reg_writel(ISPCTRL_SBL_AUTOIDLE, OMAP3_ISP_IOMEM_MAIN,
744+ ISP_CTRL);
745+ }
746+}
747+
748+#define BIT_SET(var, shift, mask, val) \
749+ do { \
750+ var = (var & ~(mask << shift)) \
751+ | (val << shift); \
752+ } while (0)
753+
754+static int isp_init_csi(struct isp_interface_config *config)
755+{
756+ u32 i = 0, val, reg;
757+ int format;
758+
759+ switch (config->u.csi.format) {
760+ case V4L2_PIX_FMT_SGRBG10:
761+ format = 0x16; /* RAW10+VP */
762+ break;
763+ case V4L2_PIX_FMT_SGRBG10DPCM8:
764+ format = 0x12; /* RAW8+DPCM10+VP */
765+ break;
766+ default:
767+ printk(KERN_ERR "isp_init_csi: bad csi format\n");
768+ return -EINVAL;
769+ }
770+
771+ /* Reset the CSI and wait for reset to complete */
772+ isp_reg_writel(isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, ISPCSI1_SYSCONFIG) |
773+ BIT(1),
774+ OMAP3_ISP_IOMEM_CCP2,
775+ ISPCSI1_SYSCONFIG);
776+ while (!(isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, ISPCSI1_SYSSTATUS) &
777+ BIT(0))) {
778+ udelay(10);
779+ if (i++ > 10)
780+ break;
781+ }
782+ if (!(isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, ISPCSI1_SYSSTATUS) &
783+ BIT(0))) {
784+ printk(KERN_WARNING
785+ "omap3_isp: timeout waiting for csi reset\n");
786+ }
787+
788+ /* ISPCSI1_CTRL */
789+ val = isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, ISPCSI1_CTRL);
790+ val &= ~BIT(11); /* Enable VP only off ->
791+ extract embedded data to interconnect */
792+ BIT_SET(val, 8, 0x3, config->u.csi.vpclk); /* Video port clock */
793+/* val |= BIT(3); */ /* Wait for FEC before disabling interface */
794+ val |= BIT(2); /* I/O cell output is parallel
795+ (no effect, but errata says should be enabled
796+ for class 1/2) */
797+ val |= BIT(12); /* VP clock polarity to falling edge
798+ (needed or bad picture!) */
799+
800+ /* Data/strobe physical layer */
801+ BIT_SET(val, 1, 1, config->u.csi.signalling);
802+ BIT_SET(val, 10, 1, config->u.csi.strobe_clock_inv);
803+ val |= BIT(4); /* Magic bit to enable CSI1 and strobe mode */
804+ isp_reg_writel(val, OMAP3_ISP_IOMEM_CCP2, ISPCSI1_CTRL);
805+
806+ /* ISPCSI1_LCx_CTRL logical channel #0 */
807+ reg = ISPCSI1_LCx_CTRL(0); /* reg = ISPCSI1_CTRL1; */
808+ val = isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, reg);
809+ /* Format = RAW10+VP or RAW8+DPCM10+VP*/
810+ BIT_SET(val, 3, 0x1f, format);
811+ /* Enable setting of frame regions of interest */
812+ BIT_SET(val, 1, 1, 1);
813+ BIT_SET(val, 2, 1, config->u.csi.crc);
814+ isp_reg_writel(val, OMAP3_ISP_IOMEM_CCP2, reg);
815+
816+ /* ISPCSI1_DAT_START for logical channel #0 */
817+ reg = ISPCSI1_LCx_DAT_START(0); /* reg = ISPCSI1_DAT_START; */
818+ val = isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, reg);
819+ BIT_SET(val, 16, 0xfff, config->u.csi.data_start);
820+ isp_reg_writel(val, OMAP3_ISP_IOMEM_CCP2, reg);
821+
822+ /* ISPCSI1_DAT_SIZE for logical channel #0 */
823+ reg = ISPCSI1_LCx_DAT_SIZE(0); /* reg = ISPCSI1_DAT_SIZE; */
824+ val = isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, reg);
825+ BIT_SET(val, 16, 0xfff, config->u.csi.data_size);
826+ isp_reg_writel(val, OMAP3_ISP_IOMEM_CCP2, reg);
827+
828+ /* Clear status bits for logical channel #0 */
829+ isp_reg_writel(0xFFF & ~BIT(6), OMAP3_ISP_IOMEM_CCP2,
830+ ISPCSI1_LC01_IRQSTATUS);
831+
832+ /* Enable CSI1 */
833+ val = isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, ISPCSI1_CTRL);
834+ val |= BIT(0) | BIT(4);
835+ isp_reg_writel(val, OMAP3_ISP_IOMEM_CCP2, ISPCSI1_CTRL);
836+
837+ if (!(isp_reg_readl(OMAP3_ISP_IOMEM_CCP2, ISPCSI1_CTRL) & BIT(4))) {
838+ printk(KERN_WARNING "OMAP3 CSI1 bus not available\n");
839+ if (config->u.csi.signalling) /* Strobe mode requires CSI1 */
840+ return -EIO;
841+ }
842+
843+ return 0;
844+}
845+
846+/**
847+ * isp_configure_interface - Configures ISP Control I/F related parameters.
848+ * @config: Pointer to structure containing the desired configuration for the
849+ * ISP.
850+ *
851+ * Configures ISP control register (ISP_CTRL) with the values specified inside
852+ * the config structure. Controls:
853+ * - Selection of parallel or serial input to the preview hardware.
854+ * - Data lane shifter.
855+ * - Pixel clock polarity.
856+ * - 8 to 16-bit bridge at the input of CCDC module.
857+ * - HS or VS synchronization signal detection
858+ **/
859+int isp_configure_interface(struct isp_interface_config *config)
860+{
861+ u32 ispctrl_val = isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
862+ int r;
863+
864+ isp_obj.config = config;
865+
866+ ispctrl_val &= ISPCTRL_SHIFT_MASK;
867+ ispctrl_val |= config->dataline_shift << ISPCTRL_SHIFT_SHIFT;
868+ ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
869+
870+ ispctrl_val &= ISPCTRL_PAR_SER_CLK_SEL_MASK;
871+
872+ isp_buf_init();
873+
874+ switch (config->ccdc_par_ser) {
875+ case ISP_PARLL:
876+ ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
877+ ispctrl_val |= config->u.par.par_clk_pol
878+ << ISPCTRL_PAR_CLK_POL_SHIFT;
879+ ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_BENDIAN;
880+ ispctrl_val |= config->u.par.par_bridge
881+ << ISPCTRL_PAR_BRIDGE_SHIFT;
882+ break;
883+ case ISP_CSIA:
884+ ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA;
885+ ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_BENDIAN;
886+
887+ isp_csi2_ctx_config_format(0, config->u.csi.format);
888+ isp_csi2_ctx_update(0, false);
889+
890+ if (config->u.csi.crc)
891+ isp_csi2_ctrl_config_ecc_enable(true);
892+
893+ isp_csi2_ctrl_config_vp_out_ctrl(config->u.csi.vpclk);
894+ isp_csi2_ctrl_config_vp_only_enable(true);
895+ isp_csi2_ctrl_config_vp_clk_enable(true);
896+ isp_csi2_ctrl_update(false);
897+
898+ isp_csi2_irq_complexio1_set(1);
899+ isp_csi2_irq_status_set(1);
900+ isp_csi2_irq_set(1);
901+
902+ isp_csi2_enable(1);
903+ mdelay(3);
904+ break;
905+ case ISP_CSIB:
906+ ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB;
907+ r = isp_init_csi(config);
908+ if (r)
909+ return r;
910+ break;
911+ case ISP_NONE:
912+ return 0;
913+ default:
914+ return -EINVAL;
915+ }
916+
917+ ispctrl_val &= ~ISPCTRL_SYNC_DETECT_VSRISE;
918+ ispctrl_val |= config->hsvs_syncdetect;
919+
920+ isp_reg_writel(ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
921+
922+ /* Set sensor specific fields in CCDC and Previewer module.*/
923+ isppreview_set_skip(config->prev_sph, config->prev_slv);
924+ ispccdc_set_wenlog(config->wenlog);
925+
926+ return 0;
927+}
928+EXPORT_SYMBOL(isp_configure_interface);
929+
930+static int isp_buf_process(struct isp_bufs *bufs);
931+
932+/**
933+ * omap34xx_isp_isr - Interrupt Service Routine for Camera ISP module.
934+ * @irq: Not used currently.
935+ * @ispirq_disp: Pointer to the object that is passed while request_irq is
936+ * called. This is the isp_obj.irq object containing info on the
937+ * callback.
938+ *
939+ * Handles the corresponding callback if plugged in.
940+ *
941+ * Returns IRQ_HANDLED when IRQ was correctly handled, or IRQ_NONE when the
942+ * IRQ wasn't handled.
943+ **/
944+static irqreturn_t omap34xx_isp_isr(int irq, void *_isp)
945+{
946+ struct isp *isp = _isp;
947+ struct isp_irq *irqdis = &isp->irq;
948+ struct isp_bufs *bufs = &isp->bufs;
949+ unsigned long flags;
950+ u32 irqstatus = 0;
951+ unsigned long irqflags = 0;
952+ int wait_hs_vs = 0;
953+
954+ irqstatus = isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
955+ isp_reg_writel(irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
956+
957+ spin_lock_irqsave(&bufs->lock, flags);
958+ wait_hs_vs = bufs->wait_hs_vs;
959+ if (irqstatus & HS_VS && bufs->wait_hs_vs)
960+ bufs->wait_hs_vs--;
961+ spin_unlock_irqrestore(&bufs->lock, flags);
962+
963+ spin_lock_irqsave(&isp_obj.lock, irqflags);
964+ /*
965+ * We need to wait for the first HS_VS interrupt from CCDC.
966+ * Otherwise our frame (and everything else) might be bad.
967+ */
968+ if (wait_hs_vs)
969+ goto out_ignore_buff;
970+
971+ if (irqstatus & CCDC_VD0) {
972+ if (RAW_CAPTURE(&isp_obj))
973+ isp_buf_process(bufs);
974+ if (!ispccdc_busy())
975+ ispccdc_config_shadow_registers();
976+ }
977+
978+ if (irqstatus & PREV_DONE) {
979+ if (irqdis->isp_callbk[CBK_PREV_DONE])
980+ irqdis->isp_callbk[CBK_PREV_DONE](
981+ PREV_DONE,
982+ irqdis->isp_callbk_arg1[CBK_PREV_DONE],
983+ irqdis->isp_callbk_arg2[CBK_PREV_DONE]);
984+ else if (!RAW_CAPTURE(&isp_obj) && !ispresizer_busy()) {
985+ if (isp_obj.module.applyCrop) {
986+ ispresizer_applycrop();
987+ if (!ispresizer_busy())
988+ isp_obj.module.applyCrop = 0;
989+ }
990+ if (!isppreview_busy()) {
991+ ispresizer_enable(1);
992+ if (isppreview_busy()) {
993+ /* FIXME: locking! */
994+ ISP_BUF_DONE(bufs)->vb_state =
995+ VIDEOBUF_ERROR;
996+ printk(KERN_ERR "%s: can't stop"
997+ " preview\n", __func__);
998+ }
999+ }
1000+ if (!isppreview_busy())
1001+ isppreview_config_shadow_registers();
1002+ if (!isppreview_busy())
1003+ isph3a_update_wb();
1004+ }
1005+ }
1006+
1007+ if (irqstatus & RESZ_DONE) {
1008+ if (!RAW_CAPTURE(&isp_obj)) {
1009+ if (!ispresizer_busy())
1010+ ispresizer_config_shadow_registers();
1011+ isp_buf_process(bufs);
1012+ }
1013+ }
1014+
1015+ if (irqstatus & H3A_AWB_DONE) {
1016+ if (irqdis->isp_callbk[CBK_H3A_AWB_DONE])
1017+ irqdis->isp_callbk[CBK_H3A_AWB_DONE](
1018+ H3A_AWB_DONE,
1019+ irqdis->isp_callbk_arg1[CBK_H3A_AWB_DONE],
1020+ irqdis->isp_callbk_arg2[CBK_H3A_AWB_DONE]);
1021+ }
1022+
1023+ if (irqstatus & HIST_DONE) {
1024+ if (irqdis->isp_callbk[CBK_HIST_DONE])
1025+ irqdis->isp_callbk[CBK_HIST_DONE](
1026+ HIST_DONE,
1027+ irqdis->isp_callbk_arg1[CBK_HIST_DONE],
1028+ irqdis->isp_callbk_arg2[CBK_HIST_DONE]);
1029+ }
1030+
1031+ if (irqstatus & H3A_AF_DONE) {
1032+ if (irqdis->isp_callbk[CBK_H3A_AF_DONE])
1033+ irqdis->isp_callbk[CBK_H3A_AF_DONE](
1034+ H3A_AF_DONE,
1035+ irqdis->isp_callbk_arg1[CBK_H3A_AF_DONE],
1036+ irqdis->isp_callbk_arg2[CBK_H3A_AF_DONE]);
1037+ }
1038+
1039+
1040+out_ignore_buff:
1041+ if (irqstatus & LSC_PRE_ERR) {
1042+ struct isp_buf *buf = ISP_BUF_DONE(bufs);
1043+ /* Mark buffer faulty. */
1044+ buf->vb_state = VIDEOBUF_ERROR;
1045+ ispccdc_lsc_error_handler();
1046+ printk(KERN_ERR "%s: lsc prefetch error\n", __func__);
1047+ }
1048+
1049+ if (irqstatus & CSIA) {
1050+ struct isp_buf *buf = ISP_BUF_DONE(bufs);
1051+ isp_csi2_isr();
1052+ buf->vb_state = VIDEOBUF_ERROR;
1053+ }
1054+
1055+ if (irqstatus & IRQ0STATUS_CSIB_IRQ) {
1056+ u32 ispcsi1_irqstatus;
1057+
1058+ ispcsi1_irqstatus = isp_reg_readl(OMAP3_ISP_IOMEM_CCP2,
1059+ ISPCSI1_LC01_IRQSTATUS);
1060+ DPRINTK_ISPCTRL("%x\n", ispcsi1_irqstatus);
1061+ }
1062+
1063+ if (irqdis->isp_callbk[CBK_CATCHALL]) {
1064+ irqdis->isp_callbk[CBK_CATCHALL](
1065+ irqstatus,
1066+ irqdis->isp_callbk_arg1[CBK_CATCHALL],
1067+ irqdis->isp_callbk_arg2[CBK_CATCHALL]);
1068+ }
1069+
1070+ spin_unlock_irqrestore(&isp_obj.lock, irqflags);
1071+
1072+#if 1
1073+ {
1074+ static const struct {
1075+ int num;
1076+ char *name;
1077+ } bits[] = {
1078+ { 31, "HS_VS_IRQ" },
1079+ { 30, "SEC_ERR_IRQ" },
1080+ { 29, "OCP_ERR_IRQ" },
1081+ { 28, "MMU_ERR_IRQ" },
1082+ { 27, "res27" },
1083+ { 26, "res26" },
1084+ { 25, "OVF_IRQ" },
1085+ { 24, "RSZ_DONE_IRQ" },
1086+ { 23, "res23" },
1087+ { 22, "res22" },
1088+ { 21, "CBUFF_IRQ" },
1089+ { 20, "PRV_DONE_IRQ" },
1090+ { 19, "CCDC_LSC_PREFETCH_ERROR" },
1091+ { 18, "CCDC_LSC_PREFETCH_COMPLETED" },
1092+ { 17, "CCDC_LSC_DONE" },
1093+ { 16, "HIST_DONE_IRQ" },
1094+ { 15, "res15" },
1095+ { 14, "res14" },
1096+ { 13, "H3A_AWB_DONE_IRQ" },
1097+ { 12, "H3A_AF_DONE_IRQ" },
1098+ { 11, "CCDC_ERR_IRQ" },
1099+ { 10, "CCDC_VD2_IRQ" },
1100+ { 9, "CCDC_VD1_IRQ" },
1101+ { 8, "CCDC_VD0_IRQ" },
1102+ { 7, "res7" },
1103+ { 6, "res6" },
1104+ { 5, "res5" },
1105+ { 4, "CSIB_IRQ" },
1106+ { 3, "CSIB_LCM_IRQ" },
1107+ { 2, "res2" },
1108+ { 1, "res1" },
1109+ { 0, "CSIA_IRQ" },
1110+ };
1111+ int i;
1112+ for (i = 0; i < ARRAY_SIZE(bits); i++) {
1113+ if ((1 << bits[i].num) & irqstatus)
1114+ DPRINTK_ISPCTRL("%s ", bits[i].name);
1115+ }
1116+ DPRINTK_ISPCTRL("\n");
1117+ }
1118+#endif
1119+
1120+ return IRQ_HANDLED;
1121+}
1122+
1123+/* Device name, needed for resource tracking layer */
1124+struct device_driver camera_drv = {
1125+ .name = "camera"
1126+};
1127+
1128+struct device camera_dev = {
1129+ .driver = &camera_drv,
1130+};
1131+
1132+/**
1133+ * isp_tmp_buf_free - To free allocated 10MB memory
1134+ *
1135+ **/
1136+static void isp_tmp_buf_free(void)
1137+{
1138+ if (isp_obj.tmp_buf) {
1139+ ispmmu_vfree(isp_obj.tmp_buf);
1140+ isp_obj.tmp_buf = 0;
1141+ isp_obj.tmp_buf_size = 0;
1142+ }
1143+}
1144+
1145+/**
1146+ * isp_tmp_buf_alloc - To allocate a 10MB memory
1147+ *
1148+ **/
1149+static u32 isp_tmp_buf_alloc(size_t size)
1150+{
1151+ isp_tmp_buf_free();
1152+
1153+ printk(KERN_INFO "%s: allocating %d bytes\n", __func__, size);
1154+
1155+ isp_obj.tmp_buf = ispmmu_vmalloc(size);
1156+ if (IS_ERR((void *)isp_obj.tmp_buf)) {
1157+ printk(KERN_ERR "ispmmu_vmap mapping failed ");
1158+ return -ENOMEM;
1159+ }
1160+ isp_obj.tmp_buf_size = size;
1161+
1162+ isppreview_set_outaddr(isp_obj.tmp_buf);
1163+ ispresizer_set_inaddr(isp_obj.tmp_buf);
1164+
1165+ return 0;
1166+}
1167+
1168+/**
1169+ * isp_start - Starts ISP submodule
1170+ *
1171+ * Start the needed isp components assuming these components
1172+ * are configured correctly.
1173+ **/
1174+void isp_start(void)
1175+{
1176+ if (isp_obj.module.isp_pipeline & OMAP_ISP_PREVIEW
1177+ && is_isppreview_enabled())
1178+ isppreview_enable(1);
1179+
1180+ return;
1181+}
1182+EXPORT_SYMBOL(isp_start);
1183+
1184+#define ISP_STATISTICS_BUSY \
1185+ ()
1186+#define ISP_STOP_TIMEOUT msecs_to_jiffies(1000)
1187+static int __isp_disable_modules(int suspend)
1188+{
1189+ unsigned long timeout = jiffies + ISP_STOP_TIMEOUT;
1190+ int reset = 0;
1191+
1192+ /*
1193+ * We need to stop all the modules after CCDC first or they'll
1194+ * never stop since they may not get a full frame from CCDC.
1195+ */
1196+ if (suspend) {
1197+ isp_af_suspend();
1198+ isph3a_aewb_suspend();
1199+ isp_hist_suspend();
1200+ isppreview_suspend();
1201+ ispresizer_suspend();
1202+ } else {
1203+ isp_af_enable(0);
1204+ isph3a_aewb_enable(0);
1205+ isp_hist_enable(0);
1206+ isppreview_enable(0);
1207+ ispresizer_enable(0);
1208+ }
1209+
1210+ timeout = jiffies + ISP_STOP_TIMEOUT;
1211+ while (isp_af_busy()
1212+ || isph3a_aewb_busy()
1213+ || isp_hist_busy()
1214+ || isppreview_busy()
1215+ || ispresizer_busy()) {
1216+ if (time_after(jiffies, timeout)) {
1217+ printk(KERN_ERR "%s: can't stop non-ccdc modules\n",
1218+ __func__);
1219+ reset = 1;
1220+ break;
1221+ }
1222+ msleep(1);
1223+ }
1224+
1225+ /* Let's stop CCDC now. */
1226+ if (suspend)
1227+ /* This function supends lsc too */
1228+ ispccdc_suspend();
1229+ else {
1230+ ispccdc_enable_lsc(0);
1231+ ispccdc_enable(0);
1232+ }
1233+
1234+ timeout = jiffies + ISP_STOP_TIMEOUT;
1235+ while (ispccdc_busy()) {
1236+ if (time_after(jiffies, timeout)) {
1237+ printk(KERN_ERR "%s: can't stop ccdc\n", __func__);
1238+ reset = 1;
1239+ break;
1240+ }
1241+ msleep(1);
1242+ }
1243+
1244+ return reset;
1245+}
1246+
1247+static int isp_stop_modules(void)
1248+{
1249+ return __isp_disable_modules(0);
1250+}
1251+
1252+static int isp_suspend_modules(void)
1253+{
1254+ return __isp_disable_modules(1);
1255+}
1256+
1257+static void isp_resume_modules(void)
1258+{
1259+ ispresizer_resume();
1260+ isppreview_resume();
1261+ isp_hist_resume();
1262+ isph3a_aewb_resume();
1263+ isp_af_resume();
1264+ ispccdc_resume();
1265+}
1266+
1267+static void isp_reset(void)
1268+{
1269+ unsigned long timeout = 0;
1270+
1271+ isp_reg_writel(isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG)
1272+ | ISP_SYSCONFIG_SOFTRESET,
1273+ OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
1274+ while (!(isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_SYSSTATUS) & 0x1)) {
1275+ if (timeout++ > 10000) {
1276+ printk(KERN_ALERT "%s: cannot reset ISP\n", __func__);
1277+ break;
1278+ }
1279+ udelay(1);
1280+ }
1281+}
1282+
1283+/**
1284+ * isp_stop - Stops isp submodules
1285+ **/
1286+void isp_stop()
1287+{
1288+ int reset;
1289+
1290+ isp_disable_interrupts();
1291+ reset = isp_stop_modules();
1292+ isp_buf_init();
1293+ if (!reset)
1294+ return;
1295+
1296+ isp_save_ctx();
1297+ isp_reset();
1298+ isp_restore_ctx();
1299+}
1300+EXPORT_SYMBOL(isp_stop);
1301+
1302+static void isp_set_buf(struct isp_buf *buf)
1303+{
1304+ if (isp_obj.module.isp_pipeline & OMAP_ISP_RESIZER
1305+ && is_ispresizer_enabled())
1306+ ispresizer_set_outaddr(buf->isp_addr);
1307+ else if (isp_obj.module.isp_pipeline & OMAP_ISP_CCDC)
1308+ ispccdc_set_outaddr(buf->isp_addr);
1309+
1310+}
1311+
1312+/**
1313+ * isp_calc_pipeline - Sets pipeline depending of input and output pixel format
1314+ * @pix_input: Pointer to V4L2 pixel format structure for input image.
1315+ * @pix_output: Pointer to V4L2 pixel format structure for output image.
1316+ **/
1317+static u32 isp_calc_pipeline(struct v4l2_pix_format *pix_input,
1318+ struct v4l2_pix_format *pix_output)
1319+{
1320+ isp_release_resources();
1321+ if ((pix_input->pixelformat == V4L2_PIX_FMT_SGRBG10
1322+ || pix_input->pixelformat == V4L2_PIX_FMT_SGRBG10DPCM8)
1323+ && pix_output->pixelformat != V4L2_PIX_FMT_SGRBG10) {
1324+ isp_obj.module.isp_pipeline =
1325+ OMAP_ISP_CCDC | OMAP_ISP_PREVIEW | OMAP_ISP_RESIZER;
1326+ ispccdc_request();
1327+ isppreview_request();
1328+ ispresizer_request();
1329+ ispccdc_config_datapath(CCDC_RAW, CCDC_OTHERS_VP);
1330+ isppreview_config_datapath(PRV_RAW_CCDC, PREVIEW_MEM);
1331+ ispresizer_config_datapath(RSZ_MEM_YUV);
1332+ } else {
1333+ isp_obj.module.isp_pipeline = OMAP_ISP_CCDC;
1334+ ispccdc_request();
1335+ if (pix_input->pixelformat == V4L2_PIX_FMT_SGRBG10
1336+ || pix_input->pixelformat == V4L2_PIX_FMT_SGRBG10DPCM8)
1337+ ispccdc_config_datapath(CCDC_RAW, CCDC_OTHERS_VP_MEM);
1338+ else
1339+ ispccdc_config_datapath(CCDC_YUV_SYNC,
1340+ CCDC_OTHERS_MEM);
1341+ }
1342+ return 0;
1343+}
1344+
1345+/**
1346+ * isp_config_pipeline - Configures the image size and ycpos for ISP submodules
1347+ * @pix_input: Pointer to V4L2 pixel format structure for input image.
1348+ * @pix_output: Pointer to V4L2 pixel format structure for output image.
1349+ *
1350+ * The configuration of ycpos depends on the output pixel format for both the
1351+ * Preview and Resizer submodules.
1352+ **/
1353+static void isp_config_pipeline(struct v4l2_pix_format *pix_input,
1354+ struct v4l2_pix_format *pix_output)
1355+{
1356+ ispccdc_config_size(isp_obj.module.ccdc_input_width,
1357+ isp_obj.module.ccdc_input_height,
1358+ isp_obj.module.ccdc_output_width,
1359+ isp_obj.module.ccdc_output_height);
1360+
1361+ if (isp_obj.module.isp_pipeline & OMAP_ISP_PREVIEW) {
1362+ isppreview_config_size(isp_obj.module.preview_input_width,
1363+ isp_obj.module.preview_input_height,
1364+ isp_obj.module.preview_output_width,
1365+ isp_obj.module.preview_output_height);
1366+ }
1367+
1368+ if (isp_obj.module.isp_pipeline & OMAP_ISP_RESIZER) {
1369+ ispresizer_config_size(isp_obj.module.resizer_input_width,
1370+ isp_obj.module.resizer_input_height,
1371+ isp_obj.module.resizer_output_width,
1372+ isp_obj.module.resizer_output_height);
1373+ }
1374+
1375+ if (pix_output->pixelformat == V4L2_PIX_FMT_UYVY) {
1376+ isppreview_config_ycpos(YCPOS_YCrYCb);
1377+ if (is_ispresizer_enabled())
1378+ ispresizer_config_ycpos(0);
1379+ } else {
1380+ isppreview_config_ycpos(YCPOS_CrYCbY);
1381+ if (is_ispresizer_enabled())
1382+ ispresizer_config_ycpos(1);
1383+ }
1384+
1385+ return;
1386+}
1387+
1388+static void isp_buf_init(void)
1389+{
1390+ struct isp_bufs *bufs = &isp_obj.bufs;
1391+ int sg;
1392+
1393+ bufs->queue = 0;
1394+ bufs->done = 0;
1395+ bufs->wait_hs_vs = isp_obj.config->wait_hs_vs;
1396+ for (sg = 0; sg < NUM_BUFS; sg++) {
1397+ bufs->buf[sg].complete = NULL;
1398+ bufs->buf[sg].vb = NULL;
1399+ bufs->buf[sg].priv = NULL;
1400+ }
1401+}
1402+
1403+/**
1404+ * isp_vbq_sync - Walks the pages table and flushes the cache for
1405+ * each page.
1406+ **/
1407+static int isp_vbq_sync(struct videobuf_buffer *vb, int when)
1408+{
1409+ flush_cache_all();
1410+
1411+ return 0;
1412+}
1413+
1414+static int isp_buf_process(struct isp_bufs *bufs)
1415+{
1416+ struct isp_buf *buf = NULL;
1417+ unsigned long flags;
1418+ int last;
1419+
1420+ spin_lock_irqsave(&bufs->lock, flags);
1421+
1422+ if (ISP_BUFS_IS_EMPTY(bufs))
1423+ goto out;
1424+
1425+ if (RAW_CAPTURE(&isp_obj) && ispccdc_sbl_wait_idle(1000)) {
1426+ printk(KERN_ERR "ccdc %d won't become idle!\n",
1427+ RAW_CAPTURE(&isp_obj));
1428+ goto out;
1429+ }
1430+
1431+ /* We had at least one buffer in queue. */
1432+ buf = ISP_BUF_DONE(bufs);
1433+ last = ISP_BUFS_IS_LAST(bufs);
1434+
1435+ if (!last) {
1436+ /* Set new buffer address. */
1437+ isp_set_buf(ISP_BUF_NEXT_DONE(bufs));
1438+ } else {
1439+ /* Tell ISP not to write any of our buffers. */
1440+ isp_disable_interrupts();
1441+ if (RAW_CAPTURE(&isp_obj))
1442+ ispccdc_enable(0);
1443+ else
1444+ ispresizer_enable(0);
1445+ /*
1446+ * We must wait for the HS_VS since before that the
1447+ * CCDC may trigger interrupts even if it's not
1448+ * receiving a frame.
1449+ */
1450+ bufs->wait_hs_vs = isp_obj.config->wait_hs_vs;
1451+ }
1452+ if ((RAW_CAPTURE(&isp_obj) && ispccdc_busy())
1453+ || (!RAW_CAPTURE(&isp_obj) && ispresizer_busy())) {
1454+ /*
1455+ * Next buffer available: for the transfer to succeed, the
1456+ * CCDC (RAW capture) or resizer (YUV capture) must be idle
1457+ * for the duration of transfer setup. Bad things happen
1458+ * otherwise!
1459+ *
1460+ * Next buffer not available: if we fail to stop the
1461+ * ISP the buffer is probably going to be bad.
1462+ */
1463+ /* Mark this buffer faulty. */
1464+ buf->vb_state = VIDEOBUF_ERROR;
1465+ /* Mark next faulty, too, in case we have one. */
1466+ if (!last) {
1467+ ISP_BUF_NEXT_DONE(bufs)->vb_state =
1468+ VIDEOBUF_ERROR;
1469+ printk(KERN_ALERT "OUCH!!!\n");
1470+ } else {
1471+ printk(KERN_ALERT "Ouch!\n");
1472+ }
1473+ }
1474+
1475+ /* Mark the current buffer as done. */
1476+ ISP_BUF_MARK_DONE(bufs);
1477+
1478+ DPRINTK_ISPCTRL(KERN_ALERT "%s: finish %d mmu %p\n", __func__,
1479+ (bufs->done - 1 + NUM_BUFS) % NUM_BUFS,
1480+ (bufs->buf+((bufs->done - 1 + NUM_BUFS)
1481+ % NUM_BUFS))->isp_addr);
1482+
1483+out:
1484+ spin_unlock_irqrestore(&bufs->lock, flags);
1485+
1486+ if (buf != NULL) {
1487+ /*
1488+ * We want to dequeue a buffer from the video buffer
1489+ * queue. Let's do it!
1490+ */
1491+ isp_vbq_sync(buf->vb, DMA_FROM_DEVICE);
1492+ buf->vb->state = buf->vb_state;
1493+ buf->complete(buf->vb, buf->priv);
1494+ }
1495+
1496+ return 0;
1497+}
1498+
1499+int isp_buf_queue(struct videobuf_buffer *vb,
1500+ void (*complete)(struct videobuf_buffer *vb, void *priv),
1501+ void *priv)
1502+{
1503+ unsigned long flags;
1504+ struct isp_buf *buf;
1505+ struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
1506+ const struct scatterlist *sglist = dma->sglist;
1507+ struct isp_bufs *bufs = &isp_obj.bufs;
1508+ int sglen = dma->sglen;
1509+
1510+ BUG_ON(sglen < 0 || !sglist);
1511+
1512+ isp_vbq_sync(vb, DMA_TO_DEVICE);
1513+
1514+ spin_lock_irqsave(&bufs->lock, flags);
1515+
1516+ BUG_ON(ISP_BUFS_IS_FULL(bufs));
1517+
1518+ buf = ISP_BUF_QUEUE(bufs);
1519+
1520+ buf->isp_addr = bufs->isp_addr_capture[vb->i];
1521+ buf->complete = complete;
1522+ buf->vb = vb;
1523+ buf->priv = priv;
1524+ buf->vb_state = VIDEOBUF_DONE;
1525+
1526+ if (ISP_BUFS_IS_EMPTY(bufs)) {
1527+ isp_enable_interrupts(RAW_CAPTURE(&isp_obj));
1528+ isp_set_buf(buf);
1529+ ispccdc_enable(1);
1530+ isp_start();
1531+ }
1532+
1533+ ISP_BUF_MARK_QUEUED(bufs);
1534+
1535+ spin_unlock_irqrestore(&bufs->lock, flags);
1536+
1537+ DPRINTK_ISPCTRL(KERN_ALERT "%s: queue %d vb %d, mmu %p\n", __func__,
1538+ (bufs->queue - 1 + NUM_BUFS) % NUM_BUFS, vb->i,
1539+ buf->isp_addr);
1540+
1541+ return 0;
1542+}
1543+EXPORT_SYMBOL(isp_buf_queue);
1544+
1545+int isp_vbq_setup(struct videobuf_queue *vbq, unsigned int *cnt,
1546+ unsigned int *size)
1547+{
1548+ int rval = 0;
1549+ size_t tmp_size = PAGE_ALIGN(isp_obj.module.preview_output_width
1550+ * isp_obj.module.preview_output_height
1551+ * ISP_BYTES_PER_PIXEL);
1552+
1553+ if (isp_obj.module.isp_pipeline & OMAP_ISP_PREVIEW
1554+ && isp_obj.tmp_buf_size < tmp_size)
1555+ rval = isp_tmp_buf_alloc(tmp_size);
1556+
1557+ return rval;
1558+}
1559+EXPORT_SYMBOL(isp_vbq_setup);
1560+
1561+/**
1562+ * isp_vbq_prepare - Videobuffer queue prepare.
1563+ * @vbq: Pointer to videobuf_queue structure.
1564+ * @vb: Pointer to videobuf_buffer structure.
1565+ * @field: Requested Field order for the videobuffer.
1566+ *
1567+ * Returns 0 if successful, or -EIO if the ispmmu was unable to map a
1568+ * scatter-gather linked list data space.
1569+ **/
1570+int isp_vbq_prepare(struct videobuf_queue *vbq, struct videobuf_buffer *vb,
1571+ enum v4l2_field field)
1572+{
1573+ unsigned int isp_addr;
1574+ struct videobuf_dmabuf *vdma;
1575+ struct isp_bufs *bufs = &isp_obj.bufs;
1576+
1577+ int err = 0;
1578+
1579+ vdma = videobuf_to_dma(vb);
1580+
1581+ isp_addr = ispmmu_vmap(vdma->sglist, vdma->sglen);
1582+
1583+ if (IS_ERR_VALUE(isp_addr))
1584+ err = -EIO;
1585+ else
1586+ bufs->isp_addr_capture[vb->i] = isp_addr;
1587+
1588+ return err;
1589+}
1590+EXPORT_SYMBOL(isp_vbq_prepare);
1591+
1592+/**
1593+ * isp_vbq_release - Videobuffer queue release.
1594+ * @vbq: Pointer to videobuf_queue structure.
1595+ * @vb: Pointer to videobuf_buffer structure.
1596+ **/
1597+void isp_vbq_release(struct videobuf_queue *vbq, struct videobuf_buffer *vb)
1598+{
1599+ struct isp_bufs *bufs = &isp_obj.bufs;
1600+
1601+ ispmmu_vunmap(bufs->isp_addr_capture[vb->i]);
1602+ bufs->isp_addr_capture[vb->i] = (dma_addr_t)NULL;
1603+ return;
1604+}
1605+EXPORT_SYMBOL(isp_vbq_release);
1606+
1607+/**
1608+ * isp_queryctrl - Query V4L2 control from existing controls in ISP.
1609+ * @a: Pointer to v4l2_queryctrl structure. It only needs the id field filled.
1610+ *
1611+ * Returns 0 if successful, or -EINVAL if not found in ISP.
1612+ **/
1613+int isp_queryctrl(struct v4l2_queryctrl *a)
1614+{
1615+ int i;
1616+
1617+ if (a->id & V4L2_CTRL_FLAG_NEXT_CTRL) {
1618+ a->id &= ~V4L2_CTRL_FLAG_NEXT_CTRL;
1619+ i = find_next_vctrl(a->id);
1620+ } else {
1621+ i = find_vctrl(a->id);
1622+ }
1623+
1624+ if (i < 0)
1625+ return -EINVAL;
1626+
1627+ *a = video_control[i].qc;
1628+ return 0;
1629+}
1630+EXPORT_SYMBOL(isp_queryctrl);
1631+
1632+/**
1633+ * isp_queryctrl - Query V4L2 control from existing controls in ISP.
1634+ * @a: Pointer to v4l2_queryctrl structure. It only needs the id field filled.
1635+ *
1636+ * Returns 0 if successful, or -EINVAL if not found in ISP.
1637+ **/
1638+int isp_querymenu(struct v4l2_querymenu *a)
1639+{
1640+ int i;
1641+
1642+ i = find_vmenu(a->id, a->index);
1643+
1644+ if (i < 0)
1645+ return -EINVAL;
1646+
1647+ *a = video_menu[i];
1648+ return 0;
1649+}
1650+EXPORT_SYMBOL(isp_querymenu);
1651+
1652+/**
1653+ * isp_g_ctrl - Gets value of the desired V4L2 control.
1654+ * @a: V4L2 control to read actual value from.
1655+ *
1656+ * Return 0 if successful, or -EINVAL if chosen control is not found.
1657+ **/
1658+int isp_g_ctrl(struct v4l2_control *a)
1659+{
1660+ u8 current_value;
1661+ int rval = 0;
1662+
1663+ if (!isp_obj.ref_count)
1664+ return -EINVAL;
1665+
1666+ switch (a->id) {
1667+ case V4L2_CID_BRIGHTNESS:
1668+ isppreview_query_brightness(&current_value);
1669+ a->value = current_value / ISPPRV_BRIGHT_UNITS;
1670+ break;
1671+ case V4L2_CID_CONTRAST:
1672+ isppreview_query_contrast(&current_value);
1673+ a->value = current_value / ISPPRV_CONTRAST_UNITS;
1674+ break;
1675+ case V4L2_CID_COLORFX:
1676+ isppreview_get_color(&current_value);
1677+ a->value = current_value;
1678+ break;
1679+ default:
1680+ rval = -EINVAL;
1681+ break;
1682+ }
1683+
1684+ return rval;
1685+}
1686+EXPORT_SYMBOL(isp_g_ctrl);
1687+
1688+/**
1689+ * isp_s_ctrl - Sets value of the desired V4L2 control.
1690+ * @a: V4L2 control to read actual value from.
1691+ *
1692+ * Return 0 if successful, -EINVAL if chosen control is not found or value
1693+ * is out of bounds, -EFAULT if copy_from_user or copy_to_user operation fails
1694+ * from camera abstraction layer related controls or the transfered user space
1695+ * pointer via the value field is not set properly.
1696+ **/
1697+int isp_s_ctrl(struct v4l2_control *a)
1698+{
1699+ int rval = 0;
1700+ u8 new_value = a->value;
1701+
1702+ if (!isp_obj.ref_count)
1703+ return -EINVAL;
1704+
1705+ switch (a->id) {
1706+ case V4L2_CID_BRIGHTNESS:
1707+ if (new_value > ISPPRV_BRIGHT_HIGH)
1708+ rval = -EINVAL;
1709+ else
1710+ isppreview_update_brightness(&new_value);
1711+ break;
1712+ case V4L2_CID_CONTRAST:
1713+ if (new_value > ISPPRV_CONTRAST_HIGH)
1714+ rval = -EINVAL;
1715+ else
1716+ isppreview_update_contrast(&new_value);
1717+ break;
1718+ case V4L2_CID_COLORFX:
1719+ if (new_value > V4L2_COLORFX_SEPIA)
1720+ rval = -EINVAL;
1721+ else
1722+ isppreview_set_color(&new_value);
1723+ break;
1724+ default:
1725+ rval = -EINVAL;
1726+ break;
1727+ }
1728+
1729+ return rval;
1730+}
1731+EXPORT_SYMBOL(isp_s_ctrl);
1732+
1733+/**
1734+ * isp_handle_private - Handle all private ioctls for isp module.
1735+ * @cmd: ioctl cmd value
1736+ * @arg: ioctl arg value
1737+ *
1738+ * Return 0 if successful, -EINVAL if chosen cmd value is not handled or value
1739+ * is out of bounds, -EFAULT if ioctl arg value is not valid.
1740+ * Function simply routes the input ioctl cmd id to the appropriate handler in
1741+ * the isp module.
1742+ **/
1743+int isp_handle_private(int cmd, void *arg)
1744+{
1745+ int rval = 0;
1746+
1747+ if (!isp_obj.ref_count)
1748+ return -EINVAL;
1749+
1750+ switch (cmd) {
1751+ case VIDIOC_PRIVATE_ISP_CCDC_CFG:
1752+ rval = omap34xx_isp_ccdc_config(arg);
1753+ break;
1754+ case VIDIOC_PRIVATE_ISP_PRV_CFG:
1755+ rval = omap34xx_isp_preview_config(arg);
1756+ break;
1757+ case VIDIOC_PRIVATE_ISP_AEWB_CFG: {
1758+ struct isph3a_aewb_config *params;
1759+ params = (struct isph3a_aewb_config *)arg;
1760+ rval = isph3a_aewb_configure(params);
1761+ }
1762+ break;
1763+ case VIDIOC_PRIVATE_ISP_AEWB_REQ: {
1764+ struct isph3a_aewb_data *data;
1765+ data = (struct isph3a_aewb_data *)arg;
1766+ rval = isph3a_aewb_request_statistics(data);
1767+ }
1768+ break;
1769+ case VIDIOC_PRIVATE_ISP_HIST_CFG: {
1770+ struct isp_hist_config *params;
1771+ params = (struct isp_hist_config *)arg;
1772+ rval = isp_hist_configure(params);
1773+ }
1774+ break;
1775+ case VIDIOC_PRIVATE_ISP_HIST_REQ: {
1776+ struct isp_hist_data *data;
1777+ data = (struct isp_hist_data *)arg;
1778+ rval = isp_hist_request_statistics(data);
1779+ }
1780+ break;
1781+ case VIDIOC_PRIVATE_ISP_AF_CFG: {
1782+ struct af_configuration *params;
1783+ params = (struct af_configuration *)arg;
1784+ rval = isp_af_configure(params);
1785+ }
1786+ break;
1787+ case VIDIOC_PRIVATE_ISP_AF_REQ: {
1788+ struct isp_af_data *data;
1789+ data = (struct isp_af_data *)arg;
1790+ rval = isp_af_request_statistics(data);
1791+ }
1792+ break;
1793+ default:
1794+ rval = -EINVAL;
1795+ break;
1796+ }
1797+ return rval;
1798+}
1799+EXPORT_SYMBOL(isp_handle_private);
1800+
1801+/**
1802+ * isp_enum_fmt_cap - Gets more information of chosen format index and type
1803+ * @f: Pointer to structure containing index and type of format to read from.
1804+ *
1805+ * Returns 0 if successful, or -EINVAL if format index or format type is
1806+ * invalid.
1807+ **/
1808+int isp_enum_fmt_cap(struct v4l2_fmtdesc *f)
1809+{
1810+ int index = f->index;
1811+ enum v4l2_buf_type type = f->type;
1812+ int rval = -EINVAL;
1813+
1814+ if (index >= NUM_ISP_CAPTURE_FORMATS)
1815+ goto err;
1816+
1817+ memset(f, 0, sizeof(*f));
1818+ f->index = index;
1819+ f->type = type;
1820+
1821+ switch (f->type) {
1822+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
1823+ rval = 0;
1824+ break;
1825+ default:
1826+ goto err;
1827+ }
1828+
1829+ f->flags = isp_formats[index].flags;
1830+ strncpy(f->description, isp_formats[index].description,
1831+ sizeof(f->description));
1832+ f->pixelformat = isp_formats[index].pixelformat;
1833+err:
1834+ return rval;
1835+}
1836+EXPORT_SYMBOL(isp_enum_fmt_cap);
1837+
1838+/**
1839+ * isp_g_fmt_cap - Gets current output image format.
1840+ * @f: Pointer to V4L2 format structure to be filled with current output format
1841+ **/
1842+void isp_g_fmt_cap(struct v4l2_pix_format *pix)
1843+{
1844+ *pix = isp_obj.module.pix;
1845+ return;
1846+}
1847+EXPORT_SYMBOL(isp_g_fmt_cap);
1848+
1849+/**
1850+ * isp_s_fmt_cap - Sets I/O formats and crop and configures pipeline in ISP
1851+ * @f: Pointer to V4L2 format structure to be filled with current output format
1852+ *
1853+ * Returns 0 if successful, or return value of either isp_try_size or
1854+ * isp_try_fmt if there is an error.
1855+ **/
1856+int isp_s_fmt_cap(struct v4l2_pix_format *pix_input,
1857+ struct v4l2_pix_format *pix_output)
1858+{
1859+ int crop_scaling_w = 0, crop_scaling_h = 0;
1860+ int rval = 0;
1861+
1862+ if (!isp_obj.ref_count)
1863+ return -EINVAL;
1864+
1865+ rval = isp_calc_pipeline(pix_input, pix_output);
1866+ if (rval)
1867+ goto out;
1868+
1869+ rval = isp_try_size(pix_input, pix_output);
1870+ if (rval)
1871+ goto out;
1872+
1873+ rval = isp_try_fmt(pix_input, pix_output);
1874+ if (rval)
1875+ goto out;
1876+
1877+ if (ispcroprect.width != pix_output->width) {
1878+ crop_scaling_w = 1;
1879+ ispcroprect.left = 0;
1880+ ispcroprect.width = pix_output->width;
1881+ }
1882+
1883+ if (ispcroprect.height != pix_output->height) {
1884+ crop_scaling_h = 1;
1885+ ispcroprect.top = 0;
1886+ ispcroprect.height = pix_output->height;
1887+ }
1888+
1889+ isp_config_pipeline(pix_input, pix_output);
1890+
1891+ if (isp_obj.module.isp_pipeline & OMAP_ISP_RESIZER
1892+ && (crop_scaling_h || crop_scaling_w))
1893+ isp_config_crop(pix_output);
1894+
1895+out:
1896+ return rval;
1897+}
1898+EXPORT_SYMBOL(isp_s_fmt_cap);
1899+
1900+/**
1901+ * isp_config_crop - Configures crop parameters in isp resizer.
1902+ * @croppix: Pointer to V4L2 pixel format structure containing crop parameters
1903+ **/
1904+void isp_config_crop(struct v4l2_pix_format *croppix)
1905+{
1906+ u8 crop_scaling_w;
1907+ u8 crop_scaling_h;
1908+ unsigned long org_left, num_pix, new_top;
1909+
1910+ struct v4l2_pix_format *pix = croppix;
1911+
1912+ crop_scaling_w = (isp_obj.module.preview_output_width * 10) /
1913+ pix->width;
1914+ crop_scaling_h = (isp_obj.module.preview_output_height * 10) /
1915+ pix->height;
1916+
1917+ cur_rect.left = (ispcroprect.left * crop_scaling_w) / 10;
1918+ cur_rect.top = (ispcroprect.top * crop_scaling_h) / 10;
1919+ cur_rect.width = (ispcroprect.width * crop_scaling_w) / 10;
1920+ cur_rect.height = (ispcroprect.height * crop_scaling_h) / 10;
1921+
1922+ org_left = cur_rect.left;
1923+ while (((int)cur_rect.left & 0xFFFFFFF0) != (int)cur_rect.left)
1924+ (int)cur_rect.left--;
1925+
1926+ num_pix = org_left - cur_rect.left;
1927+ new_top = (int)(num_pix * 3) / 4;
1928+ cur_rect.top = cur_rect.top - new_top;
1929+ cur_rect.height = (2 * new_top) + cur_rect.height;
1930+
1931+ cur_rect.width = cur_rect.width + (2 * num_pix);
1932+ while (((int)cur_rect.width & 0xFFFFFFF0) != (int)cur_rect.width)
1933+ (int)cur_rect.width--;
1934+
1935+ isp_obj.tmp_buf_offset =
1936+ cur_rect.left * 2 +
1937+ isp_obj.module.preview_output_width * 2 * cur_rect.top;
1938+
1939+ ispresizer_trycrop(cur_rect.left, cur_rect.top, cur_rect.width,
1940+ cur_rect.height,
1941+ isp_obj.module.resizer_output_width,
1942+ isp_obj.module.resizer_output_height);
1943+
1944+ return;
1945+}
1946+EXPORT_SYMBOL(isp_config_crop);
1947+
1948+/**
1949+ * isp_g_crop - Gets crop rectangle size and position.
1950+ * @a: Pointer to V4L2 crop structure to be filled.
1951+ *
1952+ * Always returns 0.
1953+ **/
1954+int isp_g_crop(struct v4l2_crop *a)
1955+{
1956+ struct v4l2_crop *crop = a;
1957+
1958+ crop->c = ispcroprect;
1959+
1960+ return 0;
1961+}
1962+EXPORT_SYMBOL(isp_g_crop);
1963+
1964+/**
1965+ * isp_s_crop - Sets crop rectangle size and position and queues crop operation
1966+ * @a: Pointer to V4L2 crop structure with desired parameters.
1967+ * @pix: Pointer to V4L2 pixel format structure with desired parameters.
1968+ *
1969+ * Returns 0 if successful, or -EINVAL if crop parameters are out of bounds.
1970+ **/
1971+int isp_s_crop(struct v4l2_crop *a, struct v4l2_pix_format *pix)
1972+{
1973+ struct v4l2_crop *crop = a;
1974+ int rval = 0;
1975+
1976+ if (!isp_obj.ref_count)
1977+ return -EINVAL;
1978+
1979+ if (crop->c.left < 0)
1980+ crop->c.left = 0;
1981+ if (crop->c.width < 0)
1982+ crop->c.width = 0;
1983+ if (crop->c.top < 0)
1984+ crop->c.top = 0;
1985+ if (crop->c.height < 0)
1986+ crop->c.height = 0;
1987+
1988+ if (crop->c.left >= pix->width)
1989+ crop->c.left = pix->width - 1;
1990+ if (crop->c.top >= pix->height)
1991+ crop->c.top = pix->height - 1;
1992+
1993+ if (crop->c.left + crop->c.width > pix->width)
1994+ crop->c.width = pix->width - crop->c.left;
1995+ if (crop->c.top + crop->c.height > pix->height)
1996+ crop->c.height = pix->height - crop->c.top;
1997+
1998+ ispcroprect.left = crop->c.left;
1999+ ispcroprect.top = crop->c.top;
2000+ ispcroprect.width = crop->c.width;
2001+ ispcroprect.height = crop->c.height;
2002+
2003+ isp_config_crop(pix);
2004+
2005+ isp_obj.module.applyCrop = 1;
2006+
2007+ return rval;
2008+}
2009+EXPORT_SYMBOL(isp_s_crop);
2010+
2011+/**
2012+ * isp_try_fmt_cap - Tries desired input/output image formats
2013+ * @pix_input: Pointer to V4L2 pixel format structure for input image.
2014+ * @pix_output: Pointer to V4L2 pixel format structure for output image.
2015+ *
2016+ * Returns 0 if successful, or return value of either isp_try_size or
2017+ * isp_try_fmt if there is an error.
2018+ **/
2019+int isp_try_fmt_cap(struct v4l2_pix_format *pix_input,
2020+ struct v4l2_pix_format *pix_output)
2021+{
2022+ int rval = 0;
2023+
2024+ rval = isp_calc_pipeline(pix_input, pix_output);
2025+ if (rval)
2026+ goto out;
2027+
2028+ rval = isp_try_size(pix_input, pix_output);
2029+ if (rval)
2030+ goto out;
2031+
2032+ rval = isp_try_fmt(pix_input, pix_output);
2033+ if (rval)
2034+ goto out;
2035+
2036+out:
2037+ return rval;
2038+}
2039+EXPORT_SYMBOL(isp_try_fmt_cap);
2040+
2041+/**
2042+ * isp_try_size - Tries size configuration for I/O images of each ISP submodule
2043+ * @pix_input: Pointer to V4L2 pixel format structure for input image.
2044+ * @pix_output: Pointer to V4L2 pixel format structure for output image.
2045+ *
2046+ * Returns 0 if successful, or return value of ispccdc_try_size,
2047+ * isppreview_try_size, or ispresizer_try_size (depending on the pipeline
2048+ * configuration) if there is an error.
2049+ **/
2050+static int isp_try_size(struct v4l2_pix_format *pix_input,
2051+ struct v4l2_pix_format *pix_output)
2052+{
2053+ int rval = 0;
2054+
2055+ if (pix_output->width <= ISPRSZ_MIN_OUTPUT
2056+ || pix_output->height <= ISPRSZ_MIN_OUTPUT)
2057+ return -EINVAL;
2058+
2059+ if (pix_output->width >= ISPRSZ_MAX_OUTPUT
2060+ || pix_output->height > ISPRSZ_MAX_OUTPUT)
2061+ return -EINVAL;
2062+
2063+ isp_obj.module.ccdc_input_width = pix_input->width;
2064+ isp_obj.module.ccdc_input_height = pix_input->height;
2065+ isp_obj.module.resizer_output_width = pix_output->width;
2066+ isp_obj.module.resizer_output_height = pix_output->height;
2067+
2068+ if (isp_obj.module.isp_pipeline & OMAP_ISP_CCDC) {
2069+ rval = ispccdc_try_size(isp_obj.module.ccdc_input_width,
2070+ isp_obj.module.ccdc_input_height,
2071+ &isp_obj.module.ccdc_output_width,
2072+ &isp_obj.module.ccdc_output_height);
2073+ if (rval) {
2074+ printk(KERN_ERR "ISP_ERR: The dimensions %dx%d are not"
2075+ " supported\n", pix_input->width,
2076+ pix_input->height);
2077+ return rval;
2078+ }
2079+ pix_output->width = isp_obj.module.ccdc_output_width;
2080+ pix_output->height = isp_obj.module.ccdc_output_height;
2081+ }
2082+
2083+ if (isp_obj.module.isp_pipeline & OMAP_ISP_PREVIEW) {
2084+ isp_obj.module.preview_input_width =
2085+ isp_obj.module.ccdc_output_width;
2086+ isp_obj.module.preview_input_height =
2087+ isp_obj.module.ccdc_output_height;
2088+ rval = isppreview_try_size(
2089+ isp_obj.module.preview_input_width,
2090+ isp_obj.module.preview_input_height,
2091+ &isp_obj.module.preview_output_width,
2092+ &isp_obj.module.preview_output_height);
2093+ if (rval) {
2094+ printk(KERN_ERR "ISP_ERR: The dimensions %dx%d are not"
2095+ " supported\n", pix_input->width,
2096+ pix_input->height);
2097+ return rval;
2098+ }
2099+ pix_output->width = isp_obj.module.preview_output_width;
2100+ pix_output->height = isp_obj.module.preview_output_height;
2101+ }
2102+
2103+ if (isp_obj.module.isp_pipeline & OMAP_ISP_RESIZER) {
2104+ isp_obj.module.resizer_input_width =
2105+ isp_obj.module.preview_output_width;
2106+ isp_obj.module.resizer_input_height =
2107+ isp_obj.module.preview_output_height;
2108+ rval = ispresizer_try_size(
2109+ &isp_obj.module.resizer_input_width,
2110+ &isp_obj.module.resizer_input_height,
2111+ &isp_obj.module.resizer_output_width,
2112+ &isp_obj.module.resizer_output_height);
2113+ if (rval) {
2114+ printk(KERN_ERR "ISP_ERR: The dimensions %dx%d are not"
2115+ " supported\n", pix_input->width,
2116+ pix_input->height);
2117+ return rval;
2118+ }
2119+ pix_output->width = isp_obj.module.resizer_output_width;
2120+ pix_output->height = isp_obj.module.resizer_output_height;
2121+ }
2122+
2123+ return rval;
2124+}
2125+
2126+/**
2127+ * isp_try_fmt - Validates input/output format parameters.
2128+ * @pix_input: Pointer to V4L2 pixel format structure for input image.
2129+ * @pix_output: Pointer to V4L2 pixel format structure for output image.
2130+ *
2131+ * Always returns 0.
2132+ **/
2133+int isp_try_fmt(struct v4l2_pix_format *pix_input,
2134+ struct v4l2_pix_format *pix_output)
2135+{
2136+ int ifmt;
2137+
2138+ for (ifmt = 0; ifmt < NUM_ISP_CAPTURE_FORMATS; ifmt++) {
2139+ if (pix_output->pixelformat == isp_formats[ifmt].pixelformat)
2140+ break;
2141+ }
2142+ if (ifmt == NUM_ISP_CAPTURE_FORMATS)
2143+ ifmt = 1;
2144+ pix_output->pixelformat = isp_formats[ifmt].pixelformat;
2145+ pix_output->field = V4L2_FIELD_NONE;
2146+ pix_output->bytesperline = pix_output->width * ISP_BYTES_PER_PIXEL;
2147+ pix_output->sizeimage =
2148+ PAGE_ALIGN(pix_output->bytesperline * pix_output->height);
2149+ pix_output->priv = 0;
2150+ switch (pix_output->pixelformat) {
2151+ case V4L2_PIX_FMT_YUYV:
2152+ case V4L2_PIX_FMT_UYVY:
2153+ pix_output->colorspace = V4L2_COLORSPACE_JPEG;
2154+ break;
2155+ default:
2156+ pix_output->colorspace = V4L2_COLORSPACE_SRGB;
2157+ }
2158+
2159+ isp_obj.module.pix.pixelformat = pix_output->pixelformat;
2160+ isp_obj.module.pix.width = pix_output->width;
2161+ isp_obj.module.pix.height = pix_output->height;
2162+ isp_obj.module.pix.field = pix_output->field;
2163+ isp_obj.module.pix.bytesperline = pix_output->bytesperline;
2164+ isp_obj.module.pix.sizeimage = pix_output->sizeimage;
2165+ isp_obj.module.pix.priv = pix_output->priv;
2166+ isp_obj.module.pix.colorspace = pix_output->colorspace;
2167+
2168+ return 0;
2169+}
2170+EXPORT_SYMBOL(isp_try_fmt);
2171+
2172+/**
2173+ * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
2174+ *
2175+ * Routine for saving the context of each module in the ISP.
2176+ * CCDC, HIST, H3A, PREV, RESZ and MMU.
2177+ **/
2178+static void isp_save_ctx(void)
2179+{
2180+ isp_save_context(isp_reg_list);
2181+ ispccdc_save_context();
2182+ ispmmu_save_context();
2183+ isphist_save_context();
2184+ isph3a_save_context();
2185+ isppreview_save_context();
2186+ ispresizer_save_context();
2187+}
2188+
2189+/**
2190+ * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
2191+ *
2192+ * Routine for restoring the context of each module in the ISP.
2193+ * CCDC, HIST, H3A, PREV, RESZ and MMU.
2194+ **/
2195+static void isp_restore_ctx(void)
2196+{
2197+ isp_restore_context(isp_reg_list);
2198+ ispccdc_restore_context();
2199+ ispmmu_restore_context();
2200+ isphist_restore_context();
2201+ isph3a_restore_context();
2202+ isppreview_restore_context();
2203+ ispresizer_restore_context();
2204+}
2205+
2206+static int isp_enable_clocks(void)
2207+{
2208+ int r;
2209+
2210+ r = clk_enable(isp_obj.cam_ick);
2211+ if (r) {
2212+ DPRINTK_ISPCTRL("ISP_ERR: clk_en for ick failed\n");
2213+ goto out_clk_enable_ick;
2214+ }
2215+ r = clk_enable(isp_obj.cam_mclk);
2216+ if (r) {
2217+ DPRINTK_ISPCTRL("ISP_ERR: clk_en for mclk failed\n");
2218+ goto out_clk_enable_mclk;
2219+ }
2220+ r = clk_enable(isp_obj.csi2_fck);
2221+ if (r) {
2222+ DPRINTK_ISPCTRL("ISP_ERR: clk_en for csi2_fclk"
2223+ " failed\n");
2224+ goto out_clk_enable_csi2_fclk;
2225+ }
2226+ return 0;
2227+
2228+out_clk_enable_csi2_fclk:
2229+ clk_disable(isp_obj.cam_mclk);
2230+out_clk_enable_mclk:
2231+ clk_disable(isp_obj.cam_ick);
2232+out_clk_enable_ick:
2233+ return r;
2234+}
2235+
2236+static void isp_disable_clocks(void)
2237+{
2238+ clk_disable(isp_obj.cam_ick);
2239+ clk_disable(isp_obj.cam_mclk);
2240+ clk_disable(isp_obj.csi2_fck);
2241+}
2242+
2243+/**
2244+ * isp_get - Adquires the ISP resource.
2245+ *
2246+ * Initializes the clocks for the first acquire.
2247+ **/
2248+int isp_get(void)
2249+{
2250+ static int has_context;
2251+ int ret_err = 0;
2252+
2253+ if (omap3isp == NULL)
2254+ return -EBUSY;
2255+
2256+ DPRINTK_ISPCTRL("isp_get: old %d\n", isp_obj.ref_count);
2257+ mutex_lock(&(isp_obj.isp_mutex));
2258+ if (isp_obj.ref_count == 0) {
2259+ ret_err = isp_enable_clocks();
2260+ if (ret_err)
2261+ goto out_err;
2262+ /* We don't want to restore context before saving it! */
2263+ if (has_context)
2264+ isp_restore_ctx();
2265+ else
2266+ has_context = 1;
2267+ } else {
2268+ mutex_unlock(&isp_obj.isp_mutex);
2269+ return -EBUSY;
2270+ }
2271+ isp_obj.ref_count++;
2272+ mutex_unlock(&(isp_obj.isp_mutex));
2273+
2274+ DPRINTK_ISPCTRL("isp_get: new %d\n", isp_obj.ref_count);
2275+ return isp_obj.ref_count;
2276+
2277+out_err:
2278+ mutex_unlock(&(isp_obj.isp_mutex));
2279+ return ret_err;
2280+}
2281+EXPORT_SYMBOL(isp_get);
2282+
2283+/**
2284+ * isp_put - Releases the ISP resource.
2285+ *
2286+ * Releases the clocks also for the last release.
2287+ **/
2288+int isp_put(void)
2289+{
2290+ if (omap3isp == NULL)
2291+ return -EBUSY;
2292+
2293+ DPRINTK_ISPCTRL("isp_put: old %d\n", isp_obj.ref_count);
2294+ mutex_lock(&(isp_obj.isp_mutex));
2295+ if (isp_obj.ref_count) {
2296+ if (--isp_obj.ref_count == 0) {
2297+ isp_save_ctx();
2298+ isp_tmp_buf_free();
2299+ isp_release_resources();
2300+ isp_obj.module.isp_pipeline = 0;
2301+ isp_disable_clocks();
2302+ memset(&ispcroprect, 0, sizeof(ispcroprect));
2303+ memset(&cur_rect, 0, sizeof(cur_rect));
2304+ }
2305+ }
2306+ mutex_unlock(&(isp_obj.isp_mutex));
2307+ DPRINTK_ISPCTRL("isp_put: new %d\n", isp_obj.ref_count);
2308+ return isp_obj.ref_count;
2309+}
2310+EXPORT_SYMBOL(isp_put);
2311+
2312+/**
2313+ * isp_save_context - Saves the values of the ISP module registers.
2314+ * @reg_list: Structure containing pairs of register address and value to
2315+ * modify on OMAP.
2316+ **/
2317+void isp_save_context(struct isp_reg *reg_list)
2318+{
2319+ struct isp_reg *next = reg_list;
2320+
2321+ for (; next->reg != ISP_TOK_TERM; next++)
2322+ next->val = isp_reg_readl(next->mmio_range, next->reg);
2323+}
2324+EXPORT_SYMBOL(isp_save_context);
2325+
2326+/**
2327+ * isp_restore_context - Restores the values of the ISP module registers.
2328+ * @reg_list: Structure containing pairs of register address and value to
2329+ * modify on OMAP.
2330+ **/
2331+void isp_restore_context(struct isp_reg *reg_list)
2332+{
2333+ struct isp_reg *next = reg_list;
2334+
2335+ for (; next->reg != ISP_TOK_TERM; next++)
2336+ isp_reg_writel(next->val, next->mmio_range, next->reg);
2337+}
2338+EXPORT_SYMBOL(isp_restore_context);
2339+
2340+static int isp_remove(struct platform_device *pdev)
2341+{
2342+ struct isp_device *isp = platform_get_drvdata(pdev);
2343+ int i;
2344+
2345+ isp_csi2_cleanup();
2346+ isp_af_exit();
2347+ isp_resizer_cleanup();
2348+ isp_preview_cleanup();
2349+ ispmmu_cleanup();
2350+ isph3a_aewb_cleanup();
2351+ isp_hist_cleanup();
2352+ isp_ccdc_cleanup();
2353+
2354+ if (!isp)
2355+ return 0;
2356+
2357+ clk_put(isp_obj.cam_ick);
2358+ clk_put(isp_obj.cam_mclk);
2359+ clk_put(isp_obj.csi2_fck);
2360+
2361+ free_irq(isp->irq, &isp_obj);
2362+
2363+ for (i = 0; i <= OMAP3_ISP_IOMEM_CSI2PHY; i++) {
2364+ if (isp->mmio_base[i]) {
2365+ iounmap((void *)isp->mmio_base[i]);
2366+ isp->mmio_base[i] = 0;
2367+ }
2368+
2369+ if (isp->mmio_base_phys[i]) {
2370+ release_mem_region(isp->mmio_base_phys[i],
2371+ isp->mmio_size[i]);
2372+ isp->mmio_base_phys[i] = 0;
2373+ }
2374+ }
2375+
2376+ omap3isp = NULL;
2377+
2378+ kfree(isp);
2379+
2380+ return 0;
2381+}
2382+
2383+#ifdef CONFIG_PM
2384+
2385+static int isp_suspend(struct platform_device *pdev, pm_message_t state)
2386+{
2387+ int reset;
2388+
2389+ mutex_lock(&(isp_obj.isp_mutex));
2390+ DPRINTK_ISPCTRL("isp_suspend: starting\n");
2391+ if (isp_obj.ref_count == 0)
2392+ goto out;
2393+
2394+ isp_disable_interrupts();
2395+ reset = isp_suspend_modules();
2396+ isp_save_ctx();
2397+ if (reset)
2398+ isp_reset();
2399+
2400+ isp_disable_clocks();
2401+
2402+out:
2403+ DPRINTK_ISPCTRL("isp_suspend: done\n");
2404+ mutex_unlock(&(isp_obj.isp_mutex));
2405+ return 0;
2406+}
2407+
2408+static int isp_resume(struct platform_device *pdev)
2409+{
2410+ int ret_err = 0;
2411+
2412+ DPRINTK_ISPCTRL("isp_resume: starting\n");
2413+
2414+ if (omap3isp == NULL)
2415+ goto out;
2416+
2417+ if (isp_obj.ref_count >= 0) {
2418+ ret_err = isp_enable_clocks();
2419+ if (ret_err)
2420+ goto out;
2421+ isp_restore_ctx();
2422+ isp_resume_modules();
2423+ isp_enable_interrupts(RAW_CAPTURE(&isp_obj));
2424+ isp_start();
2425+ }
2426+
2427+out:
2428+ DPRINTK_ISPCTRL("isp_resume: done \n");
2429+ return ret_err;
2430+}
2431+
2432+#else
2433+
2434+#define isp_suspend NULL
2435+#define isp_resume NULL
2436+
2437+#endif /* CONFIG_PM */
2438+
2439+
2440+static int isp_probe(struct platform_device *pdev)
2441+{
2442+ struct isp_device *isp;
2443+ int ret_err = 0;
2444+ int i;
2445+
2446+ isp = kzalloc(sizeof(*isp), GFP_KERNEL);
2447+ if (!isp) {
2448+ dev_err(&pdev->dev, "could not allocate memory\n");
2449+ return -ENOMEM;
2450+ }
2451+
2452+ platform_set_drvdata(pdev, isp);
2453+
2454+ isp->dev = &pdev->dev;
2455+
2456+ for (i = 0; i <= OMAP3_ISP_IOMEM_CSI2PHY; i++) {
2457+ struct resource *mem;
2458+ /* request the mem region for the camera registers */
2459+ mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
2460+ if (!mem) {
2461+ dev_err(isp->dev, "no mem resource?\n");
2462+ return -ENODEV;
2463+ }
2464+
2465+ if (!request_mem_region(mem->start, mem->end - mem->start + 1,
2466+ pdev->name)) {
2467+ dev_err(isp->dev,
2468+ "cannot reserve camera register I/O region\n");
2469+ return -ENODEV;
2470+
2471+ }
2472+ isp->mmio_base_phys[i] = mem->start;
2473+ isp->mmio_size[i] = mem->end - mem->start + 1;
2474+
2475+ /* map the region */
2476+ isp->mmio_base[i] = (unsigned long)
2477+ ioremap_nocache(isp->mmio_base_phys[i],
2478+ isp->mmio_size[i]);
2479+ if (!isp->mmio_base[i]) {
2480+ dev_err(isp->dev,
2481+ "cannot map camera register I/O region\n");
2482+ return -ENODEV;
2483+ }
2484+ }
2485+
2486+ isp->irq = platform_get_irq(pdev, 0);
2487+ if (isp->irq <= 0) {
2488+ dev_err(isp->dev, "no irq for camera?\n");
2489+ return -ENODEV;
2490+ }
2491+
2492+ isp_obj.cam_ick = clk_get(&camera_dev, "cam_ick");
2493+ if (IS_ERR(isp_obj.cam_ick)) {
2494+ DPRINTK_ISPCTRL("ISP_ERR: clk_get for "
2495+ "cam_ick failed\n");
2496+ return PTR_ERR(isp_obj.cam_ick);
2497+ }
2498+ isp_obj.cam_mclk = clk_get(&camera_dev, "cam_mclk");
2499+ if (IS_ERR(isp_obj.cam_mclk)) {
2500+ DPRINTK_ISPCTRL("ISP_ERR: clk_get for "
2501+ "cam_mclk failed\n");
2502+ ret_err = PTR_ERR(isp_obj.cam_mclk);
2503+ goto out_clk_get_mclk;
2504+ }
2505+ isp_obj.csi2_fck = clk_get(&camera_dev, "csi2_96m_fck");
2506+ if (IS_ERR(isp_obj.csi2_fck)) {
2507+ DPRINTK_ISPCTRL("ISP_ERR: clk_get for csi2_fclk"
2508+ " failed\n");
2509+ ret_err = PTR_ERR(isp_obj.csi2_fck);
2510+ goto out_clk_get_csi2_fclk;
2511+ }
2512+
2513+ if (request_irq(isp->irq, omap34xx_isp_isr, IRQF_SHARED,
2514+ "Omap 3 Camera ISP", &isp_obj)) {
2515+ DPRINTK_ISPCTRL("Could not install ISR\n");
2516+ ret_err = -EINVAL;
2517+ goto out_request_irq;
2518+ }
2519+
2520+ isp_obj.ref_count = 0;
2521+
2522+ mutex_init(&(isp_obj.isp_mutex));
2523+ spin_lock_init(&isp_obj.lock);
2524+ spin_lock_init(&isp_obj.bufs.lock);
2525+
2526+ omap3isp = isp;
2527+
2528+ ret_err = ispmmu_init();
2529+ if (ret_err)
2530+ goto out_ispmmu_init;
2531+
2532+ isp_ccdc_init();
2533+ isp_hist_init();
2534+ isph3a_aewb_init();
2535+ isp_preview_init();
2536+ isp_resizer_init();
2537+ isp_af_init();
2538+ isp_csi2_init();
2539+
2540+ isp_get();
2541+ isp_power_settings(1);
2542+ isp_put();
2543+
2544+ isph3a_notify(1);
2545+ isp_af_notify(1);
2546+
2547+ return 0;
2548+
2549+out_ispmmu_init:
2550+ omap3isp = NULL;
2551+ free_irq(isp->irq, &isp_obj);
2552+out_request_irq:
2553+ clk_put(isp_obj.csi2_fck);
2554+out_clk_get_csi2_fclk:
2555+ clk_put(isp_obj.cam_mclk);
2556+out_clk_get_mclk:
2557+ clk_put(isp_obj.cam_ick);
2558+
2559+ return ret_err;
2560+}
2561+
2562+static struct platform_driver omap3isp_driver = {
2563+ .probe = isp_probe,
2564+ .remove = isp_remove,
2565+ .suspend = isp_suspend,
2566+ .resume = isp_resume,
2567+ .driver = {
2568+ .name = "omap3isp",
2569+ },
2570+};
2571+
2572+/**
2573+ * isp_init - ISP module initialization.
2574+ **/
2575+static int __init isp_init(void)
2576+{
2577+ return platform_driver_register(&omap3isp_driver);
2578+}
2579+
2580+/**
2581+ * isp_cleanup - ISP module cleanup.
2582+ **/
2583+static void __exit isp_cleanup(void)
2584+{
2585+ platform_driver_unregister(&omap3isp_driver);
2586+}
2587+
2588+/**
2589+ * isp_print_status - Prints the values of the ISP Control Module registers
2590+ *
2591+ * Also prints other debug information stored in the ISP module structure.
2592+ **/
2593+void isp_print_status(void)
2594+{
2595+ if (!is_ispctrl_debug_enabled())
2596+ return;
2597+
2598+ DPRINTK_ISPCTRL("###ISP_CTRL=0x%x\n",
2599+ isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_CTRL));
2600+ DPRINTK_ISPCTRL("###ISP_TCTRL_CTRL=0x%x\n",
2601+ isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL));
2602+ DPRINTK_ISPCTRL("###ISP_SYSCONFIG=0x%x\n",
2603+ isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG));
2604+ DPRINTK_ISPCTRL("###ISP_SYSSTATUS=0x%x\n",
2605+ isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_SYSSTATUS));
2606+ DPRINTK_ISPCTRL("###ISP_IRQ0ENABLE=0x%x\n",
2607+ isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE));
2608+ DPRINTK_ISPCTRL("###ISP_IRQ0STATUS=0x%x\n",
2609+ isp_reg_readl(OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS));
2610+}
2611+EXPORT_SYMBOL(isp_print_status);
2612+
2613+module_init(isp_init);
2614+module_exit(isp_cleanup);
2615+
2616+MODULE_AUTHOR("Texas Instruments");
2617+MODULE_DESCRIPTION("ISP Control Module Library");
2618+MODULE_LICENSE("GPL");
2619diff --git a/drivers/media/video/isp/isp.h b/drivers/media/video/isp/isp.h
2620new file mode 100644
2621index 0000000..55c98a9
2622--- /dev/null
2623+++ b/drivers/media/video/isp/isp.h
2624@@ -0,0 +1,318 @@
2625+/*
2626+ * isp.h
2627+ *
2628+ * Top level public header file for ISP Control module in
2629+ * TI's OMAP3 Camera ISP
2630+ *
2631+ * Copyright (C) 2009 Texas Instruments.
2632+ * Copyright (C) 2009 Nokia.
2633+ *
2634+ * Contributors:
2635+ * Sameer Venkatraman <sameerv@ti.com>
2636+ * Mohit Jalori <mjalori@ti.com>
2637+ * Sergio Aguirre <saaguirre@ti.com>
2638+ * Sakari Ailus <sakari.ailus@nokia.com>
2639+ * Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
2640+ *
2641+ * This package is free software; you can redistribute it and/or modify
2642+ * it under the terms of the GNU General Public License version 2 as
2643+ * published by the Free Software Foundation.
2644+ *
2645+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
2646+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
2647+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
2648+ */
2649+
2650+#ifndef OMAP_ISP_TOP_H
2651+#define OMAP_ISP_TOP_H
2652+#include <mach/cpu.h>
2653+#include <media/videobuf-dma-sg.h>
2654+#include <linux/videodev2.h>
2655+#define OMAP_ISP_CCDC (1 << 0)
2656+#define OMAP_ISP_PREVIEW (1 << 1)
2657+#define OMAP_ISP_RESIZER (1 << 2)
2658+#define OMAP_ISP_AEWB (1 << 3)
2659+#define OMAP_ISP_AF (1 << 4)
2660+#define OMAP_ISP_HIST (1 << 5)
2661+
2662+#define ISP_TOK_TERM 0xFFFFFFFF /*
2663+ * terminating token for ISP
2664+ * modules reg list
2665+ */
2666+#define NUM_BUFS VIDEO_MAX_FRAME
2667+
2668+#ifndef CONFIG_ARCH_OMAP3410
2669+#define USE_ISP_PREVIEW
2670+#define USE_ISP_RESZ
2671+#define is_isppreview_enabled() 1
2672+#define is_ispresizer_enabled() 1
2673+#else
2674+#define is_isppreview_enabled() 0
2675+#define is_ispresizer_enabled() 0
2676+#endif
2677+
2678+#define ISP_BYTES_PER_PIXEL 2
2679+#define NUM_ISP_CAPTURE_FORMATS (sizeof(isp_formats) / \
2680+ sizeof(isp_formats[0]))
2681+typedef int (*isp_vbq_callback_ptr) (struct videobuf_buffer *vb);
2682+typedef void (*isp_callback_t) (unsigned long status,
2683+ isp_vbq_callback_ptr arg1, void *arg2);
2684+
2685+enum isp_mem_resources {
2686+ OMAP3_ISP_IOMEM_MAIN,
2687+ OMAP3_ISP_IOMEM_CBUFF,
2688+ OMAP3_ISP_IOMEM_CCP2,
2689+ OMAP3_ISP_IOMEM_CCDC,
2690+ OMAP3_ISP_IOMEM_HIST,
2691+ OMAP3_ISP_IOMEM_H3A,
2692+ OMAP3_ISP_IOMEM_PREV,
2693+ OMAP3_ISP_IOMEM_RESZ,
2694+ OMAP3_ISP_IOMEM_SBL,
2695+ OMAP3_ISP_IOMEM_CSI2A,
2696+ OMAP3_ISP_IOMEM_CSI2PHY
2697+};
2698+
2699+struct isp_device {
2700+ struct device *dev;
2701+
2702+ /*** platform HW resources ***/
2703+ unsigned int irq;
2704+
2705+#define mmio_base_main mmio_base[OMAP3_ISP_IOMEM_MAIN]
2706+#define mmio_cbuff_main mmio_base[OMAP3_ISP_IOMEM_CBUFF]
2707+#define mmio_ccp2_main mmio_base[OMAP3_ISP_IOMEM_CCP2]
2708+#define mmio_ccdc_main mmio_base[OMAP3_ISP_IOMEM_CCDC]
2709+#define mmio_hist_main mmio_base[OMAP3_ISP_IOMEM_HIST]
2710+#define mmio_h3a_main mmio_base[OMAP3_ISP_IOMEM_H3A]
2711+#define mmio_prev_main mmio_base[OMAP3_ISP_IOMEM_PREV]
2712+#define mmio_resz_main mmio_base[OMAP3_ISP_IOMEM_RESZ]
2713+#define mmio_sbl_main mmio_base[OMAP3_ISP_IOMEM_SBL]
2714+#define mmio_csi2_main mmio_base[OMAP3_ISP_IOMEM_CSI2A]
2715+#define mmio_csi2phy_main mmio_base[OMAP3_ISP_IOMEM_CSI2PHY]
2716+ unsigned long mmio_base[OMAP3_ISP_IOMEM_CSI2PHY + 1];
2717+ unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_CSI2PHY + 1];
2718+ unsigned long mmio_size[OMAP3_ISP_IOMEM_CSI2PHY + 1];
2719+};
2720+
2721+enum isp_interface_type {
2722+ ISP_PARLL = 1,
2723+ ISP_CSIA = 2,
2724+ ISP_CSIB = 4,
2725+ ISP_NONE = 8 /* memory input to preview / resizer */
2726+};
2727+
2728+enum isp_irqevents {
2729+ CSIA = 0x01,
2730+ CSIB = 0x10,
2731+ CCDC_VD0 = 0x100,
2732+ CCDC_VD1 = 0x200,
2733+ CCDC_VD2 = 0x400,
2734+ CCDC_ERR = 0x800,
2735+ H3A_AWB_DONE = 0x2000,
2736+ H3A_AF_DONE = 0x1000,
2737+ HIST_DONE = 0x10000,
2738+ PREV_DONE = 0x100000,
2739+ LSC_DONE = 0x20000,
2740+ LSC_PRE_COMP = 0x40000,
2741+ LSC_PRE_ERR = 0x80000,
2742+ RESZ_DONE = 0x1000000,
2743+ SBL_OVF = 0x2000000,
2744+ MMU_ERR = 0x10000000,
2745+ OCP_ERR = 0x20000000,
2746+ HS_VS = 0x80000000
2747+};
2748+
2749+enum isp_callback_type {
2750+ CBK_CCDC_VD0,
2751+ CBK_CCDC_VD1,
2752+ CBK_PREV_DONE,
2753+ CBK_RESZ_DONE,
2754+ CBK_MMU_ERR,
2755+ CBK_H3A_AWB_DONE,
2756+ CBK_HIST_DONE,
2757+ CBK_HS_VS,
2758+ CBK_LSC_ISR,
2759+ CBK_H3A_AF_DONE,
2760+ CBK_CATCHALL,
2761+ CBK_CSIA,
2762+ CBK_CSIB,
2763+ CBK_END,
2764+};
2765+
2766+/**
2767+ * struct isp_reg - Structure for ISP register values.
2768+ * @reg: 32-bit Register address.
2769+ * @val: 32-bit Register value.
2770+ */
2771+struct isp_reg {
2772+ enum isp_mem_resources mmio_range;
2773+ u32 reg;
2774+ u32 val;
2775+};
2776+
2777+/**
2778+ * struct isp_interface_config - ISP interface configuration.
2779+ * @ccdc_par_ser: ISP interface type. 0 - Parallel, 1 - CSIA, 2 - CSIB to CCDC.
2780+ * @par_bridge: CCDC Bridge input control. Parallel interface.
2781+ * 0 - Disable, 1 - Enable, first byte->cam_d(bits 7 to 0)
2782+ * 2 - Enable, first byte -> cam_d(bits 15 to 8)
2783+ * @par_clk_pol: Pixel clock polarity on the parallel interface.
2784+ * 0 - Non Inverted, 1 - Inverted
2785+ * @dataline_shift: Data lane shifter.
2786+ * 0 - No Shift, 1 - CAMEXT[13 to 2]->CAM[11 to 0]
2787+ * 2 - CAMEXT[13 to 4]->CAM[9 to 0]
2788+ * 3 - CAMEXT[13 to 6]->CAM[7 to 0]
2789+ * @hsvs_syncdetect: HS or VS synchronization signal detection.
2790+ * 0 - HS Falling, 1 - HS rising
2791+ * 2 - VS falling, 3 - VS rising
2792+ * @strobe: Strobe related parameter.
2793+ * @prestrobe: PreStrobe related parameter.
2794+ * @shutter: Shutter related parameter.
2795+ * @hskip: Horizontal Start Pixel performed in Preview module.
2796+ * @vskip: Vertical Start Line performed in Preview module.
2797+ * @wenlog: Store the value for the sensor specific wenlog field.
2798+ * @wait_hs_vs: Wait for this many hs_vs before anything else in the beginning.
2799+ */
2800+struct isp_interface_config {
2801+ enum isp_interface_type ccdc_par_ser;
2802+ u8 dataline_shift;
2803+ u32 hsvs_syncdetect;
2804+ int strobe;
2805+ int prestrobe;
2806+ int shutter;
2807+ u32 prev_sph;
2808+ u32 prev_slv;
2809+ u32 wenlog;
2810+ int wait_hs_vs;
2811+ union {
2812+ struct par {
2813+ unsigned par_bridge:2;
2814+ unsigned par_clk_pol:1;
2815+ } par;
2816+ struct csi {
2817+ unsigned crc:1;
2818+ unsigned mode:1;
2819+ unsigned edge:1;
2820+ unsigned signalling:1;
2821+ unsigned strobe_clock_inv:1;
2822+ unsigned vs_edge:1;
2823+ unsigned channel:3;
2824+ unsigned vpclk:2; /* Video port output clock */
2825+ unsigned int data_start;
2826+ unsigned int data_size;
2827+ u32 format; /* V4L2_PIX_FMT_* */
2828+ } csi;
2829+ } u;
2830+};
2831+
2832+u32 isp_reg_readl(enum isp_mem_resources isp_mmio_range, u32 reg_offset);
2833+
2834+void isp_reg_writel(u32 reg_value, enum isp_mem_resources isp_mmio_range,
2835+ u32 reg_offset);
2836+
2837+static inline void isp_reg_and(enum isp_mem_resources mmio_range, u32 reg,
2838+ u32 and_bits)
2839+{
2840+ u32 v = isp_reg_readl(mmio_range, reg);
2841+
2842+ isp_reg_writel(v & and_bits, mmio_range, reg);
2843+}
2844+
2845+static inline void isp_reg_or(enum isp_mem_resources mmio_range, u32 reg,
2846+ u32 or_bits)
2847+{
2848+ u32 v = isp_reg_readl(mmio_range, reg);
2849+
2850+ isp_reg_writel(v | or_bits, mmio_range, reg);
2851+}
2852+
2853+static inline void isp_reg_and_or(enum isp_mem_resources mmio_range, u32 reg,
2854+ u32 and_bits, u32 or_bits)
2855+{
2856+ u32 v = isp_reg_readl(mmio_range, reg);
2857+
2858+ isp_reg_writel((v & and_bits) | or_bits, mmio_range, reg);
2859+}
2860+
2861+void isp_start(void);
2862+
2863+void isp_stop(void);
2864+
2865+int isp_buf_queue(struct videobuf_buffer *vb,
2866+ void (*complete)(struct videobuf_buffer *vb, void *priv),
2867+ void *priv);
2868+
2869+int isp_vbq_setup(struct videobuf_queue *vbq, unsigned int *cnt,
2870+ unsigned int *size);
2871+
2872+int isp_vbq_prepare(struct videobuf_queue *vbq, struct videobuf_buffer *vb,
2873+ enum v4l2_field field);
2874+
2875+void isp_vbq_release(struct videobuf_queue *vbq, struct videobuf_buffer *vb);
2876+
2877+int isp_set_callback(enum isp_callback_type type, isp_callback_t callback,
2878+ isp_vbq_callback_ptr arg1, void *arg2);
2879+
2880+int isp_unset_callback(enum isp_callback_type type);
2881+
2882+u32 isp_set_xclk(u32 xclk, u8 xclksel);
2883+
2884+int isp_configure_interface(struct isp_interface_config *config);
2885+
2886+int isp_get(void);
2887+
2888+int isp_put(void);
2889+
2890+int isp_queryctrl(struct v4l2_queryctrl *a);
2891+
2892+int isp_querymenu(struct v4l2_querymenu *a);
2893+
2894+int isp_g_ctrl(struct v4l2_control *a);
2895+
2896+int isp_s_ctrl(struct v4l2_control *a);
2897+
2898+int isp_enum_fmt_cap(struct v4l2_fmtdesc *f);
2899+
2900+int isp_try_fmt_cap(struct v4l2_pix_format *pix_input,
2901+ struct v4l2_pix_format *pix_output);
2902+
2903+void isp_g_fmt_cap(struct v4l2_pix_format *pix);
2904+
2905+int isp_s_fmt_cap(struct v4l2_pix_format *pix_input,
2906+ struct v4l2_pix_format *pix_output);
2907+
2908+int isp_g_crop(struct v4l2_crop *a);
2909+
2910+int isp_s_crop(struct v4l2_crop *a, struct v4l2_pix_format *pix);
2911+
2912+void isp_config_crop(struct v4l2_pix_format *pix);
2913+
2914+int isp_try_fmt(struct v4l2_pix_format *pix_input,
2915+ struct v4l2_pix_format *pix_output);
2916+
2917+int isp_handle_private(int cmd, void *arg);
2918+
2919+void isp_save_context(struct isp_reg *);
2920+
2921+void isp_restore_context(struct isp_reg *);
2922+
2923+void isp_print_status(void);
2924+
2925+int __init isp_ccdc_init(void);
2926+int __init isp_hist_init(void);
2927+int __init isph3a_aewb_init(void);
2928+int __init isp_preview_init(void);
2929+int __init isp_resizer_init(void);
2930+int __init isp_af_init(void);
2931+int __init isp_csi2_init(void);
2932+
2933+void isp_ccdc_cleanup(void);
2934+void isp_hist_cleanup(void);
2935+void isph3a_aewb_cleanup(void);
2936+void isp_preview_cleanup(void);
2937+void isp_hist_cleanup(void);
2938+void isp_resizer_cleanup(void);
2939+void isp_af_exit(void);
2940+void isp_csi2_cleanup(void);
2941+
2942+#endif /* OMAP_ISP_TOP_H */
2943diff --git a/drivers/media/video/isp/ispreg.h b/drivers/media/video/isp/ispreg.h
2944new file mode 100644
2945index 0000000..4f8e1ef
2946--- /dev/null
2947+++ b/drivers/media/video/isp/ispreg.h
2948@@ -0,0 +1,1674 @@
2949+/*
2950+ * ispreg.h
2951+ *
2952+ * Header file for all the ISP module in TI's OMAP3 Camera ISP.
2953+ * It has the OMAP HW register definitions.
2954+ *
2955+ * Copyright (C) 2009 Texas Instruments.
2956+ * Copyright (C) 2009 Nokia.
2957+ *
2958+ * Contributors:
2959+ * Tuukka Toivonen <tuukka.o.toivonen@nokia.com>
2960+ * Thara Gopinath <thara@ti.com>
2961+ * Sergio Aguirre <saaguirre@ti.com>
2962+ *
2963+ * This package is free software; you can redistribute it and/or modify
2964+ * it under the terms of the GNU General Public License version 2 as
2965+ * published by the Free Software Foundation.
2966+ *
2967+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
2968+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
2969+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
2970+ */
2971+
2972+#ifndef __ISPREG_H__
2973+#define __ISPREG_H__
2974+
2975+#include <mach/omap34xx.h>
2976+
2977+/* Note: Uncomment below defines as needed for enabling module specific debug
2978+ * messages
2979+ */
2980+
2981+/*
2982+ #define OMAP_ISPCTRL_DEBUG
2983+ #define OMAP_ISPCCDC_DEBUG
2984+ #define OMAP_ISPPREV_DEBUG
2985+ #define OMAP_ISPRESZ_DEBUG
2986+ #define OMAP_ISPMMU_DEBUG
2987+ #define OMAP_ISPH3A_DEBUG
2988+ #define OMAP_ISP_AF_DEBUG
2989+ #define OMAP_ISPHIST_DEBUG
2990+*/
2991+
2992+#ifdef OMAP_ISPCTRL_DEBUG
2993+#define DPRINTK_ISPCTRL(format, ...) \
2994+ printk(KERN_INFO "ISPCTRL: " format, ## __VA_ARGS__)
2995+#define is_ispctrl_debug_enabled() 1
2996+#else
2997+#define DPRINTK_ISPCTRL(format, ...)
2998+#define is_ispctrl_debug_enabled() 0
2999+#endif
3000+
3001+#ifdef OMAP_ISPCCDC_DEBUG
3002+#define DPRINTK_ISPCCDC(format, ...) \
3003+ printk(KERN_INFO "ISPCCDC: " format, ## __VA_ARGS__)
3004+#define is_ispccdc_debug_enabled() 1
3005+#else
3006+#define DPRINTK_ISPCCDC(format, ...)
3007+#define is_ispccdc_debug_enabled() 0
3008+#endif
3009+
3010+#ifdef OMAP_ISPPREV_DEBUG
3011+#define DPRINTK_ISPPREV(format, ...) \
3012+ printk(KERN_INFO "ISPPREV: " format, ## __VA_ARGS__)
3013+#define is_ispprev_debug_enabled() 1
3014+#else
3015+#define DPRINTK_ISPPREV(format, ...)
3016+#define is_ispprev_debug_enabled() 0
3017+#endif
3018+
3019+#ifdef OMAP_ISPRESZ_DEBUG
3020+#define DPRINTK_ISPRESZ(format, ...) \
3021+ printk(KERN_INFO "ISPRESZ: " format, ## __VA_ARGS__)
3022+#define is_ispresz_debug_enabled() 1
3023+#else
3024+#define DPRINTK_ISPRESZ(format, ...)
3025+#define is_ispresz_debug_enabled() 0
3026+#endif
3027+
3028+#ifdef OMAP_ISPMMU_DEBUG
3029+#define DPRINTK_ISPMMU(format, ...) \
3030+ printk(KERN_INFO "ISPMMU: " format, ## __VA_ARGS__)
3031+#define is_ispmmu_debug_enabled() 1
3032+#else
3033+#define DPRINTK_ISPMMU(format, ...)
3034+#define is_ispmmu_debug_enabled() 0
3035+#endif
3036+
3037+#ifdef OMAP_ISPH3A_DEBUG
3038+#define DPRINTK_ISPH3A(format, ...) \
3039+ printk(KERN_INFO "ISPH3A: " format, ## __VA_ARGS__)
3040+#define is_isph3a_debug_enabled() 1
3041+#else
3042+#define DPRINTK_ISPH3A(format, ...)
3043+#define is_isph3a_debug_enabled() 0
3044+#endif
3045+
3046+#ifdef OMAP_ISP_AF_DEBUG
3047+#define DPRINTK_ISP_AF(format, ...) \
3048+ printk(KERN_INFO "ISP_AF: " format, ## __VA_ARGS__)
3049+#define is_isp_af_debug_enabled() 1
3050+#else
3051+#define DPRINTK_ISP_AF(format, ...)
3052+#define is_isp_af_debug_enabled() 0
3053+#endif
3054+
3055+#ifdef OMAP_ISPHIST_DEBUG
3056+#define DPRINTK_ISPHIST(format, ...) \
3057+ printk(KERN_INFO "ISPHIST: " format, ## __VA_ARGS__)
3058+#define is_isphist_debug_enabled() 1
3059+#else
3060+#define DPRINTK_ISPHIST(format, ...)
3061+#define is_isphist_debug_enabled() 0
3062+#endif
3063+
3064+#define ISP_32B_BOUNDARY_BUF 0xFFFFFFE0
3065+#define ISP_32B_BOUNDARY_OFFSET 0x0000FFE0
3066+
3067+#define CM_CAM_MCLK_HZ 216000000
3068+
3069+/* ISP Submodules offset */
3070+
3071+#define OMAP3ISP_REG_BASE OMAP3430_ISP_BASE
3072+#define OMAP3ISP_REG(offset) (OMAP3ISP_REG_BASE + (offset))
3073+
3074+#define OMAP3ISP_CBUFF_REG_OFFSET 0x0100
3075+#define OMAP3ISP_CBUFF_REG_BASE (OMAP3ISP_REG_BASE + \
3076+ OMAP3ISP_CBUFF_REG_OFFSET)
3077+#define OMAP3ISP_CBUFF_REG(offset) (OMAP3ISP_CBUFF_REG_BASE + (offset))
3078+
3079+#define OMAP3ISP_CCP2_REG_OFFSET 0x0400
3080+#define OMAP3ISP_CCP2_REG_BASE (OMAP3ISP_REG_BASE + \
3081+ OMAP3ISP_CCP2_REG_OFFSET)
3082+#define OMAP3ISP_CCP2_REG(offset) (OMAP3ISP_CCP2_REG_BASE + (offset))
3083+
3084+#define OMAP3ISP_CCDC_REG_OFFSET 0x0600
3085+#define OMAP3ISP_CCDC_REG_BASE (OMAP3ISP_REG_BASE + \
3086+ OMAP3ISP_CCDC_REG_OFFSET)
3087+#define OMAP3ISP_CCDC_REG(offset) (OMAP3ISP_CCDC_REG_BASE + (offset))
3088+
3089+#define OMAP3ISP_HIST_REG_OFFSET 0x0A00
3090+#define OMAP3ISP_HIST_REG_BASE (OMAP3ISP_REG_BASE + \
3091+ OMAP3ISP_HIST_REG_OFFSET)
3092+#define OMAP3ISP_HIST_REG(offset) (OMAP3ISP_HIST_REG_BASE + (offset))
3093+
3094+#define OMAP3ISP_H3A_REG_OFFSET 0x0C00
3095+#define OMAP3ISP_H3A_REG_BASE (OMAP3ISP_REG_BASE + \
3096+ OMAP3ISP_H3A_REG_OFFSET)
3097+#define OMAP3ISP_H3A_REG(offset) (OMAP3ISP_H3A_REG_BASE + (offset))
3098+
3099+#define OMAP3ISP_PREV_REG_OFFSET 0x0E00
3100+#define OMAP3ISP_PREV_REG_BASE (OMAP3ISP_REG_BASE + \
3101+ OMAP3ISP_PREV_REG_OFFSET)
3102+#define OMAP3ISP_PREV_REG(offset) (OMAP3ISP_PREV_REG_BASE + (offset))
3103+
3104+#define OMAP3ISP_RESZ_REG_OFFSET 0x1000
3105+#define OMAP3ISP_RESZ_REG_BASE (OMAP3ISP_REG_BASE + \
3106+ OMAP3ISP_RESZ_REG_OFFSET)
3107+#define OMAP3ISP_RESZ_REG(offset) (OMAP3ISP_RESZ_REG_BASE + (offset))
3108+
3109+#define OMAP3ISP_SBL_REG_OFFSET 0x1200
3110+#define OMAP3ISP_SBL_REG_BASE (OMAP3ISP_REG_BASE + \
3111+ OMAP3ISP_SBL_REG_OFFSET)
3112+#define OMAP3ISP_SBL_REG(offset) (OMAP3ISP_SBL_REG_BASE + (offset))
3113+
3114+#define OMAP3ISP_MMU_REG_OFFSET 0x1400
3115+#define OMAP3ISP_MMU_REG_BASE (OMAP3ISP_REG_BASE + \
3116+ OMAP3ISP_MMU_REG_OFFSET)
3117+#define OMAP3ISP_MMU_REG(offset) (OMAP3ISP_MMU_REG_BASE + (offset))
3118+
3119+#define OMAP3ISP_CSI2A_REG_OFFSET 0x1800
3120+#define OMAP3ISP_CSI2A_REG_BASE (OMAP3ISP_REG_BASE + \
3121+ OMAP3ISP_CSI2A_REG_OFFSET)
3122+#define OMAP3ISP_CSI2A_REG(offset) (OMAP3ISP_CSI2A_REG_BASE + (offset))
3123+
3124+#define OMAP3ISP_CSI2PHY_REG_OFFSET 0x1970
3125+#define OMAP3ISP_CSI2PHY_REG_BASE (OMAP3ISP_REG_BASE + \
3126+ OMAP3ISP_CSI2PHY_REG_OFFSET)
3127+#define OMAP3ISP_CSI2PHY_REG(offset) (OMAP3ISP_CSI2PHY_REG_BASE + (offset))
3128+
3129+/* ISP module register offset */
3130+
3131+#define ISP_REVISION (0x000)
3132+#define ISP_SYSCONFIG (0x004)
3133+#define ISP_SYSSTATUS (0x008)
3134+#define ISP_IRQ0ENABLE (0x00C)
3135+#define ISP_IRQ0STATUS (0x010)
3136+#define ISP_IRQ1ENABLE (0x014)
3137+#define ISP_IRQ1STATUS (0x018)
3138+#define ISP_TCTRL_GRESET_LENGTH (0x030)
3139+#define ISP_TCTRL_PSTRB_REPLAY (0x034)
3140+#define ISP_CTRL (0x040)
3141+#define ISP_SECURE (0x044)
3142+#define ISP_TCTRL_CTRL (0x050)
3143+#define ISP_TCTRL_FRAME (0x054)
3144+#define ISP_TCTRL_PSTRB_DELAY (0x058)
3145+#define ISP_TCTRL_STRB_DELAY (0x05C)
3146+#define ISP_TCTRL_SHUT_DELAY (0x060)
3147+#define ISP_TCTRL_PSTRB_LENGTH (0x064)
3148+#define ISP_TCTRL_STRB_LENGTH (0x068)
3149+#define ISP_TCTRL_SHUT_LENGTH (0x06C)
3150+#define ISP_PING_PONG_ADDR (0x070)
3151+#define ISP_PING_PONG_MEM_RANGE (0x074)
3152+#define ISP_PING_PONG_BUF_SIZE (0x078)
3153+
3154+/* CSI1 receiver registers (ES2.0) */
3155+#define ISPCSI1_REVISION (0x000)
3156+#define ISPCSI1_SYSCONFIG (0x004)
3157+#define ISPCSI1_SYSSTATUS (0x008)
3158+#define ISPCSI1_LC01_IRQENABLE (0x00C)
3159+#define ISPCSI1_LC01_IRQSTATUS (0x010)
3160+#define ISPCSI1_LC23_IRQENABLE (0x014)
3161+#define ISPCSI1_LC23_IRQSTATUS (0x018)
3162+#define ISPCSI1_LCM_IRQENABLE (0x02C)
3163+#define ISPCSI1_LCM_IRQSTATUS (0x030)
3164+#define ISPCSI1_CTRL (0x040)
3165+#define ISPCSI1_DBG (0x044)
3166+#define ISPCSI1_GNQ (0x048)
3167+#define ISPCSI1_LCx_CTRL(x) ((0x050)+0x30*(x))
3168+#define ISPCSI1_LCx_CODE(x) ((0x054)+0x30*(x))
3169+#define ISPCSI1_LCx_STAT_START(x) ((0x058)+0x30*(x))
3170+#define ISPCSI1_LCx_STAT_SIZE(x) ((0x05C)+0x30*(x))
3171+#define ISPCSI1_LCx_SOF_ADDR(x) ((0x060)+0x30*(x))
3172+#define ISPCSI1_LCx_EOF_ADDR(x) ((0x064)+0x30*(x))
3173+#define ISPCSI1_LCx_DAT_START(x) ((0x068)+0x30*(x))
3174+#define ISPCSI1_LCx_DAT_SIZE(x) ((0x06C)+0x30*(x))
3175+#define ISPCSI1_LCx_DAT_PING_ADDR(x) ((0x070)+0x30*(x))
3176+#define ISPCSI1_LCx_DAT_PONG_ADDR(x) ((0x074)+0x30*(x))
3177+#define ISPCSI1_LCx_DAT_OFST(x) ((0x078)+0x30*(x))
3178+#define ISPCSI1_LCM_CTRL (0x1D0)
3179+#define ISPCSI1_LCM_VSIZE (0x1D4)
3180+#define ISPCSI1_LCM_HSIZE (0x1D8)
3181+#define ISPCSI1_LCM_PREFETCH (0x1DC)
3182+#define ISPCSI1_LCM_SRC_ADDR (0x1E0)
3183+#define ISPCSI1_LCM_SRC_OFST (0x1E4)
3184+#define ISPCSI1_LCM_DST_ADDR (0x1E8)
3185+#define ISPCSI1_LCM_DST_OFST (0x1EC)
3186+#define ISP_CSIB_SYSCONFIG ISPCSI1_SYSCONFIG
3187+#define ISP_CSIA_SYSCONFIG ISPCSI2_SYSCONFIG
3188+
3189+/* ISP_CBUFF Registers */
3190+
3191+#define ISP_CBUFF_SYSCONFIG (0x010)
3192+#define ISP_CBUFF_IRQENABLE (0x01C)
3193+
3194+#define ISP_CBUFF0_CTRL (0x020)
3195+#define ISP_CBUFF1_CTRL (0x024)
3196+
3197+#define ISP_CBUFF0_START (0x040)
3198+#define ISP_CBUFF1_START (0x044)
3199+
3200+#define ISP_CBUFF0_END (0x050)
3201+#define ISP_CBUFF1_END (0x054)
3202+
3203+#define ISP_CBUFF0_WINDOWSIZE (0x060)
3204+#define ISP_CBUFF1_WINDOWSIZE (0x064)
3205+
3206+#define ISP_CBUFF0_THRESHOLD (0x070)
3207+#define ISP_CBUFF1_THRESHOLD (0x074)
3208+
3209+/* CCDC module register offset */
3210+
3211+#define ISPCCDC_PID (0x000)
3212+#define ISPCCDC_PCR (0x004)
3213+#define ISPCCDC_SYN_MODE (0x008)
3214+#define ISPCCDC_HD_VD_WID (0x00C)
3215+#define ISPCCDC_PIX_LINES (0x010)
3216+#define ISPCCDC_HORZ_INFO (0x014)
3217+#define ISPCCDC_VERT_START (0x018)
3218+#define ISPCCDC_VERT_LINES (0x01C)
3219+#define ISPCCDC_CULLING (0x020)
3220+#define ISPCCDC_HSIZE_OFF (0x024)
3221+#define ISPCCDC_SDOFST (0x028)
3222+#define ISPCCDC_SDR_ADDR (0x02C)
3223+#define ISPCCDC_CLAMP (0x030)
3224+#define ISPCCDC_DCSUB (0x034)
3225+#define ISPCCDC_COLPTN (0x038)
3226+#define ISPCCDC_BLKCMP (0x03C)
3227+#define ISPCCDC_FPC (0x040)
3228+#define ISPCCDC_FPC_ADDR (0x044)
3229+#define ISPCCDC_VDINT (0x048)
3230+#define ISPCCDC_ALAW (0x04C)
3231+#define ISPCCDC_REC656IF (0x050)
3232+#define ISPCCDC_CFG (0x054)
3233+#define ISPCCDC_FMTCFG (0x058)
3234+#define ISPCCDC_FMT_HORZ (0x05C)
3235+#define ISPCCDC_FMT_VERT (0x060)
3236+#define ISPCCDC_FMT_ADDR0 (0x064)
3237+#define ISPCCDC_FMT_ADDR1 (0x068)
3238+#define ISPCCDC_FMT_ADDR2 (0x06C)
3239+#define ISPCCDC_FMT_ADDR3 (0x070)
3240+#define ISPCCDC_FMT_ADDR4 (0x074)
3241+#define ISPCCDC_FMT_ADDR5 (0x078)
3242+#define ISPCCDC_FMT_ADDR6 (0x07C)
3243+#define ISPCCDC_FMT_ADDR7 (0x080)
3244+#define ISPCCDC_PRGEVEN0 (0x084)
3245+#define ISPCCDC_PRGEVEN1 (0x088)
3246+#define ISPCCDC_PRGODD0 (0x08C)
3247+#define ISPCCDC_PRGODD1 (0x090)
3248+#define ISPCCDC_VP_OUT (0x094)
3249+
3250+#define ISPCCDC_LSC_CONFIG (0x098)
3251+#define ISPCCDC_LSC_INITIAL (0x09C)
3252+#define ISPCCDC_LSC_TABLE_BASE (0x0A0)
3253+#define ISPCCDC_LSC_TABLE_OFFSET (0x0A4)
3254+
3255+/* SBL */
3256+#define ISPSBL_CCDC_WR_0 (0x028)
3257+#define ISPSBL_CCDC_WR_0_DATA_READY (1 << 21)
3258+#define ISPSBL_CCDC_WR_1 (0x02C)
3259+#define ISPSBL_CCDC_WR_2 (0x030)
3260+#define ISPSBL_CCDC_WR_3 (0x034)
3261+
3262+/* Histogram registers */
3263+#define ISPHIST_PID (0x000)
3264+#define ISPHIST_PCR (0x004)
3265+#define ISPHIST_CNT (0x008)
3266+#define ISPHIST_WB_GAIN (0x00C)
3267+#define ISPHIST_R0_HORZ (0x010)
3268+#define ISPHIST_R0_VERT (0x014)
3269+#define ISPHIST_R1_HORZ (0x018)
3270+#define ISPHIST_R1_VERT (0x01C)
3271+#define ISPHIST_R2_HORZ (0x020)
3272+#define ISPHIST_R2_VERT (0x024)
3273+#define ISPHIST_R3_HORZ (0x028)
3274+#define ISPHIST_R3_VERT (0x02C)
3275+#define ISPHIST_ADDR (0x030)
3276+#define ISPHIST_DATA (0x034)
3277+#define ISPHIST_RADD (0x038)
3278+#define ISPHIST_RADD_OFF (0x03C)
3279+#define ISPHIST_H_V_INFO (0x040)
3280+
3281+/* H3A module registers */
3282+#define ISPH3A_PID (0x000)
3283+#define ISPH3A_PCR (0x004)
3284+#define ISPH3A_AEWWIN1 (0x04C)
3285+#define ISPH3A_AEWINSTART (0x050)
3286+#define ISPH3A_AEWINBLK (0x054)
3287+#define ISPH3A_AEWSUBWIN (0x058)
3288+#define ISPH3A_AEWBUFST (0x05C)
3289+#define ISPH3A_AFPAX1 (0x008)
3290+#define ISPH3A_AFPAX2 (0x00C)
3291+#define ISPH3A_AFPAXSTART (0x010)
3292+#define ISPH3A_AFIIRSH (0x014)
3293+#define ISPH3A_AFBUFST (0x018)
3294+#define ISPH3A_AFCOEF010 (0x01C)
3295+#define ISPH3A_AFCOEF032 (0x020)
3296+#define ISPH3A_AFCOEF054 (0x024)
3297+#define ISPH3A_AFCOEF076 (0x028)
3298+#define ISPH3A_AFCOEF098 (0x02C)
3299+#define ISPH3A_AFCOEF0010 (0x030)
3300+#define ISPH3A_AFCOEF110 (0x034)
3301+#define ISPH3A_AFCOEF132 (0x038)
3302+#define ISPH3A_AFCOEF154 (0x03C)
3303+#define ISPH3A_AFCOEF176 (0x040)
3304+#define ISPH3A_AFCOEF198 (0x044)
3305+#define ISPH3A_AFCOEF1010 (0x048)
3306+
3307+#define ISPPRV_PCR (0x004)
3308+#define ISPPRV_HORZ_INFO (0x008)
3309+#define ISPPRV_VERT_INFO (0x00C)
3310+#define ISPPRV_RSDR_ADDR (0x010)
3311+#define ISPPRV_RADR_OFFSET (0x014)
3312+#define ISPPRV_DSDR_ADDR (0x018)
3313+#define ISPPRV_DRKF_OFFSET (0x01C)
3314+#define ISPPRV_WSDR_ADDR (0x020)
3315+#define ISPPRV_WADD_OFFSET (0x024)
3316+#define ISPPRV_AVE (0x028)
3317+#define ISPPRV_HMED (0x02C)
3318+#define ISPPRV_NF (0x030)
3319+#define ISPPRV_WB_DGAIN (0x034)
3320+#define ISPPRV_WBGAIN (0x038)
3321+#define ISPPRV_WBSEL (0x03C)
3322+#define ISPPRV_CFA (0x040)
3323+#define ISPPRV_BLKADJOFF (0x044)
3324+#define ISPPRV_RGB_MAT1 (0x048)
3325+#define ISPPRV_RGB_MAT2 (0x04C)
3326+#define ISPPRV_RGB_MAT3 (0x050)
3327+#define ISPPRV_RGB_MAT4 (0x054)
3328+#define ISPPRV_RGB_MAT5 (0x058)
3329+#define ISPPRV_RGB_OFF1 (0x05C)
3330+#define ISPPRV_RGB_OFF2 (0x060)
3331+#define ISPPRV_CSC0 (0x064)
3332+#define ISPPRV_CSC1 (0x068)
3333+#define ISPPRV_CSC2 (0x06C)
3334+#define ISPPRV_CSC_OFFSET (0x070)
3335+#define ISPPRV_CNT_BRT (0x074)
3336+#define ISPPRV_CSUP (0x078)
3337+#define ISPPRV_SETUP_YC (0x07C)
3338+#define ISPPRV_SET_TBL_ADDR (0x080)
3339+#define ISPPRV_SET_TBL_DATA (0x084)
3340+#define ISPPRV_CDC_THR0 (0x090)
3341+#define ISPPRV_CDC_THR1 (ISPPRV_CDC_THR0 + (0x4))
3342+#define ISPPRV_CDC_THR2 (ISPPRV_CDC_THR0 + (0x4) * 2)
3343+#define ISPPRV_CDC_THR3 (ISPPRV_CDC_THR0 + (0x4) * 3)
3344+
3345+#define ISPPRV_REDGAMMA_TABLE_ADDR 0x0000
3346+#define ISPPRV_GREENGAMMA_TABLE_ADDR 0x0400
3347+#define ISPPRV_BLUEGAMMA_TABLE_ADDR 0x0800
3348+#define ISPPRV_NF_TABLE_ADDR 0x0C00
3349+#define ISPPRV_YENH_TABLE_ADDR 0x1000
3350+#define ISPPRV_CFA_TABLE_ADDR 0x1400
3351+
3352+#define ISPPRV_MAXOUTPUT_WIDTH 1280
3353+#define ISPPRV_MAXOUTPUT_WIDTH_ES2 3300
3354+#define ISPRSZ_MIN_OUTPUT 64
3355+#define ISPRSZ_MAX_OUTPUT 3312
3356+
3357+/* Resizer module register offset */
3358+#define ISPRSZ_PID (0x000)
3359+#define ISPRSZ_PCR (0x004)
3360+#define ISPRSZ_CNT (0x008)
3361+#define ISPRSZ_OUT_SIZE (0x00C)
3362+#define ISPRSZ_IN_START (0x010)
3363+#define ISPRSZ_IN_SIZE (0x014)
3364+#define ISPRSZ_SDR_INADD (0x018)
3365+#define ISPRSZ_SDR_INOFF (0x01C)
3366+#define ISPRSZ_SDR_OUTADD (0x020)
3367+#define ISPRSZ_SDR_OUTOFF (0x024)
3368+#define ISPRSZ_HFILT10 (0x028)
3369+#define ISPRSZ_HFILT32 (0x02C)
3370+#define ISPRSZ_HFILT54 (0x030)
3371+#define ISPRSZ_HFILT76 (0x034)
3372+#define ISPRSZ_HFILT98 (0x038)
3373+#define ISPRSZ_HFILT1110 (0x03C)
3374+#define ISPRSZ_HFILT1312 (0x040)
3375+#define ISPRSZ_HFILT1514 (0x044)
3376+#define ISPRSZ_HFILT1716 (0x048)
3377+#define ISPRSZ_HFILT1918 (0x04C)
3378+#define ISPRSZ_HFILT2120 (0x050)
3379+#define ISPRSZ_HFILT2322 (0x054)
3380+#define ISPRSZ_HFILT2524 (0x058)
3381+#define ISPRSZ_HFILT2726 (0x05C)
3382+#define ISPRSZ_HFILT2928 (0x060)
3383+#define ISPRSZ_HFILT3130 (0x064)
3384+#define ISPRSZ_VFILT10 (0x068)
3385+#define ISPRSZ_VFILT32 (0x06C)
3386+#define ISPRSZ_VFILT54 (0x070)
3387+#define ISPRSZ_VFILT76 (0x074)
3388+#define ISPRSZ_VFILT98 (0x078)
3389+#define ISPRSZ_VFILT1110 (0x07C)
3390+#define ISPRSZ_VFILT1312 (0x080)
3391+#define ISPRSZ_VFILT1514 (0x084)
3392+#define ISPRSZ_VFILT1716 (0x088)
3393+#define ISPRSZ_VFILT1918 (0x08C)
3394+#define ISPRSZ_VFILT2120 (0x090)
3395+#define ISPRSZ_VFILT2322 (0x094)
3396+#define ISPRSZ_VFILT2524 (0x098)
3397+#define ISPRSZ_VFILT2726 (0x09C)
3398+#define ISPRSZ_VFILT2928 (0x0A0)
3399+#define ISPRSZ_VFILT3130 (0x0A4)
3400+#define ISPRSZ_YENH (0x0A8)
3401+
3402+/* MMU module registers */
3403+#define ISPMMU_REVISION (0x000)
3404+#define ISPMMU_SYSCONFIG (0x010)
3405+#define ISPMMU_SYSSTATUS (0x014)
3406+#define ISPMMU_IRQSTATUS (0x018)
3407+#define ISPMMU_IRQENABLE (0x01C)
3408+#define ISPMMU_WALKING_ST (0x040)
3409+#define ISPMMU_CNTL (0x044)
3410+#define ISPMMU_FAULT_AD (0x048)
3411+#define ISPMMU_TTB (0x04C)
3412+#define ISPMMU_LOCK (0x050)
3413+#define ISPMMU_LD_TLB (0x054)
3414+#define ISPMMU_CAM (0x058)
3415+#define ISPMMU_RAM (0x05C)
3416+#define ISPMMU_GFLUSH (0x060)
3417+#define ISPMMU_FLUSH_ENTRY (0x064)
3418+#define ISPMMU_READ_CAM (0x068)
3419+#define ISPMMU_READ_RAM (0x06c)
3420+#define ISPMMU_EMU_FAULT_AD (0x070)
3421+
3422+#define ISP_INT_CLR 0xFF113F11
3423+#define ISPPRV_PCR_EN 1
3424+#define ISPPRV_PCR_BUSY (1 << 1)
3425+#define ISPPRV_PCR_SOURCE (1 << 2)
3426+#define ISPPRV_PCR_ONESHOT (1 << 3)
3427+#define ISPPRV_PCR_WIDTH (1 << 4)
3428+#define ISPPRV_PCR_INVALAW (1 << 5)
3429+#define ISPPRV_PCR_DRKFEN (1 << 6)
3430+#define ISPPRV_PCR_DRKFCAP (1 << 7)
3431+#define ISPPRV_PCR_HMEDEN (1 << 8)
3432+#define ISPPRV_PCR_NFEN (1 << 9)
3433+#define ISPPRV_PCR_CFAEN (1 << 10)
3434+#define ISPPRV_PCR_CFAFMT_SHIFT 11
3435+#define ISPPRV_PCR_CFAFMT_MASK 0x7800
3436+#define ISPPRV_PCR_CFAFMT_BAYER (0 << 11)
3437+#define ISPPRV_PCR_CFAFMT_SONYVGA (1 << 11)
3438+#define ISPPRV_PCR_CFAFMT_RGBFOVEON (2 << 11)
3439+#define ISPPRV_PCR_CFAFMT_DNSPL (3 << 11)
3440+#define ISPPRV_PCR_CFAFMT_HONEYCOMB (4 << 11)
3441+#define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON (5 << 11)
3442+#define ISPPRV_PCR_YNENHEN (1 << 15)
3443+#define ISPPRV_PCR_SUPEN (1 << 16)
3444+#define ISPPRV_PCR_YCPOS_SHIFT 17
3445+#define ISPPRV_PCR_YCPOS_YCrYCb (0 << 17)
3446+#define ISPPRV_PCR_YCPOS_YCbYCr (1 << 17)
3447+#define ISPPRV_PCR_YCPOS_CbYCrY (2 << 17)
3448+#define ISPPRV_PCR_YCPOS_CrYCbY (3 << 17)
3449+#define ISPPRV_PCR_RSZPORT (1 << 19)
3450+#define ISPPRV_PCR_SDRPORT (1 << 20)
3451+#define ISPPRV_PCR_SCOMP_EN (1 << 21)
3452+#define ISPPRV_PCR_SCOMP_SFT_SHIFT (22)
3453+#define ISPPRV_PCR_SCOMP_SFT_MASK (~(7 << 22))
3454+#define ISPPRV_PCR_GAMMA_BYPASS (1 << 26)
3455+#define ISPPRV_PCR_DCOREN (1 << 27)
3456+#define ISPPRV_PCR_DCCOUP (1 << 28)
3457+#define ISPPRV_PCR_DRK_FAIL (1 << 31)
3458+
3459+#define ISPPRV_HORZ_INFO_EPH_SHIFT 0
3460+#define ISPPRV_HORZ_INFO_EPH_MASK 0x3fff
3461+#define ISPPRV_HORZ_INFO_SPH_SHIFT 16
3462+#define ISPPRV_HORZ_INFO_SPH_MASK 0x3fff0
3463+
3464+#define ISPPRV_VERT_INFO_ELV_SHIFT 0
3465+#define ISPPRV_VERT_INFO_ELV_MASK 0x3fff
3466+#define ISPPRV_VERT_INFO_SLV_SHIFT 16
3467+#define ISPPRV_VERT_INFO_SLV_MASK 0x3fff0
3468+
3469+#define ISPPRV_AVE_EVENDIST_SHIFT 2
3470+#define ISPPRV_AVE_EVENDIST_1 0x0
3471+#define ISPPRV_AVE_EVENDIST_2 0x1
3472+#define ISPPRV_AVE_EVENDIST_3 0x2
3473+#define ISPPRV_AVE_EVENDIST_4 0x3
3474+#define ISPPRV_AVE_ODDDIST_SHIFT 4
3475+#define ISPPRV_AVE_ODDDIST_1 0x0
3476+#define ISPPRV_AVE_ODDDIST_2 0x1
3477+#define ISPPRV_AVE_ODDDIST_3 0x2
3478+#define ISPPRV_AVE_ODDDIST_4 0x3
3479+
3480+#define ISPPRV_HMED_THRESHOLD_SHIFT 0
3481+#define ISPPRV_HMED_EVENDIST (1 << 8)
3482+#define ISPPRV_HMED_ODDDIST (1 << 9)
3483+
3484+#define ISPPRV_WBGAIN_COEF0_SHIFT 0
3485+#define ISPPRV_WBGAIN_COEF1_SHIFT 8
3486+#define ISPPRV_WBGAIN_COEF2_SHIFT 16
3487+#define ISPPRV_WBGAIN_COEF3_SHIFT 24
3488+
3489+#define ISPPRV_WBSEL_COEF0 0x0
3490+#define ISPPRV_WBSEL_COEF1 0x1
3491+#define ISPPRV_WBSEL_COEF2 0x2
3492+#define ISPPRV_WBSEL_COEF3 0x3
3493+
3494+#define ISPPRV_WBSEL_N0_0_SHIFT 0
3495+#define ISPPRV_WBSEL_N0_1_SHIFT 2
3496+#define ISPPRV_WBSEL_N0_2_SHIFT 4
3497+#define ISPPRV_WBSEL_N0_3_SHIFT 6
3498+#define ISPPRV_WBSEL_N1_0_SHIFT 8
3499+#define ISPPRV_WBSEL_N1_1_SHIFT 10
3500+#define ISPPRV_WBSEL_N1_2_SHIFT 12
3501+#define ISPPRV_WBSEL_N1_3_SHIFT 14
3502+#define ISPPRV_WBSEL_N2_0_SHIFT 16
3503+#define ISPPRV_WBSEL_N2_1_SHIFT 18
3504+#define ISPPRV_WBSEL_N2_2_SHIFT 20
3505+#define ISPPRV_WBSEL_N2_3_SHIFT 22
3506+#define ISPPRV_WBSEL_N3_0_SHIFT 24
3507+#define ISPPRV_WBSEL_N3_1_SHIFT 26
3508+#define ISPPRV_WBSEL_N3_2_SHIFT 28
3509+#define ISPPRV_WBSEL_N3_3_SHIFT 30
3510+
3511+#define ISPPRV_CFA_GRADTH_HOR_SHIFT 0
3512+#define ISPPRV_CFA_GRADTH_VER_SHIFT 8
3513+
3514+#define ISPPRV_BLKADJOFF_B_SHIFT 0
3515+#define ISPPRV_BLKADJOFF_G_SHIFT 8
3516+#define ISPPRV_BLKADJOFF_R_SHIFT 16
3517+
3518+#define ISPPRV_RGB_MAT1_MTX_RR_SHIFT 0
3519+#define ISPPRV_RGB_MAT1_MTX_GR_SHIFT 16
3520+
3521+#define ISPPRV_RGB_MAT2_MTX_BR_SHIFT 0
3522+#define ISPPRV_RGB_MAT2_MTX_RG_SHIFT 16
3523+
3524+#define ISPPRV_RGB_MAT3_MTX_GG_SHIFT 0
3525+#define ISPPRV_RGB_MAT3_MTX_BG_SHIFT 16
3526+
3527+#define ISPPRV_RGB_MAT4_MTX_RB_SHIFT 0
3528+#define ISPPRV_RGB_MAT4_MTX_GB_SHIFT 16
3529+
3530+#define ISPPRV_RGB_MAT5_MTX_BB_SHIFT 0
3531+
3532+#define ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT 0
3533+#define ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT 16
3534+
3535+#define ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT 0
3536+
3537+#define ISPPRV_CSC0_RY_SHIFT 0
3538+#define ISPPRV_CSC0_GY_SHIFT 10
3539+#define ISPPRV_CSC0_BY_SHIFT 20
3540+
3541+#define ISPPRV_CSC1_RCB_SHIFT 0
3542+#define ISPPRV_CSC1_GCB_SHIFT 10
3543+#define ISPPRV_CSC1_BCB_SHIFT 20
3544+
3545+#define ISPPRV_CSC2_RCR_SHIFT 0
3546+#define ISPPRV_CSC2_GCR_SHIFT 10
3547+#define ISPPRV_CSC2_BCR_SHIFT 20
3548+
3549+#define ISPPRV_CSC_OFFSET_CR_SHIFT 0
3550+#define ISPPRV_CSC_OFFSET_CB_SHIFT 8
3551+#define ISPPRV_CSC_OFFSET_Y_SHIFT 16
3552+
3553+#define ISPPRV_CNT_BRT_BRT_SHIFT 0
3554+#define ISPPRV_CNT_BRT_CNT_SHIFT 8
3555+
3556+#define ISPPRV_CONTRAST_MAX 0x10
3557+#define ISPPRV_CONTRAST_MIN 0xFF
3558+#define ISPPRV_BRIGHT_MIN 0x00
3559+#define ISPPRV_BRIGHT_MAX 0xFF
3560+
3561+#define ISPPRV_CSUP_CSUPG_SHIFT 0
3562+#define ISPPRV_CSUP_THRES_SHIFT 8
3563+#define ISPPRV_CSUP_HPYF_SHIFT 16
3564+
3565+#define ISPPRV_SETUP_YC_MINC_SHIFT 0
3566+#define ISPPRV_SETUP_YC_MAXC_SHIFT 8
3567+#define ISPPRV_SETUP_YC_MINY_SHIFT 16
3568+#define ISPPRV_SETUP_YC_MAXY_SHIFT 24
3569+#define ISPPRV_YC_MAX 0xFF
3570+#define ISPPRV_YC_MIN 0x0
3571+
3572+/* Define bit fields within selected registers */
3573+#define ISP_REVISION_SHIFT 0
3574+
3575+#define ISP_SYSCONFIG_AUTOIDLE 0
3576+#define ISP_SYSCONFIG_SOFTRESET (1 << 1)
3577+#define ISP_SYSCONFIG_MIDLEMODE_SHIFT 12
3578+#define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY 0x0
3579+#define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY 0x1
3580+#define ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY 0x2
3581+
3582+#define ISP_SYSSTATUS_RESETDONE 0
3583+
3584+#define IRQ0ENABLE_CSIA_IRQ 1
3585+#define IRQ0ENABLE_CSIA_LC1_IRQ (1 << 1)
3586+#define IRQ0ENABLE_CSIA_LC2_IRQ (1 << 2)
3587+#define IRQ0ENABLE_CSIA_LC3_IRQ (1 << 3)
3588+#define IRQ0ENABLE_CSIB_IRQ (1 << 4)
3589+#define IRQ0ENABLE_CSIB_LC1_IRQ (1 << 5)
3590+#define IRQ0ENABLE_CSIB_LC2_IRQ (1 << 6)
3591+#define IRQ0ENABLE_CSIB_LC3_IRQ (1 << 7)
3592+#define IRQ0ENABLE_CCDC_VD0_IRQ (1 << 8)
3593+#define IRQ0ENABLE_CCDC_VD1_IRQ (1 << 9)
3594+#define IRQ0ENABLE_CCDC_VD2_IRQ (1 << 10)
3595+#define IRQ0ENABLE_CCDC_ERR_IRQ (1 << 11)
3596+#define IRQ0ENABLE_H3A_AF_DONE_IRQ (1 << 12)
3597+#define IRQ0ENABLE_H3A_AWB_DONE_IRQ (1 << 13)
3598+#define IRQ0ENABLE_HIST_DONE_IRQ (1 << 16)
3599+#define IRQ0ENABLE_CCDC_LSC_DONE_IRQ (1 << 17)
3600+#define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ (1 << 18)
3601+#define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ (1 << 19)
3602+#define IRQ0ENABLE_PRV_DONE_IRQ (1 << 20)
3603+#define IRQ0ENABLE_RSZ_DONE_IRQ (1 << 24)
3604+#define IRQ0ENABLE_OVF_IRQ (1 << 25)
3605+#define IRQ0ENABLE_PING_IRQ (1 << 26)
3606+#define IRQ0ENABLE_PONG_IRQ (1 << 27)
3607+#define IRQ0ENABLE_MMU_ERR_IRQ (1 << 28)
3608+#define IRQ0ENABLE_OCP_ERR_IRQ (1 << 29)
3609+#define IRQ0ENABLE_SEC_ERR_IRQ (1 << 30)
3610+#define IRQ0ENABLE_HS_VS_IRQ (1 << 31)
3611+
3612+#define IRQ0STATUS_CSIA_IRQ 1
3613+#define IRQ0STATUS_CSIA_LC1_IRQ (1 << 1)
3614+#define IRQ0STATUS_CSIA_LC2_IRQ (1 << 2)
3615+#define IRQ0STATUS_CSIA_LC3_IRQ (1 << 3)
3616+#define IRQ0STATUS_CSIB_IRQ (1 << 4)
3617+#define IRQ0STATUS_CSIB_LC1_IRQ (1 << 5)
3618+#define IRQ0STATUS_CSIB_LC2_IRQ (1 << 6)
3619+#define IRQ0STATUS_CSIB_LC3_IRQ (1 << 7)
3620+#define IRQ0STATUS_CCDC_VD0_IRQ (1 << 8)
3621+#define IRQ0STATUS_CCDC_VD1_IRQ (1 << 9)
3622+#define IRQ0STATUS_CCDC_VD2_IRQ (1 << 10)
3623+#define IRQ0STATUS_CCDC_ERR_IRQ (1 << 11)
3624+#define IRQ0STATUS_H3A_AF_DONE_IRQ (1 << 12)
3625+#define IRQ0STATUS_H3A_AWB_DONE_IRQ (1 << 13)
3626+#define IRQ0STATUS_HIST_DONE_IRQ (1 << 16)
3627+#define IRQ0STATUS_PRV_DONE_IRQ (1 << 20)
3628+#define IRQ0STATUS_RSZ_DONE_IRQ (1 << 24)
3629+#define IRQ0STATUS_OVF_IRQ (1 << 25)
3630+#define IRQ0STATUS_PING_IRQ (1 << 26)
3631+#define IRQ0STATUS_PONG_IRQ (1 << 27)
3632+#define IRQ0STATUS_MMU_ERR_IRQ (1 << 28)
3633+#define IRQ0STATUS_OCP_ERR_IRQ (1 << 29)
3634+#define IRQ0STATUS_SEC_ERR_IRQ (1 << 30)
3635+#define IRQ0STATUS_HS_VS_IRQ (1 << 31)
3636+
3637+#define TCTRL_GRESET_LEN 0
3638+
3639+#define TCTRL_PSTRB_REPLAY_DELAY 0
3640+#define TCTRL_PSTRB_REPLAY_COUNTER_SHIFT 25
3641+
3642+#define ISPCTRL_PAR_SER_CLK_SEL_PARALLEL 0x0
3643+#define ISPCTRL_PAR_SER_CLK_SEL_CSIA 0x1
3644+#define ISPCTRL_PAR_SER_CLK_SEL_CSIB 0x2
3645+#define ISPCTRL_PAR_SER_CLK_SEL_MASK 0xFFFFFFFC
3646+
3647+#define ISPCTRL_PAR_BRIDGE_SHIFT 2
3648+#define ISPCTRL_PAR_BRIDGE_DISABLE (0x0 << 2)
3649+#define ISPCTRL_PAR_BRIDGE_LENDIAN (0x2 << 2)
3650+#define ISPCTRL_PAR_BRIDGE_BENDIAN (0x3 << 2)
3651+
3652+#define ISPCTRL_PAR_CLK_POL_SHIFT 4
3653+#define ISPCTRL_PAR_CLK_POL_INV (1 << 4)
3654+#define ISPCTRL_PING_PONG_EN (1 << 5)
3655+#define ISPCTRL_SHIFT_SHIFT 6
3656+#define ISPCTRL_SHIFT_0 (0x0 << 6)
3657+#define ISPCTRL_SHIFT_2 (0x1 << 6)
3658+#define ISPCTRL_SHIFT_4 (0x2 << 6)
3659+#define ISPCTRL_SHIFT_MASK (~(0x3 << 6))
3660+
3661+#define ISPCTRL_CCDC_CLK_EN (1 << 8)
3662+#define ISPCTRL_SCMP_CLK_EN (1 << 9)
3663+#define ISPCTRL_H3A_CLK_EN (1 << 10)
3664+#define ISPCTRL_HIST_CLK_EN (1 << 11)
3665+#define ISPCTRL_PREV_CLK_EN (1 << 12)
3666+#define ISPCTRL_RSZ_CLK_EN (1 << 13)
3667+#define ISPCTRL_SYNC_DETECT_SHIFT 14
3668+#define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT)
3669+#define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT)
3670+#define ISPCTRL_SYNC_DETECT_VSFALL (0x2 << ISPCTRL_SYNC_DETECT_SHIFT)
3671+#define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
3672+#define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
3673+
3674+#define ISPCTRL_CCDC_RAM_EN (1 << 16)
3675+#define ISPCTRL_PREV_RAM_EN (1 << 17)
3676+#define ISPCTRL_SBL_RD_RAM_EN (1 << 18)
3677+#define ISPCTRL_SBL_WR1_RAM_EN (1 << 19)
3678+#define ISPCTRL_SBL_WR0_RAM_EN (1 << 20)
3679+#define ISPCTRL_SBL_AUTOIDLE (1 << 21)
3680+#define ISPCTRL_SBL_SHARED_RPORTB (1 << 28)
3681+#define ISPCTRL_JPEG_FLUSH (1 << 30)
3682+#define ISPCTRL_CCDC_FLUSH (1 << 31)
3683+
3684+#define ISPSECURE_SECUREMODE 0
3685+
3686+#define ISPTCTRL_CTRL_DIV_LOW 0x0
3687+#define ISPTCTRL_CTRL_DIV_HIGH 0x1
3688+#define ISPTCTRL_CTRL_DIV_BYPASS 0x1F
3689+
3690+#define ISPTCTRL_CTRL_DIVA_SHIFT 0
3691+#define ISPTCTRL_CTRL_DIVA_MASK (0x1F << ISPTCTRL_CTRL_DIVA_SHIFT)
3692+
3693+#define ISPTCTRL_CTRL_DIVB_SHIFT 5
3694+#define ISPTCTRL_CTRL_DIVB_MASK (0x1F << ISPTCTRL_CTRL_DIVB_SHIFT)
3695+
3696+#define ISPTCTRL_CTRL_DIVC_SHIFT 10
3697+#define ISPTCTRL_CTRL_DIVC_NOCLOCK (0x0 << 10)
3698+
3699+#define ISPTCTRL_CTRL_SHUTEN (1 << 21)
3700+#define ISPTCTRL_CTRL_PSTRBEN (1 << 22)
3701+#define ISPTCTRL_CTRL_STRBEN (1 << 23)
3702+#define ISPTCTRL_CTRL_SHUTPOL (1 << 24)
3703+#define ISPTCTRL_CTRL_STRBPSTRBPOL (1 << 26)
3704+
3705+#define ISPTCTRL_CTRL_INSEL_SHIFT 27
3706+#define ISPTCTRL_CTRL_INSEL_PARALLEL (0x0 << 27)
3707+#define ISPTCTRL_CTRL_INSEL_CSIA (0x1 << 27)
3708+#define ISPTCTRL_CTRL_INSEL_CSIB (0x2 << 27)
3709+
3710+#define ISPTCTRL_CTRL_GRESETEn (1 << 29)
3711+#define ISPTCTRL_CTRL_GRESETPOL (1 << 30)
3712+#define ISPTCTRL_CTRL_GRESETDIR (1 << 31)
3713+
3714+#define ISPTCTRL_FRAME_SHUT_SHIFT 0
3715+#define ISPTCTRL_FRAME_PSTRB_SHIFT 6
3716+#define ISPTCTRL_FRAME_STRB_SHIFT 12
3717+
3718+#define ISPCCDC_PID_PREV_SHIFT 0
3719+#define ISPCCDC_PID_CID_SHIFT 8
3720+#define ISPCCDC_PID_TID_SHIFT 16
3721+
3722+#define ISPCCDC_PCR_EN 1
3723+#define ISPCCDC_PCR_BUSY (1 << 1)
3724+
3725+#define ISPCCDC_SYN_MODE_VDHDOUT 0x1
3726+#define ISPCCDC_SYN_MODE_FLDOUT (1 << 1)
3727+#define ISPCCDC_SYN_MODE_VDPOL (1 << 2)
3728+#define ISPCCDC_SYN_MODE_HDPOL (1 << 3)
3729+#define ISPCCDC_SYN_MODE_FLDPOL (1 << 4)
3730+#define ISPCCDC_SYN_MODE_EXWEN (1 << 5)
3731+#define ISPCCDC_SYN_MODE_DATAPOL (1 << 6)
3732+#define ISPCCDC_SYN_MODE_FLDMODE (1 << 7)
3733+#define ISPCCDC_SYN_MODE_DATSIZ_MASK 0xFFFFF8FF
3734+#define ISPCCDC_SYN_MODE_DATSIZ_8_16 (0x0 << 8)
3735+#define ISPCCDC_SYN_MODE_DATSIZ_12 (0x4 << 8)
3736+#define ISPCCDC_SYN_MODE_DATSIZ_11 (0x5 << 8)
3737+#define ISPCCDC_SYN_MODE_DATSIZ_10 (0x6 << 8)
3738+#define ISPCCDC_SYN_MODE_DATSIZ_8 (0x7 << 8)
3739+#define ISPCCDC_SYN_MODE_PACK8 (1 << 11)
3740+#define ISPCCDC_SYN_MODE_INPMOD_MASK 0xFFFFCFFF
3741+#define ISPCCDC_SYN_MODE_INPMOD_RAW (0 << 12)
3742+#define ISPCCDC_SYN_MODE_INPMOD_YCBCR16 (1 << 12)
3743+#define ISPCCDC_SYN_MODE_INPMOD_YCBCR8 (2 << 12)
3744+#define ISPCCDC_SYN_MODE_LPF (1 << 14)
3745+#define ISPCCDC_SYN_MODE_FLDSTAT (1 << 15)
3746+#define ISPCCDC_SYN_MODE_VDHDEN (1 << 16)
3747+#define ISPCCDC_SYN_MODE_WEN (1 << 17)
3748+#define ISPCCDC_SYN_MODE_VP2SDR (1 << 18)
3749+#define ISPCCDC_SYN_MODE_SDR2RSZ (1 << 19)
3750+
3751+#define ISPCCDC_HD_VD_WID_VDW_SHIFT 0
3752+#define ISPCCDC_HD_VD_WID_HDW_SHIFT 16
3753+
3754+#define ISPCCDC_PIX_LINES_HLPRF_SHIFT 0
3755+#define ISPCCDC_PIX_LINES_PPLN_SHIFT 16
3756+
3757+#define ISPCCDC_HORZ_INFO_NPH_SHIFT 0
3758+#define ISPCCDC_HORZ_INFO_NPH_MASK 0xFFFF8000
3759+#define ISPCCDC_HORZ_INFO_SPH_MASK 0x1000FFFF
3760+#define ISPCCDC_HORZ_INFO_SPH_SHIFT 16
3761+
3762+#define ISPCCDC_VERT_START_SLV0_SHIFT 16
3763+#define ISPCCDC_VERT_START_SLV0_MASK 0x1000FFFF
3764+#define ISPCCDC_VERT_START_SLV1_SHIFT 0
3765+
3766+#define ISPCCDC_VERT_LINES_NLV_MASK 0xFFFF8000
3767+#define ISPCCDC_VERT_LINES_NLV_SHIFT 0
3768+
3769+#define ISPCCDC_CULLING_CULV_SHIFT 0
3770+#define ISPCCDC_CULLING_CULHODD_SHIFT 16
3771+#define ISPCCDC_CULLING_CULHEVN_SHIFT 24
3772+
3773+#define ISPCCDC_HSIZE_OFF_SHIFT 0
3774+
3775+#define ISPCCDC_SDOFST_FINV (1 << 14)
3776+#define ISPCCDC_SDOFST_FOFST_1L 0
3777+#define ISPCCDC_SDOFST_FOFST_4L (3 << 12)
3778+#define ISPCCDC_SDOFST_LOFST3_SHIFT 0
3779+#define ISPCCDC_SDOFST_LOFST2_SHIFT 3
3780+#define ISPCCDC_SDOFST_LOFST1_SHIFT 6
3781+#define ISPCCDC_SDOFST_LOFST0_SHIFT 9
3782+#define EVENEVEN 1
3783+#define ODDEVEN 2
3784+#define EVENODD 3
3785+#define ODDODD 4
3786+
3787+#define ISPCCDC_CLAMP_OBGAIN_SHIFT 0
3788+#define ISPCCDC_CLAMP_OBST_SHIFT 10
3789+#define ISPCCDC_CLAMP_OBSLN_SHIFT 25
3790+#define ISPCCDC_CLAMP_OBSLEN_SHIFT 28
3791+#define ISPCCDC_CLAMP_CLAMPEN (1 << 31)
3792+
3793+#define ISPCCDC_COLPTN_R_Ye 0x0
3794+#define ISPCCDC_COLPTN_Gr_Cy 0x1
3795+#define ISPCCDC_COLPTN_Gb_G 0x2
3796+#define ISPCCDC_COLPTN_B_Mg 0x3
3797+#define ISPCCDC_COLPTN_CP0PLC0_SHIFT 0
3798+#define ISPCCDC_COLPTN_CP0PLC1_SHIFT 2
3799+#define ISPCCDC_COLPTN_CP0PLC2_SHIFT 4
3800+#define ISPCCDC_COLPTN_CP0PLC3_SHIFT 6
3801+#define ISPCCDC_COLPTN_CP1PLC0_SHIFT 8
3802+#define ISPCCDC_COLPTN_CP1PLC1_SHIFT 10
3803+#define ISPCCDC_COLPTN_CP1PLC2_SHIFT 12
3804+#define ISPCCDC_COLPTN_CP1PLC3_SHIFT 14
3805+#define ISPCCDC_COLPTN_CP2PLC0_SHIFT 16
3806+#define ISPCCDC_COLPTN_CP2PLC1_SHIFT 18
3807+#define ISPCCDC_COLPTN_CP2PLC2_SHIFT 20
3808+#define ISPCCDC_COLPTN_CP2PLC3_SHIFT 22
3809+#define ISPCCDC_COLPTN_CP3PLC0_SHIFT 24
3810+#define ISPCCDC_COLPTN_CP3PLC1_SHIFT 26
3811+#define ISPCCDC_COLPTN_CP3PLC2_SHIFT 28
3812+#define ISPCCDC_COLPTN_CP3PLC3_SHIFT 30
3813+
3814+#define ISPCCDC_BLKCMP_B_MG_SHIFT 0
3815+#define ISPCCDC_BLKCMP_GB_G_SHIFT 8
3816+#define ISPCCDC_BLKCMP_GR_CY_SHIFT 16
3817+#define ISPCCDC_BLKCMP_R_YE_SHIFT 24
3818+
3819+#define ISPCCDC_FPC_FPNUM_SHIFT 0
3820+#define ISPCCDC_FPC_FPCEN (1 << 15)
3821+#define ISPCCDC_FPC_FPERR (1 << 16)
3822+
3823+#define ISPCCDC_VDINT_1_SHIFT 0
3824+#define ISPCCDC_VDINT_0_SHIFT 16
3825+#define ISPCCDC_VDINT_0_MASK 0x7FFF
3826+#define ISPCCDC_VDINT_1_MASK 0x7FFF
3827+
3828+#define ISPCCDC_ALAW_GWDI_SHIFT 0
3829+#define ISPCCDC_ALAW_CCDTBL (1 << 3)
3830+
3831+#define ISPCCDC_REC656IF_R656ON 1
3832+#define ISPCCDC_REC656IF_ECCFVH (1 << 1)
3833+
3834+#define ISPCCDC_CFG_BW656 (1 << 5)
3835+#define ISPCCDC_CFG_FIDMD_SHIFT 6
3836+#define ISPCCDC_CFG_WENLOG (1 << 8)
3837+#define ISPCCDC_CFG_WENLOG_AND (0 << 8)
3838+#define ISPCCDC_CFG_WENLOG_OR (1 << 8)
3839+#define ISPCCDC_CFG_Y8POS (1 << 11)
3840+#define ISPCCDC_CFG_BSWD (1 << 12)
3841+#define ISPCCDC_CFG_MSBINVI (1 << 13)
3842+#define ISPCCDC_CFG_VDLC (1 << 15)
3843+
3844+#define ISPCCDC_FMTCFG_FMTEN 0x1
3845+#define ISPCCDC_FMTCFG_LNALT (1 << 1)
3846+#define ISPCCDC_FMTCFG_LNUM_SHIFT 2
3847+#define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT 4
3848+#define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT 8
3849+#define ISPCCDC_FMTCFG_VPIN_MASK 0xFFFF8000
3850+#define ISPCCDC_FMTCFG_VPIN_12_3 (0x3 << 12)
3851+#define ISPCCDC_FMTCFG_VPIN_11_2 (0x4 << 12)
3852+#define ISPCCDC_FMTCFG_VPIN_10_1 (0x5 << 12)
3853+#define ISPCCDC_FMTCFG_VPIN_9_0 (0x6 << 12)
3854+#define ISPCCDC_FMTCFG_VPEN (1 << 15)
3855+
3856+#define ISPCCDC_FMTCF_VPIF_FRQ_MASK 0xFFF8FFFF
3857+#define ISPCCDC_FMTCF_VPIF_FRQ_BY2 (0x0 << 16)
3858+#define ISPCCDC_FMTCF_VPIF_FRQ_BY3 (0x1 << 16)
3859+#define ISPCCDC_FMTCF_VPIF_FRQ_BY4 (0x2 << 16)
3860+#define ISPCCDC_FMTCF_VPIF_FRQ_BY5 (0x3 << 16)
3861+#define ISPCCDC_FMTCF_VPIF_FRQ_BY6 (0x4 << 16)
3862+
3863+#define ISPCCDC_FMT_HORZ_FMTLNH_SHIFT 0
3864+#define ISPCCDC_FMT_HORZ_FMTSPH_SHIFT 16
3865+
3866+#define ISPCCDC_FMT_VERT_FMTLNV_SHIFT 0
3867+#define ISPCCDC_FMT_VERT_FMTSLV_SHIFT 16
3868+
3869+#define ISPCCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF0000
3870+#define ISPCCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF
3871+
3872+#define ISPCCDC_FMT_VERT_FMTSLV_MASK 0x1FFF0000
3873+#define ISPCCDC_FMT_VERT_FMTLNV_MASK 0x1FFF
3874+
3875+#define ISPCCDC_VP_OUT_HORZ_ST_SHIFT 0
3876+#define ISPCCDC_VP_OUT_HORZ_NUM_SHIFT 4
3877+#define ISPCCDC_VP_OUT_VERT_NUM_SHIFT 17
3878+
3879+#define ISPRSZ_PID_PREV_SHIFT 0
3880+#define ISPRSZ_PID_CID_SHIFT 8
3881+#define ISPRSZ_PID_TID_SHIFT 16
3882+
3883+#define ISPRSZ_PCR_ENABLE 0x5
3884+#define ISPRSZ_PCR_BUSY (1 << 1)
3885+
3886+#define ISPRSZ_CNT_HRSZ_SHIFT 0
3887+#define ISPRSZ_CNT_HRSZ_MASK 0x3FF
3888+#define ISPRSZ_CNT_VRSZ_SHIFT 10
3889+#define ISPRSZ_CNT_VRSZ_MASK 0xFFC00
3890+#define ISPRSZ_CNT_HSTPH_SHIFT 20
3891+#define ISPRSZ_CNT_HSTPH_MASK 0x700000
3892+#define ISPRSZ_CNT_VSTPH_SHIFT 23
3893+#define ISPRSZ_CNT_VSTPH_MASK 0x3800000
3894+#define ISPRSZ_CNT_CBILIN_MASK 0x20000000
3895+#define ISPRSZ_CNT_INPTYP_MASK 0x08000000
3896+#define ISPRSZ_CNT_PIXFMT_MASK 0x04000000
3897+#define ISPRSZ_CNT_YCPOS (1 << 26)
3898+#define ISPRSZ_CNT_INPTYP (1 << 27)
3899+#define ISPRSZ_CNT_INPSRC (1 << 28)
3900+#define ISPRSZ_CNT_CBILIN (1 << 29)
3901+
3902+#define ISPRSZ_OUT_SIZE_HORZ_SHIFT 0
3903+#define ISPRSZ_OUT_SIZE_HORZ_MASK 0x7FF
3904+#define ISPRSZ_OUT_SIZE_VERT_SHIFT 16
3905+#define ISPRSZ_OUT_SIZE_VERT_MASK 0x7FF0000
3906+
3907+
3908+#define ISPRSZ_IN_START_HORZ_ST_SHIFT 0
3909+#define ISPRSZ_IN_START_HORZ_ST_MASK 0x1FFF
3910+#define ISPRSZ_IN_START_VERT_ST_SHIFT 16
3911+#define ISPRSZ_IN_START_VERT_ST_MASK 0x1FFF0000
3912+
3913+
3914+#define ISPRSZ_IN_SIZE_HORZ_SHIFT 0
3915+#define ISPRSZ_IN_SIZE_HORZ_MASK 0x1FFF
3916+#define ISPRSZ_IN_SIZE_VERT_SHIFT 16
3917+#define ISPRSZ_IN_SIZE_VERT_MASK 0x1FFF0000
3918+
3919+#define ISPRSZ_SDR_INADD_ADDR_SHIFT 0
3920+#define ISPRSZ_SDR_INADD_ADDR_MASK 0xFFFFFFFF
3921+
3922+#define ISPRSZ_SDR_INOFF_OFFSET_SHIFT 0
3923+#define ISPRSZ_SDR_INOFF_OFFSET_MASK 0xFFFF
3924+
3925+#define ISPRSZ_SDR_OUTADD_ADDR_SHIFT 0
3926+#define ISPRSZ_SDR_OUTADD_ADDR_MASK 0xFFFFFFFF
3927+
3928+
3929+#define ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT 0
3930+#define ISPRSZ_SDR_OUTOFF_OFFSET_MASK 0xFFFF
3931+
3932+#define ISPRSZ_HFILT10_COEF0_SHIFT 0
3933+#define ISPRSZ_HFILT10_COEF0_MASK 0x3FF
3934+#define ISPRSZ_HFILT10_COEF1_SHIFT 16
3935+#define ISPRSZ_HFILT10_COEF1_MASK 0x3FF0000
3936+
3937+#define ISPRSZ_HFILT32_COEF2_SHIFT 0
3938+#define ISPRSZ_HFILT32_COEF2_MASK 0x3FF
3939+#define ISPRSZ_HFILT32_COEF3_SHIFT 16
3940+#define ISPRSZ_HFILT32_COEF3_MASK 0x3FF0000
3941+
3942+#define ISPRSZ_HFILT54_COEF4_SHIFT 0
3943+#define ISPRSZ_HFILT54_COEF4_MASK 0x3FF
3944+#define ISPRSZ_HFILT54_COEF5_SHIFT 16
3945+#define ISPRSZ_HFILT54_COEF5_MASK 0x3FF0000
3946+
3947+#define ISPRSZ_HFILT76_COEFF6_SHIFT 0
3948+#define ISPRSZ_HFILT76_COEFF6_MASK 0x3FF
3949+#define ISPRSZ_HFILT76_COEFF7_SHIFT 16
3950+#define ISPRSZ_HFILT76_COEFF7_MASK 0x3FF0000
3951+
3952+#define ISPRSZ_HFILT98_COEFF8_SHIFT 0
3953+#define ISPRSZ_HFILT98_COEFF8_MASK 0x3FF
3954+#define ISPRSZ_HFILT98_COEFF9_SHIFT 16
3955+#define ISPRSZ_HFILT98_COEFF9_MASK 0x3FF0000
3956+
3957+#define ISPRSZ_HFILT1110_COEF10_SHIFT 0
3958+#define ISPRSZ_HFILT1110_COEF10_MASK 0x3FF
3959+#define ISPRSZ_HFILT1110_COEF11_SHIFT 16
3960+#define ISPRSZ_HFILT1110_COEF11_MASK 0x3FF0000
3961+
3962+#define ISPRSZ_HFILT1312_COEFF12_SHIFT 0
3963+#define ISPRSZ_HFILT1312_COEFF12_MASK 0x3FF
3964+#define ISPRSZ_HFILT1312_COEFF13_SHIFT 16
3965+#define ISPRSZ_HFILT1312_COEFF13_MASK 0x3FF0000
3966+
3967+#define ISPRSZ_HFILT1514_COEFF14_SHIFT 0
3968+#define ISPRSZ_HFILT1514_COEFF14_MASK 0x3FF
3969+#define ISPRSZ_HFILT1514_COEFF15_SHIFT 16
3970+#define ISPRSZ_HFILT1514_COEFF15_MASK 0x3FF0000
3971+
3972+#define ISPRSZ_HFILT1716_COEF16_SHIFT 0
3973+#define ISPRSZ_HFILT1716_COEF16_MASK 0x3FF
3974+#define ISPRSZ_HFILT1716_COEF17_SHIFT 16
3975+#define ISPRSZ_HFILT1716_COEF17_MASK 0x3FF0000
3976+
3977+#define ISPRSZ_HFILT1918_COEF18_SHIFT 0
3978+#define ISPRSZ_HFILT1918_COEF18_MASK 0x3FF
3979+#define ISPRSZ_HFILT1918_COEF19_SHIFT 16
3980+#define ISPRSZ_HFILT1918_COEF19_MASK 0x3FF0000
3981+
3982+#define ISPRSZ_HFILT2120_COEF20_SHIFT 0
3983+#define ISPRSZ_HFILT2120_COEF20_MASK 0x3FF
3984+#define ISPRSZ_HFILT2120_COEF21_SHIFT 16
3985+#define ISPRSZ_HFILT2120_COEF21_MASK 0x3FF0000
3986+
3987+#define ISPRSZ_HFILT2322_COEF22_SHIFT 0
3988+#define ISPRSZ_HFILT2322_COEF22_MASK 0x3FF
3989+#define ISPRSZ_HFILT2322_COEF23_SHIFT 16
3990+#define ISPRSZ_HFILT2322_COEF23_MASK 0x3FF0000
3991+
3992+#define ISPRSZ_HFILT2524_COEF24_SHIFT 0
3993+#define ISPRSZ_HFILT2524_COEF24_MASK 0x3FF
3994+#define ISPRSZ_HFILT2524_COEF25_SHIFT 16
3995+#define ISPRSZ_HFILT2524_COEF25_MASK 0x3FF0000
3996+
3997+#define ISPRSZ_HFILT2726_COEF26_SHIFT 0
3998+#define ISPRSZ_HFILT2726_COEF26_MASK 0x3FF
3999+#define ISPRSZ_HFILT2726_COEF27_SHIFT 16
4000+#define ISPRSZ_HFILT2726_COEF27_MASK 0x3FF0000
4001+
4002+#define ISPRSZ_HFILT2928_COEF28_SHIFT 0
4003+#define ISPRSZ_HFILT2928_COEF28_MASK 0x3FF
4004+#define ISPRSZ_HFILT2928_COEF29_SHIFT 16
4005+#define ISPRSZ_HFILT2928_COEF29_MASK 0x3FF0000
4006+
4007+#define ISPRSZ_HFILT3130_COEF30_SHIFT 0
4008+#define ISPRSZ_HFILT3130_COEF30_MASK 0x3FF
4009+#define ISPRSZ_HFILT3130_COEF31_SHIFT 16
4010+#define ISPRSZ_HFILT3130_COEF31_MASK 0x3FF0000
4011+
4012+#define ISPRSZ_VFILT10_COEF0_SHIFT 0
4013+#define ISPRSZ_VFILT10_COEF0_MASK 0x3FF
4014+#define ISPRSZ_VFILT10_COEF1_SHIFT 16
4015+#define ISPRSZ_VFILT10_COEF1_MASK 0x3FF0000
4016+
4017+#define ISPRSZ_VFILT32_COEF2_SHIFT 0
4018+#define ISPRSZ_VFILT32_COEF2_MASK 0x3FF
4019+#define ISPRSZ_VFILT32_COEF3_SHIFT 16
4020+#define ISPRSZ_VFILT32_COEF3_MASK 0x3FF0000
4021+
4022+#define ISPRSZ_VFILT54_COEF4_SHIFT 0
4023+#define ISPRSZ_VFILT54_COEF4_MASK 0x3FF
4024+#define ISPRSZ_VFILT54_COEF5_SHIFT 16
4025+#define ISPRSZ_VFILT54_COEF5_MASK 0x3FF0000
4026+
4027+#define ISPRSZ_VFILT76_COEFF6_SHIFT 0
4028+#define ISPRSZ_VFILT76_COEFF6_MASK 0x3FF
4029+#define ISPRSZ_VFILT76_COEFF7_SHIFT 16
4030+#define ISPRSZ_VFILT76_COEFF7_MASK 0x3FF0000
4031+
4032+#define ISPRSZ_VFILT98_COEFF8_SHIFT 0
4033+#define ISPRSZ_VFILT98_COEFF8_MASK 0x3FF
4034+#define ISPRSZ_VFILT98_COEFF9_SHIFT 16
4035+#define ISPRSZ_VFILT98_COEFF9_MASK 0x3FF0000
4036+
4037+#define ISPRSZ_VFILT1110_COEF10_SHIFT 0
4038+#define ISPRSZ_VFILT1110_COEF10_MASK 0x3FF
4039+#define ISPRSZ_VFILT1110_COEF11_SHIFT 16
4040+#define ISPRSZ_VFILT1110_COEF11_MASK 0x3FF0000
4041+
4042+#define ISPRSZ_VFILT1312_COEFF12_SHIFT 0
4043+#define ISPRSZ_VFILT1312_COEFF12_MASK 0x3FF
4044+#define ISPRSZ_VFILT1312_COEFF13_SHIFT 16
4045+#define ISPRSZ_VFILT1312_COEFF13_MASK 0x3FF0000
4046+
4047+#define ISPRSZ_VFILT1514_COEFF14_SHIFT 0
4048+#define ISPRSZ_VFILT1514_COEFF14_MASK 0x3FF
4049+#define ISPRSZ_VFILT1514_COEFF15_SHIFT 16
4050+#define ISPRSZ_VFILT1514_COEFF15_MASK 0x3FF0000
4051+
4052+#define ISPRSZ_VFILT1716_COEF16_SHIFT 0
4053+#define ISPRSZ_VFILT1716_COEF16_MASK 0x3FF
4054+#define ISPRSZ_VFILT1716_COEF17_SHIFT 16
4055+#define ISPRSZ_VFILT1716_COEF17_MASK 0x3FF0000
4056+
4057+#define ISPRSZ_VFILT1918_COEF18_SHIFT 0
4058+#define ISPRSZ_VFILT1918_COEF18_MASK 0x3FF
4059+#define ISPRSZ_VFILT1918_COEF19_SHIFT 16
4060+#define ISPRSZ_VFILT1918_COEF19_MASK 0x3FF0000
4061+
4062+#define ISPRSZ_VFILT2120_COEF20_SHIFT 0
4063+#define ISPRSZ_VFILT2120_COEF20_MASK 0x3FF
4064+#define ISPRSZ_VFILT2120_COEF21_SHIFT 16
4065+#define ISPRSZ_VFILT2120_COEF21_MASK 0x3FF0000
4066+
4067+#define ISPRSZ_VFILT2322_COEF22_SHIFT 0
4068+#define ISPRSZ_VFILT2322_COEF22_MASK 0x3FF
4069+#define ISPRSZ_VFILT2322_COEF23_SHIFT 16
4070+#define ISPRSZ_VFILT2322_COEF23_MASK 0x3FF0000
4071+
4072+#define ISPRSZ_VFILT2524_COEF24_SHIFT 0
4073+#define ISPRSZ_VFILT2524_COEF24_MASK 0x3FF
4074+#define ISPRSZ_VFILT2524_COEF25_SHIFT 16
4075+#define ISPRSZ_VFILT2524_COEF25_MASK 0x3FF0000
4076+
4077+#define ISPRSZ_VFILT2726_COEF26_SHIFT 0
4078+#define ISPRSZ_VFILT2726_COEF26_MASK 0x3FF
4079+#define ISPRSZ_VFILT2726_COEF27_SHIFT 16
4080+#define ISPRSZ_VFILT2726_COEF27_MASK 0x3FF0000
4081+
4082+#define ISPRSZ_VFILT2928_COEF28_SHIFT 0
4083+#define ISPRSZ_VFILT2928_COEF28_MASK 0x3FF
4084+#define ISPRSZ_VFILT2928_COEF29_SHIFT 16
4085+#define ISPRSZ_VFILT2928_COEF29_MASK 0x3FF0000
4086+
4087+#define ISPRSZ_VFILT3130_COEF30_SHIFT 0
4088+#define ISPRSZ_VFILT3130_COEF30_MASK 0x3FF
4089+#define ISPRSZ_VFILT3130_COEF31_SHIFT 16
4090+#define ISPRSZ_VFILT3130_COEF31_MASK 0x3FF0000
4091+
4092+#define ISPRSZ_YENH_CORE_SHIFT 0
4093+#define ISPRSZ_YENH_CORE_MASK 0xFF
4094+#define ISPRSZ_YENH_SLOP_SHIFT 8
4095+#define ISPRSZ_YENH_SLOP_MASK 0xF00
4096+#define ISPRSZ_YENH_GAIN_SHIFT 12
4097+#define ISPRSZ_YENH_GAIN_MASK 0xF000
4098+#define ISPRSZ_YENH_ALGO_SHIFT 16
4099+#define ISPRSZ_YENH_ALGO_MASK 0x30000
4100+
4101+#define ISPH3A_PCR_AEW_ALAW_EN_SHIFT 1
4102+#define ISPH3A_PCR_AF_MED_TH_SHIFT 3
4103+#define ISPH3A_PCR_AF_RGBPOS_SHIFT 11
4104+#define ISPH3A_PCR_AEW_AVE2LMT_SHIFT 22
4105+#define ISPH3A_PCR_AEW_AVE2LMT_MASK 0xFFC00000
4106+#define ISPH3A_PCR_BUSYAF (1 << 15)
4107+#define ISPH3A_PCR_BUSYAEAWB (1 << 18)
4108+
4109+#define ISPH3A_AEWWIN1_WINHC_SHIFT 0
4110+#define ISPH3A_AEWWIN1_WINHC_MASK 0x3F
4111+#define ISPH3A_AEWWIN1_WINVC_SHIFT 6
4112+#define ISPH3A_AEWWIN1_WINVC_MASK 0x1FC0
4113+#define ISPH3A_AEWWIN1_WINW_SHIFT 13
4114+#define ISPH3A_AEWWIN1_WINW_MASK 0xFE000
4115+#define ISPH3A_AEWWIN1_WINH_SHIFT 24
4116+#define ISPH3A_AEWWIN1_WINH_MASK 0x7F000000
4117+
4118+#define ISPH3A_AEWINSTART_WINSH_SHIFT 0
4119+#define ISPH3A_AEWINSTART_WINSH_MASK 0x0FFF
4120+#define ISPH3A_AEWINSTART_WINSV_SHIFT 16
4121+#define ISPH3A_AEWINSTART_WINSV_MASK 0x0FFF0000
4122+
4123+#define ISPH3A_AEWINBLK_WINH_SHIFT 0
4124+#define ISPH3A_AEWINBLK_WINH_MASK 0x7F
4125+#define ISPH3A_AEWINBLK_WINSV_SHIFT 16
4126+#define ISPH3A_AEWINBLK_WINSV_MASK 0x0FFF0000
4127+
4128+#define ISPH3A_AEWSUBWIN_AEWINCH_SHIFT 0
4129+#define ISPH3A_AEWSUBWIN_AEWINCH_MASK 0x0F
4130+#define ISPH3A_AEWSUBWIN_AEWINCV_SHIFT 8
4131+#define ISPH3A_AEWSUBWIN_AEWINCV_MASK 0x0F00
4132+
4133+#define ISPHIST_PCR_ENABLE_SHIFT 0
4134+#define ISPHIST_PCR_ENABLE_MASK 0x01
4135+#define ISPHIST_PCR_BUSY 0x02
4136+
4137+#define ISPHIST_CNT_DATASIZE_SHIFT 8
4138+#define ISPHIST_CNT_DATASIZE_MASK 0x0100
4139+#define ISPHIST_CNT_CLEAR_SHIFT 7
4140+#define ISPHIST_CNT_CLEAR_MASK 0x080
4141+#define ISPHIST_CNT_CFA_SHIFT 6
4142+#define ISPHIST_CNT_CFA_MASK 0x040
4143+#define ISPHIST_CNT_BINS_SHIFT 4
4144+#define ISPHIST_CNT_BINS_MASK 0x030
4145+#define ISPHIST_CNT_SOURCE_SHIFT 3
4146+#define ISPHIST_CNT_SOURCE_MASK 0x08
4147+#define ISPHIST_CNT_SHIFT_SHIFT 0
4148+#define ISPHIST_CNT_SHIFT_MASK 0x07
4149+
4150+#define ISPHIST_WB_GAIN_WG00_SHIFT 24
4151+#define ISPHIST_WB_GAIN_WG00_MASK 0xFF000000
4152+#define ISPHIST_WB_GAIN_WG01_SHIFT 16
4153+#define ISPHIST_WB_GAIN_WG01_MASK 0xFF0000
4154+#define ISPHIST_WB_GAIN_WG02_SHIFT 8
4155+#define ISPHIST_WB_GAIN_WG02_MASK 0xFF00
4156+#define ISPHIST_WB_GAIN_WG03_SHIFT 0
4157+#define ISPHIST_WB_GAIN_WG03_MASK 0xFF
4158+
4159+#define ISPHIST_REGHORIZ_HSTART_SHIFT 16 /*
4160+ * REGION 0 to 3 HORZ
4161+ * and VERT
4162+ */
4163+#define ISPHIST_REGHORIZ_HSTART_MASK 0x3FFF0000
4164+#define ISPHIST_REGHORIZ_HEND_SHIFT 0
4165+#define ISPHIST_REGHORIZ_HEND_MASK 0x3FFF
4166+#define ISPHIST_REGVERT_VSTART_SHIFT 16
4167+#define ISPHIST_REGVERT_VSTART_MASK 0x3FFF0000
4168+#define ISPHIST_REGVERT_VEND_SHIFT 0
4169+#define ISPHIST_REGVERT_VEND_MASK 0x3FFF
4170+
4171+#define ISPHIST_REGHORIZ_MASK 0x3FFF3FFF
4172+#define ISPHIST_REGVERT_MASK 0x3FFF3FFF
4173+
4174+#define ISPHIST_ADDR_SHIFT 0
4175+#define ISPHIST_ADDR_MASK 0x3FF
4176+
4177+#define ISPHIST_DATA_SHIFT 0
4178+#define ISPHIST_DATA_MASK 0xFFFFF
4179+
4180+#define ISPHIST_RADD_SHIFT 0
4181+#define ISPHIST_RADD_MASK 0xFFFFFFFF
4182+
4183+#define ISPHIST_RADD_OFF_SHIFT 0
4184+#define ISPHIST_RADD_OFF_MASK 0xFFFF
4185+
4186+#define ISPHIST_HV_INFO_HSIZE_SHIFT 16
4187+#define ISPHIST_HV_INFO_HSIZE_MASK 0x3FFF0000
4188+#define ISPHIST_HV_INFO_VSIZE_SHIFT 0
4189+#define ISPHIST_HV_INFO_VSIZE_MASK 0x3FFF
4190+
4191+#define ISPHIST_HV_INFO_MASK 0x3FFF3FFF
4192+
4193+#define ISPCCDC_LSC_GAIN_MODE_N_MASK 0x700
4194+#define ISPCCDC_LSC_GAIN_MODE_N_SHIFT 8
4195+#define ISPCCDC_LSC_GAIN_MODE_M_MASK 0x3800
4196+#define ISPCCDC_LSC_GAIN_MODE_M_SHIFT 12
4197+#define ISPCCDC_LSC_GAIN_FORMAT_MASK 0xE
4198+#define ISPCCDC_LSC_GAIN_FORMAT_SHIFT 1
4199+#define ISPCCDC_LSC_AFTER_REFORMATTER_MASK (1<<6)
4200+
4201+#define ISPCCDC_LSC_INITIAL_X_MASK 0x3F
4202+#define ISPCCDC_LSC_INITIAL_X_SHIFT 0
4203+#define ISPCCDC_LSC_INITIAL_Y_MASK 0x3F0000
4204+#define ISPCCDC_LSC_INITIAL_Y_SHIFT 16
4205+
4206+#define ISPMMU_REVISION_REV_MINOR_MASK 0xF
4207+#define ISPMMU_REVISION_REV_MAJOR_SHIFT 0x4
4208+
4209+#define IRQENABLE_MULTIHITFAULT (1<<4)
4210+#define IRQENABLE_TWFAULT (1<<3)
4211+#define IRQENABLE_EMUMISS (1<<2)
4212+#define IRQENABLE_TRANSLNFAULT (1<<1)
4213+#define IRQENABLE_TLBMISS (1)
4214+
4215+#define ISPMMU_MMUCNTL_MMU_EN (1<<1)
4216+#define ISPMMU_MMUCNTL_TWL_EN (1<<2)
4217+#define ISPMMU_MMUCNTL_EMUTLBUPDATE (1<<3)
4218+#define ISPMMU_AUTOIDLE 0x1
4219+#define ISPMMU_SIDLEMODE_FORCEIDLE 0
4220+#define ISPMMU_SIDLEMODE_NOIDLE 1
4221+#define ISPMMU_SIDLEMODE_SMARTIDLE 2
4222+#define ISPMMU_SIDLEMODE_SHIFT 3
4223+
4224+#define ISPCSI1_AUTOIDLE 0x1
4225+#define ISPCSI1_MIDLEMODE_SHIFT 12
4226+#define ISPCSI1_MIDLEMODE_FORCESTANDBY 0x0
4227+#define ISPCSI1_MIDLEMODE_NOSTANDBY 0x1
4228+#define ISPCSI1_MIDLEMODE_SMARTSTANDBY 0x2
4229+
4230+/* CSI2 receiver registers (ES2.0) */
4231+#define ISPCSI2_REVISION (0x000)
4232+#define ISPCSI2_SYSCONFIG (0x010)
4233+#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12
4234+#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK \
4235+ (0x3 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
4236+#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_FORCE \
4237+ (0x0 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
4238+#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO \
4239+ (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
4240+#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART \
4241+ (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
4242+#define ISPCSI2_SYSCONFIG_SOFT_RESET_SHIFT 1
4243+#define ISPCSI2_SYSCONFIG_SOFT_RESET_MASK \
4244+ (0x1 << ISPCSI2_SYSCONFIG_SOFT_RESET_SHIFT)
4245+#define ISPCSI2_SYSCONFIG_SOFT_RESET_NORMAL \
4246+ (0x0 << ISPCSI2_SYSCONFIG_SOFT_RESET_SHIFT)
4247+#define ISPCSI2_SYSCONFIG_SOFT_RESET_RESET \
4248+ (0x1 << ISPCSI2_SYSCONFIG_SOFT_RESET_SHIFT)
4249+#define ISPCSI2_SYSCONFIG_AUTO_IDLE_SHIFT 0
4250+#define ISPCSI2_SYSCONFIG_AUTO_IDLE_MASK \
4251+ (0x1 << ISPCSI2_SYSCONFIG_AUTO_IDLE_SHIFT)
4252+#define ISPCSI2_SYSCONFIG_AUTO_IDLE_FREE \
4253+ (0x0 << ISPCSI2_SYSCONFIG_AUTO_IDLE_SHIFT)
4254+#define ISPCSI2_SYSCONFIG_AUTO_IDLE_AUTO \
4255+ (0x1 << ISPCSI2_SYSCONFIG_AUTO_IDLE_SHIFT)
4256+#define ISPCSI2_SYSSTATUS (0x014)
4257+#define ISPCSI2_SYSSTATUS_RESET_DONE_SHIFT 0
4258+#define ISPCSI2_SYSSTATUS_RESET_DONE_MASK \
4259+ (0x1 << ISPCSI2_SYSSTATUS_RESET_DONE_SHIFT)
4260+#define ISPCSI2_SYSSTATUS_RESET_DONE_ONGOING \
4261+ (0x0 << ISPCSI2_SYSSTATUS_RESET_DONE_SHIFT)
4262+#define ISPCSI2_SYSSTATUS_RESET_DONE_DONE \
4263+ (0x1 << ISPCSI2_SYSSTATUS_RESET_DONE_SHIFT)
4264+#define ISPCSI2_IRQSTATUS (0x018)
4265+#define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ (1 << 14)
4266+#define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ (1 << 13)
4267+#define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 12)
4268+#define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ (1 << 11)
4269+#define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ (1 << 10)
4270+#define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ (1 << 9)
4271+#define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ (1 << 8)
4272+#define ISPCSI2_IRQSTATUS_CONTEXT(n) (1 << (n))
4273+
4274+#define ISPCSI2_IRQENABLE (0x01C)
4275+#define ISPCSI2_CTRL (0x040)
4276+#define ISPCSI2_CTRL_VP_CLK_EN_SHIFT 15
4277+#define ISPCSI2_CTRL_VP_CLK_EN_MASK (0x1 << ISPCSI2_CTRL_VP_CLK_EN_SHIFT)
4278+#define ISPCSI2_CTRL_VP_CLK_EN_DISABLE (0x0 << ISPCSI2_CTRL_VP_CLK_EN_SHIFT)
4279+#define ISPCSI2_CTRL_VP_CLK_EN_ENABLE (0x1 << ISPCSI2_CTRL_VP_CLK_EN_SHIFT)
4280+
4281+#define ISPCSI2_CTRL_VP_ONLY_EN_SHIFT 11
4282+#define ISPCSI2_CTRL_VP_ONLY_EN_MASK (0x1 << ISPCSI2_CTRL_VP_ONLY_EN_SHIFT)
4283+#define ISPCSI2_CTRL_VP_ONLY_EN_DISABLE (0x0 << ISPCSI2_CTRL_VP_ONLY_EN_SHIFT)
4284+#define ISPCSI2_CTRL_VP_ONLY_EN_ENABLE (0x1 << ISPCSI2_CTRL_VP_ONLY_EN_SHIFT)
4285+
4286+#define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT 8
4287+#define ISPCSI2_CTRL_VP_OUT_CTRL_MASK (0x3 << \
4288+ ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
4289+#define ISPCSI2_CTRL_VP_OUT_CTRL_DISABLE (0x0 << \
4290+ ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
4291+#define ISPCSI2_CTRL_VP_OUT_CTRL_DIV2 (0x1 << \
4292+ ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
4293+#define ISPCSI2_CTRL_VP_OUT_CTRL_DIV3 (0x2 << \
4294+ ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
4295+#define ISPCSI2_CTRL_VP_OUT_CTRL_DIV4 (0x3 << \
4296+ ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
4297+
4298+#define ISPCSI2_CTRL_DBG_EN_SHIFT 7
4299+#define ISPCSI2_CTRL_DBG_EN_MASK (0x1 << ISPCSI2_CTRL_DBG_EN_SHIFT)
4300+#define ISPCSI2_CTRL_DBG_EN_DISABLE (0x0 << ISPCSI2_CTRL_DBG_EN_SHIFT)
4301+#define ISPCSI2_CTRL_DBG_EN_ENABLE (0x1 << ISPCSI2_CTRL_DBG_EN_SHIFT)
4302+
4303+#define ISPCSI2_CTRL_BURST_SIZE_SHIFT 5
4304+#define ISPCSI2_CTRL_BURST_SIZE_MASK (0x3 << \
4305+ ISPCSI2_CTRL_BURST_SIZE_SHIFT)
4306+#define ISPCSI2_CTRL_BURST_SIZE_MYSTERY_VAL (0x2 << \
4307+ ISPCSI2_CTRL_BURST_SIZE_SHIFT)
4308+
4309+#define ISPCSI2_CTRL_FRAME_SHIFT 3
4310+#define ISPCSI2_CTRL_FRAME_MASK (0x1 << ISPCSI2_CTRL_FRAME_SHIFT)
4311+#define ISPCSI2_CTRL_FRAME_DISABLE_IMM (0x0 << ISPCSI2_CTRL_FRAME_SHIFT)
4312+#define ISPCSI2_CTRL_FRAME_DISABLE_FEC (0x1 << ISPCSI2_CTRL_FRAME_SHIFT)
4313+
4314+#define ISPCSI2_CTRL_ECC_EN_SHIFT 2
4315+#define ISPCSI2_CTRL_ECC_EN_MASK (0x1 << ISPCSI2_CTRL_ECC_EN_SHIFT)
4316+#define ISPCSI2_CTRL_ECC_EN_DISABLE (0x0 << ISPCSI2_CTRL_ECC_EN_SHIFT)
4317+#define ISPCSI2_CTRL_ECC_EN_ENABLE (0x1 << ISPCSI2_CTRL_ECC_EN_SHIFT)
4318+
4319+#define ISPCSI2_CTRL_SECURE_SHIFT 1
4320+#define ISPCSI2_CTRL_SECURE_MASK (0x1 << ISPCSI2_CTRL_SECURE_SHIFT)
4321+#define ISPCSI2_CTRL_SECURE_DISABLE (0x0 << ISPCSI2_CTRL_SECURE_SHIFT)
4322+#define ISPCSI2_CTRL_SECURE_ENABLE (0x1 << ISPCSI2_CTRL_SECURE_SHIFT)
4323+
4324+#define ISPCSI2_CTRL_IF_EN_SHIFT 0
4325+#define ISPCSI2_CTRL_IF_EN_MASK (0x1 << ISPCSI2_CTRL_IF_EN_SHIFT)
4326+#define ISPCSI2_CTRL_IF_EN_DISABLE (0x0 << ISPCSI2_CTRL_IF_EN_SHIFT)
4327+#define ISPCSI2_CTRL_IF_EN_ENABLE (0x1 << ISPCSI2_CTRL_IF_EN_SHIFT)
4328+
4329+#define ISPCSI2_DBG_H (0x044)
4330+#define ISPCSI2_GNQ (0x048)
4331+#define ISPCSI2_COMPLEXIO_CFG1 (0x050)
4332+#define ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_SHIFT 29
4333+#define ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_MASK \
4334+ (0x1 << ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_SHIFT)
4335+#define ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_ONGOING \
4336+ (0x0 << ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_SHIFT)
4337+#define ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_DONE \
4338+ (0x1 << ISPCSI2_COMPLEXIO_CFG1_RESET_DONE_SHIFT)
4339+#define ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_SHIFT 27
4340+#define ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_MASK \
4341+ (0x3 << ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_SHIFT)
4342+#define ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_OFF \
4343+ (0x0 << ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_SHIFT)
4344+#define ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_ON \
4345+ (0x1 << ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_SHIFT)
4346+#define ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_ULPW \
4347+ (0x2 << ISPCSI2_COMPLEXIO_CFG1_PWR_CMD_SHIFT)
4348+#define ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_SHIFT 25
4349+#define ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_MASK \
4350+ (0x3 << ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_SHIFT)
4351+#define ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_OFF \
4352+ (0x0 << ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_SHIFT)
4353+#define ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_ON \
4354+ (0x1 << ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_SHIFT)
4355+#define ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_ULPW \
4356+ (0x2 << ISPCSI2_COMPLEXIO_CFG1_PWR_STATUS_SHIFT)
4357+#define ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_SHIFT 24
4358+#define ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_MASK \
4359+ (0x1 << ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_SHIFT)
4360+#define ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_DISABLE \
4361+ (0x0 << ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_SHIFT)
4362+#define ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_ENABLE \
4363+ (0x1 << ISPCSI2_COMPLEXIO_CFG1_PWR_AUTO_SHIFT)
4364+
4365+#define ISPCSI2_COMPLEXIO_CFG1_DATA_POL_SHIFT(n) (3 + ((n) * 4))
4366+#define ISPCSI2_COMPLEXIO_CFG1_DATA_POL_MASK(n) \
4367+ (0x1 << ISPCSI2_COMPLEXIO_CFG1_DATA_POL_SHIFT(n))
4368+#define ISPCSI2_COMPLEXIO_CFG1_DATA_POL_PN(n) \
4369+ (0x0 << ISPCSI2_COMPLEXIO_CFG1_DATA_POL_SHIFT(n))
4370+#define ISPCSI2_COMPLEXIO_CFG1_DATA_POL_NP(n) \
4371+ (0x1 << ISPCSI2_COMPLEXIO_CFG1_DATA_POL_SHIFT(n))
4372+
4373+#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n) ((n) * 4)
4374+#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_MASK(n) \
4375+ (0x7 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
4376+#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_NC(n) \
4377+ (0x0 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
4378+#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_1(n) \
4379+ (0x1 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
4380+#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_2(n) \
4381+ (0x2 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
4382+#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_3(n) \
4383+ (0x3 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
4384+#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_4(n) \
4385+ (0x4 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
4386+#define ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_5(n) \
4387+ (0x5 << ISPCSI2_COMPLEXIO_CFG1_DATA_POSITION_SHIFT(n))
4388+
4389+#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_SHIFT 3
4390+#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_MASK \
4391+ (0x1 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_SHIFT)
4392+#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_PN \
4393+ (0x0 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_SHIFT)
4394+#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_NP \
4395+ (0x1 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POL_SHIFT)
4396+
4397+#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT 0
4398+#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_MASK \
4399+ (0x7 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT)
4400+#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_1 \
4401+ (0x1 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT)
4402+#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_2 \
4403+ (0x2 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT)
4404+#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_3 \
4405+ (0x3 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT)
4406+#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_4 \
4407+ (0x4 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT)
4408+#define ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_5 \
4409+ (0x5 << ISPCSI2_COMPLEXIO_CFG1_CLOCK_POSITION_SHIFT)
4410+
4411+#define ISPCSI2_COMPLEXIO1_IRQSTATUS (0x054)
4412+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEALLULPMEXIT (1 << 26)
4413+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEALLULPMENTER (1 << 25)
4414+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEULPM5 (1 << 24)
4415+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEULPM4 (1 << 23)
4416+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEULPM3 (1 << 22)
4417+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEULPM2 (1 << 21)
4418+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_STATEULPM1 (1 << 20)
4419+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRCONTROL5 (1 << 19)
4420+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRCONTROL4 (1 << 18)
4421+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRCONTROL3 (1 << 17)
4422+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRCONTROL2 (1 << 16)
4423+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRCONTROL1 (1 << 15)
4424+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRESC5 (1 << 14)
4425+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRESC4 (1 << 13)
4426+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRESC3 (1 << 12)
4427+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRESC2 (1 << 11)
4428+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRESC1 (1 << 10)
4429+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTSYNCHS5 (1 << 9)
4430+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTSYNCHS4 (1 << 8)
4431+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTSYNCHS3 (1 << 7)
4432+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTSYNCHS2 (1 << 6)
4433+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTSYNCHS1 (1 << 5)
4434+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTHS5 (1 << 4)
4435+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTHS4 (1 << 3)
4436+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTHS3 (1 << 2)
4437+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTHS2 (1 << 1)
4438+#define ISPCSI2_COMPLEXIO1_IRQSTATUS_ERRSOTHS1 1
4439+
4440+#define ISPCSI2_SHORT_PACKET (0x05C)
4441+#define ISPCSI2_COMPLEXIO1_IRQENABLE (0x060)
4442+#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEALLULPMEXIT (1 << 26)
4443+#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEALLULPMENTER (1 << 25)
4444+#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM5 (1 << 24)
4445+#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM4 (1 << 23)
4446+#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM3 (1 << 22)
4447+#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM2 (1 << 21)
4448+#define ISPCSI2_COMPLEXIO1_IRQENABLE_STATEULPM1 (1 << 20)
4449+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL5 (1 << 19)
4450+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL4 (1 << 18)
4451+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL3 (1 << 17)
4452+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL2 (1 << 16)
4453+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRCONTROL1 (1 << 15)
4454+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC5 (1 << 14)
4455+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC4 (1 << 13)
4456+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC3 (1 << 12)
4457+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC2 (1 << 11)
4458+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRESC1 (1 << 10)
4459+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS5 (1 << 9)
4460+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS4 (1 << 8)
4461+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS3 (1 << 7)
4462+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS2 (1 << 6)
4463+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTSYNCHS1 (1 << 5)
4464+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS5 (1 << 4)
4465+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS4 (1 << 3)
4466+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS3 (1 << 2)
4467+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS2 (1 << 1)
4468+#define ISPCSI2_COMPLEXIO1_IRQENABLE_ERRSOTHS1 1
4469+#define ISPCSI2_DBG_P (0x068)
4470+#define ISPCSI2_TIMING (0x06C)
4471+
4472+
4473+#define ISPCSI2_TIMING_FORCE_RX_MODE_IO_SHIFT(n) \
4474+ ((16 * ((n) - 1)) + 15)
4475+#define ISPCSI2_TIMING_FORCE_RX_MODE_IO_MASK(n) \
4476+ (0x1 << ISPCSI2_TIMING_FORCE_RX_MODE_IO_SHIFT(n))
4477+#define ISPCSI2_TIMING_FORCE_RX_MODE_IO_DISABLE(n) \
4478+ (0x0 << ISPCSI2_TIMING_FORCE_RX_MODE_IO_SHIFT(n))
4479+#define ISPCSI2_TIMING_FORCE_RX_MODE_IO_ENABLE(n) \
4480+ (0x1 << ISPCSI2_TIMING_FORCE_RX_MODE_IO_SHIFT(n))
4481+#define ISPCSI2_TIMING_STOP_STATE_X16_IO_SHIFT(n) ((16 * ((n) - 1)) + 14)
4482+#define ISPCSI2_TIMING_STOP_STATE_X16_IO_MASK(n) \
4483+ (0x1 << ISPCSI2_TIMING_STOP_STATE_X16_IO_SHIFT(n))
4484+#define ISPCSI2_TIMING_STOP_STATE_X16_IO_DISABLE(n) \
4485+ (0x0 << ISPCSI2_TIMING_STOP_STATE_X16_IO_SHIFT(n))
4486+#define ISPCSI2_TIMING_STOP_STATE_X16_IO_ENABLE(n) \
4487+ (0x1 << ISPCSI2_TIMING_STOP_STATE_X16_IO_SHIFT(n))
4488+#define ISPCSI2_TIMING_STOP_STATE_X4_IO_SHIFT(n) ((16 * ((n) - 1)) + 13)
4489+#define ISPCSI2_TIMING_STOP_STATE_X4_IO_MASK(n) \
4490+ (0x1 << ISPCSI2_TIMING_STOP_STATE_X4_IO_SHIFT(n))
4491+#define ISPCSI2_TIMING_STOP_STATE_X4_IO_DISABLE(n) \
4492+ (0x0 << ISPCSI2_TIMING_STOP_STATE_X4_IO_SHIFT(n))
4493+#define ISPCSI2_TIMING_STOP_STATE_X4_IO_ENABLE(n) \
4494+ (0x1 << ISPCSI2_TIMING_STOP_STATE_X4_IO_SHIFT(n))
4495+#define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n) (16 * ((n) - 1))
4496+#define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(n) \
4497+ (0x1fff << ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n))
4498+
4499+#define ISPCSI2_CTX_CTRL1(n) ((0x070) + 0x20 * (n))
4500+#define ISPCSI2_CTX_CTRL1_COUNT_SHIFT 8
4501+#define ISPCSI2_CTX_CTRL1_COUNT_MASK (0xFF << \
4502+ ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
4503+#define ISPCSI2_CTX_CTRL1_EOF_EN_SHIFT 7
4504+#define ISPCSI2_CTX_CTRL1_EOF_EN_MASK \
4505+ (0x1 << ISPCSI2_CTX_CTRL1_EOF_EN_SHIFT)
4506+#define ISPCSI2_CTX_CTRL1_EOF_EN_DISABLE \
4507+ (0x0 << ISPCSI2_CTX_CTRL1_EOF_EN_SHIFT)
4508+#define ISPCSI2_CTX_CTRL1_EOF_EN_ENABLE \
4509+ (0x1 << ISPCSI2_CTX_CTRL1_EOF_EN_SHIFT)
4510+#define ISPCSI2_CTX_CTRL1_EOL_EN_SHIFT 6
4511+#define ISPCSI2_CTX_CTRL1_EOL_EN_MASK \
4512+ (0x1 << ISPCSI2_CTX_CTRL1_EOL_EN_SHIFT)
4513+#define ISPCSI2_CTX_CTRL1_EOL_EN_DISABLE \
4514+ (0x0 << ISPCSI2_CTX_CTRL1_EOL_EN_SHIFT)
4515+#define ISPCSI2_CTX_CTRL1_EOL_EN_ENABLE \
4516+ (0x1 << ISPCSI2_CTX_CTRL1_EOL_EN_SHIFT)
4517+#define ISPCSI2_CTX_CTRL1_CS_EN_SHIFT 5
4518+#define ISPCSI2_CTX_CTRL1_CS_EN_MASK \
4519+ (0x1 << ISPCSI2_CTX_CTRL1_CS_EN_SHIFT)
4520+#define ISPCSI2_CTX_CTRL1_CS_EN_DISABLE \
4521+ (0x0 << ISPCSI2_CTX_CTRL1_CS_EN_SHIFT)
4522+#define ISPCSI2_CTX_CTRL1_CS_EN_ENABLE \
4523+ (0x1 << ISPCSI2_CTX_CTRL1_CS_EN_SHIFT)
4524+#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_SHIFT 4
4525+#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_MASK \
4526+ (0x1 << ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_SHIFT)
4527+#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_DISABLE \
4528+ (0x0 << ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_SHIFT)
4529+#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_ENABLE \
4530+ (0x1 << ISPCSI2_CTX_CTRL1_COUNT_UNLOCK_EN_SHIFT)
4531+#define ISPCSI2_CTX_CTRL1_PING_PONG_SHIFT 3
4532+#define ISPCSI2_CTX_CTRL1_PING_PONG_MASK \
4533+ (0x1 << ISPCSI2_CTX_CTRL1_PING_PONG_SHIFT)
4534+#define ISPCSI2_CTX_CTRL1_CTX_EN_SHIFT 0
4535+#define ISPCSI2_CTX_CTRL1_CTX_EN_MASK \
4536+ (0x1 << ISPCSI2_CTX_CTRL1_CTX_EN_SHIFT)
4537+#define ISPCSI2_CTX_CTRL1_CTX_EN_DISABLE \
4538+ (0x0 << ISPCSI2_CTX_CTRL1_CTX_EN_SHIFT)
4539+#define ISPCSI2_CTX_CTRL1_CTX_EN_ENABLE \
4540+ (0x1 << ISPCSI2_CTX_CTRL1_CTX_EN_SHIFT)
4541+
4542+#define ISPCSI2_CTX_CTRL2(n) ((0x074) + 0x20 * (n))
4543+#define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT 11
4544+#define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK \
4545+ (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT)
4546+#define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT 0
4547+#define ISPCSI2_CTX_CTRL2_FORMAT_MASK (0x3FF << \
4548+ ISPCSI2_CTX_CTRL2_FORMAT_SHIFT)
4549+
4550+#define ISPCSI2_CTX_DAT_OFST(n) ((0x078) + 0x20 * (n))
4551+#define ISPCSI2_CTX_DAT_OFST_OFST_SHIFT 5
4552+#define ISPCSI2_CTX_DAT_OFST_OFST_MASK (0x7FF << \
4553+ ISPCSI2_CTX_DAT_OFST_OFST_SHIFT)
4554+
4555+#define ISPCSI2_CTX_DAT_PING_ADDR(n) ((0x07C) + 0x20 * (n))
4556+#define ISPCSI2_CTX_DAT_PONG_ADDR(n) ((0x080) + 0x20 * (n))
4557+#define ISPCSI2_CTX_IRQENABLE(n) ((0x084) + 0x20 * (n))
4558+#define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ (1 << 8)
4559+#define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ (1 << 7)
4560+#define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ (1 << 6)
4561+#define ISPCSI2_CTX_IRQENABLE_CS_IRQ (1 << 5)
4562+#define ISPCSI2_CTX_IRQENABLE_LE_IRQ (1 << 3)
4563+#define ISPCSI2_CTX_IRQENABLE_LS_IRQ (1 << 2)
4564+#define ISPCSI2_CTX_IRQENABLE_FE_IRQ (1 << 1)
4565+#define ISPCSI2_CTX_IRQENABLE_FS_IRQ 1
4566+#define ISPCSI2_CTX_IRQSTATUS(n) ((0x088) + 0x20 * (n))
4567+#define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 8)
4568+#define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ (1 << 7)
4569+#define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ (1 << 6)
4570+#define ISPCSI2_CTX_IRQSTATUS_CS_IRQ (1 << 5)
4571+#define ISPCSI2_CTX_IRQSTATUS_LE_IRQ (1 << 3)
4572+#define ISPCSI2_CTX_IRQSTATUS_LS_IRQ (1 << 2)
4573+#define ISPCSI2_CTX_IRQSTATUS_FE_IRQ (1 << 1)
4574+#define ISPCSI2_CTX_IRQSTATUS_FS_IRQ 1
4575+
4576+#define ISPCSI2_CTX_CTRL3(n) ((0x08C) + 0x20 * (n))
4577+#define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT 5
4578+#define ISPCSI2_CTX_CTRL3_ALPHA_MASK (0x3FFF << \
4579+ ISPCSI2_CTX_CTRL3_ALPHA_SHIFT)
4580+
4581+#define ISPCSI2PHY_CFG0 (0x000)
4582+#define ISPCSI2PHY_CFG0_THS_TERM_SHIFT 8
4583+#define ISPCSI2PHY_CFG0_THS_TERM_MASK \
4584+ (0xFF << ISPCSI2PHY_CFG0_THS_TERM_SHIFT)
4585+#define ISPCSI2PHY_CFG0_THS_TERM_RESETVAL \
4586+ (0x04 << ISPCSI2PHY_CFG0_THS_TERM_SHIFT)
4587+#define ISPCSI2PHY_CFG0_THS_SETTLE_SHIFT 0
4588+#define ISPCSI2PHY_CFG0_THS_SETTLE_MASK \
4589+ (0xFF << ISPCSI2PHY_CFG0_THS_SETTLE_SHIFT)
4590+#define ISPCSI2PHY_CFG0_THS_SETTLE_RESETVAL \
4591+ (0x27 << ISPCSI2PHY_CFG0_THS_SETTLE_SHIFT)
4592+#define ISPCSI2PHY_CFG1 (0x004)
4593+#define ISPCSI2PHY_CFG1_TCLK_TERM_SHIFT 18
4594+#define ISPCSI2PHY_CFG1_TCLK_TERM_MASK \
4595+ (0x7F << ISPCSI2PHY_CFG1_TCLK_TERM_SHIFT)
4596+#define ISPCSI2PHY_CFG1_TCLK_TERM__RESETVAL \
4597+ (0x00 << ISPCSI2PHY_CFG1_TCLK_TERM_SHIFT)
4598+#define ISPCSI2PHY_CFG1_RESERVED1_SHIFT 10
4599+#define ISPCSI2PHY_CFG1_RESERVED1_MASK \
4600+ (0xFF << ISPCSI2PHY_CFG1_RESERVED1_SHIFT)
4601+#define ISPCSI2PHY_CFG1_RESERVED1__RESETVAL \
4602+ (0xB8 << ISPCSI2PHY_CFG1_RESERVED1_SHIFT)
4603+#define ISPCSI2PHY_CFG1_TCLK_MISS_SHIFT 8
4604+#define ISPCSI2PHY_CFG1_TCLK_MISS_MASK \
4605+ (0x3 << ISPCSI2PHY_CFG1_TCLK_MISS_SHIFT)
4606+#define ISPCSI2PHY_CFG1_TCLK_MISS__RESETVAL \
4607+ (0x1 << ISPCSI2PHY_CFG1_TCLK_MISS_SHIFT)
4608+#define ISPCSI2PHY_CFG1_TCLK_SETTLE_SHIFT 0
4609+#define ISPCSI2PHY_CFG1_TCLK_SETTLE_MASK \
4610+ (0xFF << ISPCSI2PHY_CFG1_TCLK_TERM_SHIFT)
4611+#define ISPCSI2PHY_CFG1_TCLK_SETTLE__RESETVAL \
4612+ (0x0E << ISPCSI2PHY_CFG1_TCLK_TERM_SHIFT)
4613+#define ISPCSI2PHY_CFG1__RESETVAL (ISPCSI2PHY_CFG1_TCLK_TERM__RESETVAL | \
4614+ ISPCSI2PHY_CFG1_RESERVED1__RESETVAL | \
4615+ ISPCSI2PHY_CFG1_TCLK_MISS__RESETVAL | \
4616+ ISPCSI2PHY_CFG1_TCLK_SETTLE__RESETVAL)
4617+#define ISPCSI2PHY_CFG1__EDITABLE_MASK (ISPCSI2PHY_CFG1_TCLK_TERM_MASK | \
4618+ ISPCSI2PHY_CFG1_RESERVED1_MASK | \
4619+ ISPCSI2PHY_CFG1_TCLK_MISS_MASK | \
4620+ ISPCSI2PHY_CFG1_TCLK_SETTLE_MASK)
4621+
4622+#endif /* __ISPREG_H__ */
4623--
46241.5.6.5
4625
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-04-27 08:03:06 +0000