diff options
Diffstat (limited to 'meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu')
8 files changed, 3010 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0001-omap-iommu-tlb-and-pagetable-primitives.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0001-omap-iommu-tlb-and-pagetable-primitives.patch new file mode 100644 index 0000000000..c2c9bc2b62 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0001-omap-iommu-tlb-and-pagetable-primitives.patch | |||
@@ -0,0 +1,1226 @@ | |||
1 | From a62a047ed02162573e4bece18ecf8bdd66ccd06b Mon Sep 17 00:00:00 2001 | ||
2 | From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
3 | Date: Mon, 26 Jan 2009 15:13:40 +0200 | ||
4 | Subject: [PATCH] omap iommu: tlb and pagetable primitives | ||
5 | |||
6 | This patch provides: | ||
7 | |||
8 | - iotlb_*() : iommu tlb operations | ||
9 | - iopgtable_*() : iommu pagetable(twl) operations | ||
10 | - iommu_*() : the other generic operations | ||
11 | |||
12 | and the entry points to register and acquire iommu object. | ||
13 | |||
14 | Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
15 | --- | ||
16 | arch/arm/plat-omap/include/mach/iommu.h | 157 +++++ | ||
17 | arch/arm/plat-omap/iommu.c | 953 +++++++++++++++++++++++++++++++ | ||
18 | arch/arm/plat-omap/iopgtable.h | 72 +++ | ||
19 | 3 files changed, 1182 insertions(+), 0 deletions(-) | ||
20 | create mode 100644 arch/arm/plat-omap/include/mach/iommu.h | ||
21 | create mode 100644 arch/arm/plat-omap/iommu.c | ||
22 | create mode 100644 arch/arm/plat-omap/iopgtable.h | ||
23 | |||
24 | diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/mach/iommu.h | ||
25 | new file mode 100644 | ||
26 | index 0000000..ef04d7a | ||
27 | --- /dev/null | ||
28 | +++ b/arch/arm/plat-omap/include/mach/iommu.h | ||
29 | @@ -0,0 +1,157 @@ | ||
30 | +/* | ||
31 | + * omap iommu: main structures | ||
32 | + * | ||
33 | + * Copyright (C) 2008-2009 Nokia Corporation | ||
34 | + * | ||
35 | + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
36 | + * | ||
37 | + * This program is free software; you can redistribute it and/or modify | ||
38 | + * it under the terms of the GNU General Public License version 2 as | ||
39 | + * published by the Free Software Foundation. | ||
40 | + */ | ||
41 | + | ||
42 | +#ifndef __MACH_IOMMU_H | ||
43 | +#define __MACH_IOMMU_H | ||
44 | + | ||
45 | +struct iotlb_entry { | ||
46 | + u32 da; | ||
47 | + u32 pa; | ||
48 | + u32 pgsz, prsvd, valid; | ||
49 | + union { | ||
50 | + u16 ap; | ||
51 | + struct { | ||
52 | + u32 endian, elsz, mixed; | ||
53 | + }; | ||
54 | + }; | ||
55 | +}; | ||
56 | + | ||
57 | +struct iommu { | ||
58 | + const char *name; | ||
59 | + struct module *owner; | ||
60 | + struct clk *clk; | ||
61 | + void __iomem *regbase; | ||
62 | + struct device *dev; | ||
63 | + | ||
64 | + unsigned int refcount; | ||
65 | + struct mutex iommu_lock; /* global for this whole object */ | ||
66 | + | ||
67 | + /* | ||
68 | + * We don't change iopgd for a situation like pgd for a task, | ||
69 | + * but share it globally for each iommu. | ||
70 | + */ | ||
71 | + u32 *iopgd; | ||
72 | + spinlock_t page_table_lock; /* protect iopgd */ | ||
73 | + | ||
74 | + int nr_tlb_entries; | ||
75 | + | ||
76 | + struct list_head mmap; | ||
77 | + struct mutex mmap_lock; /* protect mmap */ | ||
78 | + | ||
79 | + int (*isr)(struct iommu *obj); | ||
80 | + | ||
81 | + void *ctx; /* iommu context: registres saved area */ | ||
82 | +}; | ||
83 | + | ||
84 | +struct cr_regs { | ||
85 | + union { | ||
86 | + struct { | ||
87 | + u16 cam_l; | ||
88 | + u16 cam_h; | ||
89 | + }; | ||
90 | + u32 cam; | ||
91 | + }; | ||
92 | + union { | ||
93 | + struct { | ||
94 | + u16 ram_l; | ||
95 | + u16 ram_h; | ||
96 | + }; | ||
97 | + u32 ram; | ||
98 | + }; | ||
99 | +}; | ||
100 | + | ||
101 | +struct iotlb_lock { | ||
102 | + short base; | ||
103 | + short vict; | ||
104 | +}; | ||
105 | + | ||
106 | +/* architecture specific functions */ | ||
107 | +struct iommu_functions { | ||
108 | + unsigned long version; | ||
109 | + | ||
110 | + int (*enable)(struct iommu *obj); | ||
111 | + void (*disable)(struct iommu *obj); | ||
112 | + u32 (*fault_isr)(struct iommu *obj, u32 *ra); | ||
113 | + | ||
114 | + void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); | ||
115 | + void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr); | ||
116 | + | ||
117 | + struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e); | ||
118 | + int (*cr_valid)(struct cr_regs *cr); | ||
119 | + u32 (*cr_to_virt)(struct cr_regs *cr); | ||
120 | + void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e); | ||
121 | + ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf); | ||
122 | + | ||
123 | + u32 (*get_pte_attr)(struct iotlb_entry *e); | ||
124 | + | ||
125 | + void (*save_ctx)(struct iommu *obj); | ||
126 | + void (*restore_ctx)(struct iommu *obj); | ||
127 | + ssize_t (*dump_ctx)(struct iommu *obj, char *buf); | ||
128 | +}; | ||
129 | + | ||
130 | +struct iommu_platform_data { | ||
131 | + const char *name; | ||
132 | + const char *clk_name; | ||
133 | + const int nr_tlb_entries; | ||
134 | +}; | ||
135 | + | ||
136 | +#include <mach/iommu2.h> | ||
137 | + | ||
138 | +/* | ||
139 | + * utilities for super page(16MB, 1MB, 64KB and 4KB) | ||
140 | + */ | ||
141 | + | ||
142 | +#define iopgsz_max(bytes) \ | ||
143 | + (((bytes) >= SZ_16M) ? SZ_16M : \ | ||
144 | + ((bytes) >= SZ_1M) ? SZ_1M : \ | ||
145 | + ((bytes) >= SZ_64K) ? SZ_64K : \ | ||
146 | + ((bytes) >= SZ_4K) ? SZ_4K : 0) | ||
147 | + | ||
148 | +#define bytes_to_iopgsz(bytes) \ | ||
149 | + (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \ | ||
150 | + ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \ | ||
151 | + ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \ | ||
152 | + ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1) | ||
153 | + | ||
154 | +#define iopgsz_to_bytes(iopgsz) \ | ||
155 | + (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \ | ||
156 | + ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \ | ||
157 | + ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \ | ||
158 | + ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0) | ||
159 | + | ||
160 | +#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0) | ||
161 | + | ||
162 | +/* | ||
163 | + * global functions | ||
164 | + */ | ||
165 | +extern u32 iommu_arch_version(void); | ||
166 | + | ||
167 | +extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); | ||
168 | +extern void flush_iotlb_page(struct iommu *obj, u32 da); | ||
169 | +extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); | ||
170 | +extern void flush_iotlb_all(struct iommu *obj); | ||
171 | + | ||
172 | +ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf); | ||
173 | + | ||
174 | +extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); | ||
175 | +extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); | ||
176 | + | ||
177 | +extern struct iommu *iommu_get(const char *name); | ||
178 | +extern void iommu_put(struct iommu *obj); | ||
179 | + | ||
180 | +extern void iommu_save_ctx(struct iommu *obj); | ||
181 | +extern void iommu_restore_ctx(struct iommu *obj); | ||
182 | + | ||
183 | +extern int install_iommu_arch(const struct iommu_functions *ops); | ||
184 | +extern void uninstall_iommu_arch(const struct iommu_functions *ops); | ||
185 | + | ||
186 | +#endif /* __MACH_IOMMU_H */ | ||
187 | diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c | ||
188 | new file mode 100644 | ||
189 | index 0000000..e638883 | ||
190 | --- /dev/null | ||
191 | +++ b/arch/arm/plat-omap/iommu.c | ||
192 | @@ -0,0 +1,953 @@ | ||
193 | +/* | ||
194 | + * omap iommu: tlb and pagetable primitives | ||
195 | + * | ||
196 | + * Copyright (C) 2008-2009 Nokia Corporation | ||
197 | + * | ||
198 | + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | ||
199 | + * Paul Mundt and Toshihiro Kobayashi | ||
200 | + * | ||
201 | + * This program is free software; you can redistribute it and/or modify | ||
202 | + * it under the terms of the GNU General Public License version 2 as | ||
203 | + * published by the Free Software Foundation. | ||
204 | + */ | ||
205 | + | ||
206 | +#include <linux/err.h> | ||
207 | +#include <linux/module.h> | ||
208 | +#include <linux/interrupt.h> | ||
209 | +#include <linux/ioport.h> | ||
210 | +#include <linux/clk.h> | ||
211 | +#include <linux/platform_device.h> | ||
212 | + | ||
213 | +#include <asm/io.h> | ||
214 | +#include <asm/cacheflush.h> | ||
215 | + | ||
216 | +#include <mach/clock.h> | ||
217 | +#include <mach/iommu.h> | ||
218 | + | ||
219 | +#include "iopgtable.h" | ||
220 | + | ||
221 | +/* accommodate the difference between omap1 and omap2/3 */ | ||
222 | +static const struct iommu_functions *arch_iommu; | ||
223 | + | ||
224 | +static struct platform_driver omap_iommu_driver; | ||
225 | +static struct kmem_cache *iopte_cachep; | ||
226 | + | ||
227 | +/** | ||
228 | + * install_iommu_arch() - Install archtecure specific iommu functions | ||
229 | + * @ops: a pointer to architecture specific iommu functions | ||
230 | + * | ||
231 | + * There are several kind of iommu algorithm(tlb, pagetable) among | ||
232 | + * omap series. This interface installs such an iommu algorighm. | ||
233 | + **/ | ||
234 | +int install_iommu_arch(const struct iommu_functions *ops) | ||
235 | +{ | ||
236 | + if (arch_iommu) | ||
237 | + return -EBUSY; | ||
238 | + | ||
239 | + arch_iommu = ops; | ||
240 | + return 0; | ||
241 | +} | ||
242 | +EXPORT_SYMBOL_GPL(install_iommu_arch); | ||
243 | + | ||
244 | +/** | ||
245 | + * uninstall_iommu_arch() - Uninstall archtecure specific iommu functions | ||
246 | + * @ops: a pointer to architecture specific iommu functions | ||
247 | + * | ||
248 | + * This interface uninstalls the iommu algorighm installed previously. | ||
249 | + **/ | ||
250 | +void uninstall_iommu_arch(const struct iommu_functions *ops) | ||
251 | +{ | ||
252 | + if (arch_iommu != ops) | ||
253 | + pr_err("%s: not your arch\n", __func__); | ||
254 | + | ||
255 | + arch_iommu = NULL; | ||
256 | +} | ||
257 | +EXPORT_SYMBOL_GPL(uninstall_iommu_arch); | ||
258 | + | ||
259 | +/** | ||
260 | + * iommu_save_ctx() - Save registers for pm off-mode support | ||
261 | + * @obj: target iommu | ||
262 | + **/ | ||
263 | +void iommu_save_ctx(struct iommu *obj) | ||
264 | +{ | ||
265 | + arch_iommu->save_ctx(obj); | ||
266 | +} | ||
267 | +EXPORT_SYMBOL_GPL(iommu_save_ctx); | ||
268 | + | ||
269 | +/** | ||
270 | + * iommu_restore_ctx() - Restore registers for pm off-mode support | ||
271 | + * @obj: target iommu | ||
272 | + **/ | ||
273 | +void iommu_restore_ctx(struct iommu *obj) | ||
274 | +{ | ||
275 | + arch_iommu->restore_ctx(obj); | ||
276 | +} | ||
277 | +EXPORT_SYMBOL_GPL(iommu_restore_ctx); | ||
278 | + | ||
279 | +/** | ||
280 | + * iommu_arch_version() - Return running iommu arch version | ||
281 | + **/ | ||
282 | +u32 iommu_arch_version(void) | ||
283 | +{ | ||
284 | + return arch_iommu->version; | ||
285 | +} | ||
286 | +EXPORT_SYMBOL_GPL(iommu_arch_version); | ||
287 | + | ||
288 | +static int iommu_enable(struct iommu *obj) | ||
289 | +{ | ||
290 | + int err; | ||
291 | + | ||
292 | + if (!obj) | ||
293 | + return -EINVAL; | ||
294 | + | ||
295 | + clk_enable(obj->clk); | ||
296 | + | ||
297 | + err = arch_iommu->enable(obj); | ||
298 | + | ||
299 | + clk_disable(obj->clk); | ||
300 | + return err; | ||
301 | +} | ||
302 | + | ||
303 | +static void iommu_disable(struct iommu *obj) | ||
304 | +{ | ||
305 | + if (!obj) | ||
306 | + return; | ||
307 | + | ||
308 | + clk_enable(obj->clk); | ||
309 | + | ||
310 | + arch_iommu->disable(obj); | ||
311 | + | ||
312 | + clk_disable(obj->clk); | ||
313 | +} | ||
314 | + | ||
315 | +#ifdef DEBUG | ||
316 | +static ssize_t iommu_dump_ctx(struct iommu *obj, char *buf) | ||
317 | +{ | ||
318 | + if (!obj || !buf) | ||
319 | + return -EINVAL; | ||
320 | + | ||
321 | + return arch_iommu->dump_ctx(obj, buf); | ||
322 | +} | ||
323 | +#endif | ||
324 | + | ||
325 | +/* | ||
326 | + * TLB operations | ||
327 | + */ | ||
328 | +static inline void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) | ||
329 | +{ | ||
330 | + BUG_ON(!cr || !e); | ||
331 | + | ||
332 | + arch_iommu->cr_to_e(cr, e); | ||
333 | +} | ||
334 | + | ||
335 | +static inline int iotlb_cr_valid(struct cr_regs *cr) | ||
336 | +{ | ||
337 | + if (!cr) | ||
338 | + return -EINVAL; | ||
339 | + | ||
340 | + return arch_iommu->cr_valid(cr); | ||
341 | +} | ||
342 | + | ||
343 | +static inline struct cr_regs *iotlb_alloc_cr(struct iommu *obj, | ||
344 | + struct iotlb_entry *e) | ||
345 | +{ | ||
346 | + if (!e) | ||
347 | + return NULL; | ||
348 | + | ||
349 | + return arch_iommu->alloc_cr(obj, e); | ||
350 | +} | ||
351 | + | ||
352 | +static inline u32 iotlb_cr_to_virt(struct cr_regs *cr) | ||
353 | +{ | ||
354 | + return arch_iommu->cr_to_virt(cr); | ||
355 | +} | ||
356 | + | ||
357 | +static u32 get_iopte_attr(struct iotlb_entry *e) | ||
358 | +{ | ||
359 | + return arch_iommu->get_pte_attr(e); | ||
360 | +} | ||
361 | + | ||
362 | +static u32 iommu_report_fault(struct iommu *obj, u32 *da) | ||
363 | +{ | ||
364 | + return arch_iommu->fault_isr(obj, da); | ||
365 | +} | ||
366 | + | ||
367 | +static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l) | ||
368 | +{ | ||
369 | + u32 val; | ||
370 | + | ||
371 | + val = iommu_read_reg(obj, MMU_LOCK); | ||
372 | + | ||
373 | + l->base = MMU_LOCK_BASE(val); | ||
374 | + l->vict = MMU_LOCK_VICT(val); | ||
375 | + | ||
376 | + BUG_ON(l->base != 0); /* Currently no preservation is used */ | ||
377 | +} | ||
378 | + | ||
379 | +static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l) | ||
380 | +{ | ||
381 | + u32 val; | ||
382 | + | ||
383 | + BUG_ON(l->base != 0); /* Currently no preservation is used */ | ||
384 | + | ||
385 | + val = (l->base << MMU_LOCK_BASE_SHIFT); | ||
386 | + val |= (l->vict << MMU_LOCK_VICT_SHIFT); | ||
387 | + | ||
388 | + iommu_write_reg(obj, val, MMU_LOCK); | ||
389 | +} | ||
390 | + | ||
391 | +static void iotlb_read_cr(struct iommu *obj, struct cr_regs *cr) | ||
392 | +{ | ||
393 | + arch_iommu->tlb_read_cr(obj, cr); | ||
394 | +} | ||
395 | + | ||
396 | +static void iotlb_load_cr(struct iommu *obj, struct cr_regs *cr) | ||
397 | +{ | ||
398 | + arch_iommu->tlb_load_cr(obj, cr); | ||
399 | + | ||
400 | + iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | ||
401 | + iommu_write_reg(obj, 1, MMU_LD_TLB); | ||
402 | +} | ||
403 | + | ||
404 | +/** | ||
405 | + * iotlb_dump_cr() - Dump an iommu tlb entry into buf | ||
406 | + * @obj: target iommu | ||
407 | + * @cr: contents of cam and ram register | ||
408 | + * @buf: output buffer | ||
409 | + **/ | ||
410 | +ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf) | ||
411 | +{ | ||
412 | + BUG_ON(!cr || !buf); | ||
413 | + | ||
414 | + return arch_iommu->dump_cr(obj, cr, buf); | ||
415 | +} | ||
416 | +EXPORT_SYMBOL_GPL(iotlb_dump_cr); | ||
417 | + | ||
418 | +/** | ||
419 | + * load_iotlb_entry() - Set an iommu tlb entry | ||
420 | + * @obj: target iommu | ||
421 | + * @e: an iommu tlb entry info | ||
422 | + **/ | ||
423 | +int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) | ||
424 | +{ | ||
425 | + int i; | ||
426 | + int err = 0; | ||
427 | + struct iotlb_lock l; | ||
428 | + struct cr_regs *cr; | ||
429 | + | ||
430 | + if (!obj || !obj->nr_tlb_entries || !e) | ||
431 | + return -EINVAL; | ||
432 | + | ||
433 | + clk_enable(obj->clk); | ||
434 | + | ||
435 | + for (i = 0; i < obj->nr_tlb_entries; i++) { | ||
436 | + struct cr_regs tmp; | ||
437 | + | ||
438 | + iotlb_lock_get(obj, &l); | ||
439 | + l.vict = i; | ||
440 | + iotlb_lock_set(obj, &l); | ||
441 | + iotlb_read_cr(obj, &tmp); | ||
442 | + if (!iotlb_cr_valid(&tmp)) | ||
443 | + break; | ||
444 | + } | ||
445 | + | ||
446 | + if (i == obj->nr_tlb_entries) { | ||
447 | + dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | ||
448 | + err = -EBUSY; | ||
449 | + goto out; | ||
450 | + } | ||
451 | + | ||
452 | + cr = iotlb_alloc_cr(obj, e); | ||
453 | + if (IS_ERR(cr)) { | ||
454 | + clk_disable(obj->clk); | ||
455 | + return PTR_ERR(cr); | ||
456 | + } | ||
457 | + | ||
458 | + iotlb_load_cr(obj, cr); | ||
459 | + kfree(cr); | ||
460 | + | ||
461 | + /* increment victim for next tlb load */ | ||
462 | + if (++l.vict == obj->nr_tlb_entries) | ||
463 | + l.vict = 0; | ||
464 | + iotlb_lock_set(obj, &l); | ||
465 | +out: | ||
466 | + clk_disable(obj->clk); | ||
467 | + return err; | ||
468 | +} | ||
469 | +EXPORT_SYMBOL_GPL(load_iotlb_entry); | ||
470 | + | ||
471 | +/** | ||
472 | + * flush_iotlb_page() - Clear an iommu tlb entry | ||
473 | + * @obj: target iommu | ||
474 | + * @da: iommu device virtual address | ||
475 | + * | ||
476 | + * Clear an iommu tlb entry which includes 'da' address. | ||
477 | + **/ | ||
478 | +void flush_iotlb_page(struct iommu *obj, u32 da) | ||
479 | +{ | ||
480 | + struct iotlb_lock l; | ||
481 | + int i; | ||
482 | + | ||
483 | + clk_enable(obj->clk); | ||
484 | + | ||
485 | + for (i = 0; i < obj->nr_tlb_entries; i++) { | ||
486 | + struct cr_regs cr; | ||
487 | + u32 start; | ||
488 | + size_t bytes; | ||
489 | + | ||
490 | + iotlb_lock_get(obj, &l); | ||
491 | + l.vict = i; | ||
492 | + iotlb_lock_set(obj, &l); | ||
493 | + iotlb_read_cr(obj, &cr); | ||
494 | + if (!iotlb_cr_valid(&cr)) | ||
495 | + continue; | ||
496 | + | ||
497 | + start = iotlb_cr_to_virt(&cr); | ||
498 | + bytes = iopgsz_to_bytes(cr.cam & 3); | ||
499 | + | ||
500 | + if ((start <= da) && (da < start + bytes)) { | ||
501 | + dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | ||
502 | + __func__, start, da, bytes); | ||
503 | + | ||
504 | + iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | ||
505 | + } | ||
506 | + } | ||
507 | + clk_disable(obj->clk); | ||
508 | + | ||
509 | + if (i == obj->nr_tlb_entries) | ||
510 | + dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | ||
511 | +} | ||
512 | +EXPORT_SYMBOL_GPL(flush_iotlb_page); | ||
513 | + | ||
514 | +/** | ||
515 | + * flush_iotlb_range() - Clear an iommu tlb entries | ||
516 | + * @obj: target iommu | ||
517 | + * @start: iommu device virtual address(start) | ||
518 | + * @end: iommu device virtual address(end) | ||
519 | + * | ||
520 | + * Clear an iommu tlb entry which includes 'da' address. | ||
521 | + **/ | ||
522 | +void flush_iotlb_range(struct iommu *obj, u32 start, u32 end) | ||
523 | +{ | ||
524 | + u32 da = start; | ||
525 | + | ||
526 | + while (da < end) { | ||
527 | + flush_iotlb_page(obj, da); | ||
528 | + /* FIXME: Optimize for multiple page size */ | ||
529 | + da += IOPTE_SIZE; | ||
530 | + } | ||
531 | +} | ||
532 | +EXPORT_SYMBOL_GPL(flush_iotlb_range); | ||
533 | + | ||
534 | +/** | ||
535 | + * flush_iotlb_all() - Clear all iommu tlb entries | ||
536 | + * @obj: target iommu | ||
537 | + **/ | ||
538 | +void flush_iotlb_all(struct iommu *obj) | ||
539 | +{ | ||
540 | + struct iotlb_lock l; | ||
541 | + | ||
542 | + clk_enable(obj->clk); | ||
543 | + | ||
544 | + l.base = 0; | ||
545 | + l.vict = 0; | ||
546 | + iotlb_lock_set(obj, &l); | ||
547 | + | ||
548 | + iommu_write_reg(obj, 1, MMU_GFLUSH); | ||
549 | + | ||
550 | + clk_disable(obj->clk); | ||
551 | +} | ||
552 | +EXPORT_SYMBOL_GPL(flush_iotlb_all); | ||
553 | + | ||
554 | +/* | ||
555 | + * H/W pagetable operations | ||
556 | + */ | ||
557 | +static void flush_iopgd_range(u32 *first, u32 *last) | ||
558 | +{ | ||
559 | + /* FIXME: L2 cache should be taken care of if it exists */ | ||
560 | + do { | ||
561 | + asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" | ||
562 | + : : "r" (first)); | ||
563 | + first += L1_CACHE_BYTES / sizeof(*first); | ||
564 | + } while (first <= last); | ||
565 | +} | ||
566 | + | ||
567 | +static void flush_iopte_range(u32 *first, u32 *last) | ||
568 | +{ | ||
569 | + /* FIXME: L2 cache should be taken care of if it exists */ | ||
570 | + do { | ||
571 | + asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" | ||
572 | + : : "r" (first)); | ||
573 | + first += L1_CACHE_BYTES / sizeof(*first); | ||
574 | + } while (first <= last); | ||
575 | +} | ||
576 | + | ||
577 | +static void iopte_free(u32 *iopte) | ||
578 | +{ | ||
579 | + /* Note: freed iopte's must be clean ready for re-use */ | ||
580 | + kmem_cache_free(iopte_cachep, iopte); | ||
581 | +} | ||
582 | + | ||
583 | +static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd, u32 da) | ||
584 | +{ | ||
585 | + u32 *iopte; | ||
586 | + | ||
587 | + /* a table has already existed */ | ||
588 | + if (*iopgd) | ||
589 | + goto pte_ready; | ||
590 | + | ||
591 | + /* | ||
592 | + * do the allocation outside the page table lock | ||
593 | + */ | ||
594 | + spin_unlock(&obj->page_table_lock); | ||
595 | + iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | ||
596 | + spin_lock(&obj->page_table_lock); | ||
597 | + | ||
598 | + if (!*iopgd) { | ||
599 | + if (!iopte) | ||
600 | + return ERR_PTR(-ENOMEM); | ||
601 | + | ||
602 | + *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; | ||
603 | + flush_iopgd_range(iopgd, iopgd); | ||
604 | + | ||
605 | + dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); | ||
606 | + } else { | ||
607 | + /* We raced, free the reduniovant table */ | ||
608 | + iopte_free(iopte); | ||
609 | + } | ||
610 | + | ||
611 | +pte_ready: | ||
612 | + iopte = iopte_offset(iopgd, da); | ||
613 | + | ||
614 | + dev_vdbg(obj->dev, | ||
615 | + "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | ||
616 | + __func__, da, iopgd, *iopgd, iopte, *iopte); | ||
617 | + | ||
618 | + return iopte; | ||
619 | +} | ||
620 | + | ||
621 | +static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot) | ||
622 | +{ | ||
623 | + u32 *iopgd = iopgd_offset(obj, da); | ||
624 | + | ||
625 | + *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; | ||
626 | + flush_iopgd_range(iopgd, iopgd); | ||
627 | + return 0; | ||
628 | +} | ||
629 | + | ||
630 | +static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot) | ||
631 | +{ | ||
632 | + u32 *iopgd = iopgd_offset(obj, da); | ||
633 | + int i; | ||
634 | + | ||
635 | + for (i = 0; i < 16; i++) | ||
636 | + *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | ||
637 | + flush_iopgd_range(iopgd, iopgd + 15); | ||
638 | + return 0; | ||
639 | +} | ||
640 | + | ||
641 | +static int iopte_alloc_page(struct iommu *obj, u32 da, u32 pa, u32 prot) | ||
642 | +{ | ||
643 | + u32 *iopgd = iopgd_offset(obj, da); | ||
644 | + u32 *iopte = iopte_alloc(obj, iopgd, da); | ||
645 | + | ||
646 | + if (IS_ERR(iopte)) | ||
647 | + return PTR_ERR(iopte); | ||
648 | + | ||
649 | + *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | ||
650 | + flush_iopte_range(iopte, iopte); | ||
651 | + | ||
652 | + dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | ||
653 | + __func__, da, pa, iopte, *iopte); | ||
654 | + | ||
655 | + return 0; | ||
656 | +} | ||
657 | + | ||
658 | +static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot) | ||
659 | +{ | ||
660 | + u32 *iopgd = iopgd_offset(obj, da); | ||
661 | + u32 *iopte = iopte_alloc(obj, iopgd, da); | ||
662 | + int i; | ||
663 | + | ||
664 | + if (IS_ERR(iopte)) | ||
665 | + return PTR_ERR(iopte); | ||
666 | + | ||
667 | + for (i = 0; i < 16; i++) | ||
668 | + *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | ||
669 | + flush_iopte_range(iopte, iopte + 15); | ||
670 | + return 0; | ||
671 | +} | ||
672 | + | ||
673 | +static int iopgtable_store_entry_core(struct iommu *obj, struct iotlb_entry *e) | ||
674 | +{ | ||
675 | + int (*fn)(struct iommu *, u32, u32, u32); | ||
676 | + u32 prot; | ||
677 | + int err; | ||
678 | + | ||
679 | + if (!obj || !e) | ||
680 | + return -EINVAL; | ||
681 | + | ||
682 | + switch (e->pgsz) { | ||
683 | + case MMU_CAM_PGSZ_16M: | ||
684 | + fn = iopgd_alloc_super; | ||
685 | + break; | ||
686 | + case MMU_CAM_PGSZ_1M: | ||
687 | + fn = iopgd_alloc_section; | ||
688 | + break; | ||
689 | + case MMU_CAM_PGSZ_64K: | ||
690 | + fn = iopte_alloc_large; | ||
691 | + break; | ||
692 | + case MMU_CAM_PGSZ_4K: | ||
693 | + fn = iopte_alloc_page; | ||
694 | + break; | ||
695 | + default: | ||
696 | + fn = NULL; | ||
697 | + BUG(); | ||
698 | + break; | ||
699 | + } | ||
700 | + | ||
701 | + prot = get_iopte_attr(e); | ||
702 | + | ||
703 | + spin_lock(&obj->page_table_lock); | ||
704 | + err = fn(obj, e->da, e->pa, prot); | ||
705 | + spin_unlock(&obj->page_table_lock); | ||
706 | + | ||
707 | + return err; | ||
708 | +} | ||
709 | + | ||
710 | +#ifdef DEBUG | ||
711 | +static void dump_tlb_entries(struct iommu *obj) | ||
712 | +{ | ||
713 | + int i; | ||
714 | + struct iotlb_lock l; | ||
715 | + | ||
716 | + clk_enable(obj->clk); | ||
717 | + | ||
718 | + pr_info("%8s %8s\n", "cam:", "ram:"); | ||
719 | + pr_info("-----------------------------------------\n"); | ||
720 | + | ||
721 | + for (i = 0; i < obj->nr_tlb_entries; i++) { | ||
722 | + struct cr_regs cr; | ||
723 | + static char buf[4096]; | ||
724 | + | ||
725 | + iotlb_lock_get(obj, &l); | ||
726 | + l.vict = i; | ||
727 | + iotlb_lock_set(obj, &l); | ||
728 | + iotlb_read_cr(obj, &cr); | ||
729 | + if (!iotlb_cr_valid(&cr)) | ||
730 | + continue; | ||
731 | + | ||
732 | + memset(buf, 0, 4096); | ||
733 | + iotlb_dump_cr(obj, &cr, buf); | ||
734 | + pr_err("%s", buf); | ||
735 | + } | ||
736 | + | ||
737 | + clk_disable(obj->clk); | ||
738 | +} | ||
739 | +#else | ||
740 | +static inline void dump_tlb_entries(struct iommu *obj) {} | ||
741 | +#endif | ||
742 | + | ||
743 | +/** | ||
744 | + * iopgtable_store_entry() - Make an iommu pte entry | ||
745 | + * @obj: target iommu | ||
746 | + * @e: an iommu tlb entry info | ||
747 | + **/ | ||
748 | +int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e) | ||
749 | +{ | ||
750 | + int err; | ||
751 | + | ||
752 | + flush_iotlb_page(obj, e->da); | ||
753 | + err = iopgtable_store_entry_core(obj, e); | ||
754 | +#ifdef USE_IOTLB | ||
755 | + if (!err) | ||
756 | + load_iotlb_entry(obj, e); | ||
757 | +#endif | ||
758 | + return err; | ||
759 | +} | ||
760 | +EXPORT_SYMBOL_GPL(iopgtable_store_entry); | ||
761 | + | ||
762 | +/** | ||
763 | + * iopgtable_lookup_entry() - Lookup an iommu pte entry | ||
764 | + * @obj: target iommu | ||
765 | + * @da: iommu device virtual address | ||
766 | + * @ppgd: iommu pgd entry pointer to be returned | ||
767 | + * @ppte: iommu pte entry pointer to be returned | ||
768 | + **/ | ||
769 | +void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | ||
770 | +{ | ||
771 | + u32 *iopgd, *iopte = NULL; | ||
772 | + | ||
773 | + iopgd = iopgd_offset(obj, da); | ||
774 | + if (!*iopgd) | ||
775 | + goto out; | ||
776 | + | ||
777 | + if (*iopgd & IOPGD_TABLE) | ||
778 | + iopte = iopte_offset(iopgd, da); | ||
779 | +out: | ||
780 | + *ppgd = iopgd; | ||
781 | + *ppte = iopte; | ||
782 | +} | ||
783 | +EXPORT_SYMBOL_GPL(iopgtable_lookup_entry); | ||
784 | + | ||
785 | +static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) | ||
786 | +{ | ||
787 | + size_t bytes; | ||
788 | + u32 *iopgd = iopgd_offset(obj, da); | ||
789 | + int nent = 1; | ||
790 | + | ||
791 | + if (!*iopgd) | ||
792 | + return 0; | ||
793 | + | ||
794 | + if (*iopgd & IOPGD_TABLE) { | ||
795 | + int i; | ||
796 | + u32 *iopte = iopte_offset(iopgd, da); | ||
797 | + | ||
798 | + bytes = IOPTE_SIZE; | ||
799 | + if (*iopte & IOPTE_LARGE) { | ||
800 | + nent *= 16; | ||
801 | + /* rewind to the 1st entry */ | ||
802 | + iopte = (u32 *)((u32)iopte & IOLARGE_MASK); | ||
803 | + } | ||
804 | + bytes *= nent; | ||
805 | + memset(iopte, 0, nent * sizeof(*iopte)); | ||
806 | + flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); | ||
807 | + | ||
808 | + /* | ||
809 | + * do table walk to check if this table is necessary or not | ||
810 | + */ | ||
811 | + iopte = iopte_offset(iopgd, 0); | ||
812 | + for (i = 0; i < PTRS_PER_IOPTE; i++) | ||
813 | + if (iopte[i]) | ||
814 | + goto out; | ||
815 | + | ||
816 | + iopte_free(iopte); | ||
817 | + nent = 1; /* for the next L1 entry */ | ||
818 | + } else { | ||
819 | + bytes = IOPGD_SIZE; | ||
820 | + if (*iopgd & IOPGD_SUPER) { | ||
821 | + nent *= 16; | ||
822 | + /* rewind to the 1st entry */ | ||
823 | + iopgd = (u32 *)((u32)iopgd & IOSUPER_MASK); | ||
824 | + } | ||
825 | + bytes *= nent; | ||
826 | + } | ||
827 | + memset(iopgd, 0, nent * sizeof(*iopgd)); | ||
828 | + flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); | ||
829 | +out: | ||
830 | + return bytes; | ||
831 | +} | ||
832 | + | ||
833 | +/** | ||
834 | + * iopgtable_clear_entry() - Remove an iommu pte entry | ||
835 | + * @obj: target iommu | ||
836 | + * @da: iommu device virtual address | ||
837 | + **/ | ||
838 | +size_t iopgtable_clear_entry(struct iommu *obj, u32 da) | ||
839 | +{ | ||
840 | + size_t bytes; | ||
841 | + | ||
842 | + spin_lock(&obj->page_table_lock); | ||
843 | + | ||
844 | + bytes = iopgtable_clear_entry_core(obj, da); | ||
845 | + flush_iotlb_page(obj, da); | ||
846 | + | ||
847 | + spin_unlock(&obj->page_table_lock); | ||
848 | + | ||
849 | + return bytes; | ||
850 | +} | ||
851 | +EXPORT_SYMBOL_GPL(iopgtable_clear_entry); | ||
852 | + | ||
853 | +static void iopgtable_clear_entry_all(struct iommu *obj) | ||
854 | +{ | ||
855 | + int i; | ||
856 | + | ||
857 | + spin_lock(&obj->page_table_lock); | ||
858 | + | ||
859 | + for (i = 0; i < PTRS_PER_IOPGD; i++) { | ||
860 | + u32 da; | ||
861 | + u32 *iopgd; | ||
862 | + | ||
863 | + da = i << IOPGD_SHIFT; | ||
864 | + iopgd = iopgd_offset(obj, da); | ||
865 | + | ||
866 | + if (!*iopgd) | ||
867 | + continue; | ||
868 | + | ||
869 | + if (*iopgd & IOPGD_TABLE) | ||
870 | + iopte_free(iopte_offset(iopgd, 0)); | ||
871 | + | ||
872 | + *iopgd = 0; | ||
873 | + flush_iopgd_range(iopgd, iopgd); | ||
874 | + } | ||
875 | + | ||
876 | + flush_iotlb_all(obj); | ||
877 | + | ||
878 | + spin_unlock(&obj->page_table_lock); | ||
879 | +} | ||
880 | + | ||
881 | +/* | ||
882 | + * Device IOMMU generic operations | ||
883 | + */ | ||
884 | +static irqreturn_t iommu_fault_handler(int irq, void *data) | ||
885 | +{ | ||
886 | + u32 stat, da; | ||
887 | + u32 *iopgd, *iopte; | ||
888 | + int err = -EIO; | ||
889 | + struct iommu *obj = data; | ||
890 | + | ||
891 | + /* Dynamic loading TLB or PTE */ | ||
892 | + if (obj->isr) | ||
893 | + err = obj->isr(obj); | ||
894 | + | ||
895 | + if (!err) | ||
896 | + return IRQ_HANDLED; | ||
897 | + | ||
898 | + stat = iommu_report_fault(obj, &da); | ||
899 | + if (!stat) | ||
900 | + return IRQ_HANDLED; | ||
901 | + | ||
902 | + iopgd = iopgd_offset(obj, da); | ||
903 | + | ||
904 | + if (!(*iopgd & IOPGD_TABLE)) { | ||
905 | + dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__, | ||
906 | + da, iopgd, *iopgd); | ||
907 | + return IRQ_NONE; | ||
908 | + } | ||
909 | + | ||
910 | + iopte = iopte_offset(iopgd, da); | ||
911 | + | ||
912 | + dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | ||
913 | + __func__, da, iopgd, *iopgd, iopte, *iopte); | ||
914 | + | ||
915 | + dump_tlb_entries(obj); | ||
916 | + | ||
917 | + return IRQ_NONE; | ||
918 | +} | ||
919 | + | ||
920 | +static int device_match_by_alias(struct device *dev, void *data) | ||
921 | +{ | ||
922 | + struct iommu *obj = to_iommu(dev); | ||
923 | + const char *name = data; | ||
924 | + | ||
925 | + pr_debug("%s: %s %s\n", __func__, obj->name, name); | ||
926 | + | ||
927 | + return strcmp(obj->name, name) == 0; | ||
928 | +} | ||
929 | + | ||
930 | +/** | ||
931 | + * iommu_put() - Get iommu handler | ||
932 | + * @name: target iommu name | ||
933 | + **/ | ||
934 | +struct iommu *iommu_get(const char *name) | ||
935 | +{ | ||
936 | + int err = -ENOMEM; | ||
937 | + struct device *dev; | ||
938 | + struct iommu *obj; | ||
939 | + | ||
940 | + dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, | ||
941 | + device_match_by_alias); | ||
942 | + if (!dev) | ||
943 | + return ERR_PTR(-ENODEV); | ||
944 | + | ||
945 | + obj = to_iommu(dev); | ||
946 | + | ||
947 | + mutex_lock(&obj->iommu_lock); | ||
948 | + | ||
949 | + if (obj->refcount++ == 0) { | ||
950 | + err = iommu_enable(obj); | ||
951 | + if (err) | ||
952 | + goto err_enable; | ||
953 | + flush_iotlb_all(obj); | ||
954 | + } | ||
955 | + | ||
956 | + if (!try_module_get(obj->owner)) | ||
957 | + goto err_module; | ||
958 | + | ||
959 | + mutex_unlock(&obj->iommu_lock); | ||
960 | + | ||
961 | + dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | ||
962 | + return obj; | ||
963 | + | ||
964 | +err_module: | ||
965 | + if (obj->refcount == 1) | ||
966 | + iommu_disable(obj); | ||
967 | +err_enable: | ||
968 | + mutex_unlock(&obj->iommu_lock); | ||
969 | + return ERR_PTR(err); | ||
970 | +} | ||
971 | +EXPORT_SYMBOL_GPL(iommu_get); | ||
972 | + | ||
973 | +/** | ||
974 | + * iommu_put() - Put back iommu handler | ||
975 | + * @obj: target iommu | ||
976 | + **/ | ||
977 | +void iommu_put(struct iommu *obj) | ||
978 | +{ | ||
979 | + if (!obj && IS_ERR(obj)) | ||
980 | + return; | ||
981 | + | ||
982 | + mutex_lock(&obj->iommu_lock); | ||
983 | + | ||
984 | + if (--obj->refcount == 0) | ||
985 | + iommu_disable(obj); | ||
986 | + | ||
987 | + module_put(obj->owner); | ||
988 | + | ||
989 | + mutex_unlock(&obj->iommu_lock); | ||
990 | + | ||
991 | + dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | ||
992 | +} | ||
993 | +EXPORT_SYMBOL_GPL(iommu_put); | ||
994 | + | ||
995 | +/* | ||
996 | + * OMAP Device MMU(IOMMU) detection | ||
997 | + */ | ||
998 | +static int __devinit omap_iommu_probe(struct platform_device *pdev) | ||
999 | +{ | ||
1000 | + int err = -ENODEV; | ||
1001 | + void *p; | ||
1002 | + int irq; | ||
1003 | + struct iommu *obj; | ||
1004 | + struct resource *res; | ||
1005 | + struct iommu_platform_data *pdata = pdev->dev.platform_data; | ||
1006 | + | ||
1007 | + if (pdev->num_resources != 2) | ||
1008 | + return -EINVAL; | ||
1009 | + | ||
1010 | + obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); | ||
1011 | + if (!obj) | ||
1012 | + return -ENOMEM; | ||
1013 | + | ||
1014 | + obj->clk = clk_get(&pdev->dev, pdata->clk_name); | ||
1015 | + if (IS_ERR(obj->clk)) | ||
1016 | + goto err_clk; | ||
1017 | + | ||
1018 | + obj->nr_tlb_entries = pdata->nr_tlb_entries; | ||
1019 | + obj->name = pdata->name; | ||
1020 | + obj->dev = &pdev->dev; | ||
1021 | + obj->ctx = (void *)obj + sizeof(*obj); | ||
1022 | + | ||
1023 | + mutex_init(&obj->iommu_lock); | ||
1024 | + mutex_init(&obj->mmap_lock); | ||
1025 | + spin_lock_init(&obj->page_table_lock); | ||
1026 | + INIT_LIST_HEAD(&obj->mmap); | ||
1027 | + | ||
1028 | + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1029 | + if (!res) { | ||
1030 | + err = -ENODEV; | ||
1031 | + goto err_mem; | ||
1032 | + } | ||
1033 | + obj->regbase = ioremap(res->start, resource_size(res)); | ||
1034 | + if (!obj->regbase) { | ||
1035 | + err = -ENOMEM; | ||
1036 | + goto err_mem; | ||
1037 | + } | ||
1038 | + | ||
1039 | + res = request_mem_region(res->start, resource_size(res), | ||
1040 | + dev_name(&pdev->dev)); | ||
1041 | + if (!res) { | ||
1042 | + err = -EIO; | ||
1043 | + goto err_mem; | ||
1044 | + } | ||
1045 | + | ||
1046 | + irq = platform_get_irq(pdev, 0); | ||
1047 | + if (irq < 0) { | ||
1048 | + err = -ENODEV; | ||
1049 | + goto err_irq; | ||
1050 | + } | ||
1051 | + err = request_irq(irq, iommu_fault_handler, IRQF_SHARED, | ||
1052 | + dev_name(&pdev->dev), obj); | ||
1053 | + if (err < 0) | ||
1054 | + goto err_irq; | ||
1055 | + platform_set_drvdata(pdev, obj); | ||
1056 | + | ||
1057 | + p = (void *)__get_free_pages(GFP_KERNEL, get_order(IOPGD_TABLE_SIZE)); | ||
1058 | + if (!p) { | ||
1059 | + err = -ENOMEM; | ||
1060 | + goto err_pgd; | ||
1061 | + } | ||
1062 | + memset(p, 0, IOPGD_TABLE_SIZE); | ||
1063 | + clean_dcache_area(p, IOPGD_TABLE_SIZE); | ||
1064 | + obj->iopgd = p; | ||
1065 | + | ||
1066 | + BUG_ON(!IS_ALIGNED((unsigned long)obj->iopgd, IOPGD_TABLE_SIZE)); | ||
1067 | + | ||
1068 | + dev_info(&pdev->dev, "%s registered\n", obj->name); | ||
1069 | + return 0; | ||
1070 | + | ||
1071 | +err_pgd: | ||
1072 | + free_irq(irq, obj); | ||
1073 | +err_irq: | ||
1074 | + release_mem_region(res->start, resource_size(res)); | ||
1075 | + iounmap(obj->regbase); | ||
1076 | +err_mem: | ||
1077 | + clk_put(obj->clk); | ||
1078 | +err_clk: | ||
1079 | + kfree(obj); | ||
1080 | + return err; | ||
1081 | +} | ||
1082 | + | ||
1083 | +static int __devexit omap_iommu_remove(struct platform_device *pdev) | ||
1084 | +{ | ||
1085 | + int irq; | ||
1086 | + struct resource *res; | ||
1087 | + struct iommu *obj = platform_get_drvdata(pdev); | ||
1088 | + | ||
1089 | + platform_set_drvdata(pdev, NULL); | ||
1090 | + | ||
1091 | + iopgtable_clear_entry_all(obj); | ||
1092 | + free_pages((unsigned long)obj->iopgd, get_order(IOPGD_TABLE_SIZE)); | ||
1093 | + | ||
1094 | + irq = platform_get_irq(pdev, 0); | ||
1095 | + free_irq(irq, obj); | ||
1096 | + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1097 | + release_mem_region(res->start, resource_size(res)); | ||
1098 | + iounmap(obj->regbase); | ||
1099 | + | ||
1100 | + clk_put(obj->clk); | ||
1101 | + dev_info(&pdev->dev, "%s removed\n", obj->name); | ||
1102 | + kfree(obj); | ||
1103 | + return 0; | ||
1104 | +} | ||
1105 | + | ||
1106 | +static struct platform_driver omap_iommu_driver = { | ||
1107 | + .probe = omap_iommu_probe, | ||
1108 | + .remove = __devexit_p(omap_iommu_remove), | ||
1109 | + .driver = { | ||
1110 | + .name = "omap-iommu", | ||
1111 | + }, | ||
1112 | +}; | ||
1113 | + | ||
1114 | +static void iopte_cachep_ctor(void *iopte) | ||
1115 | +{ | ||
1116 | + clean_dcache_area(iopte, IOPTE_TABLE_SIZE); | ||
1117 | +} | ||
1118 | + | ||
1119 | +static int __init omap_iommu_init(void) | ||
1120 | +{ | ||
1121 | + struct kmem_cache *p; | ||
1122 | + const unsigned long flags = SLAB_HWCACHE_ALIGN; | ||
1123 | + | ||
1124 | + p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, 0, flags, | ||
1125 | + iopte_cachep_ctor); | ||
1126 | + if (!p) | ||
1127 | + return -ENOMEM; | ||
1128 | + iopte_cachep = p; | ||
1129 | + | ||
1130 | + return platform_driver_register(&omap_iommu_driver); | ||
1131 | +} | ||
1132 | +module_init(omap_iommu_init); | ||
1133 | + | ||
1134 | +static void __exit omap_iommu_exit(void) | ||
1135 | +{ | ||
1136 | + kmem_cache_destroy(iopte_cachep); | ||
1137 | + | ||
1138 | + platform_driver_unregister(&omap_iommu_driver); | ||
1139 | +} | ||
1140 | +module_exit(omap_iommu_exit); | ||
1141 | + | ||
1142 | +MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); | ||
1143 | +MODULE_ALIAS("platform:omap-iommu"); | ||
1144 | +MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | ||
1145 | +MODULE_LICENSE("GPL v2"); | ||
1146 | diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h | ||
1147 | new file mode 100644 | ||
1148 | index 0000000..37dac43 | ||
1149 | --- /dev/null | ||
1150 | +++ b/arch/arm/plat-omap/iopgtable.h | ||
1151 | @@ -0,0 +1,72 @@ | ||
1152 | +/* | ||
1153 | + * omap iommu: pagetable definitions | ||
1154 | + * | ||
1155 | + * Copyright (C) 2008-2009 Nokia Corporation | ||
1156 | + * | ||
1157 | + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
1158 | + * | ||
1159 | + * This program is free software; you can redistribute it and/or modify | ||
1160 | + * it under the terms of the GNU General Public License version 2 as | ||
1161 | + * published by the Free Software Foundation. | ||
1162 | + */ | ||
1163 | + | ||
1164 | +#ifndef __PLAT_OMAP_IOMMU_H | ||
1165 | +#define __PLAT_OMAP_IOMMU_H | ||
1166 | + | ||
1167 | +#define IOPGD_SHIFT 20 | ||
1168 | +#define IOPGD_SIZE (1 << IOPGD_SHIFT) | ||
1169 | +#define IOPGD_MASK (~(IOPGD_SIZE - 1)) | ||
1170 | +#define IOSECTION_MASK IOPGD_MASK | ||
1171 | +#define PTRS_PER_IOPGD (1 << (32 - IOPGD_SHIFT)) | ||
1172 | +#define IOPGD_TABLE_SIZE (PTRS_PER_IOPGD * sizeof(u32)) | ||
1173 | + | ||
1174 | +#define IOSUPER_SIZE (IOPGD_SIZE << 4) | ||
1175 | +#define IOSUPER_MASK (~(IOSUPER_SIZE - 1)) | ||
1176 | + | ||
1177 | +#define IOPTE_SHIFT 12 | ||
1178 | +#define IOPTE_SIZE (1 << IOPTE_SHIFT) | ||
1179 | +#define IOPTE_MASK (~(IOPTE_SIZE - 1)) | ||
1180 | +#define IOPAGE_MASK IOPTE_MASK | ||
1181 | +#define PTRS_PER_IOPTE (1 << (IOPGD_SHIFT - IOPTE_SHIFT)) | ||
1182 | +#define IOPTE_TABLE_SIZE (PTRS_PER_IOPTE * sizeof(u32)) | ||
1183 | + | ||
1184 | +#define IOLARGE_SIZE (IOPTE_SIZE << 4) | ||
1185 | +#define IOLARGE_MASK (~(IOLARGE_SIZE - 1)) | ||
1186 | + | ||
1187 | +#define IOPGD_TABLE (1 << 0) | ||
1188 | +#define IOPGD_SECTION (2 << 0) | ||
1189 | +#define IOPGD_SUPER (1 << 18 | 2 << 0) | ||
1190 | + | ||
1191 | +#define IOPTE_SMALL (2 << 0) | ||
1192 | +#define IOPTE_LARGE (1 << 0) | ||
1193 | + | ||
1194 | +#define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1)) | ||
1195 | +#define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da)) | ||
1196 | + | ||
1197 | +#define iopte_paddr(iopgd) (*iopgd & ~((1 << 10) - 1)) | ||
1198 | +#define iopte_vaddr(iopgd) ((u32 *)phys_to_virt(iopte_paddr(iopgd))) | ||
1199 | + | ||
1200 | +#define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1)) | ||
1201 | +#define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da)) | ||
1202 | + | ||
1203 | +static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, | ||
1204 | + u32 flags) | ||
1205 | +{ | ||
1206 | + memset(e, 0, sizeof(*e)); | ||
1207 | + | ||
1208 | + e->da = da; | ||
1209 | + e->pa = pa; | ||
1210 | + e->valid = 1; | ||
1211 | + /* FIXME: add OMAP1 support */ | ||
1212 | + e->pgsz = flags & MMU_CAM_PGSZ_MASK; | ||
1213 | + e->endian = flags & MMU_RAM_ENDIAN_MASK; | ||
1214 | + e->elsz = flags & MMU_RAM_ELSZ_MASK; | ||
1215 | + e->mixed = flags & MMU_RAM_MIXED_MASK; | ||
1216 | + | ||
1217 | + return iopgsz_to_bytes(e->pgsz); | ||
1218 | +} | ||
1219 | + | ||
1220 | +#define to_iommu(dev) \ | ||
1221 | + (struct iommu *)platform_get_drvdata(to_platform_device(dev)) | ||
1222 | + | ||
1223 | +#endif /* __PLAT_OMAP_IOMMU_H */ | ||
1224 | -- | ||
1225 | 1.5.6.5 | ||
1226 | |||
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0002-omap-iommu-omap2-architecture-specific-functions.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0002-omap-iommu-omap2-architecture-specific-functions.patch new file mode 100644 index 0000000000..d5f78dd14e --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0002-omap-iommu-omap2-architecture-specific-functions.patch | |||
@@ -0,0 +1,453 @@ | |||
1 | From c79d7959c45f40e47520aa6acd54c19094754787 Mon Sep 17 00:00:00 2001 | ||
2 | From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
3 | Date: Mon, 26 Jan 2009 15:13:45 +0200 | ||
4 | Subject: [PATCH] omap iommu: omap2 architecture specific functions | ||
5 | |||
6 | The structure 'arch_mmu' accommodates the difference between omap1 and | ||
7 | omap2/3. | ||
8 | |||
9 | This patch provides omap2/3 specific functions | ||
10 | |||
11 | Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
12 | --- | ||
13 | arch/arm/mach-omap2/iommu2.c | 326 ++++++++++++++++++++++++++++++ | ||
14 | arch/arm/plat-omap/include/mach/iommu2.h | 94 +++++++++ | ||
15 | 2 files changed, 420 insertions(+), 0 deletions(-) | ||
16 | create mode 100644 arch/arm/mach-omap2/iommu2.c | ||
17 | create mode 100644 arch/arm/plat-omap/include/mach/iommu2.h | ||
18 | |||
19 | diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c | ||
20 | new file mode 100644 | ||
21 | index 0000000..88a44f1 | ||
22 | --- /dev/null | ||
23 | +++ b/arch/arm/mach-omap2/iommu2.c | ||
24 | @@ -0,0 +1,326 @@ | ||
25 | +/* | ||
26 | + * omap iommu: omap2/3 architecture specific functions | ||
27 | + * | ||
28 | + * Copyright (C) 2008-2009 Nokia Corporation | ||
29 | + * | ||
30 | + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | ||
31 | + * Paul Mundt and Toshihiro Kobayashi | ||
32 | + * | ||
33 | + * This program is free software; you can redistribute it and/or modify | ||
34 | + * it under the terms of the GNU General Public License version 2 as | ||
35 | + * published by the Free Software Foundation. | ||
36 | + */ | ||
37 | + | ||
38 | +#include <linux/err.h> | ||
39 | +#include <linux/device.h> | ||
40 | +#include <linux/jiffies.h> | ||
41 | +#include <linux/module.h> | ||
42 | +#include <linux/stringify.h> | ||
43 | + | ||
44 | +#include <asm/io.h> | ||
45 | + | ||
46 | +#include <mach/iommu.h> | ||
47 | +#include <mach/iommu2.h> | ||
48 | + | ||
49 | +/* | ||
50 | + * omap2 architecture specific register bit definitions | ||
51 | + */ | ||
52 | +#define IOMMU_ARCH_VERSION 0x00000011 | ||
53 | + | ||
54 | +/* SYSCONF */ | ||
55 | +#define MMU_SYS_IDLE_SHIFT 3 | ||
56 | +#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT) | ||
57 | +#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT) | ||
58 | +#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT) | ||
59 | +#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT) | ||
60 | + | ||
61 | +#define MMU_SYS_SOFTRESET (1 << 1) | ||
62 | +#define MMU_SYS_AUTOIDLE 1 | ||
63 | + | ||
64 | +/* SYSSTATUS */ | ||
65 | +#define MMU_SYS_RESETDONE 1 | ||
66 | + | ||
67 | +/* IRQSTATUS & IRQENABLE */ | ||
68 | +#define MMU_IRQ_MULTIHITFAULT (1 << 4) | ||
69 | +#define MMU_IRQ_TABLEWALKFAULT (1 << 3) | ||
70 | +#define MMU_IRQ_EMUMISS (1 << 2) | ||
71 | +#define MMU_IRQ_TRANSLATIONFAULT (1 << 1) | ||
72 | +#define MMU_IRQ_TLBMISS (1 << 0) | ||
73 | +#define MMU_IRQ_MASK \ | ||
74 | + (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \ | ||
75 | + MMU_IRQ_TRANSLATIONFAULT) | ||
76 | + | ||
77 | +/* MMU_CNTL */ | ||
78 | +#define MMU_CNTL_SHIFT 1 | ||
79 | +#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT) | ||
80 | +#define MMU_CNTL_EML_TLB (1 << 3) | ||
81 | +#define MMU_CNTL_TWL_EN (1 << 2) | ||
82 | +#define MMU_CNTL_MMU_EN (1 << 1) | ||
83 | + | ||
84 | +#define get_cam_va_mask(pgsz) \ | ||
85 | + (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \ | ||
86 | + ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \ | ||
87 | + ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ | ||
88 | + ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) | ||
89 | + | ||
90 | +static int omap2_iommu_enable(struct iommu *obj) | ||
91 | +{ | ||
92 | + u32 l, pa; | ||
93 | + unsigned long timeout; | ||
94 | + | ||
95 | + if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) | ||
96 | + return -EINVAL; | ||
97 | + | ||
98 | + pa = virt_to_phys(obj->iopgd); | ||
99 | + if (!IS_ALIGNED(pa, SZ_16K)) | ||
100 | + return -EINVAL; | ||
101 | + | ||
102 | + iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG); | ||
103 | + | ||
104 | + timeout = jiffies + msecs_to_jiffies(20); | ||
105 | + do { | ||
106 | + l = iommu_read_reg(obj, MMU_SYSSTATUS); | ||
107 | + if (l & MMU_SYS_RESETDONE) | ||
108 | + break; | ||
109 | + } while (time_after(jiffies, timeout)); | ||
110 | + | ||
111 | + if (!(l & MMU_SYS_RESETDONE)) { | ||
112 | + dev_err(obj->dev, "can't take mmu out of reset\n"); | ||
113 | + return -ENODEV; | ||
114 | + } | ||
115 | + | ||
116 | + l = iommu_read_reg(obj, MMU_REVISION); | ||
117 | + dev_info(obj->dev, "%s: version %d.%d\n", obj->name, | ||
118 | + (l >> 4) & 0xf, l & 0xf); | ||
119 | + | ||
120 | + l = iommu_read_reg(obj, MMU_SYSCONFIG); | ||
121 | + l &= ~MMU_SYS_IDLE_MASK; | ||
122 | + l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); | ||
123 | + iommu_write_reg(obj, l, MMU_SYSCONFIG); | ||
124 | + | ||
125 | + iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE); | ||
126 | + iommu_write_reg(obj, pa, MMU_TTB); | ||
127 | + | ||
128 | + l = iommu_read_reg(obj, MMU_CNTL); | ||
129 | + l &= ~MMU_CNTL_MASK; | ||
130 | + l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); | ||
131 | + iommu_write_reg(obj, l, MMU_CNTL); | ||
132 | + | ||
133 | + return 0; | ||
134 | +} | ||
135 | + | ||
136 | +static void omap2_iommu_disable(struct iommu *obj) | ||
137 | +{ | ||
138 | + u32 l = iommu_read_reg(obj, MMU_CNTL); | ||
139 | + | ||
140 | + l &= ~MMU_CNTL_MASK; | ||
141 | + iommu_write_reg(obj, l, MMU_CNTL); | ||
142 | + iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG); | ||
143 | + | ||
144 | + dev_dbg(obj->dev, "%s is shutting down\n", obj->name); | ||
145 | +} | ||
146 | + | ||
147 | +static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) | ||
148 | +{ | ||
149 | + int i; | ||
150 | + u32 stat, da; | ||
151 | + const char *err_msg[] = { | ||
152 | + "tlb miss", | ||
153 | + "translation fault", | ||
154 | + "emulation miss", | ||
155 | + "table walk fault", | ||
156 | + "multi hit fault", | ||
157 | + }; | ||
158 | + | ||
159 | + stat = iommu_read_reg(obj, MMU_IRQSTATUS); | ||
160 | + stat &= MMU_IRQ_MASK; | ||
161 | + if (!stat) | ||
162 | + return 0; | ||
163 | + | ||
164 | + da = iommu_read_reg(obj, MMU_FAULT_AD); | ||
165 | + *ra = da; | ||
166 | + | ||
167 | + dev_err(obj->dev, "%s:\tda:%08x ", __func__, da); | ||
168 | + | ||
169 | + for (i = 0; i < ARRAY_SIZE(err_msg); i++) { | ||
170 | + if (stat & (1 << i)) | ||
171 | + printk("%s ", err_msg[i]); | ||
172 | + } | ||
173 | + printk("\n"); | ||
174 | + | ||
175 | + iommu_write_reg(obj, stat, MMU_IRQSTATUS); | ||
176 | + return stat; | ||
177 | +} | ||
178 | + | ||
179 | +static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr) | ||
180 | +{ | ||
181 | + cr->cam = iommu_read_reg(obj, MMU_READ_CAM); | ||
182 | + cr->ram = iommu_read_reg(obj, MMU_READ_RAM); | ||
183 | +} | ||
184 | + | ||
185 | +static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr) | ||
186 | +{ | ||
187 | + iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); | ||
188 | + iommu_write_reg(obj, cr->ram, MMU_RAM); | ||
189 | +} | ||
190 | + | ||
191 | +static u32 omap2_cr_to_virt(struct cr_regs *cr) | ||
192 | +{ | ||
193 | + u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; | ||
194 | + u32 mask = get_cam_va_mask(cr->cam & page_size); | ||
195 | + | ||
196 | + return cr->cam & mask; | ||
197 | +} | ||
198 | + | ||
199 | +static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e) | ||
200 | +{ | ||
201 | + struct cr_regs *cr; | ||
202 | + | ||
203 | + if (e->da & ~(get_cam_va_mask(e->pgsz))) { | ||
204 | + dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, | ||
205 | + e->da); | ||
206 | + return ERR_PTR(-EINVAL); | ||
207 | + } | ||
208 | + | ||
209 | + cr = kmalloc(sizeof(*cr), GFP_KERNEL); | ||
210 | + if (!cr) | ||
211 | + return ERR_PTR(-ENOMEM); | ||
212 | + | ||
213 | + cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz; | ||
214 | + cr->ram = e->pa | e->endian | e->elsz | e->mixed; | ||
215 | + | ||
216 | + return cr; | ||
217 | +} | ||
218 | + | ||
219 | +static inline int omap2_cr_valid(struct cr_regs *cr) | ||
220 | +{ | ||
221 | + return cr->cam & MMU_CAM_V; | ||
222 | +} | ||
223 | + | ||
224 | +static u32 omap2_get_pte_attr(struct iotlb_entry *e) | ||
225 | +{ | ||
226 | + u32 attr; | ||
227 | + | ||
228 | + attr = e->mixed << 5; | ||
229 | + attr |= e->endian; | ||
230 | + attr |= e->elsz >> 3; | ||
231 | + attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6); | ||
232 | + | ||
233 | + return attr; | ||
234 | +} | ||
235 | + | ||
236 | +static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf) | ||
237 | +{ | ||
238 | + char *p = buf; | ||
239 | + | ||
240 | + /* FIXME: Need more detail analysis of cam/ram */ | ||
241 | + p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram); | ||
242 | + | ||
243 | + return p - buf; | ||
244 | +} | ||
245 | + | ||
246 | +#define pr_reg(name) \ | ||
247 | + p += sprintf(p, "%20s: %08x\n", \ | ||
248 | + __stringify(name), iommu_read_reg(obj, MMU_##name)); | ||
249 | + | ||
250 | +static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf) | ||
251 | +{ | ||
252 | + char *p = buf; | ||
253 | + | ||
254 | + pr_reg(REVISION); | ||
255 | + pr_reg(SYSCONFIG); | ||
256 | + pr_reg(SYSSTATUS); | ||
257 | + pr_reg(IRQSTATUS); | ||
258 | + pr_reg(IRQENABLE); | ||
259 | + pr_reg(WALKING_ST); | ||
260 | + pr_reg(CNTL); | ||
261 | + pr_reg(FAULT_AD); | ||
262 | + pr_reg(TTB); | ||
263 | + pr_reg(LOCK); | ||
264 | + pr_reg(LD_TLB); | ||
265 | + pr_reg(CAM); | ||
266 | + pr_reg(RAM); | ||
267 | + pr_reg(GFLUSH); | ||
268 | + pr_reg(FLUSH_ENTRY); | ||
269 | + pr_reg(READ_CAM); | ||
270 | + pr_reg(READ_RAM); | ||
271 | + pr_reg(EMU_FAULT_AD); | ||
272 | + | ||
273 | + return p - buf; | ||
274 | +} | ||
275 | + | ||
276 | +static void omap2_iommu_save_ctx(struct iommu *obj) | ||
277 | +{ | ||
278 | + int i; | ||
279 | + u32 *p = obj->ctx; | ||
280 | + | ||
281 | + for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { | ||
282 | + p[i] = iommu_read_reg(obj, i * sizeof(u32)); | ||
283 | + dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); | ||
284 | + } | ||
285 | + | ||
286 | + BUG_ON(p[0] != IOMMU_ARCH_VERSION); | ||
287 | +} | ||
288 | + | ||
289 | +static void omap2_iommu_restore_ctx(struct iommu *obj) | ||
290 | +{ | ||
291 | + int i; | ||
292 | + u32 *p = obj->ctx; | ||
293 | + | ||
294 | + for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { | ||
295 | + iommu_write_reg(obj, p[i], i * sizeof(u32)); | ||
296 | + dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); | ||
297 | + } | ||
298 | + | ||
299 | + BUG_ON(p[0] != IOMMU_ARCH_VERSION); | ||
300 | +} | ||
301 | + | ||
302 | +static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) | ||
303 | +{ | ||
304 | + e->da = cr->cam & MMU_CAM_VATAG_MASK; | ||
305 | + e->pa = cr->ram & MMU_RAM_PADDR_MASK; | ||
306 | + e->valid = cr->cam & MMU_CAM_V; | ||
307 | + e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK; | ||
308 | + e->endian = cr->ram & MMU_RAM_ENDIAN_MASK; | ||
309 | + e->elsz = cr->ram & MMU_RAM_ELSZ_MASK; | ||
310 | + e->mixed = cr->ram & MMU_RAM_MIXED; | ||
311 | +} | ||
312 | + | ||
313 | +static const struct iommu_functions omap2_iommu_ops = { | ||
314 | + .version = IOMMU_ARCH_VERSION, | ||
315 | + | ||
316 | + .enable = omap2_iommu_enable, | ||
317 | + .disable = omap2_iommu_disable, | ||
318 | + .fault_isr = omap2_iommu_fault_isr, | ||
319 | + | ||
320 | + .tlb_read_cr = omap2_tlb_read_cr, | ||
321 | + .tlb_load_cr = omap2_tlb_load_cr, | ||
322 | + | ||
323 | + .cr_to_e = omap2_cr_to_e, | ||
324 | + .cr_to_virt = omap2_cr_to_virt, | ||
325 | + .alloc_cr = omap2_alloc_cr, | ||
326 | + .cr_valid = omap2_cr_valid, | ||
327 | + .dump_cr = omap2_dump_cr, | ||
328 | + | ||
329 | + .get_pte_attr = omap2_get_pte_attr, | ||
330 | + | ||
331 | + .save_ctx = omap2_iommu_save_ctx, | ||
332 | + .restore_ctx = omap2_iommu_restore_ctx, | ||
333 | + .dump_ctx = omap2_iommu_dump_ctx, | ||
334 | +}; | ||
335 | + | ||
336 | +static int __init omap2_iommu_init(void) | ||
337 | +{ | ||
338 | + return install_iommu_arch(&omap2_iommu_ops); | ||
339 | +} | ||
340 | +module_init(omap2_iommu_init); | ||
341 | + | ||
342 | +static void __exit omap2_iommu_exit(void) | ||
343 | +{ | ||
344 | + uninstall_iommu_arch(&omap2_iommu_ops); | ||
345 | +} | ||
346 | +module_exit(omap2_iommu_exit); | ||
347 | + | ||
348 | +MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | ||
349 | +MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions"); | ||
350 | +MODULE_LICENSE("GPL v2"); | ||
351 | diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/mach/iommu2.h | ||
352 | new file mode 100644 | ||
353 | index 0000000..d746047 | ||
354 | --- /dev/null | ||
355 | +++ b/arch/arm/plat-omap/include/mach/iommu2.h | ||
356 | @@ -0,0 +1,94 @@ | ||
357 | +/* | ||
358 | + * omap iommu: omap2 architecture specific definitions | ||
359 | + * | ||
360 | + * Copyright (C) 2008-2009 Nokia Corporation | ||
361 | + * | ||
362 | + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
363 | + * | ||
364 | + * This program is free software; you can redistribute it and/or modify | ||
365 | + * it under the terms of the GNU General Public License version 2 as | ||
366 | + * published by the Free Software Foundation. | ||
367 | + */ | ||
368 | + | ||
369 | +#ifndef __MACH_IOMMU2_H | ||
370 | +#define __MACH_IOMMU2_H | ||
371 | + | ||
372 | +/* | ||
373 | + * MMU Register offsets | ||
374 | + */ | ||
375 | +#define MMU_REVISION 0x00 | ||
376 | +#define MMU_SYSCONFIG 0x10 | ||
377 | +#define MMU_SYSSTATUS 0x14 | ||
378 | +#define MMU_IRQSTATUS 0x18 | ||
379 | +#define MMU_IRQENABLE 0x1c | ||
380 | +#define MMU_WALKING_ST 0x40 | ||
381 | +#define MMU_CNTL 0x44 | ||
382 | +#define MMU_FAULT_AD 0x48 | ||
383 | +#define MMU_TTB 0x4c | ||
384 | +#define MMU_LOCK 0x50 | ||
385 | +#define MMU_LD_TLB 0x54 | ||
386 | +#define MMU_CAM 0x58 | ||
387 | +#define MMU_RAM 0x5c | ||
388 | +#define MMU_GFLUSH 0x60 | ||
389 | +#define MMU_FLUSH_ENTRY 0x64 | ||
390 | +#define MMU_READ_CAM 0x68 | ||
391 | +#define MMU_READ_RAM 0x6c | ||
392 | +#define MMU_EMU_FAULT_AD 0x70 | ||
393 | + | ||
394 | +#define MMU_REG_SIZE 256 | ||
395 | + | ||
396 | +/* | ||
397 | + * MMU Register bit definitions | ||
398 | + */ | ||
399 | +#define MMU_LOCK_BASE_SHIFT 10 | ||
400 | +#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) | ||
401 | +#define MMU_LOCK_BASE(x) \ | ||
402 | + ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) | ||
403 | + | ||
404 | +#define MMU_LOCK_VICT_SHIFT 4 | ||
405 | +#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) | ||
406 | +#define MMU_LOCK_VICT(x) \ | ||
407 | + ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) | ||
408 | + | ||
409 | +#define MMU_CAM_VATAG_SHIFT 12 | ||
410 | +#define MMU_CAM_VATAG_MASK \ | ||
411 | + ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT) | ||
412 | +#define MMU_CAM_P (1 << 3) | ||
413 | +#define MMU_CAM_V (1 << 2) | ||
414 | +#define MMU_CAM_PGSZ_MASK 3 | ||
415 | +#define MMU_CAM_PGSZ_1M (0 << 0) | ||
416 | +#define MMU_CAM_PGSZ_64K (1 << 0) | ||
417 | +#define MMU_CAM_PGSZ_4K (2 << 0) | ||
418 | +#define MMU_CAM_PGSZ_16M (3 << 0) | ||
419 | + | ||
420 | +#define MMU_RAM_PADDR_SHIFT 12 | ||
421 | +#define MMU_RAM_PADDR_MASK \ | ||
422 | + ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT) | ||
423 | +#define MMU_RAM_ENDIAN_SHIFT 9 | ||
424 | +#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT) | ||
425 | +#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT) | ||
426 | +#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT) | ||
427 | +#define MMU_RAM_ELSZ_SHIFT 7 | ||
428 | +#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT) | ||
429 | +#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT) | ||
430 | +#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT) | ||
431 | +#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT) | ||
432 | +#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT) | ||
433 | +#define MMU_RAM_MIXED_SHIFT 6 | ||
434 | +#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT) | ||
435 | +#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK | ||
436 | + | ||
437 | +/* | ||
438 | + * register accessors | ||
439 | + */ | ||
440 | +static inline u32 iommu_read_reg(struct iommu *obj, size_t offs) | ||
441 | +{ | ||
442 | + return __raw_readl(obj->regbase + offs); | ||
443 | +} | ||
444 | + | ||
445 | +static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs) | ||
446 | +{ | ||
447 | + __raw_writel(val, obj->regbase + offs); | ||
448 | +} | ||
449 | + | ||
450 | +#endif /* __MACH_IOMMU2_H */ | ||
451 | -- | ||
452 | 1.5.6.5 | ||
453 | |||
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0003-omap-iommu-omap3-iommu-device-registration.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0003-omap-iommu-omap3-iommu-device-registration.patch new file mode 100644 index 0000000000..2954c47872 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0003-omap-iommu-omap3-iommu-device-registration.patch | |||
@@ -0,0 +1,124 @@ | |||
1 | From 6a84082597dd322713c5d5951530e3eecb878ad4 Mon Sep 17 00:00:00 2001 | ||
2 | From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
3 | Date: Wed, 28 Jan 2009 21:32:04 +0200 | ||
4 | Subject: [PATCH] omap iommu: omap3 iommu device registration | ||
5 | |||
6 | Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
7 | --- | ||
8 | arch/arm/mach-omap2/omap3-iommu.c | 104 +++++++++++++++++++++++++++++++++++++ | ||
9 | 1 files changed, 104 insertions(+), 0 deletions(-) | ||
10 | create mode 100644 arch/arm/mach-omap2/omap3-iommu.c | ||
11 | |||
12 | diff --git a/arch/arm/mach-omap2/omap3-iommu.c b/arch/arm/mach-omap2/omap3-iommu.c | ||
13 | new file mode 100644 | ||
14 | index 0000000..97481cc | ||
15 | --- /dev/null | ||
16 | +++ b/arch/arm/mach-omap2/omap3-iommu.c | ||
17 | @@ -0,0 +1,104 @@ | ||
18 | +/* | ||
19 | + * omap iommu: omap3 device registration | ||
20 | + * | ||
21 | + * Copyright (C) 2008-2009 Nokia Corporation | ||
22 | + * | ||
23 | + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
24 | + * | ||
25 | + * This program is free software; you can redistribute it and/or modify | ||
26 | + * it under the terms of the GNU General Public License version 2 as | ||
27 | + * published by the Free Software Foundation. | ||
28 | + */ | ||
29 | + | ||
30 | +#include <linux/platform_device.h> | ||
31 | +#include <linux/io.h> | ||
32 | + | ||
33 | +#include <mach/iommu.h> | ||
34 | + | ||
35 | +#define OMAP3_MMU1_BASE 0x480bd400 | ||
36 | +#define OMAP3_MMU2_BASE 0x5d000000 | ||
37 | +#define OMAP3_MMU1_IRQ 24 | ||
38 | +#define OMAP3_MMU2_IRQ 28 | ||
39 | + | ||
40 | +static struct resource omap3_iommu_res[] = { | ||
41 | + { /* Camera ISP MMU */ | ||
42 | + .start = OMAP3_MMU1_BASE, | ||
43 | + .end = OMAP3_MMU1_BASE + MMU_REG_SIZE - 1, | ||
44 | + .flags = IORESOURCE_MEM, | ||
45 | + }, | ||
46 | + { | ||
47 | + .start = OMAP3_MMU1_IRQ, | ||
48 | + .flags = IORESOURCE_IRQ, | ||
49 | + }, | ||
50 | + { /* IVA2.2 MMU */ | ||
51 | + .start = OMAP3_MMU2_BASE, | ||
52 | + .end = OMAP3_MMU2_BASE + MMU_REG_SIZE - 1, | ||
53 | + .flags = IORESOURCE_MEM, | ||
54 | + }, | ||
55 | + { | ||
56 | + .start = OMAP3_MMU2_IRQ, | ||
57 | + .flags = IORESOURCE_IRQ, | ||
58 | + }, | ||
59 | +}; | ||
60 | +#define NR_IOMMU_RES (ARRAY_SIZE(omap3_iommu_res) / 2) | ||
61 | + | ||
62 | +static const struct iommu_platform_data omap3_iommu_pdata[] __initconst = { | ||
63 | + { | ||
64 | + .name = "isp", | ||
65 | + .nr_tlb_entries = 8, | ||
66 | + .clk_name = "cam_ick", | ||
67 | + }, | ||
68 | + { | ||
69 | + .name = "iva2", | ||
70 | + .nr_tlb_entries = 32, | ||
71 | + .clk_name = "iva2_ck", | ||
72 | + }, | ||
73 | +}; | ||
74 | +#define NR_IOMMU_DEVICES ARRAY_SIZE(omap3_iommu_pdata) | ||
75 | + | ||
76 | +static struct platform_device *omap3_iommu_pdev[NR_IOMMU_DEVICES]; | ||
77 | + | ||
78 | +static int __init omap3_iommu_init(void) | ||
79 | +{ | ||
80 | + int i, err; | ||
81 | + | ||
82 | + for (i = 0; i < NR_IOMMU_DEVICES; i++) { | ||
83 | + struct platform_device *pdev; | ||
84 | + | ||
85 | + pdev = platform_device_alloc("omap-iommu", i + 1); | ||
86 | + if (!pdev) | ||
87 | + goto err_out; | ||
88 | + err = platform_device_add_resources(pdev, | ||
89 | + &omap3_iommu_res[2 * i], NR_IOMMU_RES); | ||
90 | + if (err) | ||
91 | + goto err_out; | ||
92 | + err = platform_device_add_data(pdev, &omap3_iommu_pdata[i], | ||
93 | + sizeof(omap3_iommu_pdata[0])); | ||
94 | + if (err) | ||
95 | + goto err_out; | ||
96 | + err = platform_device_add(pdev); | ||
97 | + if (err) | ||
98 | + goto err_out; | ||
99 | + omap3_iommu_pdev[i] = pdev; | ||
100 | + } | ||
101 | + return 0; | ||
102 | + | ||
103 | +err_out: | ||
104 | + while (i--) | ||
105 | + platform_device_put(omap3_iommu_pdev[i]); | ||
106 | + return err; | ||
107 | +} | ||
108 | +module_init(omap3_iommu_init); | ||
109 | + | ||
110 | +static void __exit omap3_iommu_exit(void) | ||
111 | +{ | ||
112 | + int i; | ||
113 | + | ||
114 | + for (i = 0; i < NR_IOMMU_DEVICES; i++) | ||
115 | + platform_device_unregister(omap3_iommu_pdev[i]); | ||
116 | +} | ||
117 | +module_exit(omap3_iommu_exit); | ||
118 | + | ||
119 | +MODULE_AUTHOR("Hiroshi DOYU"); | ||
120 | +MODULE_DESCRIPTION("omap iommu: omap3 device registration"); | ||
121 | +MODULE_LICENSE("GPL v2"); | ||
122 | -- | ||
123 | 1.5.6.5 | ||
124 | |||
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0004-omap-iommu-simple-virtual-address-space-management.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0004-omap-iommu-simple-virtual-address-space-management.patch new file mode 100644 index 0000000000..945778b943 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0004-omap-iommu-simple-virtual-address-space-management.patch | |||
@@ -0,0 +1,1083 @@ | |||
1 | From 07365182b998af3dc2b79e822b8e21a3f50262c4 Mon Sep 17 00:00:00 2001 | ||
2 | From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
3 | Date: Wed, 28 Jan 2009 21:32:08 +0200 | ||
4 | Subject: [PATCH] omap iommu: simple virtual address space management | ||
5 | |||
6 | This patch provides a device drivers, which has a omap iommu, with | ||
7 | address mapping APIs between device virtual address(iommu), physical | ||
8 | address and MPU virtual address. | ||
9 | |||
10 | There are 4 possible patterns for iommu virtual address(iova/da) mapping. | ||
11 | |||
12 | |iova/ mapping iommu_ page | ||
13 | | da pa va (d)-(p)-(v) function type | ||
14 | --------------------------------------------------------------------------- | ||
15 | 1 | c c c 1 - 1 - 1 _kmap() / _kunmap() s | ||
16 | 2 | c c,a c 1 - 1 - 1 _kmalloc()/ _kfree() s | ||
17 | 3 | c d c 1 - n - 1 _vmap() / _vunmap() s | ||
18 | 4 | c d,a c 1 - n - 1 _vmalloc()/ _vfree() n* | ||
19 | |||
20 | 'iova': device iommu virtual address | ||
21 | 'da': alias of 'iova' | ||
22 | 'pa': physical address | ||
23 | 'va': mpu virtual address | ||
24 | |||
25 | 'c': contiguous memory area | ||
26 | 'd': dicontiguous memory area | ||
27 | 'a': anonymous memory allocation | ||
28 | '()': optional feature | ||
29 | |||
30 | 'n': a normal page(4KB) size is used. | ||
31 | 's': multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used. | ||
32 | |||
33 | '*': not yet, but feasible. | ||
34 | |||
35 | Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
36 | --- | ||
37 | arch/arm/include/asm/io.h | 6 + | ||
38 | arch/arm/mm/ioremap.c | 11 + | ||
39 | arch/arm/plat-omap/include/mach/iovmm.h | 94 ++++ | ||
40 | arch/arm/plat-omap/iovmm.c | 891 +++++++++++++++++++++++++++++++ | ||
41 | 4 files changed, 1002 insertions(+), 0 deletions(-) | ||
42 | create mode 100644 arch/arm/plat-omap/include/mach/iovmm.h | ||
43 | create mode 100644 arch/arm/plat-omap/iovmm.c | ||
44 | |||
45 | diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h | ||
46 | index d2a59cf..cbdadfe 100644 | ||
47 | --- a/arch/arm/include/asm/io.h | ||
48 | +++ b/arch/arm/include/asm/io.h | ||
49 | @@ -75,6 +75,12 @@ extern void __iomem * __arm_ioremap(unsigned long, size_t, unsigned int); | ||
50 | extern void __iounmap(volatile void __iomem *addr); | ||
51 | |||
52 | /* | ||
53 | + * external interface to remap single page with appropriate type | ||
54 | + */ | ||
55 | +extern int ioremap_page(unsigned long virt, unsigned long phys, | ||
56 | + unsigned int mtype); | ||
57 | + | ||
58 | +/* | ||
59 | * Bad read/write accesses... | ||
60 | */ | ||
61 | extern void __readwrite_bug(const char *fn); | ||
62 | diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c | ||
63 | index 9f88dd3..8441351 100644 | ||
64 | --- a/arch/arm/mm/ioremap.c | ||
65 | +++ b/arch/arm/mm/ioremap.c | ||
66 | @@ -110,6 +110,17 @@ static int remap_area_pages(unsigned long start, unsigned long pfn, | ||
67 | return err; | ||
68 | } | ||
69 | |||
70 | +int ioremap_page(unsigned long virt, unsigned long phys, unsigned int mtype) | ||
71 | +{ | ||
72 | + const struct mem_type *type; | ||
73 | + | ||
74 | + type = get_mem_type(mtype); | ||
75 | + if (!type) | ||
76 | + return -EINVAL; | ||
77 | + | ||
78 | + return remap_area_pages(virt, __phys_to_pfn(phys), PAGE_SIZE, type); | ||
79 | +} | ||
80 | +EXPORT_SYMBOL(ioremap_page); | ||
81 | |||
82 | void __check_kvm_seq(struct mm_struct *mm) | ||
83 | { | ||
84 | diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/mach/iovmm.h | ||
85 | new file mode 100644 | ||
86 | index 0000000..bdc7ce5 | ||
87 | --- /dev/null | ||
88 | +++ b/arch/arm/plat-omap/include/mach/iovmm.h | ||
89 | @@ -0,0 +1,94 @@ | ||
90 | +/* | ||
91 | + * omap iommu: simple virtual address space management | ||
92 | + * | ||
93 | + * Copyright (C) 2008-2009 Nokia Corporation | ||
94 | + * | ||
95 | + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
96 | + * | ||
97 | + * This program is free software; you can redistribute it and/or modify | ||
98 | + * it under the terms of the GNU General Public License version 2 as | ||
99 | + * published by the Free Software Foundation. | ||
100 | + */ | ||
101 | + | ||
102 | +#ifndef __IOMMU_MMAP_H | ||
103 | +#define __IOMMU_MMAP_H | ||
104 | + | ||
105 | +struct iovm_struct { | ||
106 | + struct iommu *iommu; /* iommu object which this belongs to */ | ||
107 | + u32 da_start; /* area definition */ | ||
108 | + u32 da_end; | ||
109 | + u32 flags; /* IOVMF_: see below */ | ||
110 | + struct list_head list; /* linked in ascending order */ | ||
111 | + const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */ | ||
112 | + void *va; /* mpu side mapped address */ | ||
113 | +}; | ||
114 | + | ||
115 | +/* | ||
116 | + * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma) | ||
117 | + * | ||
118 | + * lower 16 bit is used for h/w and upper 16 bit is for s/w. | ||
119 | + */ | ||
120 | +#define IOVMF_SW_SHIFT 16 | ||
121 | +#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT) | ||
122 | +#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1) | ||
123 | +#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL | ||
124 | + | ||
125 | +/* | ||
126 | + * iovma: h/w flags derived from cam and ram attribute | ||
127 | + */ | ||
128 | +#define IOVMF_CAM_MASK (~((1 << 10) - 1)) | ||
129 | +#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK) | ||
130 | + | ||
131 | +#define IOVMF_PGSZ_MASK (3 << 0) | ||
132 | +#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M | ||
133 | +#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K | ||
134 | +#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K | ||
135 | +#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M | ||
136 | + | ||
137 | +#define IOVMF_ENDIAN_MASK (1 << 9) | ||
138 | +#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG | ||
139 | +#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE | ||
140 | + | ||
141 | +#define IOVMF_ELSZ_MASK (3 << 7) | ||
142 | +#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8 | ||
143 | +#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16 | ||
144 | +#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32 | ||
145 | +#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE | ||
146 | + | ||
147 | +#define IOVMF_MIXED_MASK (1 << 6) | ||
148 | +#define IOVMF_MIXED MMU_RAM_MIXED | ||
149 | + | ||
150 | +/* | ||
151 | + * iovma: s/w flags, used for mapping and umapping internally. | ||
152 | + */ | ||
153 | +#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT) | ||
154 | +#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT) | ||
155 | +#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT) | ||
156 | + | ||
157 | +/* "superpages" is supported just with physically linear pages */ | ||
158 | +#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT)) | ||
159 | +#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT)) | ||
160 | +#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT)) | ||
161 | + | ||
162 | +#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT)) | ||
163 | +#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT)) | ||
164 | +#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT)) | ||
165 | + | ||
166 | + | ||
167 | +extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da); | ||
168 | +extern u32 iommu_vmap(struct iommu *obj, u32 da, | ||
169 | + const struct sg_table *sgt, u32 flags); | ||
170 | +extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da); | ||
171 | +extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, | ||
172 | + u32 flags); | ||
173 | +extern void iommu_vfree(struct iommu *obj, const u32 da); | ||
174 | +extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, | ||
175 | + u32 flags); | ||
176 | +extern void iommu_kunmap(struct iommu *obj, u32 da); | ||
177 | +extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, | ||
178 | + u32 flags); | ||
179 | +extern void iommu_kfree(struct iommu *obj, u32 da); | ||
180 | + | ||
181 | +extern void *da_to_va(struct iommu *obj, u32 da); | ||
182 | + | ||
183 | +#endif /* __IOMMU_MMAP_H */ | ||
184 | diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c | ||
185 | new file mode 100644 | ||
186 | index 0000000..6726d10 | ||
187 | --- /dev/null | ||
188 | +++ b/arch/arm/plat-omap/iovmm.c | ||
189 | @@ -0,0 +1,891 @@ | ||
190 | +/* | ||
191 | + * omap iommu: simple virtual address space management | ||
192 | + * | ||
193 | + * Copyright (C) 2008-2009 Nokia Corporation | ||
194 | + * | ||
195 | + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
196 | + * | ||
197 | + * This program is free software; you can redistribute it and/or modify | ||
198 | + * it under the terms of the GNU General Public License version 2 as | ||
199 | + * published by the Free Software Foundation. | ||
200 | + */ | ||
201 | + | ||
202 | +#include <linux/err.h> | ||
203 | +#include <linux/vmalloc.h> | ||
204 | +#include <linux/device.h> | ||
205 | +#include <linux/scatterlist.h> | ||
206 | + | ||
207 | +#include <asm/io.h> | ||
208 | +#include <asm/cacheflush.h> | ||
209 | + | ||
210 | +#include <mach/iommu.h> | ||
211 | +#include <mach/iovmm.h> | ||
212 | + | ||
213 | +#include "iopgtable.h" | ||
214 | + | ||
215 | +/* | ||
216 | + * A device driver needs to create address mappings between: | ||
217 | + * | ||
218 | + * - iommu/device address | ||
219 | + * - physical address | ||
220 | + * - mpu virtual address | ||
221 | + * | ||
222 | + * There are 4 possible patterns for them: | ||
223 | + * | ||
224 | + * |iova/ mapping iommu_ page | ||
225 | + * | da pa va (d)-(p)-(v) function type | ||
226 | + * --------------------------------------------------------------------------- | ||
227 | + * 1 | c c c 1 - 1 - 1 _kmap() / _kunmap() s | ||
228 | + * 2 | c c,a c 1 - 1 - 1 _kmalloc()/ _kfree() s | ||
229 | + * 3 | c d c 1 - n - 1 _vmap() / _vunmap() s | ||
230 | + * 4 | c d,a c 1 - n - 1 _vmalloc()/ _vfree() n* | ||
231 | + * | ||
232 | + * | ||
233 | + * 'iova': device iommu virtual address | ||
234 | + * 'da': alias of 'iova' | ||
235 | + * 'pa': physical address | ||
236 | + * 'va': mpu virtual address | ||
237 | + * | ||
238 | + * 'c': contiguous memory area | ||
239 | + * 'd': dicontiguous memory area | ||
240 | + * 'a': anonymous memory allocation | ||
241 | + * '()': optional feature | ||
242 | + * | ||
243 | + * 'n': a normal page(4KB) size is used. | ||
244 | + * 's': multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used. | ||
245 | + * | ||
246 | + * '*': not yet, but feasible. | ||
247 | + */ | ||
248 | + | ||
249 | +static struct kmem_cache *iovm_area_cachep; | ||
250 | + | ||
251 | +/* return total bytes of sg buffers */ | ||
252 | +static size_t sgtable_len(const struct sg_table *sgt) | ||
253 | +{ | ||
254 | + unsigned int i, total = 0; | ||
255 | + struct scatterlist *sg; | ||
256 | + | ||
257 | + if (!sgt) | ||
258 | + return 0; | ||
259 | + | ||
260 | + for_each_sg(sgt->sgl, sg, sgt->nents, i) { | ||
261 | + size_t bytes; | ||
262 | + | ||
263 | + bytes = sg_dma_len(sg); | ||
264 | + | ||
265 | + if (!iopgsz_ok(bytes)) { | ||
266 | + pr_err("%s: sg[%d] not iommu pagesize(%x)\n", | ||
267 | + __func__, i, bytes); | ||
268 | + return 0; | ||
269 | + } | ||
270 | + | ||
271 | + total += bytes; | ||
272 | + } | ||
273 | + | ||
274 | + return total; | ||
275 | +} | ||
276 | +#define sgtable_ok(x) (!!sgtable_len(x)) | ||
277 | + | ||
278 | +/* | ||
279 | + * calculate the optimal number sg elements from total bytes based on | ||
280 | + * iommu superpages | ||
281 | + */ | ||
282 | +static unsigned int sgtable_nents(size_t bytes) | ||
283 | +{ | ||
284 | + int i; | ||
285 | + unsigned int nr_entries; | ||
286 | + const unsigned long pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, }; | ||
287 | + | ||
288 | + if (!IS_ALIGNED(bytes, PAGE_SIZE)) { | ||
289 | + pr_err("%s: wrong size %08x\n", __func__, bytes); | ||
290 | + return 0; | ||
291 | + } | ||
292 | + | ||
293 | + nr_entries = 0; | ||
294 | + for (i = 0; i < ARRAY_SIZE(pagesize); i++) { | ||
295 | + if (bytes >= pagesize[i]) { | ||
296 | + nr_entries += (bytes / pagesize[i]); | ||
297 | + bytes %= pagesize[i]; | ||
298 | + } | ||
299 | + } | ||
300 | + BUG_ON(bytes); | ||
301 | + | ||
302 | + return nr_entries; | ||
303 | +} | ||
304 | + | ||
305 | +/* allocate and initialize sg_table header(a kind of 'superblock') */ | ||
306 | +static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags) | ||
307 | +{ | ||
308 | + unsigned int nr_entries; | ||
309 | + int err; | ||
310 | + struct sg_table *sgt; | ||
311 | + | ||
312 | + if (!bytes) | ||
313 | + return ERR_PTR(-EINVAL); | ||
314 | + | ||
315 | + if (!IS_ALIGNED(bytes, PAGE_SIZE)) | ||
316 | + return ERR_PTR(-EINVAL); | ||
317 | + | ||
318 | + /* FIXME: IOVMF_DA_FIXED should support 'superpages' */ | ||
319 | + if ((flags & IOVMF_LINEAR) && (flags & IOVMF_DA_ANON)) { | ||
320 | + nr_entries = sgtable_nents(bytes); | ||
321 | + if (!nr_entries) | ||
322 | + return ERR_PTR(-EINVAL); | ||
323 | + } else | ||
324 | + nr_entries = bytes / PAGE_SIZE; | ||
325 | + | ||
326 | + sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); | ||
327 | + if (!sgt) | ||
328 | + return ERR_PTR(-ENOMEM); | ||
329 | + | ||
330 | + err = sg_alloc_table(sgt, nr_entries, GFP_KERNEL); | ||
331 | + if (err) | ||
332 | + return ERR_PTR(err); | ||
333 | + | ||
334 | + pr_debug("%s: sgt:%p(%d entries)\n", __func__, sgt, nr_entries); | ||
335 | + | ||
336 | + return sgt; | ||
337 | +} | ||
338 | + | ||
339 | +/* free sg_table header(a kind of superblock) */ | ||
340 | +static void sgtable_free(struct sg_table *sgt) | ||
341 | +{ | ||
342 | + if (!sgt) | ||
343 | + return; | ||
344 | + | ||
345 | + sg_free_table(sgt); | ||
346 | + kfree(sgt); | ||
347 | + | ||
348 | + pr_debug("%s: sgt:%p\n", __func__, sgt); | ||
349 | +} | ||
350 | + | ||
351 | +/* map 'sglist' to a contiguous mpu virtual area and return 'va' */ | ||
352 | +static void *vmap_sg(const struct sg_table *sgt) | ||
353 | +{ | ||
354 | + u32 va; | ||
355 | + size_t total; | ||
356 | + unsigned int i; | ||
357 | + struct scatterlist *sg; | ||
358 | + struct vm_struct *new; | ||
359 | + | ||
360 | + total = sgtable_len(sgt); | ||
361 | + if (!total) | ||
362 | + return ERR_PTR(-EINVAL); | ||
363 | + | ||
364 | + new = __get_vm_area(total, VM_IOREMAP, VMALLOC_START, VMALLOC_END); | ||
365 | + if (!new) | ||
366 | + return ERR_PTR(-ENOMEM); | ||
367 | + va = (u32)new->addr; | ||
368 | + | ||
369 | + for_each_sg(sgt->sgl, sg, sgt->nents, i) { | ||
370 | + size_t bytes; | ||
371 | + u32 pa; | ||
372 | + int err; | ||
373 | + | ||
374 | + pa = sg_phys(sg); | ||
375 | + bytes = sg_dma_len(sg); | ||
376 | + | ||
377 | + BUG_ON(bytes != PAGE_SIZE); | ||
378 | + | ||
379 | + err = ioremap_page(va, pa, MT_DEVICE); | ||
380 | + if (err) | ||
381 | + goto err_out; | ||
382 | + | ||
383 | + va += bytes; | ||
384 | + } | ||
385 | + | ||
386 | + flush_cache_vmap(new->addr, total); | ||
387 | + return new->addr; | ||
388 | + | ||
389 | +err_out: | ||
390 | + WARN_ON(1); /* FIXME: cleanup some mpu mappings */ | ||
391 | + vunmap(new->addr); | ||
392 | + return ERR_PTR(-EAGAIN); | ||
393 | +} | ||
394 | + | ||
395 | +static inline void vunmap_sg(const void *va) | ||
396 | +{ | ||
397 | + vunmap(va); | ||
398 | +} | ||
399 | + | ||
400 | +static struct iovm_struct *__find_iovm_area(struct iommu *obj, const u32 da) | ||
401 | +{ | ||
402 | + struct iovm_struct *tmp; | ||
403 | + | ||
404 | + list_for_each_entry(tmp, &obj->mmap, list) { | ||
405 | + if ((da >= tmp->da_start) && (da < tmp->da_end)) { | ||
406 | + size_t len; | ||
407 | + | ||
408 | + len = tmp->da_end - tmp->da_start; | ||
409 | + | ||
410 | + dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n", | ||
411 | + __func__, tmp->da_start, da, tmp->da_end, len, | ||
412 | + tmp->flags); | ||
413 | + | ||
414 | + return tmp; | ||
415 | + } | ||
416 | + } | ||
417 | + | ||
418 | + return NULL; | ||
419 | +} | ||
420 | + | ||
421 | +/** | ||
422 | + * find_iovm_area - find iovma which includes @da | ||
423 | + * @da: iommu device virtual address | ||
424 | + * | ||
425 | + * Find the existing iovma starting at @da | ||
426 | + */ | ||
427 | +struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da) | ||
428 | +{ | ||
429 | + struct iovm_struct *area; | ||
430 | + | ||
431 | + mutex_lock(&obj->mmap_lock); | ||
432 | + area = __find_iovm_area(obj, da); | ||
433 | + mutex_unlock(&obj->mmap_lock); | ||
434 | + | ||
435 | + return area; | ||
436 | +} | ||
437 | +EXPORT_SYMBOL_GPL(find_iovm_area); | ||
438 | + | ||
439 | +/* | ||
440 | + * This finds the hole(area) which fits the requested address and len | ||
441 | + * in iovmas mmap, and returns the new allocated iovma. | ||
442 | + */ | ||
443 | +static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da, | ||
444 | + size_t bytes, u32 flags) | ||
445 | +{ | ||
446 | + struct iovm_struct *new, *tmp; | ||
447 | + u32 start, prev_end, alignement; | ||
448 | + | ||
449 | + if (!obj || !bytes) | ||
450 | + return ERR_PTR(-EINVAL); | ||
451 | + | ||
452 | + start = da; | ||
453 | + alignement = PAGE_SIZE; | ||
454 | + | ||
455 | + if (flags & IOVMF_DA_ANON) { | ||
456 | + /* | ||
457 | + * Reserve the first page for NULL | ||
458 | + */ | ||
459 | + start = PAGE_SIZE; | ||
460 | + if (flags & IOVMF_LINEAR) | ||
461 | + alignement = iopgsz_max(bytes); | ||
462 | + start = roundup(start, alignement); | ||
463 | + } | ||
464 | + | ||
465 | + tmp = NULL; | ||
466 | + if (list_empty(&obj->mmap)) | ||
467 | + goto found; | ||
468 | + | ||
469 | + prev_end = 0; | ||
470 | + list_for_each_entry(tmp, &obj->mmap, list) { | ||
471 | + | ||
472 | + if ((prev_end <= start) && (start + bytes < tmp->da_start)) | ||
473 | + goto found; | ||
474 | + | ||
475 | + if (flags & IOVMF_DA_ANON) | ||
476 | + start = roundup(tmp->da_end, alignement); | ||
477 | + | ||
478 | + prev_end = tmp->da_end; | ||
479 | + } | ||
480 | + | ||
481 | + if ((start >= prev_end) && (ULONG_MAX - start >= bytes)) | ||
482 | + goto found; | ||
483 | + | ||
484 | + dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n", | ||
485 | + __func__, da, bytes, flags); | ||
486 | + | ||
487 | + return ERR_PTR(-EINVAL); | ||
488 | + | ||
489 | +found: | ||
490 | + new = kmem_cache_zalloc(iovm_area_cachep, GFP_KERNEL); | ||
491 | + if (!new) | ||
492 | + return ERR_PTR(-ENOMEM); | ||
493 | + | ||
494 | + new->iommu = obj; | ||
495 | + new->da_start = start; | ||
496 | + new->da_end = start + bytes; | ||
497 | + new->flags = flags; | ||
498 | + | ||
499 | + /* | ||
500 | + * keep ascending order of iovmas | ||
501 | + */ | ||
502 | + if (tmp) | ||
503 | + list_add_tail(&new->list, &tmp->list); | ||
504 | + else | ||
505 | + list_add(&new->list, &obj->mmap); | ||
506 | + | ||
507 | + dev_dbg(obj->dev, "%s: found %08x-%08x-%08x(%x) %08x\n", | ||
508 | + __func__, new->da_start, start, new->da_end, bytes, flags); | ||
509 | + | ||
510 | + return new; | ||
511 | +} | ||
512 | + | ||
513 | +static void free_iovm_area(struct iommu *obj, struct iovm_struct *area) | ||
514 | +{ | ||
515 | + size_t bytes; | ||
516 | + | ||
517 | + BUG_ON(!obj || !area); | ||
518 | + | ||
519 | + bytes = area->da_end - area->da_start; | ||
520 | + | ||
521 | + dev_dbg(obj->dev, "%s: %08x-%08x(%x) %08x\n", | ||
522 | + __func__, area->da_start, area->da_end, bytes, area->flags); | ||
523 | + | ||
524 | + list_del(&area->list); | ||
525 | + kmem_cache_free(iovm_area_cachep, area); | ||
526 | +} | ||
527 | + | ||
528 | +/** | ||
529 | + * da_to_va - convert (d) to (v) | ||
530 | + * @obj: objective iommu | ||
531 | + * @da: iommu device virtual address | ||
532 | + * @va: mpu virtual address | ||
533 | + * | ||
534 | + * Returns mpu virtual addr which corresponds to a given device virtual addr | ||
535 | + */ | ||
536 | +void *da_to_va(struct iommu *obj, u32 da) | ||
537 | +{ | ||
538 | + void *va = NULL; | ||
539 | + struct iovm_struct *area; | ||
540 | + | ||
541 | + mutex_lock(&obj->mmap_lock); | ||
542 | + | ||
543 | + area = __find_iovm_area(obj, da); | ||
544 | + if (!area) { | ||
545 | + dev_warn(obj->dev, "%s: no da area(%08x)\n", __func__, da); | ||
546 | + goto out; | ||
547 | + } | ||
548 | + va = area->va; | ||
549 | + mutex_unlock(&obj->mmap_lock); | ||
550 | +out: | ||
551 | + return va; | ||
552 | +} | ||
553 | +EXPORT_SYMBOL_GPL(da_to_va); | ||
554 | + | ||
555 | +static void sgtable_fill_vmalloc(struct sg_table *sgt, void *_va) | ||
556 | +{ | ||
557 | + unsigned int i; | ||
558 | + struct scatterlist *sg; | ||
559 | + void *va = _va; | ||
560 | + void *va_end; | ||
561 | + | ||
562 | + for_each_sg(sgt->sgl, sg, sgt->nents, i) { | ||
563 | + struct page *pg; | ||
564 | + const size_t bytes = PAGE_SIZE; | ||
565 | + | ||
566 | + /* | ||
567 | + * iommu 'superpage' isn't supported with 'iommu_vmalloc()' | ||
568 | + */ | ||
569 | + pg = vmalloc_to_page(va); | ||
570 | + BUG_ON(!pg); | ||
571 | + sg_set_page(sg, pg, bytes, 0); | ||
572 | + | ||
573 | + va += bytes; | ||
574 | + } | ||
575 | + | ||
576 | + va_end = _va + PAGE_SIZE * i; | ||
577 | + flush_cache_vmap(_va, va_end); | ||
578 | +} | ||
579 | + | ||
580 | +static inline void sgtable_drain_vmalloc(struct sg_table *sgt) | ||
581 | +{ | ||
582 | + /* | ||
583 | + * Actually this is not necessary at all, just exists for | ||
584 | + * consistency of the code readibility. | ||
585 | + */ | ||
586 | + BUG_ON(!sgt); | ||
587 | +} | ||
588 | + | ||
589 | +static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len) | ||
590 | +{ | ||
591 | + unsigned int i; | ||
592 | + struct scatterlist *sg; | ||
593 | + void *va; | ||
594 | + | ||
595 | + va = phys_to_virt(pa); | ||
596 | + | ||
597 | + for_each_sg(sgt->sgl, sg, sgt->nents, i) { | ||
598 | + size_t bytes; | ||
599 | + | ||
600 | + bytes = iopgsz_max(len); | ||
601 | + | ||
602 | + BUG_ON(!iopgsz_ok(bytes)); | ||
603 | + | ||
604 | + sg_set_buf(sg, phys_to_virt(pa), bytes); | ||
605 | + /* | ||
606 | + * 'pa' is cotinuous(linear). | ||
607 | + */ | ||
608 | + pa += bytes; | ||
609 | + len -= bytes; | ||
610 | + } | ||
611 | + BUG_ON(len); | ||
612 | + | ||
613 | + clean_dcache_area(va, len); | ||
614 | +} | ||
615 | + | ||
616 | +static inline void sgtable_drain_kmalloc(struct sg_table *sgt) | ||
617 | +{ | ||
618 | + /* | ||
619 | + * Actually this is not necessary at all, just exists for | ||
620 | + * consistency of the code readibility | ||
621 | + */ | ||
622 | + BUG_ON(!sgt); | ||
623 | +} | ||
624 | + | ||
625 | +/* create 'da' <-> 'pa' mapping from 'sgt' */ | ||
626 | +static int map_iovm_area(struct iommu *obj, struct iovm_struct *new, | ||
627 | + const struct sg_table *sgt, u32 flags) | ||
628 | +{ | ||
629 | + int err; | ||
630 | + unsigned int i, j; | ||
631 | + struct scatterlist *sg; | ||
632 | + u32 da = new->da_start; | ||
633 | + | ||
634 | + if (!obj || !new || !sgt) | ||
635 | + return -EINVAL; | ||
636 | + | ||
637 | + BUG_ON(!sgtable_ok(sgt)); | ||
638 | + | ||
639 | + for_each_sg(sgt->sgl, sg, sgt->nents, i) { | ||
640 | + u32 pa; | ||
641 | + int pgsz; | ||
642 | + size_t bytes; | ||
643 | + struct iotlb_entry e; | ||
644 | + | ||
645 | + pa = sg_phys(sg); | ||
646 | + bytes = sg_dma_len(sg); | ||
647 | + | ||
648 | + flags &= ~IOVMF_PGSZ_MASK; | ||
649 | + pgsz = bytes_to_iopgsz(bytes); | ||
650 | + if (pgsz < 0) | ||
651 | + goto err_out; | ||
652 | + flags |= pgsz; | ||
653 | + | ||
654 | + pr_debug("%s: [%d] %08x %08x(%x)\n", __func__, | ||
655 | + i, da, pa, bytes); | ||
656 | + | ||
657 | + iotlb_init_entry(&e, da, pa, flags); | ||
658 | + err = iopgtable_store_entry(obj, &e); | ||
659 | + if (err) | ||
660 | + goto err_out; | ||
661 | + | ||
662 | + da += bytes; | ||
663 | + } | ||
664 | + return 0; | ||
665 | + | ||
666 | +err_out: | ||
667 | + da = new->da_start; | ||
668 | + | ||
669 | + for_each_sg(sgt->sgl, sg, i, j) { | ||
670 | + size_t bytes; | ||
671 | + | ||
672 | + bytes = iopgtable_clear_entry(obj, da); | ||
673 | + | ||
674 | + BUG_ON(!iopgsz_ok(bytes)); | ||
675 | + | ||
676 | + da += bytes; | ||
677 | + } | ||
678 | + return err; | ||
679 | +} | ||
680 | + | ||
681 | +/* release 'da' <-> 'pa' mapping */ | ||
682 | +static void unmap_iovm_area(struct iommu *obj, struct iovm_struct *area) | ||
683 | +{ | ||
684 | + u32 start; | ||
685 | + size_t total = area->da_end - area->da_start; | ||
686 | + | ||
687 | + BUG_ON((!total) || !IS_ALIGNED(total, PAGE_SIZE)); | ||
688 | + | ||
689 | + start = area->da_start; | ||
690 | + while (total > 0) { | ||
691 | + size_t bytes; | ||
692 | + | ||
693 | + bytes = iopgtable_clear_entry(obj, start); | ||
694 | + if (bytes == 0) | ||
695 | + bytes = PAGE_SIZE; | ||
696 | + else | ||
697 | + dev_dbg(obj->dev, "%s: unmap %08x(%x) %08x\n", | ||
698 | + __func__, start, bytes, area->flags); | ||
699 | + | ||
700 | + BUG_ON(!IS_ALIGNED(bytes, PAGE_SIZE)); | ||
701 | + | ||
702 | + total -= bytes; | ||
703 | + start += bytes; | ||
704 | + } | ||
705 | + BUG_ON(total); | ||
706 | +} | ||
707 | + | ||
708 | +/* template function for all unmapping */ | ||
709 | +static struct sg_table *unmap_vm_area(struct iommu *obj, const u32 da, | ||
710 | + void (*fn)(const void *), u32 flags) | ||
711 | +{ | ||
712 | + struct sg_table *sgt = NULL; | ||
713 | + struct iovm_struct *area; | ||
714 | + | ||
715 | + BUG_ON(in_interrupt()); | ||
716 | + | ||
717 | + if (!IS_ALIGNED(da, PAGE_SIZE)) { | ||
718 | + dev_err(obj->dev, "%s: alignment err(%08x)\n", __func__, da); | ||
719 | + return NULL; | ||
720 | + } | ||
721 | + | ||
722 | + mutex_lock(&obj->mmap_lock); | ||
723 | + | ||
724 | + area = __find_iovm_area(obj, da); | ||
725 | + if (!area) { | ||
726 | + dev_err(obj->dev, "%s: no da area(%08x)\n", __func__, da); | ||
727 | + goto out; | ||
728 | + } | ||
729 | + | ||
730 | + if ((area->flags & flags) != flags) { | ||
731 | + dev_err(obj->dev, "%s: wrong flags(%08x)\n", __func__, | ||
732 | + area->flags); | ||
733 | + goto out; | ||
734 | + } | ||
735 | + sgt = (struct sg_table *)area->sgt; | ||
736 | + | ||
737 | + unmap_iovm_area(obj, area); | ||
738 | + | ||
739 | + fn(area->va); | ||
740 | + | ||
741 | + dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n", __func__, | ||
742 | + area->da_start, da, area->da_end, | ||
743 | + area->da_end - area->da_start, area->flags); | ||
744 | + | ||
745 | + free_iovm_area(obj, area); | ||
746 | +out: | ||
747 | + mutex_unlock(&obj->mmap_lock); | ||
748 | + | ||
749 | + return sgt; | ||
750 | +} | ||
751 | + | ||
752 | +static u32 map_iommu_region(struct iommu *obj, u32 da, | ||
753 | + const struct sg_table *sgt, void *va, size_t bytes, u32 flags) | ||
754 | +{ | ||
755 | + int err = -ENOMEM; | ||
756 | + struct iovm_struct *new; | ||
757 | + | ||
758 | + mutex_lock(&obj->mmap_lock); | ||
759 | + | ||
760 | + new = alloc_iovm_area(obj, da, bytes, flags); | ||
761 | + if (IS_ERR(new)) { | ||
762 | + err = PTR_ERR(new); | ||
763 | + goto err_alloc_iovma; | ||
764 | + } | ||
765 | + new->va = va; | ||
766 | + new->sgt = sgt; | ||
767 | + | ||
768 | + if (map_iovm_area(obj, new, sgt, new->flags)) | ||
769 | + goto err_map; | ||
770 | + | ||
771 | + mutex_unlock(&obj->mmap_lock); | ||
772 | + | ||
773 | + dev_dbg(obj->dev, "%s: da:%08x(%x) flags:%08x va:%p\n", | ||
774 | + __func__, new->da_start, bytes, new->flags, va); | ||
775 | + | ||
776 | + return new->da_start; | ||
777 | + | ||
778 | +err_map: | ||
779 | + free_iovm_area(obj, new); | ||
780 | +err_alloc_iovma: | ||
781 | + mutex_unlock(&obj->mmap_lock); | ||
782 | + return err; | ||
783 | +} | ||
784 | + | ||
785 | +static inline u32 __iommu_vmap(struct iommu *obj, u32 da, | ||
786 | + const struct sg_table *sgt, void *va, size_t bytes, u32 flags) | ||
787 | +{ | ||
788 | + return map_iommu_region(obj, da, sgt, va, bytes, flags); | ||
789 | +} | ||
790 | + | ||
791 | +/** | ||
792 | + * iommu_vmap - (d)-(p)-(v) address mapper | ||
793 | + * @obj: objective iommu | ||
794 | + * @sgt: address of scatter gather table | ||
795 | + * @flags: iovma and page property | ||
796 | + * | ||
797 | + * Creates 1-n-1 mapping with given @sgt and returns @da. | ||
798 | + * All @sgt element must be io page size aligned. | ||
799 | + */ | ||
800 | +u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt, | ||
801 | + u32 flags) | ||
802 | +{ | ||
803 | + size_t bytes; | ||
804 | + void *va; | ||
805 | + | ||
806 | + if (!obj || !obj->dev || !sgt) | ||
807 | + return -EINVAL; | ||
808 | + | ||
809 | + bytes = sgtable_len(sgt); | ||
810 | + if (!bytes) | ||
811 | + return -EINVAL; | ||
812 | + bytes = PAGE_ALIGN(bytes); | ||
813 | + | ||
814 | + va = vmap_sg(sgt); | ||
815 | + if (IS_ERR(va)) | ||
816 | + return PTR_ERR(va); | ||
817 | + | ||
818 | + flags &= IOVMF_HW_MASK; | ||
819 | + flags |= IOVMF_DISCONT; | ||
820 | + flags |= IOVMF_MMIO; | ||
821 | + flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); | ||
822 | + | ||
823 | + da = __iommu_vmap(obj, da, sgt, va, bytes, flags); | ||
824 | + if (IS_ERR_VALUE(da)) | ||
825 | + vunmap_sg(va); | ||
826 | + | ||
827 | + return da; | ||
828 | +} | ||
829 | +EXPORT_SYMBOL_GPL(iommu_vmap); | ||
830 | + | ||
831 | +/** | ||
832 | + * iommu_vunmap - release virtual mapping obtained by 'iommu_vmap()' | ||
833 | + * @obj: objective iommu | ||
834 | + * @da: iommu device virtual address | ||
835 | + * | ||
836 | + * Free the iommu virtually contiguous memory area starting at | ||
837 | + * @da, which was returned by 'iommu_vmap()'. | ||
838 | + */ | ||
839 | +struct sg_table *iommu_vunmap(struct iommu *obj, u32 da) | ||
840 | +{ | ||
841 | + struct sg_table *sgt; | ||
842 | + /* | ||
843 | + * 'sgt' is allocated before 'iommu_vmalloc()' is called. | ||
844 | + * Just returns 'sgt' to the caller to free | ||
845 | + */ | ||
846 | + sgt = unmap_vm_area(obj, da, vunmap_sg, IOVMF_DISCONT | IOVMF_MMIO); | ||
847 | + if (!sgt) | ||
848 | + dev_err(obj->dev, "%s: No sgt\n", __func__); | ||
849 | + return sgt; | ||
850 | +} | ||
851 | +EXPORT_SYMBOL_GPL(iommu_vunmap); | ||
852 | + | ||
853 | +/** | ||
854 | + * iommu_vmalloc - (d)-(p)-(v) address allocator and mapper | ||
855 | + * @obj: objective iommu | ||
856 | + * @da: contiguous iommu virtual memory | ||
857 | + * @bytes: allocation size | ||
858 | + * @flags: iovma and page property | ||
859 | + * | ||
860 | + * Allocate @bytes linearly and creates 1-n-1 mapping and returns | ||
861 | + * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set. | ||
862 | + */ | ||
863 | +u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) | ||
864 | +{ | ||
865 | + void *va; | ||
866 | + struct sg_table *sgt; | ||
867 | + | ||
868 | + if (!obj || !obj->dev || !bytes) | ||
869 | + return -EINVAL; | ||
870 | + | ||
871 | + bytes = PAGE_ALIGN(bytes); | ||
872 | + | ||
873 | + va = vmalloc(bytes); | ||
874 | + if (!va) | ||
875 | + return -ENOMEM; | ||
876 | + | ||
877 | + sgt = sgtable_alloc(bytes, flags); | ||
878 | + if (IS_ERR(sgt)) { | ||
879 | + da = PTR_ERR(sgt); | ||
880 | + goto err_sgt_alloc; | ||
881 | + } | ||
882 | + sgtable_fill_vmalloc(sgt, va); | ||
883 | + | ||
884 | + flags &= IOVMF_HW_MASK; | ||
885 | + flags |= IOVMF_DISCONT; | ||
886 | + flags |= IOVMF_ALLOC; | ||
887 | + flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); | ||
888 | + | ||
889 | + da = __iommu_vmap(obj, da, sgt, va, bytes, flags); | ||
890 | + if (IS_ERR_VALUE(da)) | ||
891 | + goto err_iommu_vmap; | ||
892 | + | ||
893 | + return da; | ||
894 | + | ||
895 | +err_iommu_vmap: | ||
896 | + sgtable_drain_vmalloc(sgt); | ||
897 | + sgtable_free(sgt); | ||
898 | +err_sgt_alloc: | ||
899 | + vfree(va); | ||
900 | + return da; | ||
901 | +} | ||
902 | +EXPORT_SYMBOL_GPL(iommu_vmalloc); | ||
903 | + | ||
904 | +/** | ||
905 | + * iommu_vfree - release memory allocated by 'iommu_vmalloc()' | ||
906 | + * @obj: objective iommu | ||
907 | + * @da: iommu device virtual address | ||
908 | + * | ||
909 | + * Frees the iommu virtually continuous memory area starting at | ||
910 | + * @da, as obtained from 'iommu_vmalloc()'. | ||
911 | + */ | ||
912 | +void iommu_vfree(struct iommu *obj, const u32 da) | ||
913 | +{ | ||
914 | + struct sg_table *sgt; | ||
915 | + | ||
916 | + sgt = unmap_vm_area(obj, da, vfree, IOVMF_DISCONT | IOVMF_ALLOC); | ||
917 | + if (!sgt) | ||
918 | + dev_err(obj->dev, "%s: No sgt\n", __func__); | ||
919 | + sgtable_free(sgt); | ||
920 | +} | ||
921 | +EXPORT_SYMBOL_GPL(iommu_vfree); | ||
922 | + | ||
923 | +static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va, | ||
924 | + size_t bytes, u32 flags) | ||
925 | +{ | ||
926 | + struct sg_table *sgt; | ||
927 | + | ||
928 | + sgt = sgtable_alloc(bytes, flags); | ||
929 | + if (IS_ERR(sgt)) | ||
930 | + return PTR_ERR(sgt); | ||
931 | + | ||
932 | + sgtable_fill_kmalloc(sgt, pa, bytes); | ||
933 | + | ||
934 | + da = map_iommu_region(obj, da, sgt, va, bytes, flags); | ||
935 | + if (IS_ERR_VALUE(da)) { | ||
936 | + sgtable_drain_kmalloc(sgt); | ||
937 | + sgtable_free(sgt); | ||
938 | + } | ||
939 | + | ||
940 | + return da; | ||
941 | +} | ||
942 | + | ||
943 | +/** | ||
944 | + * iommu_kmap - (d)-(p)-(v) address mapper | ||
945 | + * @obj: objective iommu | ||
946 | + * @da: contiguous iommu virtual memory | ||
947 | + * @pa: contiguous physical memory | ||
948 | + * @flags: iovma and page property | ||
949 | + * | ||
950 | + * Creates 1-1-1 mapping and returns @da again, which can be | ||
951 | + * adjusted if 'IOVMF_DA_ANON' is set. | ||
952 | + */ | ||
953 | +u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, | ||
954 | + u32 flags) | ||
955 | +{ | ||
956 | + void *va; | ||
957 | + | ||
958 | + if (!obj || !obj->dev || !bytes) | ||
959 | + return -EINVAL; | ||
960 | + | ||
961 | + bytes = PAGE_ALIGN(bytes); | ||
962 | + | ||
963 | + va = ioremap(pa, bytes); | ||
964 | + if (!va) | ||
965 | + return -ENOMEM; | ||
966 | + | ||
967 | + flags &= IOVMF_HW_MASK; | ||
968 | + flags |= IOVMF_LINEAR; | ||
969 | + flags |= IOVMF_MMIO; | ||
970 | + flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); | ||
971 | + | ||
972 | + da = __iommu_kmap(obj, da, pa, va, bytes, flags); | ||
973 | + if (IS_ERR_VALUE(da)) | ||
974 | + iounmap(va); | ||
975 | + | ||
976 | + return da; | ||
977 | +} | ||
978 | +EXPORT_SYMBOL_GPL(iommu_kmap); | ||
979 | + | ||
980 | +/** | ||
981 | + * iommu_kunmap - release virtual mapping obtained by 'iommu_kmap()' | ||
982 | + * @obj: objective iommu | ||
983 | + * @da: iommu device virtual address | ||
984 | + * | ||
985 | + * Frees the iommu virtually contiguous memory area starting at | ||
986 | + * @da, which was passed to and was returned by'iommu_kmap()'. | ||
987 | + */ | ||
988 | +void iommu_kunmap(struct iommu *obj, u32 da) | ||
989 | +{ | ||
990 | + struct sg_table *sgt; | ||
991 | + | ||
992 | + sgt = unmap_vm_area(obj, da, __iounmap, IOVMF_LINEAR | IOVMF_MMIO); | ||
993 | + if (!sgt) | ||
994 | + dev_err(obj->dev, "%s: No sgt\n", __func__); | ||
995 | + sgtable_free(sgt); | ||
996 | +} | ||
997 | +EXPORT_SYMBOL_GPL(iommu_kunmap); | ||
998 | + | ||
999 | +/** | ||
1000 | + * iommu_kmalloc - (d)-(p)-(v) address allocator and mapper | ||
1001 | + * @obj: objective iommu | ||
1002 | + * @da: contiguous iommu virtual memory | ||
1003 | + * @bytes: bytes for allocation | ||
1004 | + * @flags: iovma and page property | ||
1005 | + * | ||
1006 | + * Allocate @bytes linearly and creates 1-1-1 mapping and returns | ||
1007 | + * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set. | ||
1008 | + */ | ||
1009 | +u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) | ||
1010 | +{ | ||
1011 | + void *va; | ||
1012 | + u32 pa; | ||
1013 | + | ||
1014 | + if (!obj || !obj->dev || !bytes) | ||
1015 | + return -EINVAL; | ||
1016 | + | ||
1017 | + bytes = PAGE_ALIGN(bytes); | ||
1018 | + | ||
1019 | + va = kmalloc(bytes, GFP_KERNEL | GFP_DMA); | ||
1020 | + if (!va) | ||
1021 | + return -ENOMEM; | ||
1022 | + pa = virt_to_phys(va); | ||
1023 | + | ||
1024 | + flags &= IOVMF_HW_MASK; | ||
1025 | + flags |= IOVMF_LINEAR; | ||
1026 | + flags |= IOVMF_ALLOC; | ||
1027 | + flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); | ||
1028 | + | ||
1029 | + da = __iommu_kmap(obj, da, pa, va, bytes, flags); | ||
1030 | + if (IS_ERR_VALUE(da)) | ||
1031 | + kfree(va); | ||
1032 | + | ||
1033 | + return da; | ||
1034 | +} | ||
1035 | +EXPORT_SYMBOL_GPL(iommu_kmalloc); | ||
1036 | + | ||
1037 | +/** | ||
1038 | + * iommu_kfree - release virtual mapping obtained by 'iommu_kmalloc()' | ||
1039 | + * @obj: objective iommu | ||
1040 | + * @da: iommu device virtual address | ||
1041 | + * | ||
1042 | + * Frees the iommu virtually contiguous memory area starting at | ||
1043 | + * @da, which was passed to and was returned by'iommu_kmalloc()'. | ||
1044 | + */ | ||
1045 | +void iommu_kfree(struct iommu *obj, u32 da) | ||
1046 | +{ | ||
1047 | + struct sg_table *sgt; | ||
1048 | + | ||
1049 | + sgt = unmap_vm_area(obj, da, kfree, IOVMF_LINEAR | IOVMF_ALLOC); | ||
1050 | + if (!sgt) | ||
1051 | + dev_err(obj->dev, "%s: No sgt\n", __func__); | ||
1052 | + sgtable_free(sgt); | ||
1053 | +} | ||
1054 | +EXPORT_SYMBOL_GPL(iommu_kfree); | ||
1055 | + | ||
1056 | + | ||
1057 | +static int __init iovmm_init(void) | ||
1058 | +{ | ||
1059 | + const unsigned long flags = SLAB_HWCACHE_ALIGN; | ||
1060 | + struct kmem_cache *p; | ||
1061 | + | ||
1062 | + p = kmem_cache_create("iovm_area_cache", sizeof(struct iovm_struct), 0, | ||
1063 | + flags, NULL); | ||
1064 | + if (!p) | ||
1065 | + return -ENOMEM; | ||
1066 | + iovm_area_cachep = p; | ||
1067 | + | ||
1068 | + return 0; | ||
1069 | +} | ||
1070 | +module_init(iovmm_init); | ||
1071 | + | ||
1072 | +static void __exit iovmm_exit(void) | ||
1073 | +{ | ||
1074 | + kmem_cache_destroy(iovm_area_cachep); | ||
1075 | +} | ||
1076 | +module_exit(iovmm_exit); | ||
1077 | + | ||
1078 | +MODULE_DESCRIPTION("omap iommu: simple virtual address space management"); | ||
1079 | +MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>"); | ||
1080 | +MODULE_LICENSE("GPL v2"); | ||
1081 | -- | ||
1082 | 1.5.6.5 | ||
1083 | |||
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0005-omap-iommu-entries-for-Kconfig-and-Makefile.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0005-omap-iommu-entries-for-Kconfig-and-Makefile.patch new file mode 100644 index 0000000000..c0f9e4d9ac --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0005-omap-iommu-entries-for-Kconfig-and-Makefile.patch | |||
@@ -0,0 +1,45 @@ | |||
1 | From 7de046a6a8446358001c38ad1d0b2b829ca0c98c Mon Sep 17 00:00:00 2001 | ||
2 | From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
3 | Date: Wed, 28 Jan 2009 21:32:08 +0200 | ||
4 | Subject: [PATCH] omap iommu: entries for Kconfig and Makefile | ||
5 | |||
6 | Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
7 | --- | ||
8 | arch/arm/plat-omap/Kconfig | 8 ++++++++ | ||
9 | arch/arm/plat-omap/Makefile | 1 + | ||
10 | 2 files changed, 9 insertions(+), 0 deletions(-) | ||
11 | |||
12 | diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig | ||
13 | index b16ae76..2090bb5 100644 | ||
14 | --- a/arch/arm/plat-omap/Kconfig | ||
15 | +++ b/arch/arm/plat-omap/Kconfig | ||
16 | @@ -176,6 +176,14 @@ config OMAP_MBOX_FWK | ||
17 | Say Y here if you want to use OMAP Mailbox framework support for | ||
18 | DSP, IVA1.0 and IVA2 in OMAP1/2/3. | ||
19 | |||
20 | +config OMAP_IOMMU | ||
21 | + tristate "IOMMU support" | ||
22 | + depends on ARCH_OMAP | ||
23 | + default n | ||
24 | + help | ||
25 | + Say Y here if you want to use OMAP IOMMU support for IVA2 and | ||
26 | + Camera in OMAP3. | ||
27 | + | ||
28 | choice | ||
29 | prompt "System timer" | ||
30 | default OMAP_MPU_TIMER | ||
31 | diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile | ||
32 | index 3ebc09e..aa8f6df 100644 | ||
33 | --- a/arch/arm/plat-omap/Makefile | ||
34 | +++ b/arch/arm/plat-omap/Makefile | ||
35 | @@ -13,6 +13,7 @@ obj- := | ||
36 | obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o | ||
37 | |||
38 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o | ||
39 | +obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o | ||
40 | |||
41 | obj-$(CONFIG_CPU_FREQ) += cpu-omap.o | ||
42 | obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o | ||
43 | -- | ||
44 | 1.5.6.5 | ||
45 | |||
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0006-omap-iommu-Don-t-try-BUG_ON-in_interrupt.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0006-omap-iommu-Don-t-try-BUG_ON-in_interrupt.patch new file mode 100644 index 0000000000..54a7abfe85 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0006-omap-iommu-Don-t-try-BUG_ON-in_interrupt.patch | |||
@@ -0,0 +1,26 @@ | |||
1 | From b03f695e25bbdaa95a2cc87e15ee8592e7ca128d Mon Sep 17 00:00:00 2001 | ||
2 | From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com> | ||
3 | Date: Tue, 10 Feb 2009 18:01:29 +0200 | ||
4 | Subject: [PATCH] omap iommu: Don't try BUG_ON(in_interrupt()) | ||
5 | |||
6 | Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com> | ||
7 | --- | ||
8 | arch/arm/plat-omap/iovmm.c | 2 -- | ||
9 | 1 files changed, 0 insertions(+), 2 deletions(-) | ||
10 | |||
11 | diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c | ||
12 | index 6726d10..bdfbb09 100644 | ||
13 | --- a/arch/arm/plat-omap/iovmm.c | ||
14 | +++ b/arch/arm/plat-omap/iovmm.c | ||
15 | @@ -523,8 +523,6 @@ static struct sg_table *unmap_vm_area(struct iommu *obj, const u32 da, | ||
16 | struct sg_table *sgt = NULL; | ||
17 | struct iovm_struct *area; | ||
18 | |||
19 | - BUG_ON(in_interrupt()); | ||
20 | - | ||
21 | if (!IS_ALIGNED(da, PAGE_SIZE)) { | ||
22 | dev_err(obj->dev, "%s: alignment err(%08x)\n", __func__, da); | ||
23 | return NULL; | ||
24 | -- | ||
25 | 1.5.6.5 | ||
26 | |||
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0007-omap-iommu-We-support-chained-scatterlists-probabl.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0007-omap-iommu-We-support-chained-scatterlists-probabl.patch new file mode 100644 index 0000000000..d8ad0eb0b7 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0007-omap-iommu-We-support-chained-scatterlists-probabl.patch | |||
@@ -0,0 +1,24 @@ | |||
1 | From 24f984f784cae1a4515fe1be8db1ac24cdf51e84 Mon Sep 17 00:00:00 2001 | ||
2 | From: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com> | ||
3 | Date: Tue, 10 Feb 2009 18:37:41 +0200 | ||
4 | Subject: [PATCH] omap iommu: We support chained scatterlists, probably. :) | ||
5 | |||
6 | Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com> | ||
7 | --- | ||
8 | arch/arm/include/asm/scatterlist.h | 2 ++ | ||
9 | 1 files changed, 2 insertions(+), 0 deletions(-) | ||
10 | |||
11 | diff --git a/arch/arm/include/asm/scatterlist.h b/arch/arm/include/asm/scatterlist.h | ||
12 | index ca0a37d..393f8b8 100644 | ||
13 | --- a/arch/arm/include/asm/scatterlist.h | ||
14 | +++ b/arch/arm/include/asm/scatterlist.h | ||
15 | @@ -24,4 +24,6 @@ struct scatterlist { | ||
16 | #define sg_dma_address(sg) ((sg)->dma_address) | ||
17 | #define sg_dma_len(sg) ((sg)->length) | ||
18 | |||
19 | +#define ARCH_HAS_SG_CHAIN | ||
20 | + | ||
21 | #endif /* _ASMARM_SCATTERLIST_H */ | ||
22 | -- | ||
23 | 1.5.6.5 | ||
24 | |||
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0008-omap2-iommu-entries-for-Kconfig-and-Makefile.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0008-omap2-iommu-entries-for-Kconfig-and-Makefile.patch new file mode 100644 index 0000000000..298e797c37 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/isp/iommu/0008-omap2-iommu-entries-for-Kconfig-and-Makefile.patch | |||
@@ -0,0 +1,29 @@ | |||
1 | From 3c65ff4a684d3e0f4d9c59e731975408452c3743 Mon Sep 17 00:00:00 2001 | ||
2 | From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
3 | Date: Wed, 28 Jan 2009 21:32:09 +0200 | ||
4 | Subject: [PATCH] omap2 iommu: entries for Kconfig and Makefile | ||
5 | |||
6 | Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
7 | --- | ||
8 | arch/arm/mach-omap2/Makefile | 5 +++++ | ||
9 | 1 files changed, 5 insertions(+), 0 deletions(-) | ||
10 | |||
11 | diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile | ||
12 | index b44bb78..33b5aa8 100644 | ||
13 | --- a/arch/arm/mach-omap2/Makefile | ||
14 | +++ b/arch/arm/mach-omap2/Makefile | ||
15 | @@ -38,6 +38,11 @@ obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o | ||
16 | obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o | ||
17 | mailbox_mach-objs := mailbox.o | ||
18 | |||
19 | +iommu-y += iommu2.o | ||
20 | +iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o | ||
21 | + | ||
22 | +obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y) | ||
23 | + | ||
24 | # Specific board support | ||
25 | obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o | ||
26 | obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o board-h4-mmc.o | ||
27 | -- | ||
28 | 1.5.6.5 | ||
29 | |||