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-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0001-Revert-gro-Fix-legacy-path-napi_complete-crash.patch39
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0002-OMAPFB-move-omapfb.h-to-include-linux.patch1316
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0003-DSS2-OMAP2-3-Display-Subsystem-driver.patch14450
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0004-DSS2-OMAP-framebuffer-driver.patch3403
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0005-DSS2-Add-panel-drivers.patch396
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0006-DSS2-HACK-Add-DSS2-support-for-N800.patch1079
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0007-DSS2-Add-DSS2-support-for-SDP-Beagle-Overo-EVM.patch5715
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0008-DSS2-Add-function-to-display-object-to-get-the-back.patch39
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0009-DSS2-Add-acx565akm-panel.patch778
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0010-DSS2-Small-VRFB-context-allocation-bug-fixed.patch28
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0011-DSS2-Allocated-memory-for-Color-Look-up-table.patch37
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0012-DSS2-Fix-DMA-rotation.patch65
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0013-DSS2-Verify-that-overlay-paddr-0.patch41
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0014-DSS2-Add-function-to-get-DSS-logic-clock-rate.patch51
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch68
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0016-DSS2-DSI-improve-packet-len-calculation.patch58
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0017-DSS2-Disable-video-planes-on-sync-lost-error.patch103
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0018-DSS2-check-for-ovl-paddr-only-when-enabling.patch40
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0019-DSS2-Check-fclk-limits-when-configuring-video-plane.patch183
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0020-DSS2-Check-scaling-limits-against-proper-values.patch79
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0021-DSS2-Add-venc-register-dump.patch96
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0022-DSS2-FB-remove-unused-var-warning.patch27
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0023-DSS2-pass-the-default-FB-color-format-through-board.patch214
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0024-DSS2-Beagle-Use-gpio_set_value.patch48
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0025-DSS2-VRFB-Macro-for-calculating-base-address-of-th.patch28
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0026-DSS2-DSI-sidlemode-to-noidle-while-sending-frame.patch78
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0027-DSS2-VRFB-rotation-and-mirroring-implemented.patch324
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0028-DSS2-OMAPFB-Added-support-for-the-YUV-VRFB-rotatio.patch236
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0029-DSS2-OMAPFB-Set-line_length-correctly-for-YUV-with.patch61
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0030-DSS2-dispc_get_trans_key-was-returning-wrong-key-ty.patch29
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0031-DSS2-do-bootmem-reserve-for-exclusive-access.patch33
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0032-DSS2-Fix-DISPC_VID_FIR-value-for-omap34xx.patch35
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0033-DSS2-Prefer-3-tap-filter.patch82
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0034-DSS2-VRAM-improve-omap_vram_add_region.patch135
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0035-DSS2-Added-the-function-pointer-for-getting-default.patch66
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0036-DSS2-Added-support-for-setting-and-querying-alpha-b.patch118
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0037-DSS2-Added-support-for-querying-color-keying.patch150
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0038-DSS2-OMAPFB-Some-color-keying-pointerd-renamed-in-D.patch56
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0039-DSS2-Add-sysfs-entry-to-for-the-alpha-blending-supp.patch59
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0040-DSS2-Provided-proper-exclusion-for-destination-colo.patch97
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0041-DSS2-Disable-vertical-offset-with-fieldmode.patch71
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0042-DSS2-Don-t-enable-fieldmode-automatically.patch34
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0043-DSS2-Swap-field-0-and-field-1-registers.patch170
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0044-DSS2-add-sysfs-entry-for-seting-the-rotate-type.patch76
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0045-DSS2-Fixed-line-endings-from-to.patch48
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0046-DSS2-DSI-decrease-sync-timeout-from-60s-to-2s.patch26
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0047-DSS2-fix-return-value-for-rotate_type-sysfs-functio.patch44
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0048-OMAP2-3-DMA-implement-trans-copy-and-const-fill.patch123
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0049-DSS2-VRAM-clear-allocated-area-with-DMA.patch101
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0050-DSS2-OMAPFB-remove-fb-clearing-code.patch53
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0051-DSS2-VRAM-use-debugfs-not-procfs.patch170
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0052-DSS2-VRAM-fix-section-mismatch-warning.patch34
-rw-r--r--meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0053-DSS2-disable-LCD-DIGIT-before-resetting-DSS.patch41
53 files changed, 30931 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0001-Revert-gro-Fix-legacy-path-napi_complete-crash.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0001-Revert-gro-Fix-legacy-path-napi_complete-crash.patch
new file mode 100644
index 0000000000..aeab62f105
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0001-Revert-gro-Fix-legacy-path-napi_complete-crash.patch
@@ -0,0 +1,39 @@
1From 26abf45ac80be4c54a63fecf1c3c1e1efb416e0a Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Wed, 1 Apr 2009 18:27:09 +0300
4Subject: [PATCH] Revert "gro: Fix legacy path napi_complete crash"
5
6This reverts commit 303c6a0251852ecbdc5c15e466dcaff5971f7517.
7
8Fixes USB network problems
9---
10 net/core/dev.c | 5 ++---
11 1 files changed, 2 insertions(+), 3 deletions(-)
12
13diff --git a/net/core/dev.c b/net/core/dev.c
14index e3fe5c7..c1e9dc0 100644
15--- a/net/core/dev.c
16+++ b/net/core/dev.c
17@@ -2588,9 +2588,9 @@ static int process_backlog(struct napi_struct *napi, int quota)
18 local_irq_disable();
19 skb = __skb_dequeue(&queue->input_pkt_queue);
20 if (!skb) {
21+ __napi_complete(napi);
22 local_irq_enable();
23- napi_complete(napi);
24- goto out;
25+ break;
26 }
27 local_irq_enable();
28
29@@ -2599,7 +2599,6 @@ static int process_backlog(struct napi_struct *napi, int quota)
30
31 napi_gro_flush(napi);
32
33-out:
34 return work;
35 }
36
37--
381.5.6.5
39
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0002-OMAPFB-move-omapfb.h-to-include-linux.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0002-OMAPFB-move-omapfb.h-to-include-linux.patch
new file mode 100644
index 0000000000..04ac6a9ce8
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0002-OMAPFB-move-omapfb.h-to-include-linux.patch
@@ -0,0 +1,1316 @@
1From 02243f13eec816e11d16676a131bc04b8a0666ab Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Wed, 11 Feb 2009 16:33:02 +0200
4Subject: [PATCH] OMAPFB: move omapfb.h to include/linux/
5
6This is needed so that omapfb.h is automatically exported to user space.
7
8omapfb.h should be cleaned up later. Some stuff can probably be moved
9to omapfb's private include file.
10
11Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
12---
13 arch/arm/mach-omap1/board-nokia770.c | 2 +-
14 arch/arm/mach-omap2/board-n800.c | 2 +-
15 arch/arm/mach-omap2/io.c | 2 +-
16 arch/arm/plat-omap/fb.c | 2 +-
17 arch/arm/plat-omap/include/mach/omapfb.h | 398 ------------------------------
18 drivers/video/omap/blizzard.c | 2 +-
19 drivers/video/omap/dispc.c | 2 +-
20 drivers/video/omap/hwa742.c | 2 +-
21 drivers/video/omap/lcd_2430sdp.c | 2 +-
22 drivers/video/omap/lcd_ams_delta.c | 2 +-
23 drivers/video/omap/lcd_apollon.c | 2 +-
24 drivers/video/omap/lcd_h3.c | 2 +-
25 drivers/video/omap/lcd_h4.c | 3 +-
26 drivers/video/omap/lcd_inn1510.c | 2 +-
27 drivers/video/omap/lcd_inn1610.c | 2 +-
28 drivers/video/omap/lcd_ldp.c | 2 +-
29 drivers/video/omap/lcd_mipid.c | 2 +-
30 drivers/video/omap/lcd_omap2evm.c | 2 +-
31 drivers/video/omap/lcd_omap3beagle.c | 2 +-
32 drivers/video/omap/lcd_omap3evm.c | 2 +-
33 drivers/video/omap/lcd_osk.c | 2 +-
34 drivers/video/omap/lcd_overo.c | 2 +-
35 drivers/video/omap/lcd_p2.c | 2 +-
36 drivers/video/omap/lcd_palmte.c | 2 +-
37 drivers/video/omap/lcd_palmtt.c | 2 +-
38 drivers/video/omap/lcd_palmz71.c | 3 +-
39 drivers/video/omap/lcdc.c | 2 +-
40 drivers/video/omap/omapfb_main.c | 2 +-
41 drivers/video/omap/rfbi.c | 3 +-
42 drivers/video/omap/sossi.c | 2 +-
43 include/linux/omapfb.h | 398 ++++++++++++++++++++++++++++++
44 31 files changed, 427 insertions(+), 430 deletions(-)
45 delete mode 100644 arch/arm/plat-omap/include/mach/omapfb.h
46 create mode 100644 include/linux/omapfb.h
47
48diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
49index 8780ca6..ca4680a 100644
50--- a/arch/arm/mach-omap1/board-nokia770.c
51+++ b/arch/arm/mach-omap1/board-nokia770.c
52@@ -18,6 +18,7 @@
53 #include <linux/spi/spi.h>
54 #include <linux/spi/ads7846.h>
55 #include <linux/workqueue.h>
56+#include <linux/omapfb.h>
57 #include <linux/delay.h>
58
59 #include <mach/hardware.h>
60@@ -32,7 +33,6 @@
61 #include <mach/keypad.h>
62 #include <mach/common.h>
63 #include <mach/dsp_common.h>
64-#include <mach/omapfb.h>
65 #include <mach/lcd_mipid.h>
66 #include <mach/mmc.h>
67 #include <mach/usb.h>
68diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c
69index cb32b61..f6f6571 100644
70--- a/arch/arm/mach-omap2/board-n800.c
71+++ b/arch/arm/mach-omap2/board-n800.c
72@@ -27,6 +27,7 @@
73 #include <linux/i2c/lm8323.h>
74 #include <linux/i2c/menelaus.h>
75 #include <linux/i2c/lp5521.h>
76+#include <linux/omapfb.h>
77 #include <mach/hardware.h>
78 #include <asm/mach-types.h>
79 #include <asm/mach/arch.h>
80@@ -39,7 +40,6 @@
81 #include <mach/lcd_mipid.h>
82 #include <mach/clock.h>
83 #include <mach/gpio-switch.h>
84-#include <mach/omapfb.h>
85 #include <mach/blizzard.h>
86
87 #include <../drivers/cbus/tahvo.h>
88diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
89index adbe21f..a04e3ee 100644
90--- a/arch/arm/mach-omap2/io.c
91+++ b/arch/arm/mach-omap2/io.c
92@@ -18,13 +18,13 @@
93 #include <linux/module.h>
94 #include <linux/kernel.h>
95 #include <linux/init.h>
96+#include <linux/omapfb.h>
97 #include <linux/io.h>
98
99 #include <asm/tlb.h>
100
101 #include <asm/mach/map.h>
102 #include <mach/mux.h>
103-#include <mach/omapfb.h>
104 #include <mach/sram.h>
105 #include <mach/sdrc.h>
106 #include <mach/gpmc.h>
107diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
108index 3746222..40615a6 100644
109--- a/arch/arm/plat-omap/fb.c
110+++ b/arch/arm/plat-omap/fb.c
111@@ -28,13 +28,13 @@
112 #include <linux/platform_device.h>
113 #include <linux/bootmem.h>
114 #include <linux/io.h>
115+#include <linux/omapfb.h>
116
117 #include <mach/hardware.h>
118 #include <asm/mach/map.h>
119
120 #include <mach/board.h>
121 #include <mach/sram.h>
122-#include <mach/omapfb.h>
123
124 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
125
126diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
127deleted file mode 100644
128index b226bdf..0000000
129--- a/arch/arm/plat-omap/include/mach/omapfb.h
130+++ /dev/null
131@@ -1,398 +0,0 @@
132-/*
133- * File: arch/arm/plat-omap/include/mach/omapfb.h
134- *
135- * Framebuffer driver for TI OMAP boards
136- *
137- * Copyright (C) 2004 Nokia Corporation
138- * Author: Imre Deak <imre.deak@nokia.com>
139- *
140- * This program is free software; you can redistribute it and/or modify it
141- * under the terms of the GNU General Public License as published by the
142- * Free Software Foundation; either version 2 of the License, or (at your
143- * option) any later version.
144- *
145- * This program is distributed in the hope that it will be useful, but
146- * WITHOUT ANY WARRANTY; without even the implied warranty of
147- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
148- * General Public License for more details.
149- *
150- * You should have received a copy of the GNU General Public License along
151- * with this program; if not, write to the Free Software Foundation, Inc.,
152- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
153- */
154-
155-#ifndef __OMAPFB_H
156-#define __OMAPFB_H
157-
158-#include <asm/ioctl.h>
159-#include <asm/types.h>
160-
161-/* IOCTL commands. */
162-
163-#define OMAP_IOW(num, dtype) _IOW('O', num, dtype)
164-#define OMAP_IOR(num, dtype) _IOR('O', num, dtype)
165-#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype)
166-#define OMAP_IO(num) _IO('O', num)
167-
168-#define OMAPFB_MIRROR OMAP_IOW(31, int)
169-#define OMAPFB_SYNC_GFX OMAP_IO(37)
170-#define OMAPFB_VSYNC OMAP_IO(38)
171-#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int)
172-#define OMAPFB_GET_CAPS OMAP_IOR(42, struct omapfb_caps)
173-#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int)
174-#define OMAPFB_LCD_TEST OMAP_IOW(45, int)
175-#define OMAPFB_CTRL_TEST OMAP_IOW(46, int)
176-#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
177-#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key)
178-#define OMAPFB_GET_COLOR_KEY OMAP_IOW(51, struct omapfb_color_key)
179-#define OMAPFB_SETUP_PLANE OMAP_IOW(52, struct omapfb_plane_info)
180-#define OMAPFB_QUERY_PLANE OMAP_IOW(53, struct omapfb_plane_info)
181-#define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window)
182-#define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info)
183-#define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info)
184-
185-#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff
186-#define OMAPFB_CAPS_LCDC_MASK 0x00fff000
187-#define OMAPFB_CAPS_PANEL_MASK 0xff000000
188-
189-#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000
190-#define OMAPFB_CAPS_TEARSYNC 0x00002000
191-#define OMAPFB_CAPS_PLANE_RELOCATE_MEM 0x00004000
192-#define OMAPFB_CAPS_PLANE_SCALE 0x00008000
193-#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
194-#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
195-#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
196-#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000
197-#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
198-
199-/* Values from DSP must map to lower 16-bits */
200-#define OMAPFB_FORMAT_MASK 0x00ff
201-#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100
202-#define OMAPFB_FORMAT_FLAG_TEARSYNC 0x0200
203-#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC 0x0400
204-#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY 0x0800
205-#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY 0x1000
206-
207-#define OMAPFB_EVENT_READY 1
208-#define OMAPFB_EVENT_DISABLED 2
209-
210-#define OMAPFB_MEMTYPE_SDRAM 0
211-#define OMAPFB_MEMTYPE_SRAM 1
212-#define OMAPFB_MEMTYPE_MAX 1
213-
214-enum omapfb_color_format {
215- OMAPFB_COLOR_RGB565 = 0,
216- OMAPFB_COLOR_YUV422,
217- OMAPFB_COLOR_YUV420,
218- OMAPFB_COLOR_CLUT_8BPP,
219- OMAPFB_COLOR_CLUT_4BPP,
220- OMAPFB_COLOR_CLUT_2BPP,
221- OMAPFB_COLOR_CLUT_1BPP,
222- OMAPFB_COLOR_RGB444,
223- OMAPFB_COLOR_YUY422,
224-};
225-
226-struct omapfb_update_window {
227- __u32 x, y;
228- __u32 width, height;
229- __u32 format;
230- __u32 out_x, out_y;
231- __u32 out_width, out_height;
232- __u32 reserved[8];
233-};
234-
235-struct omapfb_update_window_old {
236- __u32 x, y;
237- __u32 width, height;
238- __u32 format;
239-};
240-
241-enum omapfb_plane {
242- OMAPFB_PLANE_GFX = 0,
243- OMAPFB_PLANE_VID1,
244- OMAPFB_PLANE_VID2,
245-};
246-
247-enum omapfb_channel_out {
248- OMAPFB_CHANNEL_OUT_LCD = 0,
249- OMAPFB_CHANNEL_OUT_DIGIT,
250-};
251-
252-struct omapfb_plane_info {
253- __u32 pos_x;
254- __u32 pos_y;
255- __u8 enabled;
256- __u8 channel_out;
257- __u8 mirror;
258- __u8 reserved1;
259- __u32 out_width;
260- __u32 out_height;
261- __u32 reserved2[12];
262-};
263-
264-struct omapfb_mem_info {
265- __u32 size;
266- __u8 type;
267- __u8 reserved[3];
268-};
269-
270-struct omapfb_caps {
271- __u32 ctrl;
272- __u32 plane_color;
273- __u32 wnd_color;
274-};
275-
276-enum omapfb_color_key_type {
277- OMAPFB_COLOR_KEY_DISABLED = 0,
278- OMAPFB_COLOR_KEY_GFX_DST,
279- OMAPFB_COLOR_KEY_VID_SRC,
280-};
281-
282-struct omapfb_color_key {
283- __u8 channel_out;
284- __u32 background;
285- __u32 trans_key;
286- __u8 key_type;
287-};
288-
289-enum omapfb_update_mode {
290- OMAPFB_UPDATE_DISABLED = 0,
291- OMAPFB_AUTO_UPDATE,
292- OMAPFB_MANUAL_UPDATE
293-};
294-
295-#ifdef __KERNEL__
296-
297-#include <linux/completion.h>
298-#include <linux/interrupt.h>
299-#include <linux/fb.h>
300-#include <linux/mutex.h>
301-
302-#include <mach/board.h>
303-
304-#define OMAP_LCDC_INV_VSYNC 0x0001
305-#define OMAP_LCDC_INV_HSYNC 0x0002
306-#define OMAP_LCDC_INV_PIX_CLOCK 0x0004
307-#define OMAP_LCDC_INV_OUTPUT_EN 0x0008
308-#define OMAP_LCDC_HSVS_RISING_EDGE 0x0010
309-#define OMAP_LCDC_HSVS_OPPOSITE 0x0020
310-
311-#define OMAP_LCDC_SIGNAL_MASK 0x003f
312-
313-#define OMAP_LCDC_PANEL_TFT 0x0100
314-
315-#define OMAPFB_PLANE_XRES_MIN 8
316-#define OMAPFB_PLANE_YRES_MIN 8
317-
318-#ifdef CONFIG_ARCH_OMAP1
319-#define OMAPFB_PLANE_NUM 1
320-#else
321-#define OMAPFB_PLANE_NUM 3
322-#endif
323-
324-struct omapfb_device;
325-
326-struct lcd_panel {
327- const char *name;
328- int config; /* TFT/STN, signal inversion */
329- int bpp; /* Pixel format in fb mem */
330- int data_lines; /* Lines on LCD HW interface */
331-
332- int x_res, y_res;
333- int pixel_clock; /* In kHz */
334- int hsw; /* Horizontal synchronization
335- pulse width */
336- int hfp; /* Horizontal front porch */
337- int hbp; /* Horizontal back porch */
338- int vsw; /* Vertical synchronization
339- pulse width */
340- int vfp; /* Vertical front porch */
341- int vbp; /* Vertical back porch */
342- int acb; /* ac-bias pin frequency */
343- int pcd; /* pixel clock divider.
344- Obsolete use pixel_clock instead */
345-
346- int (*init) (struct lcd_panel *panel,
347- struct omapfb_device *fbdev);
348- void (*cleanup) (struct lcd_panel *panel);
349- int (*enable) (struct lcd_panel *panel);
350- void (*disable) (struct lcd_panel *panel);
351- unsigned long (*get_caps) (struct lcd_panel *panel);
352- int (*set_bklight_level)(struct lcd_panel *panel,
353- unsigned int level);
354- unsigned int (*get_bklight_level)(struct lcd_panel *panel);
355- unsigned int (*get_bklight_max) (struct lcd_panel *panel);
356- int (*run_test) (struct lcd_panel *panel, int test_num);
357-};
358-
359-struct extif_timings {
360- int cs_on_time;
361- int cs_off_time;
362- int we_on_time;
363- int we_off_time;
364- int re_on_time;
365- int re_off_time;
366- int we_cycle_time;
367- int re_cycle_time;
368- int cs_pulse_width;
369- int access_time;
370-
371- int clk_div;
372-
373- u32 tim[5]; /* set by extif->convert_timings */
374-
375- int converted;
376-};
377-
378-struct lcd_ctrl_extif {
379- int (*init) (struct omapfb_device *fbdev);
380- void (*cleanup) (void);
381- void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div);
382- unsigned long (*get_max_tx_rate)(void);
383- int (*convert_timings) (struct extif_timings *timings);
384- void (*set_timings) (const struct extif_timings *timings);
385- void (*set_bits_per_cycle)(int bpc);
386- void (*write_command) (const void *buf, unsigned int len);
387- void (*read_data) (void *buf, unsigned int len);
388- void (*write_data) (const void *buf, unsigned int len);
389- void (*transfer_area) (int width, int height,
390- void (callback)(void * data), void *data);
391- int (*setup_tearsync) (unsigned pin_cnt,
392- unsigned hs_pulse_time, unsigned vs_pulse_time,
393- int hs_pol_inv, int vs_pol_inv, int div);
394- int (*enable_tearsync) (int enable, unsigned line);
395-
396- unsigned long max_transmit_size;
397-};
398-
399-struct omapfb_notifier_block {
400- struct notifier_block nb;
401- void *data;
402- int plane_idx;
403-};
404-
405-typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
406- unsigned long event,
407- void *fbi);
408-
409-struct omapfb_mem_region {
410- u32 paddr;
411- void __iomem *vaddr;
412- unsigned long size;
413- u8 type; /* OMAPFB_PLANE_MEM_* */
414- unsigned alloc:1; /* allocated by the driver */
415- unsigned map:1; /* kernel mapped by the driver */
416-};
417-
418-struct omapfb_mem_desc {
419- int region_cnt;
420- struct omapfb_mem_region region[OMAPFB_PLANE_NUM];
421-};
422-
423-struct lcd_ctrl {
424- const char *name;
425- void *data;
426-
427- int (*init) (struct omapfb_device *fbdev,
428- int ext_mode,
429- struct omapfb_mem_desc *req_md);
430- void (*cleanup) (void);
431- void (*bind_client) (struct omapfb_notifier_block *nb);
432- void (*get_caps) (int plane, struct omapfb_caps *caps);
433- int (*set_update_mode)(enum omapfb_update_mode mode);
434- enum omapfb_update_mode (*get_update_mode)(void);
435- int (*setup_plane) (int plane, int channel_out,
436- unsigned long offset,
437- int screen_width,
438- int pos_x, int pos_y, int width,
439- int height, int color_mode);
440- int (*set_rotate) (int angle);
441- int (*setup_mem) (int plane, size_t size,
442- int mem_type, unsigned long *paddr);
443- int (*mmap) (struct fb_info *info,
444- struct vm_area_struct *vma);
445- int (*set_scale) (int plane,
446- int orig_width, int orig_height,
447- int out_width, int out_height);
448- int (*enable_plane) (int plane, int enable);
449- int (*update_window) (struct fb_info *fbi,
450- struct omapfb_update_window *win,
451- void (*callback)(void *),
452- void *callback_data);
453- void (*sync) (void);
454- void (*suspend) (void);
455- void (*resume) (void);
456- int (*run_test) (int test_num);
457- int (*setcolreg) (u_int regno, u16 red, u16 green,
458- u16 blue, u16 transp,
459- int update_hw_mem);
460- int (*set_color_key) (struct omapfb_color_key *ck);
461- int (*get_color_key) (struct omapfb_color_key *ck);
462-};
463-
464-enum omapfb_state {
465- OMAPFB_DISABLED = 0,
466- OMAPFB_SUSPENDED= 99,
467- OMAPFB_ACTIVE = 100
468-};
469-
470-struct omapfb_plane_struct {
471- int idx;
472- struct omapfb_plane_info info;
473- enum omapfb_color_format color_mode;
474- struct omapfb_device *fbdev;
475-};
476-
477-struct omapfb_device {
478- int state;
479- int ext_lcdc; /* Using external
480- LCD controller */
481- struct mutex rqueue_mutex;
482-
483- int palette_size;
484- u32 pseudo_palette[17];
485-
486- struct lcd_panel *panel; /* LCD panel */
487- const struct lcd_ctrl *ctrl; /* LCD controller */
488- const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */
489- struct lcd_ctrl_extif *ext_if; /* LCD ctrl external
490- interface */
491- struct device *dev;
492- struct fb_var_screeninfo new_var; /* for mode changes */
493-
494- struct omapfb_mem_desc mem_desc;
495- struct fb_info *fb_info[OMAPFB_PLANE_NUM];
496-};
497-
498-struct omapfb_platform_data {
499- struct omap_lcd_config lcd;
500- struct omapfb_mem_desc mem_desc;
501- void *ctrl_platform_data;
502-};
503-
504-#ifdef CONFIG_ARCH_OMAP1
505-extern struct lcd_ctrl omap1_lcd_ctrl;
506-#else
507-extern struct lcd_ctrl omap2_disp_ctrl;
508-#endif
509-
510-extern void omapfb_reserve_sdram(void);
511-extern void omapfb_register_panel(struct lcd_panel *panel);
512-extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
513-extern void omapfb_notify_clients(struct omapfb_device *fbdev,
514- unsigned long event);
515-extern int omapfb_register_client(struct omapfb_notifier_block *nb,
516- omapfb_notifier_callback_t callback,
517- void *callback_data);
518-extern int omapfb_unregister_client(struct omapfb_notifier_block *nb);
519-extern int omapfb_update_window_async(struct fb_info *fbi,
520- struct omapfb_update_window *win,
521- void (*callback)(void *),
522- void *callback_data);
523-
524-/* in arch/arm/plat-omap/fb.c */
525-extern void omapfb_set_ctrl_platform_data(void *pdata);
526-
527-#endif /* __KERNEL__ */
528-
529-#endif /* __OMAPFB_H */
530diff --git a/drivers/video/omap/blizzard.c b/drivers/video/omap/blizzard.c
531index f60a233..8121c09 100644
532--- a/drivers/video/omap/blizzard.c
533+++ b/drivers/video/omap/blizzard.c
534@@ -25,9 +25,9 @@
535 #include <linux/fb.h>
536 #include <linux/delay.h>
537 #include <linux/clk.h>
538+#include <linux/omapfb.h>
539
540 #include <mach/dma.h>
541-#include <mach/omapfb.h>
542 #include <mach/blizzard.h>
543
544 #include "dispc.h"
545diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
546index c140c21..1915af5 100644
547--- a/drivers/video/omap/dispc.c
548+++ b/drivers/video/omap/dispc.c
549@@ -24,9 +24,9 @@
550 #include <linux/vmalloc.h>
551 #include <linux/clk.h>
552 #include <linux/io.h>
553+#include <linux/omapfb.h>
554
555 #include <mach/sram.h>
556-#include <mach/omapfb.h>
557 #include <mach/board.h>
558
559 #include "dispc.h"
560diff --git a/drivers/video/omap/hwa742.c b/drivers/video/omap/hwa742.c
561index f24df0b..9b4c506 100644
562--- a/drivers/video/omap/hwa742.c
563+++ b/drivers/video/omap/hwa742.c
564@@ -25,9 +25,9 @@
565 #include <linux/fb.h>
566 #include <linux/delay.h>
567 #include <linux/clk.h>
568+#include <linux/omapfb.h>
569
570 #include <mach/dma.h>
571-#include <mach/omapfb.h>
572 #include <mach/hwa742.h>
573
574 #define HWA742_REV_CODE_REG 0x0
575diff --git a/drivers/video/omap/lcd_2430sdp.c b/drivers/video/omap/lcd_2430sdp.c
576index a22b452..1252cc3 100644
577--- a/drivers/video/omap/lcd_2430sdp.c
578+++ b/drivers/video/omap/lcd_2430sdp.c
579@@ -26,9 +26,9 @@
580 #include <linux/delay.h>
581 #include <linux/gpio.h>
582 #include <linux/i2c/twl4030.h>
583+#include <linux/omapfb.h>
584
585 #include <mach/mux.h>
586-#include <mach/omapfb.h>
587 #include <asm/mach-types.h>
588
589 #define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91
590diff --git a/drivers/video/omap/lcd_ams_delta.c b/drivers/video/omap/lcd_ams_delta.c
591index 3fd5342..4d54725 100644
592--- a/drivers/video/omap/lcd_ams_delta.c
593+++ b/drivers/video/omap/lcd_ams_delta.c
594@@ -24,13 +24,13 @@
595
596 #include <linux/module.h>
597 #include <linux/platform_device.h>
598+#include <linux/omapfb.h>
599
600 #include <asm/delay.h>
601 #include <asm/io.h>
602
603 #include <mach/board-ams-delta.h>
604 #include <mach/hardware.h>
605-#include <mach/omapfb.h>
606
607 #define AMS_DELTA_DEFAULT_CONTRAST 112
608
609diff --git a/drivers/video/omap/lcd_apollon.c b/drivers/video/omap/lcd_apollon.c
610index beae5d9..e3b2224 100644
611--- a/drivers/video/omap/lcd_apollon.c
612+++ b/drivers/video/omap/lcd_apollon.c
613@@ -23,10 +23,10 @@
614
615 #include <linux/module.h>
616 #include <linux/platform_device.h>
617+#include <linux/omapfb.h>
618
619 #include <mach/gpio.h>
620 #include <mach/mux.h>
621-#include <mach/omapfb.h>
622
623 /* #define USE_35INCH_LCD 1 */
624
625diff --git a/drivers/video/omap/lcd_h3.c b/drivers/video/omap/lcd_h3.c
626index 2486237..f7264ea 100644
627--- a/drivers/video/omap/lcd_h3.c
628+++ b/drivers/video/omap/lcd_h3.c
629@@ -22,9 +22,9 @@
630 #include <linux/module.h>
631 #include <linux/platform_device.h>
632 #include <linux/i2c/tps65010.h>
633+#include <linux/omapfb.h>
634
635 #include <mach/gpio.h>
636-#include <mach/omapfb.h>
637
638 #define MODULE_NAME "omapfb-lcd_h3"
639
640diff --git a/drivers/video/omap/lcd_h4.c b/drivers/video/omap/lcd_h4.c
641index 6ff5643..d72df0c 100644
642--- a/drivers/video/omap/lcd_h4.c
643+++ b/drivers/video/omap/lcd_h4.c
644@@ -21,8 +21,7 @@
645
646 #include <linux/module.h>
647 #include <linux/platform_device.h>
648-
649-#include <mach/omapfb.h>
650+#include <linux/omapfb.h>
651
652 static int h4_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
653 {
654diff --git a/drivers/video/omap/lcd_inn1510.c b/drivers/video/omap/lcd_inn1510.c
655index 6953ed4..f6e05d7 100644
656--- a/drivers/video/omap/lcd_inn1510.c
657+++ b/drivers/video/omap/lcd_inn1510.c
658@@ -22,9 +22,9 @@
659 #include <linux/module.h>
660 #include <linux/platform_device.h>
661 #include <linux/io.h>
662+#include <linux/omapfb.h>
663
664 #include <mach/fpga.h>
665-#include <mach/omapfb.h>
666
667 static int innovator1510_panel_init(struct lcd_panel *panel,
668 struct omapfb_device *fbdev)
669diff --git a/drivers/video/omap/lcd_inn1610.c b/drivers/video/omap/lcd_inn1610.c
670index 4c4f7ee..c599e41 100644
671--- a/drivers/video/omap/lcd_inn1610.c
672+++ b/drivers/video/omap/lcd_inn1610.c
673@@ -21,9 +21,9 @@
674
675 #include <linux/module.h>
676 #include <linux/platform_device.h>
677+#include <linux/omapfb.h>
678
679 #include <mach/gpio.h>
680-#include <mach/omapfb.h>
681
682 #define MODULE_NAME "omapfb-lcd_h3"
683
684diff --git a/drivers/video/omap/lcd_ldp.c b/drivers/video/omap/lcd_ldp.c
685index 8925230..1c25186 100644
686--- a/drivers/video/omap/lcd_ldp.c
687+++ b/drivers/video/omap/lcd_ldp.c
688@@ -25,10 +25,10 @@
689 #include <linux/platform_device.h>
690 #include <linux/delay.h>
691 #include <linux/i2c/twl4030.h>
692+#include <linux/omapfb.h>
693
694 #include <mach/gpio.h>
695 #include <mach/mux.h>
696-#include <mach/omapfb.h>
697 #include <asm/mach-types.h>
698
699 #define LCD_PANEL_BACKLIGHT_GPIO (15 + OMAP_MAX_GPIO_LINES)
700diff --git a/drivers/video/omap/lcd_mipid.c b/drivers/video/omap/lcd_mipid.c
701index 1895997..4b28005 100644
702--- a/drivers/video/omap/lcd_mipid.c
703+++ b/drivers/video/omap/lcd_mipid.c
704@@ -22,8 +22,8 @@
705 #include <linux/delay.h>
706 #include <linux/workqueue.h>
707 #include <linux/spi/spi.h>
708+#include <linux/omapfb.h>
709
710-#include <mach/omapfb.h>
711 #include <mach/lcd_mipid.h>
712
713 #include "../../cbus/tahvo.h"
714diff --git a/drivers/video/omap/lcd_omap2evm.c b/drivers/video/omap/lcd_omap2evm.c
715index 2fc46c2..1908a2b 100644
716--- a/drivers/video/omap/lcd_omap2evm.c
717+++ b/drivers/video/omap/lcd_omap2evm.c
718@@ -25,9 +25,9 @@
719 #include <linux/platform_device.h>
720 #include <linux/gpio.h>
721 #include <linux/i2c/twl4030.h>
722+#include <linux/omapfb.h>
723
724 #include <mach/mux.h>
725-#include <mach/omapfb.h>
726 #include <asm/mach-types.h>
727
728 #define LCD_PANEL_ENABLE_GPIO 154
729diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c
730index eae43e4..6be117e 100644
731--- a/drivers/video/omap/lcd_omap3beagle.c
732+++ b/drivers/video/omap/lcd_omap3beagle.c
733@@ -24,9 +24,9 @@
734 #include <linux/platform_device.h>
735 #include <linux/gpio.h>
736 #include <linux/i2c/twl4030.h>
737+#include <linux/omapfb.h>
738
739 #include <mach/mux.h>
740-#include <mach/omapfb.h>
741 #include <asm/mach-types.h>
742
743 #define LCD_PANEL_ENABLE_GPIO 170
744diff --git a/drivers/video/omap/lcd_omap3evm.c b/drivers/video/omap/lcd_omap3evm.c
745index 1c3d814..10ba48c 100644
746--- a/drivers/video/omap/lcd_omap3evm.c
747+++ b/drivers/video/omap/lcd_omap3evm.c
748@@ -24,9 +24,9 @@
749 #include <linux/platform_device.h>
750 #include <linux/gpio.h>
751 #include <linux/i2c/twl4030.h>
752+#include <linux/omapfb.h>
753
754 #include <mach/mux.h>
755-#include <mach/omapfb.h>
756 #include <asm/mach-types.h>
757
758 #define LCD_PANEL_ENABLE_GPIO 153
759diff --git a/drivers/video/omap/lcd_osk.c b/drivers/video/omap/lcd_osk.c
760index 379c96d..d6b193e 100644
761--- a/drivers/video/omap/lcd_osk.c
762+++ b/drivers/video/omap/lcd_osk.c
763@@ -22,10 +22,10 @@
764
765 #include <linux/module.h>
766 #include <linux/platform_device.h>
767+#include <linux/omapfb.h>
768
769 #include <mach/gpio.h>
770 #include <mach/mux.h>
771-#include <mach/omapfb.h>
772
773 static int osk_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
774 {
775diff --git a/drivers/video/omap/lcd_overo.c b/drivers/video/omap/lcd_overo.c
776index 2bc5c92..40c2026 100644
777--- a/drivers/video/omap/lcd_overo.c
778+++ b/drivers/video/omap/lcd_overo.c
779@@ -22,10 +22,10 @@
780 #include <linux/module.h>
781 #include <linux/platform_device.h>
782 #include <linux/i2c/twl4030.h>
783+#include <linux/omapfb.h>
784
785 #include <mach/gpio.h>
786 #include <mach/mux.h>
787-#include <mach/omapfb.h>
788 #include <asm/mach-types.h>
789
790 #define LCD_ENABLE 144
791diff --git a/drivers/video/omap/lcd_p2.c b/drivers/video/omap/lcd_p2.c
792index dd40fd7..bc5abef 100644
793--- a/drivers/video/omap/lcd_p2.c
794+++ b/drivers/video/omap/lcd_p2.c
795@@ -24,10 +24,10 @@
796 #include <linux/module.h>
797 #include <linux/delay.h>
798 #include <linux/platform_device.h>
799+#include <linux/omapfb.h>
800
801 #include <mach/mux.h>
802 #include <mach/gpio.h>
803-#include <mach/omapfb.h>
804
805 /*
806 * File: epson-md-tft.h
807diff --git a/drivers/video/omap/lcd_palmte.c b/drivers/video/omap/lcd_palmte.c
808index 2183173..dcb456c 100644
809--- a/drivers/video/omap/lcd_palmte.c
810+++ b/drivers/video/omap/lcd_palmte.c
811@@ -22,9 +22,9 @@
812 #include <linux/module.h>
813 #include <linux/platform_device.h>
814 #include <linux/io.h>
815+#include <linux/omapfb.h>
816
817 #include <mach/fpga.h>
818-#include <mach/omapfb.h>
819
820 static int palmte_panel_init(struct lcd_panel *panel,
821 struct omapfb_device *fbdev)
822diff --git a/drivers/video/omap/lcd_palmtt.c b/drivers/video/omap/lcd_palmtt.c
823index 57b0f6c..e8adab8 100644
824--- a/drivers/video/omap/lcd_palmtt.c
825+++ b/drivers/video/omap/lcd_palmtt.c
826@@ -28,9 +28,9 @@ GPIO13 - screen blanking
827 #include <linux/platform_device.h>
828 #include <linux/module.h>
829 #include <linux/io.h>
830+#include <linux/omapfb.h>
831
832 #include <mach/gpio.h>
833-#include <mach/omapfb.h>
834
835 static int palmtt_panel_init(struct lcd_panel *panel,
836 struct omapfb_device *fbdev)
837diff --git a/drivers/video/omap/lcd_palmz71.c b/drivers/video/omap/lcd_palmz71.c
838index d33d78b..d5b3f82 100644
839--- a/drivers/video/omap/lcd_palmz71.c
840+++ b/drivers/video/omap/lcd_palmz71.c
841@@ -23,8 +23,7 @@
842 #include <linux/module.h>
843 #include <linux/platform_device.h>
844 #include <linux/io.h>
845-
846-#include <mach/omapfb.h>
847+#include <linux/omapfb.h>
848
849 static int palmz71_panel_init(struct lcd_panel *panel,
850 struct omapfb_device *fbdev)
851diff --git a/drivers/video/omap/lcdc.c b/drivers/video/omap/lcdc.c
852index ab39492..633e33c 100644
853--- a/drivers/video/omap/lcdc.c
854+++ b/drivers/video/omap/lcdc.c
855@@ -28,9 +28,9 @@
856 #include <linux/dma-mapping.h>
857 #include <linux/vmalloc.h>
858 #include <linux/clk.h>
859+#include <linux/omapfb.h>
860
861 #include <mach/dma.h>
862-#include <mach/omapfb.h>
863
864 #include <asm/mach-types.h>
865
866diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
867index 3bb4247..c6306af 100644
868--- a/drivers/video/omap/omapfb_main.c
869+++ b/drivers/video/omap/omapfb_main.c
870@@ -27,9 +27,9 @@
871 #include <linux/platform_device.h>
872 #include <linux/mm.h>
873 #include <linux/uaccess.h>
874+#include <linux/omapfb.h>
875
876 #include <mach/dma.h>
877-#include <mach/omapfb.h>
878
879 #include "lcdc.h"
880 #include "dispc.h"
881diff --git a/drivers/video/omap/rfbi.c b/drivers/video/omap/rfbi.c
882index 29fa368..118cfa9 100644
883--- a/drivers/video/omap/rfbi.c
884+++ b/drivers/video/omap/rfbi.c
885@@ -26,8 +26,7 @@
886 #include <linux/interrupt.h>
887 #include <linux/clk.h>
888 #include <linux/io.h>
889-
890-#include <mach/omapfb.h>
891+#include <linux/omapfb.h>
892
893 #include "dispc.h"
894
895diff --git a/drivers/video/omap/sossi.c b/drivers/video/omap/sossi.c
896index cc697cc..ff9dd71 100644
897--- a/drivers/video/omap/sossi.c
898+++ b/drivers/video/omap/sossi.c
899@@ -23,9 +23,9 @@
900 #include <linux/clk.h>
901 #include <linux/irq.h>
902 #include <linux/io.h>
903+#include <linux/omapfb.h>
904
905 #include <mach/dma.h>
906-#include <mach/omapfb.h>
907
908 #include "lcdc.h"
909
910diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
911new file mode 100644
912index 0000000..b226bdf
913--- /dev/null
914+++ b/include/linux/omapfb.h
915@@ -0,0 +1,398 @@
916+/*
917+ * File: arch/arm/plat-omap/include/mach/omapfb.h
918+ *
919+ * Framebuffer driver for TI OMAP boards
920+ *
921+ * Copyright (C) 2004 Nokia Corporation
922+ * Author: Imre Deak <imre.deak@nokia.com>
923+ *
924+ * This program is free software; you can redistribute it and/or modify it
925+ * under the terms of the GNU General Public License as published by the
926+ * Free Software Foundation; either version 2 of the License, or (at your
927+ * option) any later version.
928+ *
929+ * This program is distributed in the hope that it will be useful, but
930+ * WITHOUT ANY WARRANTY; without even the implied warranty of
931+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
932+ * General Public License for more details.
933+ *
934+ * You should have received a copy of the GNU General Public License along
935+ * with this program; if not, write to the Free Software Foundation, Inc.,
936+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
937+ */
938+
939+#ifndef __OMAPFB_H
940+#define __OMAPFB_H
941+
942+#include <asm/ioctl.h>
943+#include <asm/types.h>
944+
945+/* IOCTL commands. */
946+
947+#define OMAP_IOW(num, dtype) _IOW('O', num, dtype)
948+#define OMAP_IOR(num, dtype) _IOR('O', num, dtype)
949+#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype)
950+#define OMAP_IO(num) _IO('O', num)
951+
952+#define OMAPFB_MIRROR OMAP_IOW(31, int)
953+#define OMAPFB_SYNC_GFX OMAP_IO(37)
954+#define OMAPFB_VSYNC OMAP_IO(38)
955+#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int)
956+#define OMAPFB_GET_CAPS OMAP_IOR(42, struct omapfb_caps)
957+#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int)
958+#define OMAPFB_LCD_TEST OMAP_IOW(45, int)
959+#define OMAPFB_CTRL_TEST OMAP_IOW(46, int)
960+#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
961+#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key)
962+#define OMAPFB_GET_COLOR_KEY OMAP_IOW(51, struct omapfb_color_key)
963+#define OMAPFB_SETUP_PLANE OMAP_IOW(52, struct omapfb_plane_info)
964+#define OMAPFB_QUERY_PLANE OMAP_IOW(53, struct omapfb_plane_info)
965+#define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window)
966+#define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info)
967+#define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info)
968+
969+#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff
970+#define OMAPFB_CAPS_LCDC_MASK 0x00fff000
971+#define OMAPFB_CAPS_PANEL_MASK 0xff000000
972+
973+#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000
974+#define OMAPFB_CAPS_TEARSYNC 0x00002000
975+#define OMAPFB_CAPS_PLANE_RELOCATE_MEM 0x00004000
976+#define OMAPFB_CAPS_PLANE_SCALE 0x00008000
977+#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
978+#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
979+#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
980+#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000
981+#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
982+
983+/* Values from DSP must map to lower 16-bits */
984+#define OMAPFB_FORMAT_MASK 0x00ff
985+#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100
986+#define OMAPFB_FORMAT_FLAG_TEARSYNC 0x0200
987+#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC 0x0400
988+#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY 0x0800
989+#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY 0x1000
990+
991+#define OMAPFB_EVENT_READY 1
992+#define OMAPFB_EVENT_DISABLED 2
993+
994+#define OMAPFB_MEMTYPE_SDRAM 0
995+#define OMAPFB_MEMTYPE_SRAM 1
996+#define OMAPFB_MEMTYPE_MAX 1
997+
998+enum omapfb_color_format {
999+ OMAPFB_COLOR_RGB565 = 0,
1000+ OMAPFB_COLOR_YUV422,
1001+ OMAPFB_COLOR_YUV420,
1002+ OMAPFB_COLOR_CLUT_8BPP,
1003+ OMAPFB_COLOR_CLUT_4BPP,
1004+ OMAPFB_COLOR_CLUT_2BPP,
1005+ OMAPFB_COLOR_CLUT_1BPP,
1006+ OMAPFB_COLOR_RGB444,
1007+ OMAPFB_COLOR_YUY422,
1008+};
1009+
1010+struct omapfb_update_window {
1011+ __u32 x, y;
1012+ __u32 width, height;
1013+ __u32 format;
1014+ __u32 out_x, out_y;
1015+ __u32 out_width, out_height;
1016+ __u32 reserved[8];
1017+};
1018+
1019+struct omapfb_update_window_old {
1020+ __u32 x, y;
1021+ __u32 width, height;
1022+ __u32 format;
1023+};
1024+
1025+enum omapfb_plane {
1026+ OMAPFB_PLANE_GFX = 0,
1027+ OMAPFB_PLANE_VID1,
1028+ OMAPFB_PLANE_VID2,
1029+};
1030+
1031+enum omapfb_channel_out {
1032+ OMAPFB_CHANNEL_OUT_LCD = 0,
1033+ OMAPFB_CHANNEL_OUT_DIGIT,
1034+};
1035+
1036+struct omapfb_plane_info {
1037+ __u32 pos_x;
1038+ __u32 pos_y;
1039+ __u8 enabled;
1040+ __u8 channel_out;
1041+ __u8 mirror;
1042+ __u8 reserved1;
1043+ __u32 out_width;
1044+ __u32 out_height;
1045+ __u32 reserved2[12];
1046+};
1047+
1048+struct omapfb_mem_info {
1049+ __u32 size;
1050+ __u8 type;
1051+ __u8 reserved[3];
1052+};
1053+
1054+struct omapfb_caps {
1055+ __u32 ctrl;
1056+ __u32 plane_color;
1057+ __u32 wnd_color;
1058+};
1059+
1060+enum omapfb_color_key_type {
1061+ OMAPFB_COLOR_KEY_DISABLED = 0,
1062+ OMAPFB_COLOR_KEY_GFX_DST,
1063+ OMAPFB_COLOR_KEY_VID_SRC,
1064+};
1065+
1066+struct omapfb_color_key {
1067+ __u8 channel_out;
1068+ __u32 background;
1069+ __u32 trans_key;
1070+ __u8 key_type;
1071+};
1072+
1073+enum omapfb_update_mode {
1074+ OMAPFB_UPDATE_DISABLED = 0,
1075+ OMAPFB_AUTO_UPDATE,
1076+ OMAPFB_MANUAL_UPDATE
1077+};
1078+
1079+#ifdef __KERNEL__
1080+
1081+#include <linux/completion.h>
1082+#include <linux/interrupt.h>
1083+#include <linux/fb.h>
1084+#include <linux/mutex.h>
1085+
1086+#include <mach/board.h>
1087+
1088+#define OMAP_LCDC_INV_VSYNC 0x0001
1089+#define OMAP_LCDC_INV_HSYNC 0x0002
1090+#define OMAP_LCDC_INV_PIX_CLOCK 0x0004
1091+#define OMAP_LCDC_INV_OUTPUT_EN 0x0008
1092+#define OMAP_LCDC_HSVS_RISING_EDGE 0x0010
1093+#define OMAP_LCDC_HSVS_OPPOSITE 0x0020
1094+
1095+#define OMAP_LCDC_SIGNAL_MASK 0x003f
1096+
1097+#define OMAP_LCDC_PANEL_TFT 0x0100
1098+
1099+#define OMAPFB_PLANE_XRES_MIN 8
1100+#define OMAPFB_PLANE_YRES_MIN 8
1101+
1102+#ifdef CONFIG_ARCH_OMAP1
1103+#define OMAPFB_PLANE_NUM 1
1104+#else
1105+#define OMAPFB_PLANE_NUM 3
1106+#endif
1107+
1108+struct omapfb_device;
1109+
1110+struct lcd_panel {
1111+ const char *name;
1112+ int config; /* TFT/STN, signal inversion */
1113+ int bpp; /* Pixel format in fb mem */
1114+ int data_lines; /* Lines on LCD HW interface */
1115+
1116+ int x_res, y_res;
1117+ int pixel_clock; /* In kHz */
1118+ int hsw; /* Horizontal synchronization
1119+ pulse width */
1120+ int hfp; /* Horizontal front porch */
1121+ int hbp; /* Horizontal back porch */
1122+ int vsw; /* Vertical synchronization
1123+ pulse width */
1124+ int vfp; /* Vertical front porch */
1125+ int vbp; /* Vertical back porch */
1126+ int acb; /* ac-bias pin frequency */
1127+ int pcd; /* pixel clock divider.
1128+ Obsolete use pixel_clock instead */
1129+
1130+ int (*init) (struct lcd_panel *panel,
1131+ struct omapfb_device *fbdev);
1132+ void (*cleanup) (struct lcd_panel *panel);
1133+ int (*enable) (struct lcd_panel *panel);
1134+ void (*disable) (struct lcd_panel *panel);
1135+ unsigned long (*get_caps) (struct lcd_panel *panel);
1136+ int (*set_bklight_level)(struct lcd_panel *panel,
1137+ unsigned int level);
1138+ unsigned int (*get_bklight_level)(struct lcd_panel *panel);
1139+ unsigned int (*get_bklight_max) (struct lcd_panel *panel);
1140+ int (*run_test) (struct lcd_panel *panel, int test_num);
1141+};
1142+
1143+struct extif_timings {
1144+ int cs_on_time;
1145+ int cs_off_time;
1146+ int we_on_time;
1147+ int we_off_time;
1148+ int re_on_time;
1149+ int re_off_time;
1150+ int we_cycle_time;
1151+ int re_cycle_time;
1152+ int cs_pulse_width;
1153+ int access_time;
1154+
1155+ int clk_div;
1156+
1157+ u32 tim[5]; /* set by extif->convert_timings */
1158+
1159+ int converted;
1160+};
1161+
1162+struct lcd_ctrl_extif {
1163+ int (*init) (struct omapfb_device *fbdev);
1164+ void (*cleanup) (void);
1165+ void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div);
1166+ unsigned long (*get_max_tx_rate)(void);
1167+ int (*convert_timings) (struct extif_timings *timings);
1168+ void (*set_timings) (const struct extif_timings *timings);
1169+ void (*set_bits_per_cycle)(int bpc);
1170+ void (*write_command) (const void *buf, unsigned int len);
1171+ void (*read_data) (void *buf, unsigned int len);
1172+ void (*write_data) (const void *buf, unsigned int len);
1173+ void (*transfer_area) (int width, int height,
1174+ void (callback)(void * data), void *data);
1175+ int (*setup_tearsync) (unsigned pin_cnt,
1176+ unsigned hs_pulse_time, unsigned vs_pulse_time,
1177+ int hs_pol_inv, int vs_pol_inv, int div);
1178+ int (*enable_tearsync) (int enable, unsigned line);
1179+
1180+ unsigned long max_transmit_size;
1181+};
1182+
1183+struct omapfb_notifier_block {
1184+ struct notifier_block nb;
1185+ void *data;
1186+ int plane_idx;
1187+};
1188+
1189+typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
1190+ unsigned long event,
1191+ void *fbi);
1192+
1193+struct omapfb_mem_region {
1194+ u32 paddr;
1195+ void __iomem *vaddr;
1196+ unsigned long size;
1197+ u8 type; /* OMAPFB_PLANE_MEM_* */
1198+ unsigned alloc:1; /* allocated by the driver */
1199+ unsigned map:1; /* kernel mapped by the driver */
1200+};
1201+
1202+struct omapfb_mem_desc {
1203+ int region_cnt;
1204+ struct omapfb_mem_region region[OMAPFB_PLANE_NUM];
1205+};
1206+
1207+struct lcd_ctrl {
1208+ const char *name;
1209+ void *data;
1210+
1211+ int (*init) (struct omapfb_device *fbdev,
1212+ int ext_mode,
1213+ struct omapfb_mem_desc *req_md);
1214+ void (*cleanup) (void);
1215+ void (*bind_client) (struct omapfb_notifier_block *nb);
1216+ void (*get_caps) (int plane, struct omapfb_caps *caps);
1217+ int (*set_update_mode)(enum omapfb_update_mode mode);
1218+ enum omapfb_update_mode (*get_update_mode)(void);
1219+ int (*setup_plane) (int plane, int channel_out,
1220+ unsigned long offset,
1221+ int screen_width,
1222+ int pos_x, int pos_y, int width,
1223+ int height, int color_mode);
1224+ int (*set_rotate) (int angle);
1225+ int (*setup_mem) (int plane, size_t size,
1226+ int mem_type, unsigned long *paddr);
1227+ int (*mmap) (struct fb_info *info,
1228+ struct vm_area_struct *vma);
1229+ int (*set_scale) (int plane,
1230+ int orig_width, int orig_height,
1231+ int out_width, int out_height);
1232+ int (*enable_plane) (int plane, int enable);
1233+ int (*update_window) (struct fb_info *fbi,
1234+ struct omapfb_update_window *win,
1235+ void (*callback)(void *),
1236+ void *callback_data);
1237+ void (*sync) (void);
1238+ void (*suspend) (void);
1239+ void (*resume) (void);
1240+ int (*run_test) (int test_num);
1241+ int (*setcolreg) (u_int regno, u16 red, u16 green,
1242+ u16 blue, u16 transp,
1243+ int update_hw_mem);
1244+ int (*set_color_key) (struct omapfb_color_key *ck);
1245+ int (*get_color_key) (struct omapfb_color_key *ck);
1246+};
1247+
1248+enum omapfb_state {
1249+ OMAPFB_DISABLED = 0,
1250+ OMAPFB_SUSPENDED= 99,
1251+ OMAPFB_ACTIVE = 100
1252+};
1253+
1254+struct omapfb_plane_struct {
1255+ int idx;
1256+ struct omapfb_plane_info info;
1257+ enum omapfb_color_format color_mode;
1258+ struct omapfb_device *fbdev;
1259+};
1260+
1261+struct omapfb_device {
1262+ int state;
1263+ int ext_lcdc; /* Using external
1264+ LCD controller */
1265+ struct mutex rqueue_mutex;
1266+
1267+ int palette_size;
1268+ u32 pseudo_palette[17];
1269+
1270+ struct lcd_panel *panel; /* LCD panel */
1271+ const struct lcd_ctrl *ctrl; /* LCD controller */
1272+ const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */
1273+ struct lcd_ctrl_extif *ext_if; /* LCD ctrl external
1274+ interface */
1275+ struct device *dev;
1276+ struct fb_var_screeninfo new_var; /* for mode changes */
1277+
1278+ struct omapfb_mem_desc mem_desc;
1279+ struct fb_info *fb_info[OMAPFB_PLANE_NUM];
1280+};
1281+
1282+struct omapfb_platform_data {
1283+ struct omap_lcd_config lcd;
1284+ struct omapfb_mem_desc mem_desc;
1285+ void *ctrl_platform_data;
1286+};
1287+
1288+#ifdef CONFIG_ARCH_OMAP1
1289+extern struct lcd_ctrl omap1_lcd_ctrl;
1290+#else
1291+extern struct lcd_ctrl omap2_disp_ctrl;
1292+#endif
1293+
1294+extern void omapfb_reserve_sdram(void);
1295+extern void omapfb_register_panel(struct lcd_panel *panel);
1296+extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
1297+extern void omapfb_notify_clients(struct omapfb_device *fbdev,
1298+ unsigned long event);
1299+extern int omapfb_register_client(struct omapfb_notifier_block *nb,
1300+ omapfb_notifier_callback_t callback,
1301+ void *callback_data);
1302+extern int omapfb_unregister_client(struct omapfb_notifier_block *nb);
1303+extern int omapfb_update_window_async(struct fb_info *fbi,
1304+ struct omapfb_update_window *win,
1305+ void (*callback)(void *),
1306+ void *callback_data);
1307+
1308+/* in arch/arm/plat-omap/fb.c */
1309+extern void omapfb_set_ctrl_platform_data(void *pdata);
1310+
1311+#endif /* __KERNEL__ */
1312+
1313+#endif /* __OMAPFB_H */
1314--
13151.5.6.5
1316
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0003-DSS2-OMAP2-3-Display-Subsystem-driver.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0003-DSS2-OMAP2-3-Display-Subsystem-driver.patch
new file mode 100644
index 0000000000..c3523362c6
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0003-DSS2-OMAP2-3-Display-Subsystem-driver.patch
@@ -0,0 +1,14450 @@
1From 284deec412f9c6f15c971d8eaf4d0156a51a2f3b Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 2 Apr 2009 10:23:42 +0300
4Subject: [PATCH] DSS2: OMAP2/3 Display Subsystem driver
5
6Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7---
8 Documentation/arm/OMAP/DSS | 311 +++
9 arch/arm/plat-omap/Makefile | 2 +-
10 arch/arm/plat-omap/include/mach/display.h | 520 ++++
11 arch/arm/plat-omap/include/mach/vram.h | 33 +
12 arch/arm/plat-omap/include/mach/vrfb.h | 47 +
13 arch/arm/plat-omap/vram.c | 615 +++++
14 arch/arm/plat-omap/vrfb.c | 159 ++
15 drivers/video/Kconfig | 1 +
16 drivers/video/Makefile | 1 +
17 drivers/video/omap2/Kconfig | 3 +
18 drivers/video/omap2/Makefile | 4 +
19 drivers/video/omap2/dss/Kconfig | 89 +
20 drivers/video/omap2/dss/Makefile | 6 +
21 drivers/video/omap2/dss/core.c | 641 +++++
22 drivers/video/omap2/dss/dispc.c | 2968 +++++++++++++++++++++++
23 drivers/video/omap2/dss/display.c | 693 ++++++
24 drivers/video/omap2/dss/dpi.c | 393 +++
25 drivers/video/omap2/dss/dsi.c | 3752 +++++++++++++++++++++++++++++
26 drivers/video/omap2/dss/dss.c | 345 +++
27 drivers/video/omap2/dss/dss.h | 331 +++
28 drivers/video/omap2/dss/manager.c | 576 +++++
29 drivers/video/omap2/dss/overlay.c | 587 +++++
30 drivers/video/omap2/dss/rfbi.c | 1304 ++++++++++
31 drivers/video/omap2/dss/sdi.c | 245 ++
32 drivers/video/omap2/dss/venc.c | 600 +++++
33 25 files changed, 14225 insertions(+), 1 deletions(-)
34 create mode 100644 Documentation/arm/OMAP/DSS
35 create mode 100644 arch/arm/plat-omap/include/mach/display.h
36 create mode 100644 arch/arm/plat-omap/include/mach/vram.h
37 create mode 100644 arch/arm/plat-omap/include/mach/vrfb.h
38 create mode 100644 arch/arm/plat-omap/vram.c
39 create mode 100644 arch/arm/plat-omap/vrfb.c
40 create mode 100644 drivers/video/omap2/Kconfig
41 create mode 100644 drivers/video/omap2/Makefile
42 create mode 100644 drivers/video/omap2/dss/Kconfig
43 create mode 100644 drivers/video/omap2/dss/Makefile
44 create mode 100644 drivers/video/omap2/dss/core.c
45 create mode 100644 drivers/video/omap2/dss/dispc.c
46 create mode 100644 drivers/video/omap2/dss/display.c
47 create mode 100644 drivers/video/omap2/dss/dpi.c
48 create mode 100644 drivers/video/omap2/dss/dsi.c
49 create mode 100644 drivers/video/omap2/dss/dss.c
50 create mode 100644 drivers/video/omap2/dss/dss.h
51 create mode 100644 drivers/video/omap2/dss/manager.c
52 create mode 100644 drivers/video/omap2/dss/overlay.c
53 create mode 100644 drivers/video/omap2/dss/rfbi.c
54 create mode 100644 drivers/video/omap2/dss/sdi.c
55 create mode 100644 drivers/video/omap2/dss/venc.c
56
57diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
58new file mode 100644
59index 0000000..9e902a2
60--- /dev/null
61+++ b/Documentation/arm/OMAP/DSS
62@@ -0,0 +1,311 @@
63+OMAP2/3 Display Subsystem
64+-------------------------
65+
66+This is an almost total rewrite of the OMAP FB driver in drivers/video/omap
67+(let's call it DSS1). The main differences between DSS1 and DSS2 are DSI,
68+TV-out and multiple display support, but there are lots of small improvements
69+also.
70+
71+The DSS2 driver (omapdss module) is in arch/arm/plat-omap/dss/, and the FB,
72+panel and controller drivers are in drivers/video/omap2/. DSS1 and DSS2 live
73+currently side by side, you can choose which one to use.
74+
75+Features
76+--------
77+
78+Working and tested features include:
79+
80+- MIPI DPI (parallel) output
81+- MIPI DSI output in command mode
82+- MIPI DBI (RFBI) output
83+- SDI output
84+- TV output
85+- All pieces can be compiled as a module or inside kernel
86+- Use DISPC to update any of the outputs
87+- Use CPU to update RFBI or DSI output
88+- OMAP DISPC planes
89+- RGB16, RGB24 packed, RGB24 unpacked
90+- YUV2, UYVY
91+- Scaling
92+- Adjusting DSS FCK to find a good pixel clock
93+- Use DSI DPLL to create DSS FCK
94+
95+Tested boards include:
96+- OMAP3 SDP board
97+- Beagle board
98+- N810
99+
100+omapdss driver
101+--------------
102+
103+The DSS driver does not itself have any support for Linux framebuffer, V4L or
104+such like the current ones, but it has an internal kernel API that upper level
105+drivers can use.
106+
107+The DSS driver models OMAP's overlays, overlay managers and displays in a
108+flexible way to enable non-common multi-display configuration. In addition to
109+modelling the hardware overlays, omapdss supports virtual overlays and overlay
110+managers. These can be used when updating a display with CPU or system DMA.
111+
112+Panel and controller drivers
113+----------------------------
114+
115+The drivers implement panel or controller specific functionality and are not
116+usually visible to users except through omapfb driver. They register
117+themselves to the DSS driver.
118+
119+omapfb driver
120+-------------
121+
122+The omapfb driver implements arbitrary number of standard linux framebuffers.
123+These framebuffers can be routed flexibly to any overlays, thus allowing very
124+dynamic display architecture.
125+
126+The driver exports some omapfb specific ioctls, which are compatible with the
127+ioctls in the old driver.
128+
129+The rest of the non standard features are exported via sysfs. Whether the final
130+implementation will use sysfs, or ioctls, is still open.
131+
132+V4L2 drivers
133+------------
134+
135+V4L2 is being implemented in TI.
136+
137+From omapdss point of view the V4L2 drivers should be similar to framebuffer
138+driver.
139+
140+Architecture
141+--------------------
142+
143+Some clarification what the different components do:
144+
145+ - Framebuffer is a memory area inside OMAP's SRAM/SDRAM that contains the
146+ pixel data for the image. Framebuffer has width and height and color
147+ depth.
148+ - Overlay defines where the pixels are read from and where they go on the
149+ screen. The overlay may be smaller than framebuffer, thus displaying only
150+ part of the framebuffer. The position of the overlay may be changed if
151+ the overlay is smaller than the display.
152+ - Overlay manager combines the overlays in to one image and feeds them to
153+ display.
154+ - Display is the actual physical display device.
155+
156+A framebuffer can be connected to multiple overlays to show the same pixel data
157+on all of the overlays. Note that in this case the overlay input sizes must be
158+the same, but, in case of video overlays, the output size can be different. Any
159+framebuffer can be connected to any overlay.
160+
161+An overlay can be connected to one overlay manager. Also DISPC overlays can be
162+connected only to DISPC overlay managers, and virtual overlays can be only
163+connected to virtual overlays.
164+
165+An overlay manager can be connected to one display. There are certain
166+restrictions which kinds of displays an overlay manager can be connected:
167+
168+ - DISPC TV overlay manager can be only connected to TV display.
169+ - Virtual overlay managers can only be connected to DBI or DSI displays.
170+ - DISPC LCD overlay manager can be connected to all displays, except TV
171+ display.
172+
173+Sysfs
174+-----
175+The sysfs interface is mainly used for testing. I don't think sysfs
176+interface is the best for this in the final version, but I don't quite know
177+what would be the best interfaces for these things.
178+
179+The sysfs interface is divided to two parts: DSS and FB.
180+
181+/sys/class/graphics/fb? directory:
182+mirror 0=off, 1=on
183+rotate Rotation 0-3 for 0, 90, 180, 270 degrees
184+rotate_type 0 = DMA rotation, 1 = VRFB rotation
185+overlays List of overlay numbers to which framebuffer pixels go
186+phys_addr Physical address of the framebuffer
187+virt_addr Virtual address of the framebuffer
188+size Size of the framebuffer
189+
190+/sys/devices/platform/omapdss/overlay? directory:
191+enabled 0=off, 1=on
192+input_size width,height (ie. the framebuffer size)
193+manager Destination overlay manager name
194+name
195+output_size width,height
196+position x,y
197+screen_width width
198+
199+/sys/devices/platform/omapdss/manager? directory:
200+display Destination display
201+name
202+
203+/sys/devices/platform/omapdss/display? directory:
204+ctrl_name Controller name
205+mirror 0=off, 1=on
206+update_mode 0=off, 1=auto, 2=manual
207+enabled 0=off, 1=on
208+name
209+rotate Rotation 0-3 for 0, 90, 180, 270 degrees
210+timings Display timings (pixclock,xres/hfp/hbp/hsw,yres/vfp/vbp/vsw)
211+ When writing, two special timings are accepted for tv-out:
212+ "pal" and "ntsc"
213+panel_name
214+tear_elim Tearing elimination 0=off, 1=on
215+
216+There are also some debugfs files at <debugfs>/omapdss/ which show information
217+about clocks and registers.
218+
219+Examples
220+--------
221+
222+The following definitions have been made for the examples below:
223+
224+ovl0=/sys/devices/platform/omapdss/overlay0
225+ovl1=/sys/devices/platform/omapdss/overlay1
226+ovl2=/sys/devices/platform/omapdss/overlay2
227+
228+mgr0=/sys/devices/platform/omapdss/manager0
229+mgr1=/sys/devices/platform/omapdss/manager1
230+
231+lcd=/sys/devices/platform/omapdss/display0
232+dvi=/sys/devices/platform/omapdss/display1
233+tv=/sys/devices/platform/omapdss/display2
234+
235+fb0=/sys/class/graphics/fb0
236+fb1=/sys/class/graphics/fb1
237+fb2=/sys/class/graphics/fb2
238+
239+Default setup on OMAP3 SDP
240+--------------------------
241+
242+Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI
243+and TV-out are not in use. The columns from left to right are:
244+framebuffers, overlays, overlay managers, displays. Framebuffers are
245+handled by omapfb, and the rest by the DSS.
246+
247+FB0 --- GFX -\ DVI
248+FB1 --- VID1 --+- LCD ---- LCD
249+FB2 --- VID2 -/ TV ----- TV
250+
251+Example: Switch from LCD to DVI
252+----------------------
253+
254+w=`cat $dvi/horizontal | cut -d "," -f 1`
255+h=`cat $dvi/vertical | cut -d "," -f 1`
256+
257+echo "0" > $lcd/enabled
258+echo "" > $mgr0/display
259+fbset -fb /dev/fb0 -xres $w -yres $h -vxres $w -vyres $h
260+# at this point you have to switch the dvi/lcd dip-switch from the omap board
261+echo "dvi" > $mgr0/display
262+echo "1" > $dvi/enabled
263+
264+After this the configuration looks like:
265+
266+FB0 --- GFX -\ -- DVI
267+FB1 --- VID1 --+- LCD -/ LCD
268+FB2 --- VID2 -/ TV ----- TV
269+
270+Example: Clone GFX overlay to LCD and TV
271+-------------------------------
272+
273+w=`cat $tv/horizontal | cut -d "," -f 1`
274+h=`cat $tv/vertical | cut -d "," -f 1`
275+
276+echo "0" > $ovl0/enabled
277+echo "0" > $ovl1/enabled
278+
279+echo "" > $fb1/overlays
280+echo "0,1" > $fb0/overlays
281+
282+echo "$w,$h" > $ovl1/output_size
283+echo "tv" > $ovl1/manager
284+
285+echo "1" > $ovl0/enabled
286+echo "1" > $ovl1/enabled
287+
288+echo "1" > $tv/enabled
289+
290+After this the configuration looks like (only relevant parts shown):
291+
292+FB0 +-- GFX ---- LCD ---- LCD
293+ \- VID1 ---- TV ---- TV
294+
295+Misc notes
296+----------
297+
298+OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator.
299+
300+Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
301+of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.
302+
303+Rotation and mirroring currently only supports RGB565 and RGB8888 modes. VRFB
304+does not support mirroring.
305+
306+VRFB rotation requires much more memory than non-rotated framebuffer, so you
307+probably need to increase your vram setting before using VRFB rotation. Also,
308+many applications may not work with VRFB if they do not pay attention to all
309+framebuffer parameters.
310+
311+Kernel boot arguments
312+---------------------
313+
314+vram=<size>
315+ - Amount of total VRAM to preallocate. For example, "10M". omapfb
316+ allocates memory for framebuffers from VRAM.
317+
318+omapfb.mode=<display>:<mode>[,...]
319+ - Default video mode for specified displays. For example,
320+ "dvi:800x400MR-24@60". See drivers/video/modedb.c.
321+ There are also two special modes: "pal" and "ntsc" that
322+ can be used to tv out.
323+
324+omapfb.vram=<fbnum>:<size>[@<physaddr>][,...]
325+ - VRAM allocated for a framebuffer. Normally omapfb allocates vram
326+ depending on the display size. With this you can manually allocate
327+ more or define the physical address of each framebuffer. For example,
328+ "1:4M" to allocate 4M for fb1.
329+
330+omapfb.debug=<y|n>
331+ - Enable debug printing. You have to have OMAPFB debug support enabled
332+ in kernel config.
333+
334+omapfb.test=<y|n>
335+ - Draw test pattern to framebuffer whenever framebuffer settings change.
336+ You need to have OMAPFB debug support enabled in kernel config.
337+
338+omapfb.vrfb=<y|n>
339+ - Use VRFB rotation for all framebuffers.
340+
341+omapfb.rotate=<angle>
342+ - Default rotation applied to all framebuffers.
343+ 0 - 0 degree rotation
344+ 1 - 90 degree rotation
345+ 2 - 180 degree rotation
346+ 3 - 270 degree rotation
347+
348+omapfb.mirror=<y|n>
349+ - Default mirror for all framebuffers. Only works with DMA rotation.
350+
351+omapdss.def_disp=<display>
352+ - Name of default display, to which all overlays will be connected.
353+ Common examples are "lcd" or "tv".
354+
355+omapdss.debug=<y|n>
356+ - Enable debug printing. You have to have DSS debug support enabled in
357+ kernel config.
358+
359+TODO
360+----
361+
362+DSS locking
363+
364+Error checking
365+- Lots of checks are missing or implemented just as BUG()
366+
367+System DMA update for DSI
368+- Can be used for RGB16 and RGB24P modes. Probably not for RGB24U (how
369+ to skip the empty byte?)
370+
371+OMAP1 support
372+- Not sure if needed
373+
374diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
375index 3ebc09e..e6146b2 100644
376--- a/arch/arm/plat-omap/Makefile
377+++ b/arch/arm/plat-omap/Makefile
378@@ -4,7 +4,7 @@
379
380 # Common support
381 obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
382- usb.o fb.o io.o
383+ usb.o fb.o vram.o vrfb.o io.o
384 obj-m :=
385 obj-n :=
386 obj- :=
387diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
388new file mode 100644
389index 0000000..6288353
390--- /dev/null
391+++ b/arch/arm/plat-omap/include/mach/display.h
392@@ -0,0 +1,520 @@
393+/*
394+ * linux/include/asm-arm/arch-omap/display.h
395+ *
396+ * Copyright (C) 2008 Nokia Corporation
397+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
398+ *
399+ * This program is free software; you can redistribute it and/or modify it
400+ * under the terms of the GNU General Public License version 2 as published by
401+ * the Free Software Foundation.
402+ *
403+ * This program is distributed in the hope that it will be useful, but WITHOUT
404+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
405+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
406+ * more details.
407+ *
408+ * You should have received a copy of the GNU General Public License along with
409+ * this program. If not, see <http://www.gnu.org/licenses/>.
410+ */
411+
412+#ifndef __ASM_ARCH_OMAP_DISPLAY_H
413+#define __ASM_ARCH_OMAP_DISPLAY_H
414+
415+#include <linux/list.h>
416+#include <linux/kobject.h>
417+#include <asm/atomic.h>
418+
419+#define DISPC_IRQ_FRAMEDONE (1 << 0)
420+#define DISPC_IRQ_VSYNC (1 << 1)
421+#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
422+#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
423+#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
424+#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
425+#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
426+#define DISPC_IRQ_GFX_END_WIN (1 << 7)
427+#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
428+#define DISPC_IRQ_OCP_ERR (1 << 9)
429+#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
430+#define DISPC_IRQ_VID1_END_WIN (1 << 11)
431+#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
432+#define DISPC_IRQ_VID2_END_WIN (1 << 13)
433+#define DISPC_IRQ_SYNC_LOST (1 << 14)
434+#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
435+#define DISPC_IRQ_WAKEUP (1 << 16)
436+
437+enum omap_display_type {
438+ OMAP_DISPLAY_TYPE_NONE = 0,
439+ OMAP_DISPLAY_TYPE_DPI = 1 << 0,
440+ OMAP_DISPLAY_TYPE_DBI = 1 << 1,
441+ OMAP_DISPLAY_TYPE_SDI = 1 << 2,
442+ OMAP_DISPLAY_TYPE_DSI = 1 << 3,
443+ OMAP_DISPLAY_TYPE_VENC = 1 << 4,
444+};
445+
446+enum omap_plane {
447+ OMAP_DSS_GFX = 0,
448+ OMAP_DSS_VIDEO1 = 1,
449+ OMAP_DSS_VIDEO2 = 2
450+};
451+
452+enum omap_channel {
453+ OMAP_DSS_CHANNEL_LCD = 0,
454+ OMAP_DSS_CHANNEL_DIGIT = 1,
455+};
456+
457+enum omap_color_mode {
458+ OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
459+ OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
460+ OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
461+ OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
462+ OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
463+ OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
464+ OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
465+ OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
466+ OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
467+ OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
468+ OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
469+ OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
470+ OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
471+ OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
472+
473+ OMAP_DSS_COLOR_GFX_OMAP3 =
474+ OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
475+ OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
476+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
477+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
478+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
479+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
480+
481+ OMAP_DSS_COLOR_VID_OMAP3 =
482+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
483+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
484+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
485+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
486+ OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
487+};
488+
489+enum omap_lcd_display_type {
490+ OMAP_DSS_LCD_DISPLAY_STN,
491+ OMAP_DSS_LCD_DISPLAY_TFT,
492+};
493+
494+enum omap_dss_load_mode {
495+ OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
496+ OMAP_DSS_LOAD_CLUT_ONLY = 1,
497+ OMAP_DSS_LOAD_FRAME_ONLY = 2,
498+ OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
499+};
500+
501+enum omap_dss_color_key_type {
502+ OMAP_DSS_COLOR_KEY_GFX_DST = 0,
503+ OMAP_DSS_COLOR_KEY_VID_SRC = 1,
504+};
505+
506+enum omap_rfbi_te_mode {
507+ OMAP_DSS_RFBI_TE_MODE_1 = 1,
508+ OMAP_DSS_RFBI_TE_MODE_2 = 2,
509+};
510+
511+enum omap_panel_config {
512+ OMAP_DSS_LCD_IVS = 1<<0,
513+ OMAP_DSS_LCD_IHS = 1<<1,
514+ OMAP_DSS_LCD_IPC = 1<<2,
515+ OMAP_DSS_LCD_IEO = 1<<3,
516+ OMAP_DSS_LCD_RF = 1<<4,
517+ OMAP_DSS_LCD_ONOFF = 1<<5,
518+
519+ OMAP_DSS_LCD_TFT = 1<<20,
520+};
521+
522+enum omap_dss_venc_type {
523+ OMAP_DSS_VENC_TYPE_COMPOSITE,
524+ OMAP_DSS_VENC_TYPE_SVIDEO,
525+};
526+
527+struct omap_display;
528+struct omap_panel;
529+struct omap_ctrl;
530+
531+/* RFBI */
532+
533+struct rfbi_timings {
534+ int cs_on_time;
535+ int cs_off_time;
536+ int we_on_time;
537+ int we_off_time;
538+ int re_on_time;
539+ int re_off_time;
540+ int we_cycle_time;
541+ int re_cycle_time;
542+ int cs_pulse_width;
543+ int access_time;
544+
545+ int clk_div;
546+
547+ u32 tim[5]; /* set by rfbi_convert_timings() */
548+
549+ int converted;
550+};
551+
552+void omap_rfbi_write_command(const void *buf, u32 len);
553+void omap_rfbi_read_data(void *buf, u32 len);
554+void omap_rfbi_write_data(const void *buf, u32 len);
555+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
556+ u16 x, u16 y,
557+ u16 w, u16 h);
558+int omap_rfbi_enable_te(bool enable, unsigned line);
559+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
560+ unsigned hs_pulse_time, unsigned vs_pulse_time,
561+ int hs_pol_inv, int vs_pol_inv, int extif_div);
562+
563+/* DSI */
564+int dsi_vc_dcs_write(int channel, u8 *data, int len);
565+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
566+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
567+int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
568+int dsi_vc_send_null(int channel);
569+
570+/* Board specific data */
571+struct omap_dss_display_config {
572+ enum omap_display_type type;
573+
574+ union {
575+ struct {
576+ u8 data_lines;
577+ } dpi;
578+
579+ struct {
580+ u8 channel;
581+ u8 data_lines;
582+ } rfbi;
583+
584+ struct {
585+ u8 datapairs;
586+ } sdi;
587+
588+ struct {
589+ u8 clk_lane;
590+ u8 clk_pol;
591+ u8 data1_lane;
592+ u8 data1_pol;
593+ u8 data2_lane;
594+ u8 data2_pol;
595+ unsigned long ddr_clk_hz;
596+ } dsi;
597+
598+ struct {
599+ enum omap_dss_venc_type type;
600+ } venc;
601+ } u;
602+
603+ int panel_reset_gpio;
604+ int ctrl_reset_gpio;
605+
606+ const char *name; /* for debug */
607+ const char *ctrl_name;
608+ const char *panel_name;
609+
610+ void *panel_data;
611+ void *ctrl_data;
612+
613+ /* platform specific enable/disable */
614+ int (*panel_enable)(struct omap_display *display);
615+ void (*panel_disable)(struct omap_display *display);
616+ int (*ctrl_enable)(struct omap_display *display);
617+ void (*ctrl_disable)(struct omap_display *display);
618+ int (*set_backlight)(struct omap_display *display,
619+ int level);
620+};
621+
622+struct device;
623+
624+/* Board specific data */
625+struct omap_dss_board_info {
626+ unsigned (*get_last_off_on_transaction_id)(struct device *dev);
627+ int (*dsi_power_up)(void);
628+ void (*dsi_power_down)(void);
629+ int num_displays;
630+ struct omap_dss_display_config *displays[];
631+};
632+
633+struct omap_ctrl {
634+ struct module *owner;
635+
636+ const char *name;
637+
638+ int (*init)(struct omap_display *display);
639+ void (*cleanup)(struct omap_display *display);
640+ int (*enable)(struct omap_display *display);
641+ void (*disable)(struct omap_display *display);
642+ int (*suspend)(struct omap_display *display);
643+ int (*resume)(struct omap_display *display);
644+ void (*setup_update)(struct omap_display *display,
645+ u16 x, u16 y, u16 w, u16 h);
646+
647+ int (*enable_te)(struct omap_display *display, bool enable);
648+
649+ u8 (*get_rotate)(struct omap_display *display);
650+ int (*set_rotate)(struct omap_display *display, u8 rotate);
651+
652+ bool (*get_mirror)(struct omap_display *display);
653+ int (*set_mirror)(struct omap_display *display, bool enable);
654+
655+ int (*run_test)(struct omap_display *display, int test);
656+ int (*memory_read)(struct omap_display *display,
657+ void *buf, size_t size,
658+ u16 x, u16 y, u16 w, u16 h);
659+
660+ u8 pixel_size;
661+
662+ struct rfbi_timings timings;
663+
664+ void *priv;
665+};
666+
667+struct omap_video_timings {
668+ /* Unit: pixels */
669+ u16 x_res;
670+ /* Unit: pixels */
671+ u16 y_res;
672+ /* Unit: KHz */
673+ u32 pixel_clock;
674+ /* Unit: pixel clocks */
675+ u16 hsw; /* Horizontal synchronization pulse width */
676+ /* Unit: pixel clocks */
677+ u16 hfp; /* Horizontal front porch */
678+ /* Unit: pixel clocks */
679+ u16 hbp; /* Horizontal back porch */
680+ /* Unit: line clocks */
681+ u16 vsw; /* Vertical synchronization pulse width */
682+ /* Unit: line clocks */
683+ u16 vfp; /* Vertical front porch */
684+ /* Unit: line clocks */
685+ u16 vbp; /* Vertical back porch */
686+
687+};
688+
689+#ifdef CONFIG_OMAP2_DSS_VENC
690+/* Hardcoded timings for tv modes. Venc only uses these to
691+ * identify the mode, and does not actually use the configs
692+ * itself. However, the configs should be something that
693+ * a normal monitor can also show */
694+const extern struct omap_video_timings omap_dss_pal_timings;
695+const extern struct omap_video_timings omap_dss_ntsc_timings;
696+#endif
697+
698+struct omap_panel {
699+ struct module *owner;
700+
701+ const char *name;
702+
703+ int (*init)(struct omap_display *display);
704+ void (*cleanup)(struct omap_display *display);
705+ int (*remove)(struct omap_display *display);
706+ int (*enable)(struct omap_display *display);
707+ void (*disable)(struct omap_display *display);
708+ int (*suspend)(struct omap_display *display);
709+ int (*resume)(struct omap_display *display);
710+ int (*run_test)(struct omap_display *display, int test);
711+
712+ struct omap_video_timings timings;
713+
714+ int acbi; /* ac-bias pin transitions per interrupt */
715+ /* Unit: line clocks */
716+ int acb; /* ac-bias pin frequency */
717+
718+ enum omap_panel_config config;
719+
720+ u8 recommended_bpp;
721+
722+ void *priv;
723+};
724+
725+/* XXX perhaps this should be removed */
726+enum omap_dss_overlay_managers {
727+ OMAP_DSS_OVL_MGR_LCD,
728+ OMAP_DSS_OVL_MGR_TV,
729+};
730+
731+struct omap_overlay_manager;
732+
733+struct omap_overlay_info {
734+ bool enabled;
735+
736+ u32 paddr;
737+ void __iomem *vaddr;
738+ u16 screen_width;
739+ u16 width;
740+ u16 height;
741+ enum omap_color_mode color_mode;
742+ u8 rotation;
743+ bool mirror;
744+
745+ u16 pos_x;
746+ u16 pos_y;
747+ u16 out_width; /* if 0, out_width == width */
748+ u16 out_height; /* if 0, out_height == height */
749+};
750+
751+enum omap_overlay_caps {
752+ OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
753+ OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
754+};
755+
756+struct omap_overlay {
757+ struct kobject kobj;
758+ struct list_head list;
759+
760+ const char *name;
761+ int id;
762+ struct omap_overlay_manager *manager;
763+ enum omap_color_mode supported_modes;
764+ struct omap_overlay_info info;
765+ enum omap_overlay_caps caps;
766+
767+ int (*set_manager)(struct omap_overlay *ovl,
768+ struct omap_overlay_manager *mgr);
769+ int (*unset_manager)(struct omap_overlay *ovl);
770+
771+ int (*set_overlay_info)(struct omap_overlay *ovl,
772+ struct omap_overlay_info *info);
773+ void (*get_overlay_info)(struct omap_overlay *ovl,
774+ struct omap_overlay_info *info);
775+};
776+
777+enum omap_overlay_manager_caps {
778+ OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
779+};
780+
781+struct omap_overlay_manager {
782+ struct kobject kobj;
783+ struct list_head list;
784+
785+ const char *name;
786+ int id;
787+ enum omap_overlay_manager_caps caps;
788+ struct omap_display *display;
789+ int num_overlays;
790+ struct omap_overlay **overlays;
791+ enum omap_display_type supported_displays;
792+
793+ int (*set_display)(struct omap_overlay_manager *mgr,
794+ struct omap_display *display);
795+ int (*unset_display)(struct omap_overlay_manager *mgr);
796+
797+ int (*apply)(struct omap_overlay_manager *mgr);
798+
799+ void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
800+ void (*set_trans_key)(struct omap_overlay_manager *mgr,
801+ enum omap_dss_color_key_type type,
802+ u32 trans_key);
803+ void (*enable_trans_key)(struct omap_overlay_manager *mgr,
804+ bool enable);
805+};
806+
807+enum omap_display_caps {
808+ OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
809+};
810+
811+enum omap_dss_update_mode {
812+ OMAP_DSS_UPDATE_DISABLED = 0,
813+ OMAP_DSS_UPDATE_AUTO,
814+ OMAP_DSS_UPDATE_MANUAL,
815+};
816+
817+enum omap_dss_display_state {
818+ OMAP_DSS_DISPLAY_DISABLED = 0,
819+ OMAP_DSS_DISPLAY_ACTIVE,
820+ OMAP_DSS_DISPLAY_SUSPENDED,
821+};
822+
823+struct omap_display {
824+ struct kobject kobj;
825+ struct list_head list;
826+
827+ /*atomic_t ref_count;*/
828+ int ref_count;
829+ /* helper variable for driver suspend/resume */
830+ int activate_after_resume;
831+
832+ enum omap_display_type type;
833+ const char *name;
834+
835+ enum omap_display_caps caps;
836+
837+ struct omap_overlay_manager *manager;
838+
839+ enum omap_dss_display_state state;
840+
841+ struct omap_dss_display_config hw_config; /* board specific data */
842+ struct omap_ctrl *ctrl; /* static common data */
843+ struct omap_panel *panel; /* static common data */
844+
845+ int (*enable)(struct omap_display *display);
846+ void (*disable)(struct omap_display *display);
847+
848+ int (*suspend)(struct omap_display *display);
849+ int (*resume)(struct omap_display *display);
850+
851+ void (*get_resolution)(struct omap_display *display,
852+ u16 *xres, u16 *yres);
853+ int (*get_recommended_bpp)(struct omap_display *display);
854+
855+ int (*check_timings)(struct omap_display *display,
856+ struct omap_video_timings *timings);
857+ void (*set_timings)(struct omap_display *display,
858+ struct omap_video_timings *timings);
859+ void (*get_timings)(struct omap_display *display,
860+ struct omap_video_timings *timings);
861+ int (*update)(struct omap_display *display,
862+ u16 x, u16 y, u16 w, u16 h);
863+ int (*sync)(struct omap_display *display);
864+ int (*wait_vsync)(struct omap_display *display);
865+
866+ int (*set_update_mode)(struct omap_display *display,
867+ enum omap_dss_update_mode);
868+ enum omap_dss_update_mode (*get_update_mode)
869+ (struct omap_display *display);
870+
871+ int (*enable_te)(struct omap_display *display, bool enable);
872+ int (*get_te)(struct omap_display *display);
873+
874+ u8 (*get_rotate)(struct omap_display *display);
875+ int (*set_rotate)(struct omap_display *display, u8 rotate);
876+
877+ bool (*get_mirror)(struct omap_display *display);
878+ int (*set_mirror)(struct omap_display *display, bool enable);
879+
880+ int (*run_test)(struct omap_display *display, int test);
881+ int (*memory_read)(struct omap_display *display,
882+ void *buf, size_t size,
883+ u16 x, u16 y, u16 w, u16 h);
884+
885+ void (*configure_overlay)(struct omap_overlay *overlay);
886+};
887+
888+int omap_dss_get_num_displays(void);
889+struct omap_display *omap_dss_get_display(int no);
890+void omap_dss_put_display(struct omap_display *display);
891+
892+void omap_dss_register_ctrl(struct omap_ctrl *ctrl);
893+void omap_dss_unregister_ctrl(struct omap_ctrl *ctrl);
894+
895+void omap_dss_register_panel(struct omap_panel *panel);
896+void omap_dss_unregister_panel(struct omap_panel *panel);
897+
898+int omap_dss_get_num_overlay_managers(void);
899+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
900+
901+int omap_dss_get_num_overlays(void);
902+struct omap_overlay *omap_dss_get_overlay(int num);
903+
904+typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
905+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
906+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
907+
908+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
909+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
910+ unsigned long timeout);
911+
912+#endif
913diff --git a/arch/arm/plat-omap/include/mach/vram.h b/arch/arm/plat-omap/include/mach/vram.h
914new file mode 100644
915index 0000000..f176562
916--- /dev/null
917+++ b/arch/arm/plat-omap/include/mach/vram.h
918@@ -0,0 +1,33 @@
919+/*
920+ * File: arch/arm/plat-omap/include/mach/vram.h
921+ *
922+ * Copyright (C) 2009 Nokia Corporation
923+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
924+ *
925+ * This program is free software; you can redistribute it and/or modify it
926+ * under the terms of the GNU General Public License as published by the
927+ * Free Software Foundation; either version 2 of the License, or (at your
928+ * option) any later version.
929+ *
930+ * This program is distributed in the hope that it will be useful, but
931+ * WITHOUT ANY WARRANTY; without even the implied warranty of
932+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
933+ * General Public License for more details.
934+ *
935+ * You should have received a copy of the GNU General Public License along
936+ * with this program; if not, write to the Free Software Foundation, Inc.,
937+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
938+ */
939+
940+#ifndef __OMAPVRAM_H
941+#define __OMAPVRAM_H
942+
943+#include <asm/types.h>
944+
945+extern int omap_vram_free(unsigned long paddr, size_t size);
946+extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
947+extern int omap_vram_reserve(unsigned long paddr, size_t size);
948+extern void omap2_set_sdram_vram(u32 size, u32 start);
949+extern void omap2_set_sram_vram(u32 size, u32 start);
950+
951+#endif
952diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
953new file mode 100644
954index 0000000..2047862
955--- /dev/null
956+++ b/arch/arm/plat-omap/include/mach/vrfb.h
957@@ -0,0 +1,47 @@
958+/*
959+ * File: arch/arm/plat-omap/include/mach/vrfb.h
960+ *
961+ * VRFB
962+ *
963+ * Copyright (C) 2009 Nokia Corporation
964+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
965+ *
966+ * This program is free software; you can redistribute it and/or modify it
967+ * under the terms of the GNU General Public License as published by the
968+ * Free Software Foundation; either version 2 of the License, or (at your
969+ * option) any later version.
970+ *
971+ * This program is distributed in the hope that it will be useful, but
972+ * WITHOUT ANY WARRANTY; without even the implied warranty of
973+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
974+ * General Public License for more details.
975+ *
976+ * You should have received a copy of the GNU General Public License along
977+ * with this program; if not, write to the Free Software Foundation, Inc.,
978+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
979+ */
980+
981+#ifndef __VRFB_H
982+#define __VRFB_H
983+
984+#define OMAP_VRFB_LINE_LEN 2048
985+
986+struct vrfb
987+{
988+ u8 context;
989+ void __iomem *vaddr[4];
990+ unsigned long paddr[4];
991+ u16 xoffset;
992+ u16 yoffset;
993+ u8 bytespp;
994+};
995+
996+extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
997+extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
998+extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
999+ u8 bytespp);
1000+extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
1001+ u16 width, u16 height,
1002+ u8 bytespp);
1003+
1004+#endif /* __VRFB_H */
1005diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
1006new file mode 100644
1007index 0000000..f24a110
1008--- /dev/null
1009+++ b/arch/arm/plat-omap/vram.c
1010@@ -0,0 +1,615 @@
1011+/*
1012+ * linux/arch/arm/plat-omap/vram.c
1013+ *
1014+ * Copyright (C) 2008 Nokia Corporation
1015+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
1016+ *
1017+ * Some code and ideas taken from drivers/video/omap/ driver
1018+ * by Imre Deak.
1019+ *
1020+ * This program is free software; you can redistribute it and/or modify it
1021+ * under the terms of the GNU General Public License version 2 as published by
1022+ * the Free Software Foundation.
1023+ *
1024+ * This program is distributed in the hope that it will be useful, but WITHOUT
1025+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1026+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1027+ * more details.
1028+ *
1029+ * You should have received a copy of the GNU General Public License along with
1030+ * this program. If not, see <http://www.gnu.org/licenses/>.
1031+ */
1032+
1033+/*#define DEBUG*/
1034+
1035+#include <linux/vmalloc.h>
1036+#include <linux/kernel.h>
1037+#include <linux/mm.h>
1038+#include <linux/list.h>
1039+#include <linux/dma-mapping.h>
1040+#include <linux/proc_fs.h>
1041+#include <linux/seq_file.h>
1042+#include <linux/bootmem.h>
1043+#include <linux/omapfb.h>
1044+
1045+#include <asm/setup.h>
1046+
1047+#include <mach/sram.h>
1048+#include <mach/vram.h>
1049+
1050+#ifdef DEBUG
1051+#define DBG(format, ...) printk(KERN_DEBUG "VRAM: " format, ## __VA_ARGS__)
1052+#else
1053+#define DBG(format, ...)
1054+#endif
1055+
1056+#define OMAP2_SRAM_START 0x40200000
1057+/* Maximum size, in reality this is smaller if SRAM is partially locked. */
1058+#define OMAP2_SRAM_SIZE 0xa0000 /* 640k */
1059+
1060+#define REG_MAP_SIZE(_page_cnt) \
1061+ ((_page_cnt + (sizeof(unsigned long) * 8) - 1) / 8)
1062+#define REG_MAP_PTR(_rg, _page_nr) \
1063+ (((_rg)->map) + (_page_nr) / (sizeof(unsigned long) * 8))
1064+#define REG_MAP_MASK(_page_nr) \
1065+ (1 << ((_page_nr) & (sizeof(unsigned long) * 8 - 1)))
1066+
1067+#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
1068+
1069+/* postponed regions are used to temporarily store region information at boot
1070+ * time when we cannot yet allocate the region list */
1071+#define MAX_POSTPONED_REGIONS 10
1072+
1073+static int postponed_cnt __initdata;
1074+static struct {
1075+ unsigned long paddr;
1076+ size_t size;
1077+} postponed_regions[MAX_POSTPONED_REGIONS] __initdata;
1078+
1079+struct vram_alloc {
1080+ struct list_head list;
1081+ unsigned long paddr;
1082+ unsigned pages;
1083+};
1084+
1085+struct vram_region {
1086+ struct list_head list;
1087+ struct list_head alloc_list;
1088+ unsigned long paddr;
1089+ unsigned pages;
1090+};
1091+
1092+static DEFINE_MUTEX(region_mutex);
1093+static LIST_HEAD(region_list);
1094+
1095+static inline int region_mem_type(unsigned long paddr)
1096+{
1097+ if (paddr >= OMAP2_SRAM_START &&
1098+ paddr < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
1099+ return OMAPFB_MEMTYPE_SRAM;
1100+ else
1101+ return OMAPFB_MEMTYPE_SDRAM;
1102+}
1103+
1104+static struct vram_region *omap_vram_create_region(unsigned long paddr,
1105+ unsigned pages)
1106+{
1107+ struct vram_region *rm;
1108+
1109+ rm = kzalloc(sizeof(*rm), GFP_KERNEL);
1110+
1111+ if (rm) {
1112+ INIT_LIST_HEAD(&rm->alloc_list);
1113+ rm->paddr = paddr;
1114+ rm->pages = pages;
1115+ }
1116+
1117+ return rm;
1118+}
1119+
1120+#if 0
1121+static void omap_vram_free_region(struct vram_region *vr)
1122+{
1123+ list_del(&vr->list);
1124+ kfree(vr);
1125+}
1126+#endif
1127+
1128+static struct vram_alloc *omap_vram_create_allocation(struct vram_region *vr,
1129+ unsigned long paddr, unsigned pages)
1130+{
1131+ struct vram_alloc *va;
1132+ struct vram_alloc *new;
1133+
1134+ new = kzalloc(sizeof(*va), GFP_KERNEL);
1135+
1136+ if (!new)
1137+ return NULL;
1138+
1139+ new->paddr = paddr;
1140+ new->pages = pages;
1141+
1142+ list_for_each_entry(va, &vr->alloc_list, list) {
1143+ if (va->paddr > new->paddr)
1144+ break;
1145+ }
1146+
1147+ list_add_tail(&new->list, &va->list);
1148+
1149+ return new;
1150+}
1151+
1152+static void omap_vram_free_allocation(struct vram_alloc *va)
1153+{
1154+ list_del(&va->list);
1155+ kfree(va);
1156+}
1157+
1158+static __init int omap_vram_add_region_postponed(unsigned long paddr,
1159+ size_t size)
1160+{
1161+ if (postponed_cnt == MAX_POSTPONED_REGIONS)
1162+ return -ENOMEM;
1163+
1164+ postponed_regions[postponed_cnt].paddr = paddr;
1165+ postponed_regions[postponed_cnt].size = size;
1166+
1167+ ++postponed_cnt;
1168+
1169+ return 0;
1170+}
1171+
1172+/* add/remove_region can be exported if there's need to add/remove regions
1173+ * runtime */
1174+static int omap_vram_add_region(unsigned long paddr, size_t size)
1175+{
1176+ struct vram_region *rm;
1177+ unsigned pages;
1178+
1179+ DBG("adding region paddr %08lx size %d\n",
1180+ paddr, size);
1181+
1182+ size &= PAGE_MASK;
1183+ pages = size >> PAGE_SHIFT;
1184+
1185+ rm = omap_vram_create_region(paddr, pages);
1186+ if (rm == NULL)
1187+ return -ENOMEM;
1188+
1189+ list_add(&rm->list, &region_list);
1190+
1191+ return 0;
1192+}
1193+
1194+int omap_vram_free(unsigned long paddr, size_t size)
1195+{
1196+ struct vram_region *rm;
1197+ struct vram_alloc *alloc;
1198+ unsigned start, end;
1199+
1200+ DBG("free mem paddr %08lx size %d\n", paddr, size);
1201+
1202+ size = PAGE_ALIGN(size);
1203+
1204+ mutex_lock(&region_mutex);
1205+
1206+ list_for_each_entry(rm, &region_list, list) {
1207+ list_for_each_entry(alloc, &rm->alloc_list, list) {
1208+ start = alloc->paddr;
1209+ end = alloc->paddr + (alloc->pages >> PAGE_SHIFT);
1210+
1211+ if (start >= paddr && end < paddr + size)
1212+ goto found;
1213+ }
1214+ }
1215+
1216+ mutex_unlock(&region_mutex);
1217+ return -EINVAL;
1218+
1219+found:
1220+ omap_vram_free_allocation(alloc);
1221+
1222+ mutex_unlock(&region_mutex);
1223+ return 0;
1224+}
1225+EXPORT_SYMBOL(omap_vram_free);
1226+
1227+static int _omap_vram_reserve(unsigned long paddr, unsigned pages)
1228+{
1229+ struct vram_region *rm;
1230+ struct vram_alloc *alloc;
1231+ size_t size;
1232+
1233+ size = pages << PAGE_SHIFT;
1234+
1235+ list_for_each_entry(rm, &region_list, list) {
1236+ unsigned long start, end;
1237+
1238+ DBG("checking region %lx %d\n", rm->paddr, rm->pages);
1239+
1240+ if (region_mem_type(rm->paddr) != region_mem_type(paddr))
1241+ continue;
1242+
1243+ start = rm->paddr;
1244+ end = start + (rm->pages << PAGE_SHIFT) - 1;
1245+ if (start > paddr || end < paddr + size - 1)
1246+ continue;
1247+
1248+ DBG("block ok, checking allocs\n");
1249+
1250+ list_for_each_entry(alloc, &rm->alloc_list, list) {
1251+ end = alloc->paddr - 1;
1252+
1253+ if (start <= paddr && end >= paddr + size - 1)
1254+ goto found;
1255+
1256+ start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
1257+ }
1258+
1259+ end = rm->paddr + (rm->pages << PAGE_SHIFT) - 1;
1260+
1261+ if (!(start <= paddr && end >= paddr + size - 1))
1262+ continue;
1263+found:
1264+ DBG("FOUND area start %lx, end %lx\n", start, end);
1265+
1266+ if (omap_vram_create_allocation(rm, paddr, pages) == NULL)
1267+ return -ENOMEM;
1268+
1269+ return 0;
1270+ }
1271+
1272+ return -ENOMEM;
1273+}
1274+
1275+int omap_vram_reserve(unsigned long paddr, size_t size)
1276+{
1277+ unsigned pages;
1278+ int r;
1279+
1280+ DBG("reserve mem paddr %08lx size %d\n", paddr, size);
1281+
1282+ size = PAGE_ALIGN(size);
1283+ pages = size >> PAGE_SHIFT;
1284+
1285+ mutex_lock(&region_mutex);
1286+
1287+ r = _omap_vram_reserve(paddr, pages);
1288+
1289+ mutex_unlock(&region_mutex);
1290+
1291+ return r;
1292+}
1293+EXPORT_SYMBOL(omap_vram_reserve);
1294+
1295+static int _omap_vram_alloc(int mtype, unsigned pages, unsigned long *paddr)
1296+{
1297+ struct vram_region *rm;
1298+ struct vram_alloc *alloc;
1299+
1300+ list_for_each_entry(rm, &region_list, list) {
1301+ unsigned long start, end;
1302+
1303+ DBG("checking region %lx %d\n", rm->paddr, rm->pages);
1304+
1305+ if (region_mem_type(rm->paddr) != mtype)
1306+ continue;
1307+
1308+ start = rm->paddr;
1309+
1310+ list_for_each_entry(alloc, &rm->alloc_list, list) {
1311+ end = alloc->paddr;
1312+
1313+ if (end - start >= pages << PAGE_SHIFT)
1314+ goto found;
1315+
1316+ start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
1317+ }
1318+
1319+ end = rm->paddr + (rm->pages << PAGE_SHIFT);
1320+found:
1321+ if (end - start < pages << PAGE_SHIFT)
1322+ continue;
1323+
1324+ DBG("FOUND %lx, end %lx\n", start, end);
1325+
1326+ alloc = omap_vram_create_allocation(rm, start, pages);
1327+ if (alloc == NULL)
1328+ return -ENOMEM;
1329+
1330+ *paddr = start;
1331+
1332+ return 0;
1333+ }
1334+
1335+ return -ENOMEM;
1336+}
1337+
1338+int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr)
1339+{
1340+ unsigned pages;
1341+ int r;
1342+
1343+ BUG_ON(mtype > OMAPFB_MEMTYPE_MAX || !size);
1344+
1345+ DBG("alloc mem type %d size %d\n", mtype, size);
1346+
1347+ size = PAGE_ALIGN(size);
1348+ pages = size >> PAGE_SHIFT;
1349+
1350+ mutex_lock(&region_mutex);
1351+
1352+ r = _omap_vram_alloc(mtype, pages, paddr);
1353+
1354+ mutex_unlock(&region_mutex);
1355+
1356+ return r;
1357+}
1358+EXPORT_SYMBOL(omap_vram_alloc);
1359+
1360+#ifdef CONFIG_PROC_FS
1361+static void *r_next(struct seq_file *m, void *v, loff_t *pos)
1362+{
1363+ struct list_head *l = v;
1364+
1365+ (*pos)++;
1366+
1367+ if (list_is_last(l, &region_list))
1368+ return NULL;
1369+
1370+ return l->next;
1371+}
1372+
1373+static void *r_start(struct seq_file *m, loff_t *pos)
1374+{
1375+ loff_t p = *pos;
1376+ struct list_head *l = &region_list;
1377+
1378+ mutex_lock(&region_mutex);
1379+
1380+ do {
1381+ l = l->next;
1382+ if (l == &region_list)
1383+ return NULL;
1384+ } while (p--);
1385+
1386+ return l;
1387+}
1388+
1389+static void r_stop(struct seq_file *m, void *v)
1390+{
1391+ mutex_unlock(&region_mutex);
1392+}
1393+
1394+static int r_show(struct seq_file *m, void *v)
1395+{
1396+ struct vram_region *vr;
1397+ struct vram_alloc *va;
1398+ unsigned size;
1399+
1400+ vr = list_entry(v, struct vram_region, list);
1401+
1402+ size = vr->pages << PAGE_SHIFT;
1403+
1404+ seq_printf(m, "%08lx-%08lx (%d bytes)\n",
1405+ vr->paddr, vr->paddr + size - 1,
1406+ size);
1407+
1408+ list_for_each_entry(va, &vr->alloc_list, list) {
1409+ size = va->pages << PAGE_SHIFT;
1410+ seq_printf(m, " %08lx-%08lx (%d bytes)\n",
1411+ va->paddr, va->paddr + size - 1,
1412+ size);
1413+ }
1414+
1415+
1416+
1417+ return 0;
1418+}
1419+
1420+static const struct seq_operations resource_op = {
1421+ .start = r_start,
1422+ .next = r_next,
1423+ .stop = r_stop,
1424+ .show = r_show,
1425+};
1426+
1427+static int vram_open(struct inode *inode, struct file *file)
1428+{
1429+ return seq_open(file, &resource_op);
1430+}
1431+
1432+static const struct file_operations proc_vram_operations = {
1433+ .open = vram_open,
1434+ .read = seq_read,
1435+ .llseek = seq_lseek,
1436+ .release = seq_release,
1437+};
1438+
1439+static int __init omap_vram_create_proc(void)
1440+{
1441+ proc_create("omap-vram", 0, NULL, &proc_vram_operations);
1442+
1443+ return 0;
1444+}
1445+#endif
1446+
1447+static __init int omap_vram_init(void)
1448+{
1449+ int i, r;
1450+
1451+ for (i = 0; i < postponed_cnt; i++)
1452+ omap_vram_add_region(postponed_regions[i].paddr,
1453+ postponed_regions[i].size);
1454+
1455+#ifdef CONFIG_PROC_FS
1456+ r = omap_vram_create_proc();
1457+ if (r)
1458+ return -ENOMEM;
1459+#endif
1460+
1461+ return 0;
1462+}
1463+
1464+arch_initcall(omap_vram_init);
1465+
1466+/* boottime vram alloc stuff */
1467+
1468+/* set from board file */
1469+static u32 omapfb_sram_vram_start __initdata;
1470+static u32 omapfb_sram_vram_size __initdata;
1471+
1472+/* set from board file */
1473+static u32 omapfb_sdram_vram_start __initdata;
1474+static u32 omapfb_sdram_vram_size __initdata;
1475+
1476+/* set from kernel cmdline */
1477+static u32 omapfb_def_sdram_vram_size __initdata;
1478+static u32 omapfb_def_sdram_vram_start __initdata;
1479+
1480+static void __init omapfb_early_vram(char **p)
1481+{
1482+ omapfb_def_sdram_vram_size = memparse(*p, p);
1483+ if (**p == ',')
1484+ omapfb_def_sdram_vram_start = simple_strtoul((*p) + 1, p, 16);
1485+
1486+ printk("omapfb_early_vram, %d, 0x%x\n",
1487+ omapfb_def_sdram_vram_size,
1488+ omapfb_def_sdram_vram_start);
1489+}
1490+__early_param("vram=", omapfb_early_vram);
1491+
1492+/*
1493+ * Called from map_io. We need to call to this early enough so that we
1494+ * can reserve the fixed SDRAM regions before VM could get hold of them.
1495+ */
1496+void __init omapfb_reserve_sdram(void)
1497+{
1498+ struct bootmem_data *bdata;
1499+ unsigned long sdram_start, sdram_size;
1500+ u32 paddr;
1501+ u32 size = 0;
1502+
1503+ /* cmdline arg overrides the board file definition */
1504+ if (omapfb_def_sdram_vram_size) {
1505+ size = omapfb_def_sdram_vram_size;
1506+ paddr = omapfb_def_sdram_vram_start;
1507+ }
1508+
1509+ if (!size) {
1510+ size = omapfb_sdram_vram_size;
1511+ paddr = omapfb_sdram_vram_start;
1512+ }
1513+
1514+#ifdef CONFIG_OMAP2_DSS_VRAM_SIZE
1515+ if (!size) {
1516+ size = CONFIG_OMAP2_DSS_VRAM_SIZE * 1024 * 1024;
1517+ paddr = 0;
1518+ }
1519+#endif
1520+
1521+ if (!size)
1522+ return;
1523+
1524+ size = PAGE_ALIGN(size);
1525+
1526+ bdata = NODE_DATA(0)->bdata;
1527+ sdram_start = bdata->node_min_pfn << PAGE_SHIFT;
1528+ sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start;
1529+
1530+ if (paddr) {
1531+ if ((paddr & ~PAGE_MASK) || paddr < sdram_start ||
1532+ paddr + size > sdram_start + sdram_size) {
1533+ printk(KERN_ERR "Illegal SDRAM region for VRAM\n");
1534+ return;
1535+ }
1536+
1537+ reserve_bootmem(paddr, size, BOOTMEM_DEFAULT);
1538+ } else {
1539+ if (size > sdram_size) {
1540+ printk(KERN_ERR "Illegal SDRAM size for VRAM\n");
1541+ return;
1542+ }
1543+
1544+ paddr = virt_to_phys(alloc_bootmem_pages(size));
1545+ BUG_ON(paddr & ~PAGE_MASK);
1546+ }
1547+
1548+ omap_vram_add_region_postponed(paddr, size);
1549+
1550+ pr_info("Reserving %u bytes SDRAM for VRAM\n", size);
1551+}
1552+
1553+/*
1554+ * Called at sram init time, before anything is pushed to the SRAM stack.
1555+ * Because of the stack scheme, we will allocate everything from the
1556+ * start of the lowest address region to the end of SRAM. This will also
1557+ * include padding for page alignment and possible holes between regions.
1558+ *
1559+ * As opposed to the SDRAM case, we'll also do any dynamic allocations at
1560+ * this point, since the driver built as a module would have problem with
1561+ * freeing / reallocating the regions.
1562+ */
1563+unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
1564+ unsigned long sram_vstart,
1565+ unsigned long sram_size,
1566+ unsigned long pstart_avail,
1567+ unsigned long size_avail)
1568+{
1569+ unsigned long pend_avail;
1570+ unsigned long reserved;
1571+ u32 paddr;
1572+ u32 size;
1573+
1574+ paddr = omapfb_sram_vram_start;
1575+ size = omapfb_sram_vram_size;
1576+
1577+ if (!size)
1578+ return 0;
1579+
1580+ reserved = 0;
1581+ pend_avail = pstart_avail + size_avail;
1582+
1583+ if (!paddr) {
1584+ /* Dynamic allocation */
1585+ if ((size_avail & PAGE_MASK) < size) {
1586+ printk(KERN_ERR "Not enough SRAM for VRAM\n");
1587+ return 0;
1588+ }
1589+ size_avail = (size_avail - size) & PAGE_MASK;
1590+ paddr = pstart_avail + size_avail;
1591+ }
1592+
1593+ if (paddr < sram_pstart ||
1594+ paddr + size > sram_pstart + sram_size) {
1595+ printk(KERN_ERR "Illegal SRAM region for VRAM\n");
1596+ return 0;
1597+ }
1598+
1599+ /* Reserve everything above the start of the region. */
1600+ if (pend_avail - paddr > reserved)
1601+ reserved = pend_avail - paddr;
1602+ size_avail = pend_avail - reserved - pstart_avail;
1603+
1604+ omap_vram_add_region_postponed(paddr, size);
1605+
1606+ if (reserved)
1607+ pr_info("Reserving %lu bytes SRAM for VRAM\n", reserved);
1608+
1609+ return reserved;
1610+}
1611+
1612+void __init omap2_set_sdram_vram(u32 size, u32 start)
1613+{
1614+ omapfb_sdram_vram_start = start;
1615+ omapfb_sdram_vram_size = size;
1616+}
1617+
1618+void __init omap2_set_sram_vram(u32 size, u32 start)
1619+{
1620+ omapfb_sram_vram_start = start;
1621+ omapfb_sram_vram_size = size;
1622+}
1623+
1624+#endif
1625+
1626diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
1627new file mode 100644
1628index 0000000..7e0f8fc
1629--- /dev/null
1630+++ b/arch/arm/plat-omap/vrfb.c
1631@@ -0,0 +1,159 @@
1632+#include <linux/kernel.h>
1633+#include <linux/module.h>
1634+#include <linux/ioport.h>
1635+#include <asm/io.h>
1636+
1637+#include <mach/io.h>
1638+#include <mach/vrfb.h>
1639+
1640+/*#define DEBUG*/
1641+
1642+#ifdef DEBUG
1643+#define DBG(format, ...) printk(KERN_DEBUG "VRFB: " format, ## __VA_ARGS__)
1644+#else
1645+#define DBG(format, ...)
1646+#endif
1647+
1648+#define SMS_ROT_VIRT_BASE(context, rot) \
1649+ (((context >= 4) ? 0xD0000000 : 0x70000000) \
1650+ | 0x4000000 * (context) \
1651+ | 0x1000000 * (rot))
1652+
1653+#define OMAP_VRFB_SIZE (2048 * 2048 * 4)
1654+
1655+#define VRFB_PAGE_WIDTH_EXP 5 /* Assuming SDRAM pagesize= 1024 */
1656+#define VRFB_PAGE_HEIGHT_EXP 5 /* 1024 = 2^5 * 2^5 */
1657+#define VRFB_PAGE_WIDTH (1 << VRFB_PAGE_WIDTH_EXP)
1658+#define VRFB_PAGE_HEIGHT (1 << VRFB_PAGE_HEIGHT_EXP)
1659+#define SMS_IMAGEHEIGHT_OFFSET 16
1660+#define SMS_IMAGEWIDTH_OFFSET 0
1661+#define SMS_PH_OFFSET 8
1662+#define SMS_PW_OFFSET 4
1663+#define SMS_PS_OFFSET 0
1664+
1665+#define OMAP_SMS_BASE 0x6C000000
1666+#define SMS_ROT_CONTROL(context) (OMAP_SMS_BASE + 0x180 + 0x10 * context)
1667+#define SMS_ROT_SIZE(context) (OMAP_SMS_BASE + 0x184 + 0x10 * context)
1668+#define SMS_ROT_PHYSICAL_BA(context) (OMAP_SMS_BASE + 0x188 + 0x10 * context)
1669+
1670+#define VRFB_NUM_CTXS 12
1671+/* bitmap of reserved contexts */
1672+static unsigned ctx_map;
1673+
1674+void omap_vrfb_adjust_size(u16 *width, u16 *height,
1675+ u8 bytespp)
1676+{
1677+ *width = ALIGN(*width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
1678+ *height = ALIGN(*height, VRFB_PAGE_HEIGHT);
1679+}
1680+EXPORT_SYMBOL(omap_vrfb_adjust_size);
1681+
1682+void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
1683+ u16 width, u16 height,
1684+ u8 bytespp)
1685+{
1686+ unsigned pixel_size_exp;
1687+ u16 vrfb_width;
1688+ u16 vrfb_height;
1689+ u8 ctx = vrfb->context;
1690+
1691+ DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
1692+ width, height, bytespp);
1693+
1694+ if (bytespp == 4)
1695+ pixel_size_exp = 2;
1696+ else if (bytespp == 2)
1697+ pixel_size_exp = 1;
1698+ else
1699+ BUG();
1700+
1701+ vrfb_width = ALIGN(width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
1702+ vrfb_height = ALIGN(height, VRFB_PAGE_HEIGHT);
1703+
1704+ DBG("vrfb w %u, h %u\n", vrfb_width, vrfb_height);
1705+
1706+ omap_writel(paddr, SMS_ROT_PHYSICAL_BA(ctx));
1707+ omap_writel((vrfb_width << SMS_IMAGEWIDTH_OFFSET) |
1708+ (vrfb_height << SMS_IMAGEHEIGHT_OFFSET),
1709+ SMS_ROT_SIZE(ctx));
1710+
1711+ omap_writel(pixel_size_exp << SMS_PS_OFFSET |
1712+ VRFB_PAGE_WIDTH_EXP << SMS_PW_OFFSET |
1713+ VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET,
1714+ SMS_ROT_CONTROL(ctx));
1715+
1716+ DBG("vrfb offset pixels %d, %d\n",
1717+ vrfb_width - width, vrfb_height - height);
1718+
1719+ vrfb->xoffset = vrfb_width - width;
1720+ vrfb->yoffset = vrfb_height - height;
1721+ vrfb->bytespp = bytespp;
1722+}
1723+EXPORT_SYMBOL(omap_vrfb_setup);
1724+
1725+void omap_vrfb_release_ctx(struct vrfb *vrfb)
1726+{
1727+ int rot;
1728+
1729+ if (vrfb->context == 0xff)
1730+ return;
1731+
1732+ DBG("release ctx %d\n", vrfb->context);
1733+
1734+ ctx_map &= ~(1 << vrfb->context);
1735+
1736+ for (rot = 0; rot < 4; ++rot) {
1737+ if(vrfb->paddr[rot]) {
1738+ release_mem_region(vrfb->paddr[rot], OMAP_VRFB_SIZE);
1739+ vrfb->paddr[rot] = 0;
1740+ }
1741+ }
1742+
1743+ vrfb->context = 0xff;
1744+}
1745+EXPORT_SYMBOL(omap_vrfb_release_ctx);
1746+
1747+int omap_vrfb_request_ctx(struct vrfb *vrfb)
1748+{
1749+ int rot;
1750+ u32 paddr;
1751+ u8 ctx;
1752+
1753+ DBG("request ctx\n");
1754+
1755+ for (ctx = 0; ctx < VRFB_NUM_CTXS; ++ctx)
1756+ if ((ctx_map & (1 << ctx)) == 0)
1757+ break;
1758+
1759+ if (ctx == VRFB_NUM_CTXS) {
1760+ printk(KERN_ERR "vrfb: no free contexts\n");
1761+ return -EBUSY;
1762+ }
1763+
1764+ DBG("found free ctx %d\n", ctx);
1765+
1766+ ctx_map |= 1 << ctx;
1767+
1768+ memset(vrfb, 0, sizeof(*vrfb));
1769+
1770+ vrfb->context = ctx;
1771+
1772+ for (rot = 0; rot < 4; ++rot) {
1773+ paddr = SMS_ROT_VIRT_BASE(ctx, rot);
1774+ if (!request_mem_region(paddr, OMAP_VRFB_SIZE, "vrfb")) {
1775+ printk(KERN_ERR "vrfb: failed to reserve VRFB "
1776+ "area for ctx %d, rotation %d\n",
1777+ ctx, rot * 90);
1778+ omap_vrfb_release_ctx(vrfb);
1779+ return -ENOMEM;
1780+ }
1781+
1782+ vrfb->paddr[rot] = paddr;
1783+
1784+ DBG("VRFB %d/%d: %lx\n", ctx, rot*90, vrfb->paddr[rot]);
1785+ }
1786+
1787+ return 0;
1788+}
1789+EXPORT_SYMBOL(omap_vrfb_request_ctx);
1790+
1791diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
1792index fb19803..8b3752b 100644
1793--- a/drivers/video/Kconfig
1794+++ b/drivers/video/Kconfig
1795@@ -2132,6 +2132,7 @@ config FB_MX3
1796 an LCD display with your i.MX31 system, say Y here.
1797
1798 source "drivers/video/omap/Kconfig"
1799+source "drivers/video/omap2/Kconfig"
1800
1801 source "drivers/video/backlight/Kconfig"
1802 source "drivers/video/display/Kconfig"
1803diff --git a/drivers/video/Makefile b/drivers/video/Makefile
1804index 2a998ca..1db8dd4 100644
1805--- a/drivers/video/Makefile
1806+++ b/drivers/video/Makefile
1807@@ -120,6 +120,7 @@ obj-$(CONFIG_FB_SM501) += sm501fb.o
1808 obj-$(CONFIG_FB_XILINX) += xilinxfb.o
1809 obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o
1810 obj-$(CONFIG_FB_OMAP) += omap/
1811+obj-$(CONFIG_OMAP2_DSS) += omap2/
1812 obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o
1813 obj-$(CONFIG_FB_CARMINE) += carminefb.o
1814 obj-$(CONFIG_FB_MB862XX) += mb862xx/
1815diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
1816new file mode 100644
1817index 0000000..89bf210
1818--- /dev/null
1819+++ b/drivers/video/omap2/Kconfig
1820@@ -0,0 +1,3 @@
1821+source "drivers/video/omap2/dss/Kconfig"
1822+source "drivers/video/omap2/displays/Kconfig"
1823+source "drivers/video/omap2/omapfb/Kconfig"
1824diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
1825new file mode 100644
1826index 0000000..72134db
1827--- /dev/null
1828+++ b/drivers/video/omap2/Makefile
1829@@ -0,0 +1,4 @@
1830+# OMAP2/3 Display Subsystem
1831+obj-y += dss/
1832+obj-y += displays/
1833+obj-y += omapfb/
1834diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig
1835new file mode 100644
1836index 0000000..f2ce068
1837--- /dev/null
1838+++ b/drivers/video/omap2/dss/Kconfig
1839@@ -0,0 +1,89 @@
1840+menuconfig OMAP2_DSS
1841+ tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)"
1842+ depends on ARCH_OMAP2 || ARCH_OMAP3
1843+ help
1844+ OMAP2/3 Display Subsystem support.
1845+
1846+if OMAP2_DSS
1847+
1848+config OMAP2_DSS_VRAM_SIZE
1849+ int "VRAM size (MB)"
1850+ range 0 32
1851+ default 4
1852+ help
1853+ The amount of SDRAM to reserve at boot time for video RAM use.
1854+ This VRAM will be used by omapfb and other drivers that need
1855+ large continuous RAM area for video use.
1856+
1857+ You can also set this with "vram=<bytes>" kernel argument, or
1858+ in the board file.
1859+
1860+config OMAP2_DSS_DEBUG_SUPPORT
1861+ bool "Debug support"
1862+ default y
1863+ help
1864+ This enables debug messages. You need to enable printing
1865+ with 'debug' module parameter.
1866+
1867+config OMAP2_DSS_RFBI
1868+ bool "RFBI support"
1869+ default n
1870+ help
1871+ MIPI DBI, or RFBI (Remote Framebuffer Interface), support.
1872+
1873+config OMAP2_DSS_VENC
1874+ bool "VENC support"
1875+ default y
1876+ help
1877+ OMAP Video Encoder support.
1878+
1879+config OMAP2_DSS_SDI
1880+ bool "SDI support"
1881+ depends on ARCH_OMAP3
1882+ default n
1883+ help
1884+ SDI (Serial Display Interface) support.
1885+
1886+config OMAP2_DSS_DSI
1887+ bool "DSI support"
1888+ depends on ARCH_OMAP3
1889+ default n
1890+ help
1891+ MIPI DSI support.
1892+
1893+config OMAP2_DSS_USE_DSI_PLL
1894+ bool "Use DSI PLL for PCLK (EXPERIMENTAL)"
1895+ default n
1896+ depends on OMAP2_DSS_DSI
1897+ help
1898+ Use DSI PLL to generate pixel clock. Currently only for DPI output.
1899+ DSI PLL can be used to generate higher and more precise pixel clocks.
1900+
1901+config OMAP2_DSS_FAKE_VSYNC
1902+ bool "Fake VSYNC irq from manual update displays"
1903+ default n
1904+ help
1905+ If this is selected, DSI will generate a fake DISPC VSYNC interrupt
1906+ when DSI has sent a frame. This is only needed with DSI or RFBI
1907+ displays using manual mode, and you want VSYNC to, for example,
1908+ time animation.
1909+
1910+config OMAP2_DSS_MIN_FCK_PER_PCK
1911+ int "Minimum FCK/PCK ratio (for scaling)"
1912+ range 0 32
1913+ default 0
1914+ help
1915+ This can be used to adjust the minimum FCK/PCK ratio.
1916+
1917+ With this you can make sure that DISPC FCK is at least
1918+ n x PCK. Video plane scaling requires higher FCK than
1919+ normally.
1920+
1921+ If this is set to 0, there's no extra constraint on the
1922+ DISPC FCK. However, the FCK will at minimum be
1923+ 2xPCK (if active matrix) or 3xPCK (if passive matrix).
1924+
1925+ Max FCK is 173MHz, so this doesn't work if your PCK
1926+ is very high.
1927+
1928+endif
1929diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile
1930new file mode 100644
1931index 0000000..980c72c
1932--- /dev/null
1933+++ b/drivers/video/omap2/dss/Makefile
1934@@ -0,0 +1,6 @@
1935+obj-$(CONFIG_OMAP2_DSS) += omapdss.o
1936+omapdss-y := core.o dss.o dispc.o dpi.o display.o manager.o overlay.o
1937+omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
1938+omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
1939+omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
1940+omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
1941diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
1942new file mode 100644
1943index 0000000..ae7cd06
1944--- /dev/null
1945+++ b/drivers/video/omap2/dss/core.c
1946@@ -0,0 +1,641 @@
1947+/*
1948+ * linux/drivers/video/omap2/dss/core.c
1949+ *
1950+ * Copyright (C) 2009 Nokia Corporation
1951+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
1952+ *
1953+ * Some code and ideas taken from drivers/video/omap/ driver
1954+ * by Imre Deak.
1955+ *
1956+ * This program is free software; you can redistribute it and/or modify it
1957+ * under the terms of the GNU General Public License version 2 as published by
1958+ * the Free Software Foundation.
1959+ *
1960+ * This program is distributed in the hope that it will be useful, but WITHOUT
1961+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1962+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1963+ * more details.
1964+ *
1965+ * You should have received a copy of the GNU General Public License along with
1966+ * this program. If not, see <http://www.gnu.org/licenses/>.
1967+ */
1968+
1969+#define DSS_SUBSYS_NAME "CORE"
1970+
1971+#include <linux/kernel.h>
1972+#include <linux/module.h>
1973+#include <linux/clk.h>
1974+#include <linux/err.h>
1975+#include <linux/platform_device.h>
1976+#include <linux/seq_file.h>
1977+#include <linux/debugfs.h>
1978+#include <linux/io.h>
1979+
1980+#include <mach/display.h>
1981+#include <mach/clock.h>
1982+
1983+#include "dss.h"
1984+
1985+static struct {
1986+ struct platform_device *pdev;
1987+ unsigned ctx_id;
1988+
1989+ struct clk *dss_ick;
1990+ struct clk *dss1_fck;
1991+ struct clk *dss2_fck;
1992+ struct clk *dss_54m_fck;
1993+ struct clk *dss_96m_fck;
1994+ unsigned num_clks_enabled;
1995+} core;
1996+
1997+static void dss_clk_enable_all_no_ctx(void);
1998+static void dss_clk_disable_all_no_ctx(void);
1999+static void dss_clk_enable_no_ctx(enum dss_clock clks);
2000+static void dss_clk_disable_no_ctx(enum dss_clock clks);
2001+
2002+static char *def_disp_name;
2003+module_param_named(def_disp, def_disp_name, charp, 0);
2004+MODULE_PARM_DESC(def_disp_name, "default display name");
2005+
2006+#ifdef DEBUG
2007+unsigned int dss_debug;
2008+module_param_named(debug, dss_debug, bool, 0644);
2009+#endif
2010+
2011+/* CONTEXT */
2012+static unsigned dss_get_ctx_id(void)
2013+{
2014+ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
2015+
2016+ if (!pdata->get_last_off_on_transaction_id)
2017+ return 0;
2018+
2019+ return pdata->get_last_off_on_transaction_id(&core.pdev->dev);
2020+}
2021+
2022+int dss_need_ctx_restore(void)
2023+{
2024+ int id = dss_get_ctx_id();
2025+
2026+ if (id != core.ctx_id) {
2027+ DSSDBG("ctx id %u -> id %u\n",
2028+ core.ctx_id, id);
2029+ core.ctx_id = id;
2030+ return 1;
2031+ } else {
2032+ return 0;
2033+ }
2034+}
2035+
2036+static void save_all_ctx(void)
2037+{
2038+ DSSDBG("save context\n");
2039+
2040+ dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
2041+
2042+ dss_save_context();
2043+ dispc_save_context();
2044+#ifdef CONFIG_OMAP2_DSS_DSI
2045+ dsi_save_context();
2046+#endif
2047+
2048+ dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
2049+}
2050+
2051+static void restore_all_ctx(void)
2052+{
2053+ DSSDBG("restore context\n");
2054+
2055+ dss_clk_enable_all_no_ctx();
2056+
2057+ dss_restore_context();
2058+ dispc_restore_context();
2059+#ifdef CONFIG_OMAP2_DSS_DSI
2060+ dsi_restore_context();
2061+#endif
2062+
2063+ dss_clk_disable_all_no_ctx();
2064+}
2065+
2066+/* CLOCKS */
2067+void dss_dump_clocks(struct seq_file *s)
2068+{
2069+ int i;
2070+ struct clk *clocks[5] = {
2071+ core.dss_ick,
2072+ core.dss1_fck,
2073+ core.dss2_fck,
2074+ core.dss_54m_fck,
2075+ core.dss_96m_fck
2076+ };
2077+
2078+ seq_printf(s, "- dss -\n");
2079+
2080+ seq_printf(s, "internal clk count\t%u\n", core.num_clks_enabled);
2081+
2082+ for (i = 0; i < 5; i++) {
2083+ if (!clocks[i])
2084+ continue;
2085+ seq_printf(s, "%-15s\t%lu\t%d\n",
2086+ clocks[i]->name,
2087+ clk_get_rate(clocks[i]),
2088+ clocks[i]->usecount);
2089+ }
2090+}
2091+
2092+static int dss_get_clocks(void)
2093+{
2094+ const struct {
2095+ struct clk **clock;
2096+ char *omap2_name;
2097+ char *omap3_name;
2098+ } clocks[5] = {
2099+ { &core.dss_ick, "dss_ick", "dss_ick" }, /* L3 & L4 ick */
2100+ { &core.dss1_fck, "dss1_fck", "dss1_alwon_fck" },
2101+ { &core.dss2_fck, "dss2_fck", "dss2_alwon_fck" },
2102+ { &core.dss_54m_fck, "dss_54m_fck", "dss_tv_fck" },
2103+ { &core.dss_96m_fck, NULL, "dss_96m_fck" },
2104+ };
2105+
2106+ int r = 0;
2107+ int i;
2108+ const int num_clocks = 5;
2109+
2110+ for (i = 0; i < num_clocks; i++)
2111+ *clocks[i].clock = NULL;
2112+
2113+ for (i = 0; i < num_clocks; i++) {
2114+ struct clk *clk;
2115+ const char *clk_name;
2116+
2117+ clk_name = cpu_is_omap34xx() ? clocks[i].omap3_name
2118+ : clocks[i].omap2_name;
2119+
2120+ if (!clk_name)
2121+ continue;
2122+
2123+ clk = clk_get(NULL, clk_name);
2124+
2125+ if (IS_ERR(clk)) {
2126+ DSSERR("can't get clock %s", clk_name);
2127+ r = PTR_ERR(clk);
2128+ goto err;
2129+ }
2130+
2131+ DSSDBG("clk %s, rate %ld\n",
2132+ clk_name, clk_get_rate(clk));
2133+
2134+ *clocks[i].clock = clk;
2135+ }
2136+
2137+ return 0;
2138+
2139+err:
2140+ for (i = 0; i < num_clocks; i++) {
2141+ if (!IS_ERR(*clocks[i].clock))
2142+ clk_put(*clocks[i].clock);
2143+ }
2144+
2145+ return r;
2146+}
2147+
2148+static void dss_put_clocks(void)
2149+{
2150+ if (core.dss_96m_fck)
2151+ clk_put(core.dss_96m_fck);
2152+ clk_put(core.dss_54m_fck);
2153+ clk_put(core.dss1_fck);
2154+ clk_put(core.dss2_fck);
2155+ clk_put(core.dss_ick);
2156+}
2157+
2158+unsigned long dss_clk_get_rate(enum dss_clock clk)
2159+{
2160+ switch (clk) {
2161+ case DSS_CLK_ICK:
2162+ return clk_get_rate(core.dss_ick);
2163+ case DSS_CLK_FCK1:
2164+ return clk_get_rate(core.dss1_fck);
2165+ case DSS_CLK_FCK2:
2166+ return clk_get_rate(core.dss2_fck);
2167+ case DSS_CLK_54M:
2168+ return clk_get_rate(core.dss_54m_fck);
2169+ case DSS_CLK_96M:
2170+ return clk_get_rate(core.dss_96m_fck);
2171+ }
2172+
2173+ BUG();
2174+ return 0;
2175+}
2176+
2177+static unsigned count_clk_bits(enum dss_clock clks)
2178+{
2179+ unsigned num_clks = 0;
2180+
2181+ if (clks & DSS_CLK_ICK)
2182+ ++num_clks;
2183+ if (clks & DSS_CLK_FCK1)
2184+ ++num_clks;
2185+ if (clks & DSS_CLK_FCK2)
2186+ ++num_clks;
2187+ if (clks & DSS_CLK_54M)
2188+ ++num_clks;
2189+ if (clks & DSS_CLK_96M)
2190+ ++num_clks;
2191+
2192+ return num_clks;
2193+}
2194+
2195+static void dss_clk_enable_no_ctx(enum dss_clock clks)
2196+{
2197+ unsigned num_clks = count_clk_bits(clks);
2198+
2199+ if (clks & DSS_CLK_ICK)
2200+ clk_enable(core.dss_ick);
2201+ if (clks & DSS_CLK_FCK1)
2202+ clk_enable(core.dss1_fck);
2203+ if (clks & DSS_CLK_FCK2)
2204+ clk_enable(core.dss2_fck);
2205+ if (clks & DSS_CLK_54M)
2206+ clk_enable(core.dss_54m_fck);
2207+ if (clks & DSS_CLK_96M)
2208+ clk_enable(core.dss_96m_fck);
2209+
2210+ core.num_clks_enabled += num_clks;
2211+}
2212+
2213+void dss_clk_enable(enum dss_clock clks)
2214+{
2215+ dss_clk_enable_no_ctx(clks);
2216+
2217+ if (cpu_is_omap34xx() && dss_need_ctx_restore())
2218+ restore_all_ctx();
2219+}
2220+
2221+static void dss_clk_disable_no_ctx(enum dss_clock clks)
2222+{
2223+ unsigned num_clks = count_clk_bits(clks);
2224+
2225+ if (clks & DSS_CLK_ICK)
2226+ clk_disable(core.dss_ick);
2227+ if (clks & DSS_CLK_FCK1)
2228+ clk_disable(core.dss1_fck);
2229+ if (clks & DSS_CLK_FCK2)
2230+ clk_disable(core.dss2_fck);
2231+ if (clks & DSS_CLK_54M)
2232+ clk_disable(core.dss_54m_fck);
2233+ if (clks & DSS_CLK_96M)
2234+ clk_disable(core.dss_96m_fck);
2235+
2236+ core.num_clks_enabled -= num_clks;
2237+}
2238+
2239+void dss_clk_disable(enum dss_clock clks)
2240+{
2241+ if (cpu_is_omap34xx()) {
2242+ unsigned num_clks = count_clk_bits(clks);
2243+
2244+ BUG_ON(core.num_clks_enabled < num_clks);
2245+
2246+ if (core.num_clks_enabled == num_clks)
2247+ save_all_ctx();
2248+ }
2249+
2250+ dss_clk_disable_no_ctx(clks);
2251+}
2252+
2253+static void dss_clk_enable_all_no_ctx(void)
2254+{
2255+ enum dss_clock clks;
2256+
2257+ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
2258+ if (cpu_is_omap34xx())
2259+ clks |= DSS_CLK_96M;
2260+ dss_clk_enable_no_ctx(clks);
2261+}
2262+
2263+static void dss_clk_disable_all_no_ctx(void)
2264+{
2265+ enum dss_clock clks;
2266+
2267+ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
2268+ if (cpu_is_omap34xx())
2269+ clks |= DSS_CLK_96M;
2270+ dss_clk_disable_no_ctx(clks);
2271+}
2272+
2273+static void dss_clk_disable_all(void)
2274+{
2275+ enum dss_clock clks;
2276+
2277+ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
2278+ if (cpu_is_omap34xx())
2279+ clks |= DSS_CLK_96M;
2280+ dss_clk_disable(clks);
2281+}
2282+
2283+/* DEBUGFS */
2284+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
2285+static void dss_debug_dump_clocks(struct seq_file *s)
2286+{
2287+ dss_dump_clocks(s);
2288+ dispc_dump_clocks(s);
2289+#ifdef CONFIG_OMAP2_DSS_DSI
2290+ dsi_dump_clocks(s);
2291+#endif
2292+}
2293+
2294+static int dss_debug_show(struct seq_file *s, void *unused)
2295+{
2296+ void (*func)(struct seq_file *) = s->private;
2297+ func(s);
2298+ return 0;
2299+}
2300+
2301+static int dss_debug_open(struct inode *inode, struct file *file)
2302+{
2303+ return single_open(file, dss_debug_show, inode->i_private);
2304+}
2305+
2306+static const struct file_operations dss_debug_fops = {
2307+ .open = dss_debug_open,
2308+ .read = seq_read,
2309+ .llseek = seq_lseek,
2310+ .release = single_release,
2311+};
2312+
2313+static struct dentry *dss_debugfs_dir;
2314+
2315+static int dss_initialize_debugfs(void)
2316+{
2317+ dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
2318+ if (IS_ERR(dss_debugfs_dir)) {
2319+ int err = PTR_ERR(dss_debugfs_dir);
2320+ dss_debugfs_dir = NULL;
2321+ return err;
2322+ }
2323+
2324+ debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
2325+ &dss_debug_dump_clocks, &dss_debug_fops);
2326+
2327+ debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
2328+ &dss_dump_regs, &dss_debug_fops);
2329+ debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
2330+ &dispc_dump_regs, &dss_debug_fops);
2331+#ifdef CONFIG_OMAP2_DSS_RFBI
2332+ debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
2333+ &rfbi_dump_regs, &dss_debug_fops);
2334+#endif
2335+#ifdef CONFIG_OMAP2_DSS_DSI
2336+ debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
2337+ &dsi_dump_regs, &dss_debug_fops);
2338+#endif
2339+ return 0;
2340+}
2341+
2342+static void dss_uninitialize_debugfs(void)
2343+{
2344+ if (dss_debugfs_dir)
2345+ debugfs_remove_recursive(dss_debugfs_dir);
2346+}
2347+#endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
2348+
2349+
2350+/* DSI powers */
2351+int dss_dsi_power_up(void)
2352+{
2353+ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
2354+
2355+ if (!pdata->dsi_power_up)
2356+ return 0; /* presume power is always on then */
2357+
2358+ return pdata->dsi_power_up();
2359+}
2360+
2361+void dss_dsi_power_down(void)
2362+{
2363+ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
2364+
2365+ if (!pdata->dsi_power_down)
2366+ return;
2367+
2368+ pdata->dsi_power_down();
2369+}
2370+
2371+
2372+
2373+/* PLATFORM DEVICE */
2374+static int omap_dss_probe(struct platform_device *pdev)
2375+{
2376+ int skip_init = 0;
2377+ int r;
2378+
2379+ core.pdev = pdev;
2380+
2381+ r = dss_get_clocks();
2382+ if (r)
2383+ goto fail0;
2384+
2385+ dss_clk_enable_all_no_ctx();
2386+
2387+ core.ctx_id = dss_get_ctx_id();
2388+ DSSDBG("initial ctx id %u\n", core.ctx_id);
2389+
2390+#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
2391+ /* DISPC_CONTROL */
2392+ if (omap_readl(0x48050440) & 1) /* LCD enabled? */
2393+ skip_init = 1;
2394+#endif
2395+
2396+ r = dss_init(skip_init);
2397+ if (r) {
2398+ DSSERR("Failed to initialize DSS\n");
2399+ goto fail0;
2400+ }
2401+
2402+#ifdef CONFIG_OMAP2_DSS_RFBI
2403+ r = rfbi_init();
2404+ if (r) {
2405+ DSSERR("Failed to initialize rfbi\n");
2406+ goto fail0;
2407+ }
2408+#endif
2409+
2410+ r = dpi_init();
2411+ if (r) {
2412+ DSSERR("Failed to initialize dpi\n");
2413+ goto fail0;
2414+ }
2415+
2416+ r = dispc_init();
2417+ if (r) {
2418+ DSSERR("Failed to initialize dispc\n");
2419+ goto fail0;
2420+ }
2421+#ifdef CONFIG_OMAP2_DSS_VENC
2422+ r = venc_init();
2423+ if (r) {
2424+ DSSERR("Failed to initialize venc\n");
2425+ goto fail0;
2426+ }
2427+#endif
2428+ if (cpu_is_omap34xx()) {
2429+#ifdef CONFIG_OMAP2_DSS_SDI
2430+ r = sdi_init(skip_init);
2431+ if (r) {
2432+ DSSERR("Failed to initialize SDI\n");
2433+ goto fail0;
2434+ }
2435+#endif
2436+#ifdef CONFIG_OMAP2_DSS_DSI
2437+ r = dsi_init();
2438+ if (r) {
2439+ DSSERR("Failed to initialize DSI\n");
2440+ goto fail0;
2441+ }
2442+#endif
2443+ }
2444+
2445+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
2446+ r = dss_initialize_debugfs();
2447+ if (r)
2448+ goto fail0;
2449+#endif
2450+
2451+ dss_init_displays(pdev);
2452+ dss_init_overlay_managers(pdev);
2453+ dss_init_overlays(pdev, def_disp_name);
2454+
2455+ dss_clk_disable_all();
2456+
2457+ return 0;
2458+
2459+ /* XXX fail correctly */
2460+fail0:
2461+ return r;
2462+}
2463+
2464+static int omap_dss_remove(struct platform_device *pdev)
2465+{
2466+ int c;
2467+
2468+ dss_uninit_overlays(pdev);
2469+ dss_uninit_overlay_managers(pdev);
2470+ dss_uninit_displays(pdev);
2471+
2472+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
2473+ dss_uninitialize_debugfs();
2474+#endif
2475+
2476+#ifdef CONFIG_OMAP2_DSS_VENC
2477+ venc_exit();
2478+#endif
2479+ dispc_exit();
2480+ dpi_exit();
2481+#ifdef CONFIG_OMAP2_DSS_RFBI
2482+ rfbi_exit();
2483+#endif
2484+ if (cpu_is_omap34xx()) {
2485+#ifdef CONFIG_OMAP2_DSS_DSI
2486+ dsi_exit();
2487+#endif
2488+#ifdef CONFIG_OMAP2_DSS_SDI
2489+ sdi_exit();
2490+#endif
2491+ }
2492+
2493+ dss_exit();
2494+
2495+ /* these should be removed at some point */
2496+ c = core.dss_ick->usecount;
2497+ if (c > 0) {
2498+ DSSERR("warning: dss_ick usecount %d, disabling\n", c);
2499+ while (c-- > 0)
2500+ clk_disable(core.dss_ick);
2501+ }
2502+
2503+ c = core.dss1_fck->usecount;
2504+ if (c > 0) {
2505+ DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
2506+ while (c-- > 0)
2507+ clk_disable(core.dss1_fck);
2508+ }
2509+
2510+ c = core.dss2_fck->usecount;
2511+ if (c > 0) {
2512+ DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
2513+ while (c-- > 0)
2514+ clk_disable(core.dss2_fck);
2515+ }
2516+
2517+ c = core.dss_54m_fck->usecount;
2518+ if (c > 0) {
2519+ DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
2520+ while (c-- > 0)
2521+ clk_disable(core.dss_54m_fck);
2522+ }
2523+
2524+ if (core.dss_96m_fck) {
2525+ c = core.dss_96m_fck->usecount;
2526+ if (c > 0) {
2527+ DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
2528+ c);
2529+ while (c-- > 0)
2530+ clk_disable(core.dss_96m_fck);
2531+ }
2532+ }
2533+
2534+ dss_put_clocks();
2535+
2536+ return 0;
2537+}
2538+
2539+static void omap_dss_shutdown(struct platform_device *pdev)
2540+{
2541+ DSSDBG("shutdown\n");
2542+}
2543+
2544+static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
2545+{
2546+ DSSDBG("suspend %d\n", state.event);
2547+
2548+ return dss_suspend_all_displays();
2549+}
2550+
2551+static int omap_dss_resume(struct platform_device *pdev)
2552+{
2553+ DSSDBG("resume\n");
2554+
2555+ return dss_resume_all_displays();
2556+}
2557+
2558+static struct platform_driver omap_dss_driver = {
2559+ .probe = omap_dss_probe,
2560+ .remove = omap_dss_remove,
2561+ .shutdown = omap_dss_shutdown,
2562+ .suspend = omap_dss_suspend,
2563+ .resume = omap_dss_resume,
2564+ .driver = {
2565+ .name = "omapdss",
2566+ .owner = THIS_MODULE,
2567+ },
2568+};
2569+
2570+static int __init omap_dss_init(void)
2571+{
2572+ return platform_driver_register(&omap_dss_driver);
2573+}
2574+
2575+static void __exit omap_dss_exit(void)
2576+{
2577+ platform_driver_unregister(&omap_dss_driver);
2578+}
2579+
2580+subsys_initcall(omap_dss_init);
2581+module_exit(omap_dss_exit);
2582+
2583+
2584+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
2585+MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
2586+MODULE_LICENSE("GPL v2");
2587+
2588diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
2589new file mode 100644
2590index 0000000..ffb5648
2591--- /dev/null
2592+++ b/drivers/video/omap2/dss/dispc.c
2593@@ -0,0 +1,2968 @@
2594+/*
2595+ * linux/drivers/video/omap2/dss/dispc.c
2596+ *
2597+ * Copyright (C) 2009 Nokia Corporation
2598+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2599+ *
2600+ * Some code and ideas taken from drivers/video/omap/ driver
2601+ * by Imre Deak.
2602+ *
2603+ * This program is free software; you can redistribute it and/or modify it
2604+ * under the terms of the GNU General Public License version 2 as published by
2605+ * the Free Software Foundation.
2606+ *
2607+ * This program is distributed in the hope that it will be useful, but WITHOUT
2608+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2609+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
2610+ * more details.
2611+ *
2612+ * You should have received a copy of the GNU General Public License along with
2613+ * this program. If not, see <http://www.gnu.org/licenses/>.
2614+ */
2615+
2616+#define DSS_SUBSYS_NAME "DISPC"
2617+
2618+#include <linux/kernel.h>
2619+#include <linux/dma-mapping.h>
2620+#include <linux/vmalloc.h>
2621+#include <linux/clk.h>
2622+#include <linux/io.h>
2623+#include <linux/jiffies.h>
2624+#include <linux/seq_file.h>
2625+#include <linux/delay.h>
2626+#include <linux/workqueue.h>
2627+
2628+#include <mach/sram.h>
2629+#include <mach/board.h>
2630+#include <mach/clock.h>
2631+
2632+#include <mach/display.h>
2633+
2634+#include "dss.h"
2635+
2636+/* DISPC */
2637+#define DISPC_BASE 0x48050400
2638+
2639+#define DISPC_SZ_REGS SZ_1K
2640+
2641+struct dispc_reg { u16 idx; };
2642+
2643+#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
2644+
2645+/* DISPC common */
2646+#define DISPC_REVISION DISPC_REG(0x0000)
2647+#define DISPC_SYSCONFIG DISPC_REG(0x0010)
2648+#define DISPC_SYSSTATUS DISPC_REG(0x0014)
2649+#define DISPC_IRQSTATUS DISPC_REG(0x0018)
2650+#define DISPC_IRQENABLE DISPC_REG(0x001C)
2651+#define DISPC_CONTROL DISPC_REG(0x0040)
2652+#define DISPC_CONFIG DISPC_REG(0x0044)
2653+#define DISPC_CAPABLE DISPC_REG(0x0048)
2654+#define DISPC_DEFAULT_COLOR0 DISPC_REG(0x004C)
2655+#define DISPC_DEFAULT_COLOR1 DISPC_REG(0x0050)
2656+#define DISPC_TRANS_COLOR0 DISPC_REG(0x0054)
2657+#define DISPC_TRANS_COLOR1 DISPC_REG(0x0058)
2658+#define DISPC_LINE_STATUS DISPC_REG(0x005C)
2659+#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
2660+#define DISPC_TIMING_H DISPC_REG(0x0064)
2661+#define DISPC_TIMING_V DISPC_REG(0x0068)
2662+#define DISPC_POL_FREQ DISPC_REG(0x006C)
2663+#define DISPC_DIVISOR DISPC_REG(0x0070)
2664+#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
2665+#define DISPC_SIZE_DIG DISPC_REG(0x0078)
2666+#define DISPC_SIZE_LCD DISPC_REG(0x007C)
2667+
2668+/* DISPC GFX plane */
2669+#define DISPC_GFX_BA0 DISPC_REG(0x0080)
2670+#define DISPC_GFX_BA1 DISPC_REG(0x0084)
2671+#define DISPC_GFX_POSITION DISPC_REG(0x0088)
2672+#define DISPC_GFX_SIZE DISPC_REG(0x008C)
2673+#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
2674+#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
2675+#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
2676+#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
2677+#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
2678+#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
2679+#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
2680+
2681+#define DISPC_DATA_CYCLE1 DISPC_REG(0x01D4)
2682+#define DISPC_DATA_CYCLE2 DISPC_REG(0x01D8)
2683+#define DISPC_DATA_CYCLE3 DISPC_REG(0x01DC)
2684+
2685+#define DISPC_CPR_COEF_R DISPC_REG(0x0220)
2686+#define DISPC_CPR_COEF_G DISPC_REG(0x0224)
2687+#define DISPC_CPR_COEF_B DISPC_REG(0x0228)
2688+
2689+#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
2690+
2691+/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
2692+#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
2693+
2694+#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
2695+#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
2696+#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
2697+#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
2698+#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
2699+#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
2700+#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
2701+#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
2702+#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
2703+#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
2704+#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
2705+#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
2706+#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
2707+
2708+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
2709+#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
2710+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
2711+#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
2712+/* coef index i = {0, 1, 2, 3, 4} */
2713+#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
2714+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
2715+#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
2716+
2717+#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
2718+
2719+
2720+#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
2721+ DISPC_IRQ_OCP_ERR | \
2722+ DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
2723+ DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
2724+ DISPC_IRQ_SYNC_LOST | \
2725+ DISPC_IRQ_SYNC_LOST_DIGIT)
2726+
2727+#define DISPC_MAX_NR_ISRS 8
2728+
2729+struct omap_dispc_isr_data {
2730+ omap_dispc_isr_t isr;
2731+ void *arg;
2732+ u32 mask;
2733+};
2734+
2735+#define REG_GET(idx, start, end) \
2736+ FLD_GET(dispc_read_reg(idx), start, end)
2737+
2738+#define REG_FLD_MOD(idx, val, start, end) \
2739+ dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
2740+
2741+static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
2742+ DISPC_VID_ATTRIBUTES(0),
2743+ DISPC_VID_ATTRIBUTES(1) };
2744+
2745+static struct {
2746+ void __iomem *base;
2747+
2748+ struct clk *dpll4_m4_ck;
2749+
2750+ spinlock_t irq_lock;
2751+
2752+ unsigned long cache_req_pck;
2753+ unsigned long cache_prate;
2754+ struct dispc_clock_info cache_cinfo;
2755+
2756+ u32 irq_error_mask;
2757+ struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2758+
2759+ spinlock_t error_lock;
2760+ u32 error_irqs;
2761+ struct work_struct error_work;
2762+
2763+ u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
2764+} dispc;
2765+
2766+static void omap_dispc_set_irqs(void);
2767+
2768+static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
2769+{
2770+ __raw_writel(val, dispc.base + idx.idx);
2771+}
2772+
2773+static inline u32 dispc_read_reg(const struct dispc_reg idx)
2774+{
2775+ return __raw_readl(dispc.base + idx.idx);
2776+}
2777+
2778+#define SR(reg) \
2779+ dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
2780+#define RR(reg) \
2781+ dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
2782+
2783+void dispc_save_context(void)
2784+{
2785+ if (cpu_is_omap24xx())
2786+ return;
2787+
2788+ SR(SYSCONFIG);
2789+ SR(IRQENABLE);
2790+ SR(CONTROL);
2791+ SR(CONFIG);
2792+ SR(DEFAULT_COLOR0);
2793+ SR(DEFAULT_COLOR1);
2794+ SR(TRANS_COLOR0);
2795+ SR(TRANS_COLOR1);
2796+ SR(LINE_NUMBER);
2797+ SR(TIMING_H);
2798+ SR(TIMING_V);
2799+ SR(POL_FREQ);
2800+ SR(DIVISOR);
2801+ SR(GLOBAL_ALPHA);
2802+ SR(SIZE_DIG);
2803+ SR(SIZE_LCD);
2804+
2805+ SR(GFX_BA0);
2806+ SR(GFX_BA1);
2807+ SR(GFX_POSITION);
2808+ SR(GFX_SIZE);
2809+ SR(GFX_ATTRIBUTES);
2810+ SR(GFX_FIFO_THRESHOLD);
2811+ SR(GFX_ROW_INC);
2812+ SR(GFX_PIXEL_INC);
2813+ SR(GFX_WINDOW_SKIP);
2814+ SR(GFX_TABLE_BA);
2815+
2816+ SR(DATA_CYCLE1);
2817+ SR(DATA_CYCLE2);
2818+ SR(DATA_CYCLE3);
2819+
2820+ SR(CPR_COEF_R);
2821+ SR(CPR_COEF_G);
2822+ SR(CPR_COEF_B);
2823+
2824+ SR(GFX_PRELOAD);
2825+
2826+ /* VID1 */
2827+ SR(VID_BA0(0));
2828+ SR(VID_BA1(0));
2829+ SR(VID_POSITION(0));
2830+ SR(VID_SIZE(0));
2831+ SR(VID_ATTRIBUTES(0));
2832+ SR(VID_FIFO_THRESHOLD(0));
2833+ SR(VID_ROW_INC(0));
2834+ SR(VID_PIXEL_INC(0));
2835+ SR(VID_FIR(0));
2836+ SR(VID_PICTURE_SIZE(0));
2837+ SR(VID_ACCU0(0));
2838+ SR(VID_ACCU1(0));
2839+
2840+ SR(VID_FIR_COEF_H(0, 0));
2841+ SR(VID_FIR_COEF_H(0, 1));
2842+ SR(VID_FIR_COEF_H(0, 2));
2843+ SR(VID_FIR_COEF_H(0, 3));
2844+ SR(VID_FIR_COEF_H(0, 4));
2845+ SR(VID_FIR_COEF_H(0, 5));
2846+ SR(VID_FIR_COEF_H(0, 6));
2847+ SR(VID_FIR_COEF_H(0, 7));
2848+
2849+ SR(VID_FIR_COEF_HV(0, 0));
2850+ SR(VID_FIR_COEF_HV(0, 1));
2851+ SR(VID_FIR_COEF_HV(0, 2));
2852+ SR(VID_FIR_COEF_HV(0, 3));
2853+ SR(VID_FIR_COEF_HV(0, 4));
2854+ SR(VID_FIR_COEF_HV(0, 5));
2855+ SR(VID_FIR_COEF_HV(0, 6));
2856+ SR(VID_FIR_COEF_HV(0, 7));
2857+
2858+ SR(VID_CONV_COEF(0, 0));
2859+ SR(VID_CONV_COEF(0, 1));
2860+ SR(VID_CONV_COEF(0, 2));
2861+ SR(VID_CONV_COEF(0, 3));
2862+ SR(VID_CONV_COEF(0, 4));
2863+
2864+ SR(VID_FIR_COEF_V(0, 0));
2865+ SR(VID_FIR_COEF_V(0, 1));
2866+ SR(VID_FIR_COEF_V(0, 2));
2867+ SR(VID_FIR_COEF_V(0, 3));
2868+ SR(VID_FIR_COEF_V(0, 4));
2869+ SR(VID_FIR_COEF_V(0, 5));
2870+ SR(VID_FIR_COEF_V(0, 6));
2871+ SR(VID_FIR_COEF_V(0, 7));
2872+
2873+ SR(VID_PRELOAD(0));
2874+
2875+ /* VID2 */
2876+ SR(VID_BA0(1));
2877+ SR(VID_BA1(1));
2878+ SR(VID_POSITION(1));
2879+ SR(VID_SIZE(1));
2880+ SR(VID_ATTRIBUTES(1));
2881+ SR(VID_FIFO_THRESHOLD(1));
2882+ SR(VID_ROW_INC(1));
2883+ SR(VID_PIXEL_INC(1));
2884+ SR(VID_FIR(1));
2885+ SR(VID_PICTURE_SIZE(1));
2886+ SR(VID_ACCU0(1));
2887+ SR(VID_ACCU1(1));
2888+
2889+ SR(VID_FIR_COEF_H(1, 0));
2890+ SR(VID_FIR_COEF_H(1, 1));
2891+ SR(VID_FIR_COEF_H(1, 2));
2892+ SR(VID_FIR_COEF_H(1, 3));
2893+ SR(VID_FIR_COEF_H(1, 4));
2894+ SR(VID_FIR_COEF_H(1, 5));
2895+ SR(VID_FIR_COEF_H(1, 6));
2896+ SR(VID_FIR_COEF_H(1, 7));
2897+
2898+ SR(VID_FIR_COEF_HV(1, 0));
2899+ SR(VID_FIR_COEF_HV(1, 1));
2900+ SR(VID_FIR_COEF_HV(1, 2));
2901+ SR(VID_FIR_COEF_HV(1, 3));
2902+ SR(VID_FIR_COEF_HV(1, 4));
2903+ SR(VID_FIR_COEF_HV(1, 5));
2904+ SR(VID_FIR_COEF_HV(1, 6));
2905+ SR(VID_FIR_COEF_HV(1, 7));
2906+
2907+ SR(VID_CONV_COEF(1, 0));
2908+ SR(VID_CONV_COEF(1, 1));
2909+ SR(VID_CONV_COEF(1, 2));
2910+ SR(VID_CONV_COEF(1, 3));
2911+ SR(VID_CONV_COEF(1, 4));
2912+
2913+ SR(VID_FIR_COEF_V(1, 0));
2914+ SR(VID_FIR_COEF_V(1, 1));
2915+ SR(VID_FIR_COEF_V(1, 2));
2916+ SR(VID_FIR_COEF_V(1, 3));
2917+ SR(VID_FIR_COEF_V(1, 4));
2918+ SR(VID_FIR_COEF_V(1, 5));
2919+ SR(VID_FIR_COEF_V(1, 6));
2920+ SR(VID_FIR_COEF_V(1, 7));
2921+
2922+ SR(VID_PRELOAD(1));
2923+}
2924+
2925+void dispc_restore_context(void)
2926+{
2927+ RR(SYSCONFIG);
2928+ RR(IRQENABLE);
2929+ /*RR(CONTROL);*/
2930+ RR(CONFIG);
2931+ RR(DEFAULT_COLOR0);
2932+ RR(DEFAULT_COLOR1);
2933+ RR(TRANS_COLOR0);
2934+ RR(TRANS_COLOR1);
2935+ RR(LINE_NUMBER);
2936+ RR(TIMING_H);
2937+ RR(TIMING_V);
2938+ RR(POL_FREQ);
2939+ RR(DIVISOR);
2940+ RR(GLOBAL_ALPHA);
2941+ RR(SIZE_DIG);
2942+ RR(SIZE_LCD);
2943+
2944+ RR(GFX_BA0);
2945+ RR(GFX_BA1);
2946+ RR(GFX_POSITION);
2947+ RR(GFX_SIZE);
2948+ RR(GFX_ATTRIBUTES);
2949+ RR(GFX_FIFO_THRESHOLD);
2950+ RR(GFX_ROW_INC);
2951+ RR(GFX_PIXEL_INC);
2952+ RR(GFX_WINDOW_SKIP);
2953+ RR(GFX_TABLE_BA);
2954+
2955+ RR(DATA_CYCLE1);
2956+ RR(DATA_CYCLE2);
2957+ RR(DATA_CYCLE3);
2958+
2959+ RR(CPR_COEF_R);
2960+ RR(CPR_COEF_G);
2961+ RR(CPR_COEF_B);
2962+
2963+ RR(GFX_PRELOAD);
2964+
2965+ /* VID1 */
2966+ RR(VID_BA0(0));
2967+ RR(VID_BA1(0));
2968+ RR(VID_POSITION(0));
2969+ RR(VID_SIZE(0));
2970+ RR(VID_ATTRIBUTES(0));
2971+ RR(VID_FIFO_THRESHOLD(0));
2972+ RR(VID_ROW_INC(0));
2973+ RR(VID_PIXEL_INC(0));
2974+ RR(VID_FIR(0));
2975+ RR(VID_PICTURE_SIZE(0));
2976+ RR(VID_ACCU0(0));
2977+ RR(VID_ACCU1(0));
2978+
2979+ RR(VID_FIR_COEF_H(0, 0));
2980+ RR(VID_FIR_COEF_H(0, 1));
2981+ RR(VID_FIR_COEF_H(0, 2));
2982+ RR(VID_FIR_COEF_H(0, 3));
2983+ RR(VID_FIR_COEF_H(0, 4));
2984+ RR(VID_FIR_COEF_H(0, 5));
2985+ RR(VID_FIR_COEF_H(0, 6));
2986+ RR(VID_FIR_COEF_H(0, 7));
2987+
2988+ RR(VID_FIR_COEF_HV(0, 0));
2989+ RR(VID_FIR_COEF_HV(0, 1));
2990+ RR(VID_FIR_COEF_HV(0, 2));
2991+ RR(VID_FIR_COEF_HV(0, 3));
2992+ RR(VID_FIR_COEF_HV(0, 4));
2993+ RR(VID_FIR_COEF_HV(0, 5));
2994+ RR(VID_FIR_COEF_HV(0, 6));
2995+ RR(VID_FIR_COEF_HV(0, 7));
2996+
2997+ RR(VID_CONV_COEF(0, 0));
2998+ RR(VID_CONV_COEF(0, 1));
2999+ RR(VID_CONV_COEF(0, 2));
3000+ RR(VID_CONV_COEF(0, 3));
3001+ RR(VID_CONV_COEF(0, 4));
3002+
3003+ RR(VID_FIR_COEF_V(0, 0));
3004+ RR(VID_FIR_COEF_V(0, 1));
3005+ RR(VID_FIR_COEF_V(0, 2));
3006+ RR(VID_FIR_COEF_V(0, 3));
3007+ RR(VID_FIR_COEF_V(0, 4));
3008+ RR(VID_FIR_COEF_V(0, 5));
3009+ RR(VID_FIR_COEF_V(0, 6));
3010+ RR(VID_FIR_COEF_V(0, 7));
3011+
3012+ RR(VID_PRELOAD(0));
3013+
3014+ /* VID2 */
3015+ RR(VID_BA0(1));
3016+ RR(VID_BA1(1));
3017+ RR(VID_POSITION(1));
3018+ RR(VID_SIZE(1));
3019+ RR(VID_ATTRIBUTES(1));
3020+ RR(VID_FIFO_THRESHOLD(1));
3021+ RR(VID_ROW_INC(1));
3022+ RR(VID_PIXEL_INC(1));
3023+ RR(VID_FIR(1));
3024+ RR(VID_PICTURE_SIZE(1));
3025+ RR(VID_ACCU0(1));
3026+ RR(VID_ACCU1(1));
3027+
3028+ RR(VID_FIR_COEF_H(1, 0));
3029+ RR(VID_FIR_COEF_H(1, 1));
3030+ RR(VID_FIR_COEF_H(1, 2));
3031+ RR(VID_FIR_COEF_H(1, 3));
3032+ RR(VID_FIR_COEF_H(1, 4));
3033+ RR(VID_FIR_COEF_H(1, 5));
3034+ RR(VID_FIR_COEF_H(1, 6));
3035+ RR(VID_FIR_COEF_H(1, 7));
3036+
3037+ RR(VID_FIR_COEF_HV(1, 0));
3038+ RR(VID_FIR_COEF_HV(1, 1));
3039+ RR(VID_FIR_COEF_HV(1, 2));
3040+ RR(VID_FIR_COEF_HV(1, 3));
3041+ RR(VID_FIR_COEF_HV(1, 4));
3042+ RR(VID_FIR_COEF_HV(1, 5));
3043+ RR(VID_FIR_COEF_HV(1, 6));
3044+ RR(VID_FIR_COEF_HV(1, 7));
3045+
3046+ RR(VID_CONV_COEF(1, 0));
3047+ RR(VID_CONV_COEF(1, 1));
3048+ RR(VID_CONV_COEF(1, 2));
3049+ RR(VID_CONV_COEF(1, 3));
3050+ RR(VID_CONV_COEF(1, 4));
3051+
3052+ RR(VID_FIR_COEF_V(1, 0));
3053+ RR(VID_FIR_COEF_V(1, 1));
3054+ RR(VID_FIR_COEF_V(1, 2));
3055+ RR(VID_FIR_COEF_V(1, 3));
3056+ RR(VID_FIR_COEF_V(1, 4));
3057+ RR(VID_FIR_COEF_V(1, 5));
3058+ RR(VID_FIR_COEF_V(1, 6));
3059+ RR(VID_FIR_COEF_V(1, 7));
3060+
3061+ RR(VID_PRELOAD(1));
3062+
3063+ /* enable last, because LCD & DIGIT enable are here */
3064+ RR(CONTROL);
3065+}
3066+
3067+#undef SR
3068+#undef RR
3069+
3070+static inline void enable_clocks(bool enable)
3071+{
3072+ if (enable)
3073+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
3074+ else
3075+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
3076+}
3077+
3078+void dispc_go(enum omap_channel channel)
3079+{
3080+ int bit;
3081+ unsigned long tmo;
3082+
3083+ enable_clocks(1);
3084+
3085+ if (channel == OMAP_DSS_CHANNEL_LCD)
3086+ bit = 0; /* LCDENABLE */
3087+ else
3088+ bit = 1; /* DIGITALENABLE */
3089+
3090+ /* if the channel is not enabled, we don't need GO */
3091+ if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
3092+ goto end;
3093+
3094+ if (channel == OMAP_DSS_CHANNEL_LCD)
3095+ bit = 5; /* GOLCD */
3096+ else
3097+ bit = 6; /* GODIGIT */
3098+
3099+ tmo = jiffies + msecs_to_jiffies(200);
3100+ while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
3101+ if (time_after(jiffies, tmo)) {
3102+ DSSERR("timeout waiting GO flag\n");
3103+ goto end;
3104+ }
3105+ cpu_relax();
3106+ }
3107+
3108+ DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
3109+
3110+ REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
3111+end:
3112+ enable_clocks(0);
3113+}
3114+
3115+static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
3116+{
3117+ BUG_ON(plane == OMAP_DSS_GFX);
3118+
3119+ dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
3120+}
3121+
3122+static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
3123+{
3124+ BUG_ON(plane == OMAP_DSS_GFX);
3125+
3126+ dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
3127+}
3128+
3129+static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
3130+{
3131+ BUG_ON(plane == OMAP_DSS_GFX);
3132+
3133+ dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
3134+}
3135+
3136+static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
3137+ int vscaleup, int five_taps)
3138+{
3139+ /* Coefficients for horizontal up-sampling */
3140+ static const u32 coef_hup[8] = {
3141+ 0x00800000,
3142+ 0x0D7CF800,
3143+ 0x1E70F5FF,
3144+ 0x335FF5FE,
3145+ 0xF74949F7,
3146+ 0xF55F33FB,
3147+ 0xF5701EFE,
3148+ 0xF87C0DFF,
3149+ };
3150+
3151+ /* Coefficients for horizontal down-sampling */
3152+ static const u32 coef_hdown[8] = {
3153+ 0x24382400,
3154+ 0x28371FFE,
3155+ 0x2C361BFB,
3156+ 0x303516F9,
3157+ 0x11343311,
3158+ 0x1635300C,
3159+ 0x1B362C08,
3160+ 0x1F372804,
3161+ };
3162+
3163+ /* Coefficients for horizontal and vertical up-sampling */
3164+ static const u32 coef_hvup[2][8] = {
3165+ {
3166+ 0x00800000,
3167+ 0x037B02FF,
3168+ 0x0C6F05FE,
3169+ 0x205907FB,
3170+ 0x00404000,
3171+ 0x075920FE,
3172+ 0x056F0CFF,
3173+ 0x027B0300,
3174+ },
3175+ {
3176+ 0x00800000,
3177+ 0x0D7CF8FF,
3178+ 0x1E70F5FE,
3179+ 0x335FF5FB,
3180+ 0xF7404000,
3181+ 0xF55F33FE,
3182+ 0xF5701EFF,
3183+ 0xF87C0D00,
3184+ },
3185+ };
3186+
3187+ /* Coefficients for horizontal and vertical down-sampling */
3188+ static const u32 coef_hvdown[2][8] = {
3189+ {
3190+ 0x24382400,
3191+ 0x28391F04,
3192+ 0x2D381B08,
3193+ 0x3237170C,
3194+ 0x123737F7,
3195+ 0x173732F9,
3196+ 0x1B382DFB,
3197+ 0x1F3928FE,
3198+ },
3199+ {
3200+ 0x24382400,
3201+ 0x28371F04,
3202+ 0x2C361B08,
3203+ 0x3035160C,
3204+ 0x113433F7,
3205+ 0x163530F9,
3206+ 0x1B362CFB,
3207+ 0x1F3728FE,
3208+ },
3209+ };
3210+
3211+ /* Coefficients for vertical up-sampling */
3212+ static const u32 coef_vup[8] = {
3213+ 0x00000000,
3214+ 0x0000FF00,
3215+ 0x0000FEFF,
3216+ 0x0000FBFE,
3217+ 0x000000F7,
3218+ 0x0000FEFB,
3219+ 0x0000FFFE,
3220+ 0x000000FF,
3221+ };
3222+
3223+
3224+ /* Coefficients for vertical down-sampling */
3225+ static const u32 coef_vdown[8] = {
3226+ 0x00000000,
3227+ 0x000004FE,
3228+ 0x000008FB,
3229+ 0x00000CF9,
3230+ 0x0000F711,
3231+ 0x0000F90C,
3232+ 0x0000FB08,
3233+ 0x0000FE04,
3234+ };
3235+
3236+ const u32 *h_coef;
3237+ const u32 *hv_coef;
3238+ const u32 *hv_coef_mod;
3239+ const u32 *v_coef;
3240+ int i;
3241+
3242+ if (hscaleup)
3243+ h_coef = coef_hup;
3244+ else
3245+ h_coef = coef_hdown;
3246+
3247+ if (vscaleup) {
3248+ hv_coef = coef_hvup[five_taps];
3249+ v_coef = coef_vup;
3250+
3251+ if (hscaleup)
3252+ hv_coef_mod = NULL;
3253+ else
3254+ hv_coef_mod = coef_hvdown[five_taps];
3255+ } else {
3256+ hv_coef = coef_hvdown[five_taps];
3257+ v_coef = coef_vdown;
3258+
3259+ if (hscaleup)
3260+ hv_coef_mod = coef_hvup[five_taps];
3261+ else
3262+ hv_coef_mod = NULL;
3263+ }
3264+
3265+ for (i = 0; i < 8; i++) {
3266+ u32 h, hv;
3267+
3268+ h = h_coef[i];
3269+
3270+ hv = hv_coef[i];
3271+
3272+ if (hv_coef_mod) {
3273+ hv &= 0xffffff00;
3274+ hv |= (hv_coef_mod[i] & 0xff);
3275+ }
3276+
3277+ _dispc_write_firh_reg(plane, i, h);
3278+ _dispc_write_firhv_reg(plane, i, hv);
3279+ }
3280+
3281+ if (!five_taps)
3282+ return;
3283+
3284+ for (i = 0; i < 8; i++) {
3285+ u32 v;
3286+ v = v_coef[i];
3287+ _dispc_write_firv_reg(plane, i, v);
3288+ }
3289+}
3290+
3291+static void _dispc_setup_color_conv_coef(void)
3292+{
3293+ const struct color_conv_coef {
3294+ int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
3295+ int full_range;
3296+ } ctbl_bt601_5 = {
3297+ 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
3298+ };
3299+
3300+ const struct color_conv_coef *ct;
3301+
3302+#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
3303+
3304+ ct = &ctbl_bt601_5;
3305+
3306+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
3307+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
3308+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
3309+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
3310+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
3311+
3312+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
3313+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
3314+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
3315+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
3316+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
3317+
3318+#undef CVAL
3319+
3320+ REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
3321+ REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
3322+}
3323+
3324+
3325+static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
3326+{
3327+ const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
3328+ DISPC_VID_BA0(0),
3329+ DISPC_VID_BA0(1) };
3330+
3331+ dispc_write_reg(ba0_reg[plane], paddr);
3332+}
3333+
3334+static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
3335+{
3336+ const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
3337+ DISPC_VID_BA1(0),
3338+ DISPC_VID_BA1(1) };
3339+
3340+ dispc_write_reg(ba1_reg[plane], paddr);
3341+}
3342+
3343+static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
3344+{
3345+ const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
3346+ DISPC_VID_POSITION(0),
3347+ DISPC_VID_POSITION(1) };
3348+
3349+ u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
3350+ dispc_write_reg(pos_reg[plane], val);
3351+}
3352+
3353+static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
3354+{
3355+ const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
3356+ DISPC_VID_PICTURE_SIZE(0),
3357+ DISPC_VID_PICTURE_SIZE(1) };
3358+ u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
3359+ dispc_write_reg(siz_reg[plane], val);
3360+}
3361+
3362+static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
3363+{
3364+ u32 val;
3365+ const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
3366+ DISPC_VID_SIZE(1) };
3367+
3368+ BUG_ON(plane == OMAP_DSS_GFX);
3369+
3370+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
3371+ dispc_write_reg(vsi_reg[plane-1], val);
3372+}
3373+
3374+static void _dispc_set_pix_inc(enum omap_plane plane, u16 inc)
3375+{
3376+ const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
3377+ DISPC_VID_PIXEL_INC(0),
3378+ DISPC_VID_PIXEL_INC(1) };
3379+
3380+ dispc_write_reg(ri_reg[plane], inc);
3381+}
3382+
3383+static void _dispc_set_row_inc(enum omap_plane plane, u16 inc)
3384+{
3385+ const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
3386+ DISPC_VID_ROW_INC(0),
3387+ DISPC_VID_ROW_INC(1) };
3388+
3389+ dispc_write_reg(ri_reg[plane], inc);
3390+}
3391+
3392+static void _dispc_set_color_mode(enum omap_plane plane,
3393+ enum omap_color_mode color_mode)
3394+{
3395+ u32 m = 0;
3396+
3397+ switch (color_mode) {
3398+ case OMAP_DSS_COLOR_CLUT1:
3399+ m = 0x0; break;
3400+ case OMAP_DSS_COLOR_CLUT2:
3401+ m = 0x1; break;
3402+ case OMAP_DSS_COLOR_CLUT4:
3403+ m = 0x2; break;
3404+ case OMAP_DSS_COLOR_CLUT8:
3405+ m = 0x3; break;
3406+ case OMAP_DSS_COLOR_RGB12U:
3407+ m = 0x4; break;
3408+ case OMAP_DSS_COLOR_ARGB16:
3409+ m = 0x5; break;
3410+ case OMAP_DSS_COLOR_RGB16:
3411+ m = 0x6; break;
3412+ case OMAP_DSS_COLOR_RGB24U:
3413+ m = 0x8; break;
3414+ case OMAP_DSS_COLOR_RGB24P:
3415+ m = 0x9; break;
3416+ case OMAP_DSS_COLOR_YUV2:
3417+ m = 0xa; break;
3418+ case OMAP_DSS_COLOR_UYVY:
3419+ m = 0xb; break;
3420+ case OMAP_DSS_COLOR_ARGB32:
3421+ m = 0xc; break;
3422+ case OMAP_DSS_COLOR_RGBA32:
3423+ m = 0xd; break;
3424+ case OMAP_DSS_COLOR_RGBX32:
3425+ m = 0xe; break;
3426+ default:
3427+ BUG(); break;
3428+ }
3429+
3430+ REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
3431+}
3432+
3433+static void _dispc_set_channel_out(enum omap_plane plane,
3434+ enum omap_channel channel)
3435+{
3436+ int shift;
3437+ u32 val;
3438+
3439+ switch (plane) {
3440+ case OMAP_DSS_GFX:
3441+ shift = 8;
3442+ break;
3443+ case OMAP_DSS_VIDEO1:
3444+ case OMAP_DSS_VIDEO2:
3445+ shift = 16;
3446+ break;
3447+ default:
3448+ BUG();
3449+ return;
3450+ }
3451+
3452+ val = dispc_read_reg(dispc_reg_att[plane]);
3453+ val = FLD_MOD(val, channel, shift, shift);
3454+ dispc_write_reg(dispc_reg_att[plane], val);
3455+}
3456+
3457+void dispc_set_burst_size(enum omap_plane plane,
3458+ enum omap_burst_size burst_size)
3459+{
3460+ int shift;
3461+ u32 val;
3462+
3463+ enable_clocks(1);
3464+
3465+ switch (plane) {
3466+ case OMAP_DSS_GFX:
3467+ shift = 6;
3468+ break;
3469+ case OMAP_DSS_VIDEO1:
3470+ case OMAP_DSS_VIDEO2:
3471+ shift = 14;
3472+ break;
3473+ default:
3474+ BUG();
3475+ return;
3476+ }
3477+
3478+ val = dispc_read_reg(dispc_reg_att[plane]);
3479+ val = FLD_MOD(val, burst_size, shift+1, shift);
3480+ dispc_write_reg(dispc_reg_att[plane], val);
3481+
3482+ enable_clocks(0);
3483+}
3484+
3485+static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
3486+{
3487+ u32 val;
3488+
3489+ BUG_ON(plane == OMAP_DSS_GFX);
3490+
3491+ val = dispc_read_reg(dispc_reg_att[plane]);
3492+ val = FLD_MOD(val, enable, 9, 9);
3493+ dispc_write_reg(dispc_reg_att[plane], val);
3494+}
3495+
3496+void dispc_set_lcd_size(u16 width, u16 height)
3497+{
3498+ u32 val;
3499+ BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
3500+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
3501+ enable_clocks(1);
3502+ dispc_write_reg(DISPC_SIZE_LCD, val);
3503+ enable_clocks(0);
3504+}
3505+
3506+void dispc_set_digit_size(u16 width, u16 height)
3507+{
3508+ u32 val;
3509+ BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
3510+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
3511+ enable_clocks(1);
3512+ dispc_write_reg(DISPC_SIZE_DIG, val);
3513+ enable_clocks(0);
3514+}
3515+
3516+u32 dispc_get_plane_fifo_size(enum omap_plane plane)
3517+{
3518+ const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
3519+ DISPC_VID_FIFO_SIZE_STATUS(0),
3520+ DISPC_VID_FIFO_SIZE_STATUS(1) };
3521+ u32 size;
3522+
3523+ enable_clocks(1);
3524+
3525+ if (cpu_is_omap24xx())
3526+ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
3527+ else if (cpu_is_omap34xx())
3528+ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
3529+ else
3530+ BUG();
3531+
3532+ if (cpu_is_omap34xx()) {
3533+ /* FIFOMERGE */
3534+ if (REG_GET(DISPC_CONFIG, 14, 14))
3535+ size *= 3;
3536+ }
3537+
3538+ enable_clocks(0);
3539+
3540+ return size;
3541+}
3542+
3543+void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
3544+{
3545+ const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
3546+ DISPC_VID_FIFO_THRESHOLD(0),
3547+ DISPC_VID_FIFO_THRESHOLD(1) };
3548+ u32 size;
3549+
3550+ enable_clocks(1);
3551+
3552+ size = dispc_get_plane_fifo_size(plane);
3553+
3554+ BUG_ON(low > size || high > size);
3555+
3556+ DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
3557+ plane, size,
3558+ REG_GET(ftrs_reg[plane], 11, 0),
3559+ REG_GET(ftrs_reg[plane], 27, 16),
3560+ low, high);
3561+
3562+ if (cpu_is_omap24xx())
3563+ dispc_write_reg(ftrs_reg[plane],
3564+ FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
3565+ else
3566+ dispc_write_reg(ftrs_reg[plane],
3567+ FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
3568+
3569+ enable_clocks(0);
3570+}
3571+
3572+void dispc_enable_fifomerge(bool enable)
3573+{
3574+ enable_clocks(1);
3575+
3576+ DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
3577+ REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
3578+
3579+ enable_clocks(0);
3580+}
3581+
3582+static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
3583+{
3584+ u32 val;
3585+ const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
3586+ DISPC_VID_FIR(1) };
3587+
3588+ BUG_ON(plane == OMAP_DSS_GFX);
3589+
3590+ val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
3591+ dispc_write_reg(fir_reg[plane-1], val);
3592+}
3593+
3594+static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
3595+{
3596+ u32 val;
3597+ const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
3598+ DISPC_VID_ACCU0(1) };
3599+
3600+ BUG_ON(plane == OMAP_DSS_GFX);
3601+
3602+ val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
3603+ dispc_write_reg(ac0_reg[plane-1], val);
3604+}
3605+
3606+static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
3607+{
3608+ u32 val;
3609+ const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
3610+ DISPC_VID_ACCU1(1) };
3611+
3612+ BUG_ON(plane == OMAP_DSS_GFX);
3613+
3614+ val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
3615+ dispc_write_reg(ac1_reg[plane-1], val);
3616+}
3617+
3618+
3619+static void _dispc_set_scaling(enum omap_plane plane,
3620+ u16 orig_width, u16 orig_height,
3621+ u16 out_width, u16 out_height,
3622+ bool ilace)
3623+{
3624+ int fir_hinc;
3625+ int fir_vinc;
3626+ int hscaleup, vscaleup, five_taps;
3627+ int fieldmode = 0;
3628+ int accu0 = 0;
3629+ int accu1 = 0;
3630+ u32 l;
3631+
3632+ BUG_ON(plane == OMAP_DSS_GFX);
3633+
3634+ hscaleup = orig_width <= out_width;
3635+ vscaleup = orig_height <= out_height;
3636+ five_taps = orig_height > out_height * 2;
3637+
3638+ _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
3639+
3640+ if (!orig_width || orig_width == out_width)
3641+ fir_hinc = 0;
3642+ else
3643+ fir_hinc = 1024 * orig_width / out_width;
3644+
3645+ if (!orig_height || orig_height == out_height)
3646+ fir_vinc = 0;
3647+ else
3648+ fir_vinc = 1024 * orig_height / out_height;
3649+
3650+ _dispc_set_fir(plane, fir_hinc, fir_vinc);
3651+
3652+ l = dispc_read_reg(dispc_reg_att[plane]);
3653+ l &= ~((0x0f << 5) | (0x3 << 21));
3654+
3655+ l |= fir_hinc ? (1 << 5) : 0;
3656+ l |= fir_vinc ? (1 << 6) : 0;
3657+
3658+ l |= hscaleup ? 0 : (1 << 7);
3659+ l |= vscaleup ? 0 : (1 << 8);
3660+
3661+ l |= five_taps ? (1 << 21) : 0;
3662+ l |= five_taps ? (1 << 22) : 0;
3663+
3664+ dispc_write_reg(dispc_reg_att[plane], l);
3665+
3666+ if (ilace) {
3667+ if (fieldmode) {
3668+ accu0 = fir_vinc / 2;
3669+ accu1 = 0;
3670+ } else {
3671+ accu0 = 0;
3672+ accu1 = fir_vinc / 2;
3673+ if (accu1 >= 1024/2) {
3674+ accu0 = 1024/2;
3675+ accu1 -= accu0;
3676+ }
3677+ }
3678+ }
3679+
3680+ _dispc_set_vid_accu0(plane, 0, accu0);
3681+ _dispc_set_vid_accu1(plane, 0, accu1);
3682+}
3683+
3684+static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
3685+ bool mirroring, enum omap_color_mode color_mode)
3686+{
3687+ if (color_mode == OMAP_DSS_COLOR_YUV2 ||
3688+ color_mode == OMAP_DSS_COLOR_UYVY) {
3689+ int vidrot = 0;
3690+
3691+ if (mirroring) {
3692+ switch (rotation) {
3693+ case 0: vidrot = 2; break;
3694+ case 1: vidrot = 3; break;
3695+ case 2: vidrot = 0; break;
3696+ case 3: vidrot = 1; break;
3697+ }
3698+ } else {
3699+ switch (rotation) {
3700+ case 0: vidrot = 0; break;
3701+ case 1: vidrot = 1; break;
3702+ case 2: vidrot = 2; break;
3703+ case 3: vidrot = 1; break;
3704+ }
3705+ }
3706+
3707+ REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
3708+
3709+ if (rotation == 1 || rotation == 3)
3710+ REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
3711+ else
3712+ REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
3713+ } else {
3714+ REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
3715+ REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
3716+ }
3717+}
3718+
3719+static int pixinc(int pixels, u8 ps)
3720+{
3721+ if (pixels == 1)
3722+ return 1;
3723+ else if (pixels > 1)
3724+ return 1 + (pixels - 1) * ps;
3725+ else if (pixels < 0)
3726+ return 1 - (-pixels + 1) * ps;
3727+ else
3728+ BUG();
3729+}
3730+
3731+static void calc_rotation_offset(u8 rotation, bool mirror,
3732+ u16 screen_width,
3733+ u16 width, u16 height,
3734+ enum omap_color_mode color_mode, bool fieldmode,
3735+ unsigned *offset0, unsigned *offset1,
3736+ u16 *row_inc, u16 *pix_inc)
3737+{
3738+ u8 ps;
3739+ u16 fbw, fbh;
3740+
3741+ switch (color_mode) {
3742+ case OMAP_DSS_COLOR_RGB16:
3743+ case OMAP_DSS_COLOR_ARGB16:
3744+ ps = 2;
3745+ break;
3746+
3747+ case OMAP_DSS_COLOR_RGB24P:
3748+ ps = 3;
3749+ break;
3750+
3751+ case OMAP_DSS_COLOR_RGB24U:
3752+ case OMAP_DSS_COLOR_ARGB32:
3753+ case OMAP_DSS_COLOR_RGBA32:
3754+ case OMAP_DSS_COLOR_RGBX32:
3755+ ps = 4;
3756+ break;
3757+
3758+ case OMAP_DSS_COLOR_YUV2:
3759+ case OMAP_DSS_COLOR_UYVY:
3760+ ps = 2;
3761+ break;
3762+ default:
3763+ BUG();
3764+ return;
3765+ }
3766+
3767+ DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
3768+ width, height);
3769+
3770+ /* width & height are overlay sizes, convert to fb sizes */
3771+
3772+ if (rotation == 0 || rotation == 2) {
3773+ fbw = width;
3774+ fbh = height;
3775+ } else {
3776+ fbw = height;
3777+ fbh = width;
3778+ }
3779+
3780+ switch (rotation + mirror * 4) {
3781+ case 0:
3782+ *offset0 = 0;
3783+ if (fieldmode)
3784+ *offset1 = screen_width * ps;
3785+ else
3786+ *offset1 = 0;
3787+ *row_inc = pixinc(1 + (screen_width - fbw) +
3788+ (fieldmode ? screen_width : 0),
3789+ ps);
3790+ *pix_inc = pixinc(1, ps);
3791+ break;
3792+ case 1:
3793+ *offset0 = screen_width * (fbh - 1) * ps;
3794+ if (fieldmode)
3795+ *offset1 = *offset0 + ps;
3796+ else
3797+ *offset1 = *offset0;
3798+ *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
3799+ (fieldmode ? 1 : 0), ps);
3800+ *pix_inc = pixinc(-screen_width, ps);
3801+ break;
3802+ case 2:
3803+ *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
3804+ if (fieldmode)
3805+ *offset1 = *offset0 - screen_width * ps;
3806+ else
3807+ *offset1 = *offset0;
3808+ *row_inc = pixinc(-1 -
3809+ (screen_width - fbw) -
3810+ (fieldmode ? screen_width : 0),
3811+ ps);
3812+ *pix_inc = pixinc(-1, ps);
3813+ break;
3814+ case 3:
3815+ *offset0 = (fbw - 1) * ps;
3816+ if (fieldmode)
3817+ *offset1 = *offset0 - ps;
3818+ else
3819+ *offset1 = *offset0;
3820+ *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
3821+ (fieldmode ? 1 : 0), ps);
3822+ *pix_inc = pixinc(screen_width, ps);
3823+ break;
3824+
3825+ /* mirroring */
3826+ case 0 + 4:
3827+ *offset0 = (fbw - 1) * ps;
3828+ if (fieldmode)
3829+ *offset1 = *offset0 + screen_width * ps;
3830+ else
3831+ *offset1 = *offset0;
3832+ *row_inc = pixinc(screen_width * 2 - 1 +
3833+ (fieldmode ? screen_width : 0),
3834+ ps);
3835+ *pix_inc = pixinc(-1, ps);
3836+ break;
3837+
3838+ case 1 + 4:
3839+ *offset0 = 0;
3840+ if (fieldmode)
3841+ *offset1 = *offset0 + screen_width * ps;
3842+ else
3843+ *offset1 = *offset0;
3844+ *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
3845+ (fieldmode ? 1 : 0),
3846+ ps);
3847+ *pix_inc = pixinc(screen_width, ps);
3848+ break;
3849+
3850+ case 2 + 4:
3851+ *offset0 = screen_width * (fbh - 1) * ps;
3852+ if (fieldmode)
3853+ *offset1 = *offset0 + screen_width * ps;
3854+ else
3855+ *offset1 = *offset0;
3856+ *row_inc = pixinc(1 - screen_width * 2 -
3857+ (fieldmode ? screen_width : 0),
3858+ ps);
3859+ *pix_inc = pixinc(1, ps);
3860+ break;
3861+
3862+ case 3 + 4:
3863+ *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
3864+ if (fieldmode)
3865+ *offset1 = *offset0 + screen_width * ps;
3866+ else
3867+ *offset1 = *offset0;
3868+ *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
3869+ (fieldmode ? 1 : 0),
3870+ ps);
3871+ *pix_inc = pixinc(-screen_width, ps);
3872+ break;
3873+
3874+ default:
3875+ BUG();
3876+ }
3877+}
3878+
3879+static int _dispc_setup_plane(enum omap_plane plane,
3880+ enum omap_channel channel_out,
3881+ u32 paddr, u16 screen_width,
3882+ u16 pos_x, u16 pos_y,
3883+ u16 width, u16 height,
3884+ u16 out_width, u16 out_height,
3885+ enum omap_color_mode color_mode,
3886+ bool ilace,
3887+ u8 rotation, int mirror)
3888+{
3889+ const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
3890+ bool five_taps = height > out_height * 2;
3891+ bool fieldmode = 0;
3892+ int cconv = 0;
3893+ unsigned offset0, offset1;
3894+ u16 row_inc;
3895+ u16 pix_inc;
3896+
3897+ if (plane == OMAP_DSS_GFX) {
3898+ if (width != out_width || height != out_height)
3899+ return -EINVAL;
3900+
3901+ switch (color_mode) {
3902+ case OMAP_DSS_COLOR_ARGB16:
3903+ case OMAP_DSS_COLOR_RGB16:
3904+ case OMAP_DSS_COLOR_RGB24P:
3905+ case OMAP_DSS_COLOR_RGB24U:
3906+ case OMAP_DSS_COLOR_ARGB32:
3907+ case OMAP_DSS_COLOR_RGBA32:
3908+ case OMAP_DSS_COLOR_RGBX32:
3909+ break;
3910+
3911+ default:
3912+ return -EINVAL;
3913+ }
3914+ } else {
3915+ /* video plane */
3916+ if (width > (2048 >> five_taps))
3917+ return -EINVAL;
3918+
3919+ if (out_width < width / maxdownscale ||
3920+ out_width > width * 8)
3921+ return -EINVAL;
3922+
3923+ if (out_height < height / maxdownscale ||
3924+ out_height > height * 8)
3925+ return -EINVAL;
3926+
3927+ switch (color_mode) {
3928+ case OMAP_DSS_COLOR_RGB16:
3929+ case OMAP_DSS_COLOR_RGB24P:
3930+ case OMAP_DSS_COLOR_RGB24U:
3931+ case OMAP_DSS_COLOR_RGBX32:
3932+ break;
3933+
3934+ case OMAP_DSS_COLOR_ARGB16:
3935+ case OMAP_DSS_COLOR_ARGB32:
3936+ case OMAP_DSS_COLOR_RGBA32:
3937+ if (plane == OMAP_DSS_VIDEO1)
3938+ return -EINVAL;
3939+ break;
3940+
3941+ case OMAP_DSS_COLOR_YUV2:
3942+ case OMAP_DSS_COLOR_UYVY:
3943+ cconv = 1;
3944+ break;
3945+
3946+ default:
3947+ return -EINVAL;
3948+ }
3949+ }
3950+
3951+ if (ilace && height >= out_height)
3952+ fieldmode = 1;
3953+
3954+ calc_rotation_offset(rotation, mirror,
3955+ screen_width, width, height, color_mode,
3956+ fieldmode,
3957+ &offset0, &offset1, &row_inc, &pix_inc);
3958+
3959+ DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
3960+ offset0, offset1, row_inc, pix_inc);
3961+
3962+ if (ilace) {
3963+ if (fieldmode)
3964+ height /= 2;
3965+ pos_y /= 2;
3966+ out_height /= 2;
3967+
3968+ DSSDBG("adjusting for ilace: height %d, pos_y %d, "
3969+ "out_height %d\n",
3970+ height, pos_y, out_height);
3971+ }
3972+
3973+ _dispc_set_channel_out(plane, channel_out);
3974+ _dispc_set_color_mode(plane, color_mode);
3975+
3976+ _dispc_set_plane_ba0(plane, paddr + offset0);
3977+ _dispc_set_plane_ba1(plane, paddr + offset1);
3978+
3979+ _dispc_set_row_inc(plane, row_inc);
3980+ _dispc_set_pix_inc(plane, pix_inc);
3981+
3982+ DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
3983+ out_width, out_height);
3984+
3985+ _dispc_set_plane_pos(plane, pos_x, pos_y);
3986+
3987+ _dispc_set_pic_size(plane, width, height);
3988+
3989+ if (plane != OMAP_DSS_GFX) {
3990+ _dispc_set_scaling(plane, width, height,
3991+ out_width, out_height,
3992+ ilace);
3993+ _dispc_set_vid_size(plane, out_width, out_height);
3994+ _dispc_set_vid_color_conv(plane, cconv);
3995+ }
3996+
3997+ _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
3998+
3999+ return 0;
4000+}
4001+
4002+static void _dispc_enable_plane(enum omap_plane plane, bool enable)
4003+{
4004+ REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
4005+}
4006+
4007+static void dispc_disable_isr(void *data, u32 mask)
4008+{
4009+ struct completion *compl = data;
4010+ complete(compl);
4011+}
4012+
4013+static void _enable_lcd_out(bool enable)
4014+{
4015+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
4016+}
4017+
4018+void dispc_enable_lcd_out(bool enable)
4019+{
4020+ struct completion frame_done_completion;
4021+ bool is_on;
4022+ int r;
4023+
4024+ enable_clocks(1);
4025+
4026+ /* When we disable LCD output, we need to wait until frame is done.
4027+ * Otherwise the DSS is still working, and turning off the clocks
4028+ * prevents DSS from going to OFF mode */
4029+ is_on = REG_GET(DISPC_CONTROL, 0, 0);
4030+
4031+ if (!enable && is_on) {
4032+ init_completion(&frame_done_completion);
4033+
4034+ r = omap_dispc_register_isr(dispc_disable_isr,
4035+ &frame_done_completion,
4036+ DISPC_IRQ_FRAMEDONE);
4037+
4038+ if (r)
4039+ DSSERR("failed to register FRAMEDONE isr\n");
4040+ }
4041+
4042+ _enable_lcd_out(enable);
4043+
4044+ if (!enable && is_on) {
4045+ if (!wait_for_completion_timeout(&frame_done_completion,
4046+ msecs_to_jiffies(100)))
4047+ DSSERR("timeout waiting for FRAME DONE\n");
4048+
4049+ r = omap_dispc_unregister_isr(dispc_disable_isr,
4050+ &frame_done_completion,
4051+ DISPC_IRQ_FRAMEDONE);
4052+
4053+ if (r)
4054+ DSSERR("failed to unregister FRAMEDONE isr\n");
4055+ }
4056+
4057+ enable_clocks(0);
4058+}
4059+
4060+static void _enable_digit_out(bool enable)
4061+{
4062+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
4063+}
4064+
4065+void dispc_enable_digit_out(bool enable)
4066+{
4067+ struct completion frame_done_completion;
4068+ int r;
4069+
4070+ enable_clocks(1);
4071+
4072+ if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
4073+ enable_clocks(0);
4074+ return;
4075+ }
4076+
4077+ if (enable) {
4078+ /* When we enable digit output, we'll get an extra digit
4079+ * sync lost interrupt, that we need to ignore */
4080+ dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
4081+ omap_dispc_set_irqs();
4082+ }
4083+
4084+ /* When we disable digit output, we need to wait until fields are done.
4085+ * Otherwise the DSS is still working, and turning off the clocks
4086+ * prevents DSS from going to OFF mode. And when enabling, we need to
4087+ * wait for the extra sync losts */
4088+ init_completion(&frame_done_completion);
4089+
4090+ r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
4091+ DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
4092+ if (r)
4093+ DSSERR("failed to register EVSYNC isr\n");
4094+
4095+ _enable_digit_out(enable);
4096+
4097+ /* XXX I understand from TRM that we should only wait for the
4098+ * current field to complete. But it seems we have to wait
4099+ * for both fields */
4100+ if (!wait_for_completion_timeout(&frame_done_completion,
4101+ msecs_to_jiffies(100)))
4102+ DSSERR("timeout waiting for EVSYNC\n");
4103+
4104+ if (!wait_for_completion_timeout(&frame_done_completion,
4105+ msecs_to_jiffies(100)))
4106+ DSSERR("timeout waiting for EVSYNC\n");
4107+
4108+ r = omap_dispc_unregister_isr(dispc_disable_isr,
4109+ &frame_done_completion,
4110+ DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
4111+ if (r)
4112+ DSSERR("failed to unregister EVSYNC isr\n");
4113+
4114+ if (enable) {
4115+ dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
4116+ dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
4117+ omap_dispc_set_irqs();
4118+ }
4119+
4120+ enable_clocks(0);
4121+}
4122+
4123+void dispc_lcd_enable_signal_polarity(bool act_high)
4124+{
4125+ enable_clocks(1);
4126+ REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
4127+ enable_clocks(0);
4128+}
4129+
4130+void dispc_lcd_enable_signal(bool enable)
4131+{
4132+ enable_clocks(1);
4133+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
4134+ enable_clocks(0);
4135+}
4136+
4137+void dispc_pck_free_enable(bool enable)
4138+{
4139+ enable_clocks(1);
4140+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
4141+ enable_clocks(0);
4142+}
4143+
4144+void dispc_enable_fifohandcheck(bool enable)
4145+{
4146+ enable_clocks(1);
4147+ REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
4148+ enable_clocks(0);
4149+}
4150+
4151+
4152+void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
4153+{
4154+ int mode;
4155+
4156+ switch (type) {
4157+ case OMAP_DSS_LCD_DISPLAY_STN:
4158+ mode = 0;
4159+ break;
4160+
4161+ case OMAP_DSS_LCD_DISPLAY_TFT:
4162+ mode = 1;
4163+ break;
4164+
4165+ default:
4166+ BUG();
4167+ return;
4168+ }
4169+
4170+ enable_clocks(1);
4171+ REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
4172+ enable_clocks(0);
4173+}
4174+
4175+void dispc_set_loadmode(enum omap_dss_load_mode mode)
4176+{
4177+ enable_clocks(1);
4178+ REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
4179+ enable_clocks(0);
4180+}
4181+
4182+
4183+void dispc_set_default_color(enum omap_channel channel, u32 color)
4184+{
4185+ const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
4186+ DISPC_DEFAULT_COLOR1 };
4187+
4188+ enable_clocks(1);
4189+ dispc_write_reg(def_reg[channel], color);
4190+ enable_clocks(0);
4191+}
4192+
4193+u32 dispc_get_default_color(enum omap_channel channel)
4194+{
4195+ const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
4196+ DISPC_DEFAULT_COLOR1 };
4197+ u32 l;
4198+
4199+ BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
4200+ channel != OMAP_DSS_CHANNEL_LCD);
4201+
4202+ enable_clocks(1);
4203+ l = dispc_read_reg(def_reg[channel]);
4204+ enable_clocks(0);
4205+
4206+ return l;
4207+}
4208+
4209+void dispc_set_trans_key(enum omap_channel ch,
4210+ enum omap_dss_color_key_type type,
4211+ u32 trans_key)
4212+{
4213+ const struct dispc_reg tr_reg[] = {
4214+ DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
4215+
4216+ enable_clocks(1);
4217+ if (ch == OMAP_DSS_CHANNEL_LCD)
4218+ REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
4219+ else /* OMAP_DSS_CHANNEL_DIGIT */
4220+ REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
4221+
4222+ dispc_write_reg(tr_reg[ch], trans_key);
4223+ enable_clocks(0);
4224+}
4225+
4226+void dispc_get_trans_key(enum omap_channel ch,
4227+ enum omap_dss_color_key_type *type,
4228+ u32 *trans_key)
4229+{
4230+ const struct dispc_reg tr_reg[] = {
4231+ DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
4232+
4233+ enable_clocks(1);
4234+ if (type) {
4235+ if (ch == OMAP_DSS_CHANNEL_LCD)
4236+ *type = REG_GET(DISPC_CONFIG, 11, 11) >> 11;
4237+ else if (ch == OMAP_DSS_CHANNEL_DIGIT)
4238+ *type = REG_GET(DISPC_CONFIG, 13, 13) >> 13;
4239+ else
4240+ BUG();
4241+ }
4242+
4243+ if (trans_key)
4244+ *trans_key = dispc_read_reg(tr_reg[ch]);
4245+ enable_clocks(0);
4246+}
4247+
4248+void dispc_enable_trans_key(enum omap_channel ch, bool enable)
4249+{
4250+ enable_clocks(1);
4251+ if (ch == OMAP_DSS_CHANNEL_LCD)
4252+ REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
4253+ else /* OMAP_DSS_CHANNEL_DIGIT */
4254+ REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
4255+ enable_clocks(0);
4256+}
4257+
4258+bool dispc_trans_key_enabled(enum omap_channel ch)
4259+{
4260+ bool enabled;
4261+
4262+ enable_clocks(1);
4263+ if (ch == OMAP_DSS_CHANNEL_LCD)
4264+ enabled = REG_GET(DISPC_CONFIG, 10, 10);
4265+ else if (ch == OMAP_DSS_CHANNEL_DIGIT)
4266+ enabled = REG_GET(DISPC_CONFIG, 12, 12);
4267+ else BUG();
4268+ enable_clocks(0);
4269+
4270+ return enabled;
4271+}
4272+
4273+
4274+void dispc_set_tft_data_lines(u8 data_lines)
4275+{
4276+ int code;
4277+
4278+ switch (data_lines) {
4279+ case 12:
4280+ code = 0;
4281+ break;
4282+ case 16:
4283+ code = 1;
4284+ break;
4285+ case 18:
4286+ code = 2;
4287+ break;
4288+ case 24:
4289+ code = 3;
4290+ break;
4291+ default:
4292+ BUG();
4293+ return;
4294+ }
4295+
4296+ enable_clocks(1);
4297+ REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
4298+ enable_clocks(0);
4299+}
4300+
4301+void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
4302+{
4303+ u32 l;
4304+ int stallmode;
4305+ int gpout0 = 1;
4306+ int gpout1;
4307+
4308+ switch (mode) {
4309+ case OMAP_DSS_PARALLELMODE_BYPASS:
4310+ stallmode = 0;
4311+ gpout1 = 1;
4312+ break;
4313+
4314+ case OMAP_DSS_PARALLELMODE_RFBI:
4315+ stallmode = 1;
4316+ gpout1 = 0;
4317+ break;
4318+
4319+ case OMAP_DSS_PARALLELMODE_DSI:
4320+ stallmode = 1;
4321+ gpout1 = 1;
4322+ break;
4323+
4324+ default:
4325+ BUG();
4326+ return;
4327+ }
4328+
4329+ enable_clocks(1);
4330+
4331+ l = dispc_read_reg(DISPC_CONTROL);
4332+
4333+ l = FLD_MOD(l, stallmode, 11, 11);
4334+ l = FLD_MOD(l, gpout0, 15, 15);
4335+ l = FLD_MOD(l, gpout1, 16, 16);
4336+
4337+ dispc_write_reg(DISPC_CONTROL, l);
4338+
4339+ enable_clocks(0);
4340+}
4341+
4342+static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
4343+ int vsw, int vfp, int vbp)
4344+{
4345+ u32 timing_h, timing_v;
4346+
4347+ if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
4348+ BUG_ON(hsw < 1 || hsw > 64);
4349+ BUG_ON(hfp < 1 || hfp > 256);
4350+ BUG_ON(hbp < 1 || hbp > 256);
4351+
4352+ BUG_ON(vsw < 1 || vsw > 64);
4353+ BUG_ON(vfp < 0 || vfp > 255);
4354+ BUG_ON(vbp < 0 || vbp > 255);
4355+
4356+ timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
4357+ FLD_VAL(hbp-1, 27, 20);
4358+
4359+ timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
4360+ FLD_VAL(vbp, 27, 20);
4361+ } else {
4362+ BUG_ON(hsw < 1 || hsw > 256);
4363+ BUG_ON(hfp < 1 || hfp > 4096);
4364+ BUG_ON(hbp < 1 || hbp > 4096);
4365+
4366+ BUG_ON(vsw < 1 || vsw > 256);
4367+ BUG_ON(vfp < 0 || vfp > 4095);
4368+ BUG_ON(vbp < 0 || vbp > 4095);
4369+
4370+ timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
4371+ FLD_VAL(hbp-1, 31, 20);
4372+
4373+ timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
4374+ FLD_VAL(vbp, 31, 20);
4375+ }
4376+
4377+ enable_clocks(1);
4378+ dispc_write_reg(DISPC_TIMING_H, timing_h);
4379+ dispc_write_reg(DISPC_TIMING_V, timing_v);
4380+ enable_clocks(0);
4381+}
4382+
4383+/* change name to mode? */
4384+void dispc_set_lcd_timings(struct omap_video_timings *timings)
4385+{
4386+ unsigned xtot, ytot;
4387+ unsigned long ht, vt;
4388+
4389+ _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
4390+ timings->vsw, timings->vfp, timings->vbp);
4391+
4392+ dispc_set_lcd_size(timings->x_res, timings->y_res);
4393+
4394+ xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
4395+ ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
4396+
4397+ ht = (timings->pixel_clock * 1000) / xtot;
4398+ vt = (timings->pixel_clock * 1000) / xtot / ytot;
4399+
4400+ DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
4401+ DSSDBG("pck %u\n", timings->pixel_clock);
4402+ DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
4403+ timings->hsw, timings->hfp, timings->hbp,
4404+ timings->vsw, timings->vfp, timings->vbp);
4405+
4406+ DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
4407+}
4408+
4409+void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
4410+{
4411+ BUG_ON(lck_div < 1);
4412+ BUG_ON(pck_div < 2);
4413+
4414+ enable_clocks(1);
4415+ dispc_write_reg(DISPC_DIVISOR,
4416+ FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
4417+ enable_clocks(0);
4418+}
4419+
4420+static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
4421+{
4422+ u32 l;
4423+ l = dispc_read_reg(DISPC_DIVISOR);
4424+ *lck_div = FLD_GET(l, 23, 16);
4425+ *pck_div = FLD_GET(l, 7, 0);
4426+}
4427+
4428+unsigned long dispc_fclk_rate(void)
4429+{
4430+ unsigned long r = 0;
4431+
4432+ if (dss_get_dispc_clk_source() == 0)
4433+ r = dss_clk_get_rate(DSS_CLK_FCK1);
4434+ else
4435+#ifdef CONFIG_OMAP2_DSS_DSI
4436+ r = dsi_get_dsi1_pll_rate();
4437+#else
4438+ BUG();
4439+#endif
4440+ return r;
4441+}
4442+
4443+unsigned long dispc_pclk_rate(void)
4444+{
4445+ int lcd, pcd;
4446+ unsigned long r;
4447+ u32 l;
4448+
4449+ l = dispc_read_reg(DISPC_DIVISOR);
4450+
4451+ lcd = FLD_GET(l, 23, 16);
4452+ pcd = FLD_GET(l, 7, 0);
4453+
4454+ r = dispc_fclk_rate();
4455+
4456+ return r / lcd / pcd;
4457+}
4458+
4459+void dispc_dump_clocks(struct seq_file *s)
4460+{
4461+ int lcd, pcd;
4462+
4463+ enable_clocks(1);
4464+
4465+ dispc_get_lcd_divisor(&lcd, &pcd);
4466+
4467+ seq_printf(s, "- dispc -\n");
4468+
4469+ seq_printf(s, "dispc fclk source = %s\n",
4470+ dss_get_dispc_clk_source() == 0 ?
4471+ "dss1_alwon_fclk" : "dsi1_pll_fclk");
4472+
4473+ seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
4474+ dispc_fclk_rate(),
4475+ lcd, pcd,
4476+ dispc_pclk_rate());
4477+
4478+ enable_clocks(0);
4479+}
4480+
4481+void dispc_dump_regs(struct seq_file *s)
4482+{
4483+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
4484+
4485+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
4486+
4487+ DUMPREG(DISPC_REVISION);
4488+ DUMPREG(DISPC_SYSCONFIG);
4489+ DUMPREG(DISPC_SYSSTATUS);
4490+ DUMPREG(DISPC_IRQSTATUS);
4491+ DUMPREG(DISPC_IRQENABLE);
4492+ DUMPREG(DISPC_CONTROL);
4493+ DUMPREG(DISPC_CONFIG);
4494+ DUMPREG(DISPC_CAPABLE);
4495+ DUMPREG(DISPC_DEFAULT_COLOR0);
4496+ DUMPREG(DISPC_DEFAULT_COLOR1);
4497+ DUMPREG(DISPC_TRANS_COLOR0);
4498+ DUMPREG(DISPC_TRANS_COLOR1);
4499+ DUMPREG(DISPC_LINE_STATUS);
4500+ DUMPREG(DISPC_LINE_NUMBER);
4501+ DUMPREG(DISPC_TIMING_H);
4502+ DUMPREG(DISPC_TIMING_V);
4503+ DUMPREG(DISPC_POL_FREQ);
4504+ DUMPREG(DISPC_DIVISOR);
4505+ DUMPREG(DISPC_GLOBAL_ALPHA);
4506+ DUMPREG(DISPC_SIZE_DIG);
4507+ DUMPREG(DISPC_SIZE_LCD);
4508+
4509+ DUMPREG(DISPC_GFX_BA0);
4510+ DUMPREG(DISPC_GFX_BA1);
4511+ DUMPREG(DISPC_GFX_POSITION);
4512+ DUMPREG(DISPC_GFX_SIZE);
4513+ DUMPREG(DISPC_GFX_ATTRIBUTES);
4514+ DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
4515+ DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
4516+ DUMPREG(DISPC_GFX_ROW_INC);
4517+ DUMPREG(DISPC_GFX_PIXEL_INC);
4518+ DUMPREG(DISPC_GFX_WINDOW_SKIP);
4519+ DUMPREG(DISPC_GFX_TABLE_BA);
4520+
4521+ DUMPREG(DISPC_DATA_CYCLE1);
4522+ DUMPREG(DISPC_DATA_CYCLE2);
4523+ DUMPREG(DISPC_DATA_CYCLE3);
4524+
4525+ DUMPREG(DISPC_CPR_COEF_R);
4526+ DUMPREG(DISPC_CPR_COEF_G);
4527+ DUMPREG(DISPC_CPR_COEF_B);
4528+
4529+ DUMPREG(DISPC_GFX_PRELOAD);
4530+
4531+ DUMPREG(DISPC_VID_BA0(0));
4532+ DUMPREG(DISPC_VID_BA1(0));
4533+ DUMPREG(DISPC_VID_POSITION(0));
4534+ DUMPREG(DISPC_VID_SIZE(0));
4535+ DUMPREG(DISPC_VID_ATTRIBUTES(0));
4536+ DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
4537+ DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
4538+ DUMPREG(DISPC_VID_ROW_INC(0));
4539+ DUMPREG(DISPC_VID_PIXEL_INC(0));
4540+ DUMPREG(DISPC_VID_FIR(0));
4541+ DUMPREG(DISPC_VID_PICTURE_SIZE(0));
4542+ DUMPREG(DISPC_VID_ACCU0(0));
4543+ DUMPREG(DISPC_VID_ACCU1(0));
4544+
4545+ DUMPREG(DISPC_VID_BA0(1));
4546+ DUMPREG(DISPC_VID_BA1(1));
4547+ DUMPREG(DISPC_VID_POSITION(1));
4548+ DUMPREG(DISPC_VID_SIZE(1));
4549+ DUMPREG(DISPC_VID_ATTRIBUTES(1));
4550+ DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
4551+ DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
4552+ DUMPREG(DISPC_VID_ROW_INC(1));
4553+ DUMPREG(DISPC_VID_PIXEL_INC(1));
4554+ DUMPREG(DISPC_VID_FIR(1));
4555+ DUMPREG(DISPC_VID_PICTURE_SIZE(1));
4556+ DUMPREG(DISPC_VID_ACCU0(1));
4557+ DUMPREG(DISPC_VID_ACCU1(1));
4558+
4559+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
4560+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
4561+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
4562+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
4563+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
4564+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
4565+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
4566+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
4567+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
4568+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
4569+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
4570+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
4571+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
4572+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
4573+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
4574+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
4575+ DUMPREG(DISPC_VID_CONV_COEF(0, 0));
4576+ DUMPREG(DISPC_VID_CONV_COEF(0, 1));
4577+ DUMPREG(DISPC_VID_CONV_COEF(0, 2));
4578+ DUMPREG(DISPC_VID_CONV_COEF(0, 3));
4579+ DUMPREG(DISPC_VID_CONV_COEF(0, 4));
4580+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
4581+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
4582+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
4583+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
4584+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
4585+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
4586+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
4587+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
4588+
4589+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
4590+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
4591+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
4592+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
4593+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
4594+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
4595+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
4596+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
4597+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
4598+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
4599+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
4600+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
4601+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
4602+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
4603+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
4604+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
4605+ DUMPREG(DISPC_VID_CONV_COEF(1, 0));
4606+ DUMPREG(DISPC_VID_CONV_COEF(1, 1));
4607+ DUMPREG(DISPC_VID_CONV_COEF(1, 2));
4608+ DUMPREG(DISPC_VID_CONV_COEF(1, 3));
4609+ DUMPREG(DISPC_VID_CONV_COEF(1, 4));
4610+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
4611+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
4612+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
4613+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
4614+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
4615+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
4616+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
4617+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
4618+
4619+ DUMPREG(DISPC_VID_PRELOAD(0));
4620+ DUMPREG(DISPC_VID_PRELOAD(1));
4621+
4622+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
4623+#undef DUMPREG
4624+}
4625+
4626+static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
4627+ bool ihs, bool ivs, u8 acbi, u8 acb)
4628+{
4629+ u32 l = 0;
4630+
4631+ DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
4632+ onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
4633+
4634+ l |= FLD_VAL(onoff, 17, 17);
4635+ l |= FLD_VAL(rf, 16, 16);
4636+ l |= FLD_VAL(ieo, 15, 15);
4637+ l |= FLD_VAL(ipc, 14, 14);
4638+ l |= FLD_VAL(ihs, 13, 13);
4639+ l |= FLD_VAL(ivs, 12, 12);
4640+ l |= FLD_VAL(acbi, 11, 8);
4641+ l |= FLD_VAL(acb, 7, 0);
4642+
4643+ enable_clocks(1);
4644+ dispc_write_reg(DISPC_POL_FREQ, l);
4645+ enable_clocks(0);
4646+}
4647+
4648+void dispc_set_pol_freq(struct omap_panel *panel)
4649+{
4650+ _dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
4651+ (panel->config & OMAP_DSS_LCD_RF) != 0,
4652+ (panel->config & OMAP_DSS_LCD_IEO) != 0,
4653+ (panel->config & OMAP_DSS_LCD_IPC) != 0,
4654+ (panel->config & OMAP_DSS_LCD_IHS) != 0,
4655+ (panel->config & OMAP_DSS_LCD_IVS) != 0,
4656+ panel->acbi, panel->acb);
4657+}
4658+
4659+void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
4660+ u16 *lck_div, u16 *pck_div)
4661+{
4662+ u16 pcd_min = is_tft ? 2 : 3;
4663+ unsigned long best_pck;
4664+ u16 best_ld, cur_ld;
4665+ u16 best_pd, cur_pd;
4666+
4667+ best_pck = 0;
4668+ best_ld = 0;
4669+ best_pd = 0;
4670+
4671+ for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
4672+ unsigned long lck = fck / cur_ld;
4673+
4674+ for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
4675+ unsigned long pck = lck / cur_pd;
4676+ long old_delta = abs(best_pck - req_pck);
4677+ long new_delta = abs(pck - req_pck);
4678+
4679+ if (best_pck == 0 || new_delta < old_delta) {
4680+ best_pck = pck;
4681+ best_ld = cur_ld;
4682+ best_pd = cur_pd;
4683+
4684+ if (pck == req_pck)
4685+ goto found;
4686+ }
4687+
4688+ if (pck < req_pck)
4689+ break;
4690+ }
4691+
4692+ if (lck / pcd_min < req_pck)
4693+ break;
4694+ }
4695+
4696+found:
4697+ *lck_div = best_ld;
4698+ *pck_div = best_pd;
4699+}
4700+
4701+int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
4702+ struct dispc_clock_info *cinfo)
4703+{
4704+ unsigned long prate;
4705+ struct dispc_clock_info cur, best;
4706+ int match = 0;
4707+ int min_fck_per_pck;
4708+ unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
4709+
4710+ if (cpu_is_omap34xx())
4711+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
4712+ else
4713+ prate = 0;
4714+
4715+ if (req_pck == dispc.cache_req_pck &&
4716+ ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
4717+ dispc.cache_cinfo.fck == fck_rate)) {
4718+ DSSDBG("dispc clock info found from cache.\n");
4719+ *cinfo = dispc.cache_cinfo;
4720+ return 0;
4721+ }
4722+
4723+ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
4724+
4725+ if (min_fck_per_pck &&
4726+ req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
4727+ DSSERR("Requested pixel clock not possible with the current "
4728+ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
4729+ "the constraint off.\n");
4730+ min_fck_per_pck = 0;
4731+ }
4732+
4733+retry:
4734+ memset(&cur, 0, sizeof(cur));
4735+ memset(&best, 0, sizeof(best));
4736+
4737+ if (cpu_is_omap24xx()) {
4738+ /* XXX can we change the clock on omap2? */
4739+ cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
4740+ cur.fck_div = 1;
4741+
4742+ match = 1;
4743+
4744+ find_lck_pck_divs(is_tft, req_pck, cur.fck,
4745+ &cur.lck_div, &cur.pck_div);
4746+
4747+ cur.lck = cur.fck / cur.lck_div;
4748+ cur.pck = cur.lck / cur.pck_div;
4749+
4750+ best = cur;
4751+
4752+ goto found;
4753+ } else if (cpu_is_omap34xx()) {
4754+ for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
4755+ cur.fck = prate / cur.fck_div * 2;
4756+
4757+ if (cur.fck > DISPC_MAX_FCK)
4758+ continue;
4759+
4760+ if (min_fck_per_pck &&
4761+ cur.fck < req_pck * min_fck_per_pck)
4762+ continue;
4763+
4764+ match = 1;
4765+
4766+ find_lck_pck_divs(is_tft, req_pck, cur.fck,
4767+ &cur.lck_div, &cur.pck_div);
4768+
4769+ cur.lck = cur.fck / cur.lck_div;
4770+ cur.pck = cur.lck / cur.pck_div;
4771+
4772+ if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
4773+ best = cur;
4774+
4775+ if (cur.pck == req_pck)
4776+ goto found;
4777+ }
4778+ }
4779+ } else {
4780+ BUG();
4781+ }
4782+
4783+found:
4784+ if (!match) {
4785+ if (min_fck_per_pck) {
4786+ DSSERR("Could not find suitable clock settings.\n"
4787+ "Turning FCK/PCK constraint off and"
4788+ "trying again.\n");
4789+ min_fck_per_pck = 0;
4790+ goto retry;
4791+ }
4792+
4793+ DSSERR("Could not find suitable clock settings.\n");
4794+
4795+ return -EINVAL;
4796+ }
4797+
4798+ if (cinfo)
4799+ *cinfo = best;
4800+
4801+ dispc.cache_req_pck = req_pck;
4802+ dispc.cache_prate = prate;
4803+ dispc.cache_cinfo = best;
4804+
4805+ return 0;
4806+}
4807+
4808+int dispc_set_clock_div(struct dispc_clock_info *cinfo)
4809+{
4810+ unsigned long prate;
4811+ int r;
4812+
4813+ if (cpu_is_omap34xx()) {
4814+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
4815+ DSSDBG("dpll4_m4 = %ld\n", prate);
4816+ }
4817+
4818+ DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
4819+ DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
4820+ DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
4821+
4822+ if (cpu_is_omap34xx()) {
4823+ r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
4824+ if (r)
4825+ return r;
4826+ }
4827+
4828+ dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
4829+
4830+ return 0;
4831+}
4832+
4833+int dispc_get_clock_div(struct dispc_clock_info *cinfo)
4834+{
4835+ cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
4836+
4837+ if (cpu_is_omap34xx()) {
4838+ unsigned long prate;
4839+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
4840+ cinfo->fck_div = prate / (cinfo->fck / 2);
4841+ } else {
4842+ cinfo->fck_div = 0;
4843+ }
4844+
4845+ cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
4846+ cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
4847+
4848+ cinfo->lck = cinfo->fck / cinfo->lck_div;
4849+ cinfo->pck = cinfo->lck / cinfo->pck_div;
4850+
4851+ return 0;
4852+}
4853+
4854+static void omap_dispc_set_irqs(void)
4855+{
4856+ unsigned long flags;
4857+ u32 mask = dispc.irq_error_mask;
4858+ int i;
4859+ struct omap_dispc_isr_data *isr_data;
4860+
4861+ spin_lock_irqsave(&dispc.irq_lock, flags);
4862+
4863+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
4864+ isr_data = &dispc.registered_isr[i];
4865+
4866+ if (isr_data->isr == NULL)
4867+ continue;
4868+
4869+ mask |= isr_data->mask;
4870+ }
4871+
4872+ enable_clocks(1);
4873+ dispc_write_reg(DISPC_IRQENABLE, mask);
4874+ enable_clocks(0);
4875+
4876+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
4877+}
4878+
4879+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
4880+{
4881+ int i;
4882+ int ret;
4883+ unsigned long flags;
4884+ struct omap_dispc_isr_data *isr_data;
4885+
4886+ if (isr == NULL)
4887+ return -EINVAL;
4888+
4889+ spin_lock_irqsave(&dispc.irq_lock, flags);
4890+
4891+ /* check for duplicate entry */
4892+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
4893+ isr_data = &dispc.registered_isr[i];
4894+ if (isr_data->isr == isr && isr_data->arg == arg &&
4895+ isr_data->mask == mask) {
4896+ ret = -EINVAL;
4897+ goto err;
4898+ }
4899+ }
4900+
4901+ isr_data = NULL;
4902+ ret = -EBUSY;
4903+
4904+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
4905+ isr_data = &dispc.registered_isr[i];
4906+
4907+ if (isr_data->isr != NULL)
4908+ continue;
4909+
4910+ isr_data->isr = isr;
4911+ isr_data->arg = arg;
4912+ isr_data->mask = mask;
4913+ ret = 0;
4914+
4915+ break;
4916+ }
4917+err:
4918+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
4919+
4920+ if (ret == 0)
4921+ omap_dispc_set_irqs();
4922+
4923+ return ret;
4924+}
4925+EXPORT_SYMBOL(omap_dispc_register_isr);
4926+
4927+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
4928+{
4929+ int i;
4930+ unsigned long flags;
4931+ int ret = -EINVAL;
4932+ struct omap_dispc_isr_data *isr_data;
4933+
4934+ spin_lock_irqsave(&dispc.irq_lock, flags);
4935+
4936+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
4937+ isr_data = &dispc.registered_isr[i];
4938+ if (isr_data->isr != isr || isr_data->arg != arg ||
4939+ isr_data->mask != mask)
4940+ continue;
4941+
4942+ /* found the correct isr */
4943+
4944+ isr_data->isr = NULL;
4945+ isr_data->arg = NULL;
4946+ isr_data->mask = 0;
4947+
4948+ ret = 0;
4949+ break;
4950+ }
4951+
4952+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
4953+
4954+ if (ret == 0)
4955+ omap_dispc_set_irqs();
4956+
4957+ return ret;
4958+}
4959+EXPORT_SYMBOL(omap_dispc_unregister_isr);
4960+
4961+#ifdef DEBUG
4962+static void print_irq_status(u32 status)
4963+{
4964+ if ((status & dispc.irq_error_mask) == 0)
4965+ return;
4966+
4967+ printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
4968+
4969+#define PIS(x) \
4970+ if (status & DISPC_IRQ_##x) \
4971+ printk(#x " ");
4972+ PIS(GFX_FIFO_UNDERFLOW);
4973+ PIS(OCP_ERR);
4974+ PIS(VID1_FIFO_UNDERFLOW);
4975+ PIS(VID2_FIFO_UNDERFLOW);
4976+ PIS(SYNC_LOST);
4977+ PIS(SYNC_LOST_DIGIT);
4978+#undef PIS
4979+
4980+ printk("\n");
4981+}
4982+#endif
4983+
4984+/* Called from dss.c. Note that we don't touch clocks here,
4985+ * but we presume they are on because we got an IRQ. However,
4986+ * an irq handler may turn the clocks off, so we may not have
4987+ * clock later in the function. */
4988+void dispc_irq_handler(void)
4989+{
4990+ int i;
4991+ u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
4992+ u32 handledirqs = 0;
4993+ u32 unhandled_errors;
4994+ struct omap_dispc_isr_data *isr_data;
4995+
4996+#ifdef DEBUG
4997+ if (dss_debug)
4998+ print_irq_status(irqstatus);
4999+#endif
5000+ /* Ack the interrupt. Do it here before clocks are possibly turned
5001+ * off */
5002+ dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
5003+
5004+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
5005+ isr_data = &dispc.registered_isr[i];
5006+
5007+ if (!isr_data->isr)
5008+ continue;
5009+
5010+ if (isr_data->mask & irqstatus) {
5011+ isr_data->isr(isr_data->arg, irqstatus);
5012+ handledirqs |= isr_data->mask;
5013+ }
5014+ }
5015+
5016+ unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
5017+
5018+ if (unhandled_errors) {
5019+ spin_lock(&dispc.error_lock);
5020+ dispc.error_irqs |= unhandled_errors;
5021+ spin_unlock(&dispc.error_lock);
5022+
5023+ dispc.irq_error_mask &= ~unhandled_errors;
5024+ omap_dispc_set_irqs();
5025+
5026+ schedule_work(&dispc.error_work);
5027+ }
5028+}
5029+
5030+static void dispc_error_worker(struct work_struct *work)
5031+{
5032+ int i;
5033+ u32 errors;
5034+ unsigned long flags;
5035+
5036+ spin_lock_irqsave(&dispc.error_lock, flags);
5037+ errors = dispc.error_irqs;
5038+ dispc.error_irqs = 0;
5039+ spin_unlock_irqrestore(&dispc.error_lock, flags);
5040+
5041+ if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
5042+ DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
5043+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
5044+ struct omap_overlay *ovl;
5045+ ovl = omap_dss_get_overlay(i);
5046+
5047+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
5048+ continue;
5049+
5050+ if (ovl->id == 0) {
5051+ dispc_enable_plane(ovl->id, 0);
5052+ dispc_go(ovl->manager->id);
5053+ mdelay(50);
5054+ break;
5055+ }
5056+ }
5057+ }
5058+
5059+ if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
5060+ DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
5061+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
5062+ struct omap_overlay *ovl;
5063+ ovl = omap_dss_get_overlay(i);
5064+
5065+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
5066+ continue;
5067+
5068+ if (ovl->id == 1) {
5069+ dispc_enable_plane(ovl->id, 0);
5070+ dispc_go(ovl->manager->id);
5071+ mdelay(50);
5072+ break;
5073+ }
5074+ }
5075+ }
5076+
5077+ if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
5078+ DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
5079+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
5080+ struct omap_overlay *ovl;
5081+ ovl = omap_dss_get_overlay(i);
5082+
5083+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
5084+ continue;
5085+
5086+ if (ovl->id == 2) {
5087+ dispc_enable_plane(ovl->id, 0);
5088+ dispc_go(ovl->manager->id);
5089+ mdelay(50);
5090+ break;
5091+ }
5092+ }
5093+ }
5094+
5095+ if (errors & DISPC_IRQ_SYNC_LOST) {
5096+ DSSERR("SYNC_LOST, disabling LCD\n");
5097+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
5098+ struct omap_overlay_manager *mgr;
5099+ mgr = omap_dss_get_overlay_manager(i);
5100+
5101+ if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
5102+ mgr->display->disable(mgr->display);
5103+ break;
5104+ }
5105+ }
5106+ }
5107+
5108+ if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
5109+ DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
5110+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
5111+ struct omap_overlay_manager *mgr;
5112+ mgr = omap_dss_get_overlay_manager(i);
5113+
5114+ if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
5115+ mgr->display->disable(mgr->display);
5116+ break;
5117+ }
5118+ }
5119+ }
5120+
5121+ if (errors & DISPC_IRQ_OCP_ERR) {
5122+ DSSERR("OCP_ERR\n");
5123+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
5124+ struct omap_overlay_manager *mgr;
5125+ mgr = omap_dss_get_overlay_manager(i);
5126+
5127+ if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
5128+ mgr->display->disable(mgr->display);
5129+ }
5130+ }
5131+
5132+ dispc.irq_error_mask |= errors;
5133+ omap_dispc_set_irqs();
5134+}
5135+
5136+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
5137+{
5138+ void dispc_irq_wait_handler(void *data, u32 mask)
5139+ {
5140+ complete((struct completion *)data);
5141+ }
5142+
5143+ int r;
5144+ DECLARE_COMPLETION_ONSTACK(completion);
5145+
5146+ r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
5147+ irqmask);
5148+
5149+ if (r)
5150+ return r;
5151+
5152+ timeout = wait_for_completion_timeout(&completion, timeout);
5153+
5154+ omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
5155+
5156+ if (timeout == 0)
5157+ return -ETIMEDOUT;
5158+
5159+ if (timeout == -ERESTARTSYS)
5160+ return -ERESTARTSYS;
5161+
5162+ return 0;
5163+}
5164+
5165+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
5166+ unsigned long timeout)
5167+{
5168+ void dispc_irq_wait_handler(void *data, u32 mask)
5169+ {
5170+ complete((struct completion *)data);
5171+ }
5172+
5173+ int r;
5174+ DECLARE_COMPLETION_ONSTACK(completion);
5175+
5176+ r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
5177+ irqmask);
5178+
5179+ if (r)
5180+ return r;
5181+
5182+ timeout = wait_for_completion_interruptible_timeout(&completion,
5183+ timeout);
5184+
5185+ omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
5186+
5187+ if (timeout == 0)
5188+ return -ETIMEDOUT;
5189+
5190+ if (timeout == -ERESTARTSYS)
5191+ return -ERESTARTSYS;
5192+
5193+ return 0;
5194+}
5195+
5196+#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
5197+void dispc_fake_vsync_irq(void)
5198+{
5199+ u32 irqstatus = DISPC_IRQ_VSYNC;
5200+ int i;
5201+
5202+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
5203+ struct omap_dispc_isr_data *isr_data;
5204+ isr_data = &dispc.registered_isr[i];
5205+
5206+ if (!isr_data->isr)
5207+ continue;
5208+
5209+ if (isr_data->mask & irqstatus)
5210+ isr_data->isr(isr_data->arg, irqstatus);
5211+ }
5212+}
5213+#endif
5214+
5215+static void _omap_dispc_initialize_irq(void)
5216+{
5217+ memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
5218+
5219+ dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
5220+
5221+ /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
5222+ * so clear it */
5223+ dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
5224+
5225+ omap_dispc_set_irqs();
5226+}
5227+
5228+static void _omap_dispc_initial_config(void)
5229+{
5230+ u32 l;
5231+
5232+ l = dispc_read_reg(DISPC_SYSCONFIG);
5233+ l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
5234+ l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
5235+ l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
5236+ l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
5237+ dispc_write_reg(DISPC_SYSCONFIG, l);
5238+
5239+ /* FUNCGATED */
5240+ REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
5241+
5242+ /* L3 firewall setting: enable access to OCM RAM */
5243+ if (cpu_is_omap24xx())
5244+ __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
5245+
5246+ _dispc_setup_color_conv_coef();
5247+
5248+ dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
5249+}
5250+
5251+int dispc_init(void)
5252+{
5253+ u32 rev;
5254+
5255+ spin_lock_init(&dispc.irq_lock);
5256+ spin_lock_init(&dispc.error_lock);
5257+
5258+ INIT_WORK(&dispc.error_work, dispc_error_worker);
5259+
5260+ dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
5261+ if (!dispc.base) {
5262+ DSSERR("can't ioremap DISPC\n");
5263+ return -ENOMEM;
5264+ }
5265+
5266+ if (cpu_is_omap34xx()) {
5267+ dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
5268+ if (IS_ERR(dispc.dpll4_m4_ck)) {
5269+ DSSERR("Failed to get dpll4_m4_ck\n");
5270+ return -ENODEV;
5271+ }
5272+ }
5273+
5274+ enable_clocks(1);
5275+
5276+ _omap_dispc_initial_config();
5277+
5278+ _omap_dispc_initialize_irq();
5279+
5280+ dispc_save_context();
5281+
5282+ rev = dispc_read_reg(DISPC_REVISION);
5283+ printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
5284+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5285+
5286+ enable_clocks(0);
5287+
5288+ return 0;
5289+}
5290+
5291+void dispc_exit(void)
5292+{
5293+ if (cpu_is_omap34xx())
5294+ clk_put(dispc.dpll4_m4_ck);
5295+ iounmap(dispc.base);
5296+}
5297+
5298+int dispc_enable_plane(enum omap_plane plane, bool enable)
5299+{
5300+ DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
5301+
5302+ enable_clocks(1);
5303+ _dispc_enable_plane(plane, enable);
5304+ enable_clocks(0);
5305+
5306+ return 0;
5307+}
5308+
5309+int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
5310+ u32 paddr, u16 screen_width,
5311+ u16 pos_x, u16 pos_y,
5312+ u16 width, u16 height,
5313+ u16 out_width, u16 out_height,
5314+ enum omap_color_mode color_mode,
5315+ bool ilace,
5316+ u8 rotation, bool mirror)
5317+{
5318+ int r = 0;
5319+
5320+ DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
5321+ "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
5322+ plane, channel_out, paddr, screen_width, pos_x, pos_y,
5323+ width, height,
5324+ out_width, out_height,
5325+ ilace, color_mode,
5326+ rotation, mirror);
5327+
5328+ enable_clocks(1);
5329+
5330+ r = _dispc_setup_plane(plane, channel_out,
5331+ paddr, screen_width,
5332+ pos_x, pos_y,
5333+ width, height,
5334+ out_width, out_height,
5335+ color_mode, ilace,
5336+ rotation, mirror);
5337+
5338+ enable_clocks(0);
5339+
5340+ return r;
5341+}
5342+
5343+static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
5344+ int x2, int y2, int w2, int h2)
5345+{
5346+ if (x1 >= (x2+w2))
5347+ return 0;
5348+
5349+ if ((x1+w1) <= x2)
5350+ return 0;
5351+
5352+ if (y1 >= (y2+h2))
5353+ return 0;
5354+
5355+ if ((y1+h1) <= y2)
5356+ return 0;
5357+
5358+ return 1;
5359+}
5360+
5361+static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
5362+{
5363+ if (pi->width != pi->out_width)
5364+ return 1;
5365+
5366+ if (pi->height != pi->out_height)
5367+ return 1;
5368+
5369+ return 0;
5370+}
5371+
5372+/* returns the area that needs updating */
5373+void dispc_setup_partial_planes(struct omap_display *display,
5374+ u16 *xi, u16 *yi, u16 *wi, u16 *hi)
5375+{
5376+ struct omap_overlay_manager *mgr;
5377+ int i;
5378+
5379+ int x, y, w, h;
5380+
5381+ x = *xi;
5382+ y = *yi;
5383+ w = *wi;
5384+ h = *hi;
5385+
5386+ DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
5387+ *xi, *yi, *wi, *hi);
5388+
5389+
5390+ mgr = display->manager;
5391+
5392+ if (!mgr) {
5393+ DSSDBG("no manager\n");
5394+ return;
5395+ }
5396+
5397+ for (i = 0; i < mgr->num_overlays; i++) {
5398+ struct omap_overlay *ovl;
5399+ struct omap_overlay_info *pi;
5400+ ovl = mgr->overlays[i];
5401+
5402+ if (ovl->manager != mgr)
5403+ continue;
5404+
5405+ if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
5406+ continue;
5407+
5408+ pi = &ovl->info;
5409+
5410+ if (!pi->enabled)
5411+ continue;
5412+ /*
5413+ * If the plane is intersecting and scaled, we
5414+ * enlarge the update region to accomodate the
5415+ * whole area
5416+ */
5417+
5418+ if (dispc_is_intersecting(x, y, w, h,
5419+ pi->pos_x, pi->pos_y,
5420+ pi->out_width, pi->out_height)) {
5421+ if (dispc_is_overlay_scaled(pi)) {
5422+
5423+ int x1, y1, x2, y2;
5424+
5425+ if (x > pi->pos_x)
5426+ x1 = pi->pos_x;
5427+ else
5428+ x1 = x;
5429+
5430+ if (y > pi->pos_y)
5431+ y1 = pi->pos_y;
5432+ else
5433+ y1 = y;
5434+
5435+ if ((x + w) < (pi->pos_x + pi->out_width))
5436+ x2 = pi->pos_x + pi->out_width;
5437+ else
5438+ x2 = x + w;
5439+
5440+ if ((y + h) < (pi->pos_y + pi->out_height))
5441+ y2 = pi->pos_y + pi->out_height;
5442+ else
5443+ y2 = y + h;
5444+
5445+ x = x1;
5446+ y = y1;
5447+ w = x2 - x1;
5448+ h = y2 - y1;
5449+
5450+ DSSDBG("Update area after enlarge due to "
5451+ "scaling %d, %d %dx%d\n",
5452+ x, y, w, h);
5453+ }
5454+ }
5455+ }
5456+
5457+ for (i = 0; i < mgr->num_overlays; i++) {
5458+ struct omap_overlay *ovl = mgr->overlays[i];
5459+ struct omap_overlay_info *pi = &ovl->info;
5460+
5461+ int px = pi->pos_x;
5462+ int py = pi->pos_y;
5463+ int pw = pi->width;
5464+ int ph = pi->height;
5465+ int pow = pi->out_width;
5466+ int poh = pi->out_height;
5467+ u32 pa = pi->paddr;
5468+ int psw = pi->screen_width;
5469+ int bpp;
5470+
5471+ if (ovl->manager != mgr)
5472+ continue;
5473+
5474+ /*
5475+ * If plane is not enabled or the update region
5476+ * does not intersect with the plane in question,
5477+ * we really disable the plane from hardware
5478+ */
5479+
5480+ if (!pi->enabled ||
5481+ !dispc_is_intersecting(x, y, w, h,
5482+ px, py, pow, poh)) {
5483+ dispc_enable_plane(ovl->id, 0);
5484+ continue;
5485+ }
5486+
5487+ switch (pi->color_mode) {
5488+ case OMAP_DSS_COLOR_RGB16:
5489+ case OMAP_DSS_COLOR_ARGB16:
5490+ case OMAP_DSS_COLOR_YUV2:
5491+ case OMAP_DSS_COLOR_UYVY:
5492+ bpp = 16;
5493+ break;
5494+
5495+ case OMAP_DSS_COLOR_RGB24P:
5496+ bpp = 24;
5497+ break;
5498+
5499+ case OMAP_DSS_COLOR_RGB24U:
5500+ case OMAP_DSS_COLOR_ARGB32:
5501+ case OMAP_DSS_COLOR_RGBA32:
5502+ case OMAP_DSS_COLOR_RGBX32:
5503+ bpp = 32;
5504+ break;
5505+
5506+ default:
5507+ BUG();
5508+ return;
5509+ }
5510+
5511+ if (x > pi->pos_x) {
5512+ px = 0;
5513+ pw -= (x - pi->pos_x);
5514+ pa += (x - pi->pos_x) * bpp / 8;
5515+ } else {
5516+ px = pi->pos_x - x;
5517+ }
5518+
5519+ if (y > pi->pos_y) {
5520+ py = 0;
5521+ ph -= (y - pi->pos_y);
5522+ pa += (y - pi->pos_y) * psw * bpp / 8;
5523+ } else {
5524+ py = pi->pos_y - y;
5525+ }
5526+
5527+ if (w < (px+pw))
5528+ pw -= (px+pw) - (w);
5529+
5530+ if (h < (py+ph))
5531+ ph -= (py+ph) - (h);
5532+
5533+ /* Can't scale the GFX plane */
5534+ if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
5535+ dispc_is_overlay_scaled(pi) == 0) {
5536+ pow = pw;
5537+ poh = ph;
5538+ }
5539+
5540+ DSSDBG("calc plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
5541+ ovl->id, pa, psw, px, py, pw, ph, pow, poh);
5542+
5543+ dispc_setup_plane(ovl->id, mgr->id,
5544+ pa, psw,
5545+ px, py,
5546+ pw, ph,
5547+ pow, poh,
5548+ pi->color_mode, 0,
5549+ pi->rotation, // XXX rotation probably wrong
5550+ pi->mirror);
5551+
5552+ dispc_enable_plane(ovl->id, 1);
5553+ }
5554+
5555+ *xi = x;
5556+ *yi = y;
5557+ *wi = w;
5558+ *hi = h;
5559+
5560+}
5561+
5562diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
5563new file mode 100644
5564index 0000000..9aaf392
5565--- /dev/null
5566+++ b/drivers/video/omap2/dss/display.c
5567@@ -0,0 +1,693 @@
5568+/*
5569+ * linux/drivers/video/omap2/dss/display.c
5570+ *
5571+ * Copyright (C) 2009 Nokia Corporation
5572+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
5573+ *
5574+ * Some code and ideas taken from drivers/video/omap/ driver
5575+ * by Imre Deak.
5576+ *
5577+ * This program is free software; you can redistribute it and/or modify it
5578+ * under the terms of the GNU General Public License version 2 as published by
5579+ * the Free Software Foundation.
5580+ *
5581+ * This program is distributed in the hope that it will be useful, but WITHOUT
5582+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
5583+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
5584+ * more details.
5585+ *
5586+ * You should have received a copy of the GNU General Public License along with
5587+ * this program. If not, see <http://www.gnu.org/licenses/>.
5588+ */
5589+
5590+#define DSS_SUBSYS_NAME "DISPLAY"
5591+
5592+#include <linux/kernel.h>
5593+#include <linux/module.h>
5594+#include <linux/jiffies.h>
5595+#include <linux/list.h>
5596+#include <linux/platform_device.h>
5597+
5598+#include <mach/display.h>
5599+#include "dss.h"
5600+
5601+static int num_displays;
5602+static LIST_HEAD(display_list);
5603+
5604+static ssize_t display_name_show(struct omap_display *display, char *buf)
5605+{
5606+ return snprintf(buf, PAGE_SIZE, "%s\n", display->name);
5607+}
5608+
5609+static ssize_t display_enabled_show(struct omap_display *display, char *buf)
5610+{
5611+ bool enabled = display->state != OMAP_DSS_DISPLAY_DISABLED;
5612+
5613+ return snprintf(buf, PAGE_SIZE, "%d\n", enabled);
5614+}
5615+
5616+static ssize_t display_enabled_store(struct omap_display *display,
5617+ const char *buf, size_t size)
5618+{
5619+ bool enabled, r;
5620+
5621+ enabled = simple_strtoul(buf, NULL, 10);
5622+
5623+ if (enabled != (display->state != OMAP_DSS_DISPLAY_DISABLED)) {
5624+ if (enabled) {
5625+ r = display->enable(display);
5626+ if (r)
5627+ return r;
5628+ } else {
5629+ display->disable(display);
5630+ }
5631+ }
5632+
5633+ return size;
5634+}
5635+
5636+static ssize_t display_upd_mode_show(struct omap_display *display, char *buf)
5637+{
5638+ enum omap_dss_update_mode mode = OMAP_DSS_UPDATE_AUTO;
5639+ if (display->get_update_mode)
5640+ mode = display->get_update_mode(display);
5641+ return snprintf(buf, PAGE_SIZE, "%d\n", mode);
5642+}
5643+
5644+static ssize_t display_upd_mode_store(struct omap_display *display,
5645+ const char *buf, size_t size)
5646+{
5647+ int val, r;
5648+ enum omap_dss_update_mode mode;
5649+
5650+ val = simple_strtoul(buf, NULL, 10);
5651+
5652+ switch (val) {
5653+ case OMAP_DSS_UPDATE_DISABLED:
5654+ case OMAP_DSS_UPDATE_AUTO:
5655+ case OMAP_DSS_UPDATE_MANUAL:
5656+ mode = (enum omap_dss_update_mode)val;
5657+ break;
5658+ default:
5659+ return -EINVAL;
5660+ }
5661+
5662+ if ((r = display->set_update_mode(display, mode)))
5663+ return r;
5664+
5665+ return size;
5666+}
5667+
5668+static ssize_t display_tear_show(struct omap_display *display, char *buf)
5669+{
5670+ return snprintf(buf, PAGE_SIZE, "%d\n",
5671+ display->get_te ? display->get_te(display) : 0);
5672+}
5673+
5674+static ssize_t display_tear_store(struct omap_display *display,
5675+ const char *buf, size_t size)
5676+{
5677+ unsigned long te;
5678+ int r;
5679+
5680+ if (!display->enable_te || !display->get_te)
5681+ return -ENOENT;
5682+
5683+ te = simple_strtoul(buf, NULL, 0);
5684+
5685+ if ((r = display->enable_te(display, te)))
5686+ return r;
5687+
5688+ return size;
5689+}
5690+
5691+static ssize_t display_timings_show(struct omap_display *display, char *buf)
5692+{
5693+ struct omap_video_timings t;
5694+
5695+ if (!display->get_timings)
5696+ return -ENOENT;
5697+
5698+ display->get_timings(display, &t);
5699+
5700+ return snprintf(buf, PAGE_SIZE, "%u,%u/%u/%u/%u,%u/%u/%u/%u\n",
5701+ t.pixel_clock,
5702+ t.x_res, t.hfp, t.hbp, t.hsw,
5703+ t.y_res, t.vfp, t.vbp, t.vsw);
5704+}
5705+
5706+static ssize_t display_timings_store(struct omap_display *display,
5707+ const char *buf, size_t size)
5708+{
5709+ struct omap_video_timings t;
5710+ int r, found;
5711+
5712+ if (!display->set_timings || !display->check_timings)
5713+ return -ENOENT;
5714+
5715+ found = 0;
5716+#ifdef CONFIG_OMAP2_DSS_VENC
5717+ if (strncmp("pal", buf, 3) == 0) {
5718+ t = omap_dss_pal_timings;
5719+ found = 1;
5720+ } else if (strncmp("ntsc", buf, 4) == 0) {
5721+ t = omap_dss_ntsc_timings;
5722+ found = 1;
5723+ }
5724+#endif
5725+ if (!found && sscanf(buf, "%u,%hu/%hu/%hu/%hu,%hu/%hu/%hu/%hu",
5726+ &t.pixel_clock,
5727+ &t.x_res, &t.hfp, &t.hbp, &t.hsw,
5728+ &t.y_res, &t.vfp, &t.vbp, &t.vsw) != 9)
5729+ return -EINVAL;
5730+
5731+ if ((r = display->check_timings(display, &t)))
5732+ return r;
5733+
5734+ display->set_timings(display, &t);
5735+
5736+ return size;
5737+}
5738+
5739+static ssize_t display_rotate_show(struct omap_display *display, char *buf)
5740+{
5741+ int rotate;
5742+ if (!display->get_rotate)
5743+ return -ENOENT;
5744+ rotate = display->get_rotate(display);
5745+ return snprintf(buf, PAGE_SIZE, "%u\n", rotate);
5746+}
5747+
5748+static ssize_t display_rotate_store(struct omap_display *display,
5749+ const char *buf, size_t size)
5750+{
5751+ unsigned long rot;
5752+ int r;
5753+
5754+ if (!display->set_rotate || !display->get_rotate)
5755+ return -ENOENT;
5756+
5757+ rot = simple_strtoul(buf, NULL, 0);
5758+
5759+ if ((r = display->set_rotate(display, rot)))
5760+ return r;
5761+
5762+ return size;
5763+}
5764+
5765+static ssize_t display_mirror_show(struct omap_display *display, char *buf)
5766+{
5767+ int mirror;
5768+ if (!display->get_mirror)
5769+ return -ENOENT;
5770+ mirror = display->get_mirror(display);
5771+ return snprintf(buf, PAGE_SIZE, "%u\n", mirror);
5772+}
5773+
5774+static ssize_t display_mirror_store(struct omap_display *display,
5775+ const char *buf, size_t size)
5776+{
5777+ unsigned long mirror;
5778+ int r;
5779+
5780+ if (!display->set_mirror || !display->get_mirror)
5781+ return -ENOENT;
5782+
5783+ mirror = simple_strtoul(buf, NULL, 0);
5784+
5785+ if ((r = display->set_mirror(display, mirror)))
5786+ return r;
5787+
5788+ return size;
5789+}
5790+
5791+static ssize_t display_panel_name_show(struct omap_display *display, char *buf)
5792+{
5793+ return snprintf(buf, PAGE_SIZE, "%s\n",
5794+ display->panel ? display->panel->name : "");
5795+}
5796+
5797+static ssize_t display_ctrl_name_show(struct omap_display *display, char *buf)
5798+{
5799+ return snprintf(buf, PAGE_SIZE, "%s\n",
5800+ display->ctrl ? display->ctrl->name : "");
5801+}
5802+
5803+struct display_attribute {
5804+ struct attribute attr;
5805+ ssize_t (*show)(struct omap_display *, char *);
5806+ ssize_t (*store)(struct omap_display *, const char *, size_t);
5807+};
5808+
5809+#define DISPLAY_ATTR(_name, _mode, _show, _store) \
5810+ struct display_attribute display_attr_##_name = \
5811+ __ATTR(_name, _mode, _show, _store)
5812+
5813+static DISPLAY_ATTR(name, S_IRUGO, display_name_show, NULL);
5814+static DISPLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
5815+ display_enabled_show, display_enabled_store);
5816+static DISPLAY_ATTR(update_mode, S_IRUGO|S_IWUSR,
5817+ display_upd_mode_show, display_upd_mode_store);
5818+static DISPLAY_ATTR(tear_elim, S_IRUGO|S_IWUSR,
5819+ display_tear_show, display_tear_store);
5820+static DISPLAY_ATTR(timings, S_IRUGO|S_IWUSR,
5821+ display_timings_show, display_timings_store);
5822+static DISPLAY_ATTR(rotate, S_IRUGO|S_IWUSR,
5823+ display_rotate_show, display_rotate_store);
5824+static DISPLAY_ATTR(mirror, S_IRUGO|S_IWUSR,
5825+ display_mirror_show, display_mirror_store);
5826+static DISPLAY_ATTR(panel_name, S_IRUGO, display_panel_name_show, NULL);
5827+static DISPLAY_ATTR(ctrl_name, S_IRUGO, display_ctrl_name_show, NULL);
5828+
5829+static struct attribute *display_sysfs_attrs[] = {
5830+ &display_attr_name.attr,
5831+ &display_attr_enabled.attr,
5832+ &display_attr_update_mode.attr,
5833+ &display_attr_tear_elim.attr,
5834+ &display_attr_timings.attr,
5835+ &display_attr_rotate.attr,
5836+ &display_attr_mirror.attr,
5837+ &display_attr_panel_name.attr,
5838+ &display_attr_ctrl_name.attr,
5839+ NULL
5840+};
5841+
5842+static ssize_t display_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
5843+{
5844+ struct omap_display *display;
5845+ struct display_attribute *display_attr;
5846+
5847+ display = container_of(kobj, struct omap_display, kobj);
5848+ display_attr = container_of(attr, struct display_attribute, attr);
5849+
5850+ if (!display_attr->show)
5851+ return -ENOENT;
5852+
5853+ return display_attr->show(display, buf);
5854+}
5855+
5856+static ssize_t display_attr_store(struct kobject *kobj, struct attribute *attr,
5857+ const char *buf, size_t size)
5858+{
5859+ struct omap_display *display;
5860+ struct display_attribute *display_attr;
5861+
5862+ display = container_of(kobj, struct omap_display, kobj);
5863+ display_attr = container_of(attr, struct display_attribute, attr);
5864+
5865+ if (!display_attr->store)
5866+ return -ENOENT;
5867+
5868+ return display_attr->store(display, buf, size);
5869+}
5870+
5871+static struct sysfs_ops display_sysfs_ops = {
5872+ .show = display_attr_show,
5873+ .store = display_attr_store,
5874+};
5875+
5876+static struct kobj_type display_ktype = {
5877+ .sysfs_ops = &display_sysfs_ops,
5878+ .default_attrs = display_sysfs_attrs,
5879+};
5880+
5881+static void default_get_resolution(struct omap_display *display,
5882+ u16 *xres, u16 *yres)
5883+{
5884+ *xres = display->panel->timings.x_res;
5885+ *yres = display->panel->timings.y_res;
5886+}
5887+
5888+static void default_configure_overlay(struct omap_overlay *ovl)
5889+{
5890+ unsigned low, high, size;
5891+ enum omap_burst_size burst;
5892+ enum omap_plane plane = ovl->id;
5893+
5894+ burst = OMAP_DSS_BURST_16x32;
5895+ size = 16 * 32 / 8;
5896+
5897+ dispc_set_burst_size(plane, burst);
5898+
5899+ high = dispc_get_plane_fifo_size(plane) - 1;
5900+ low = dispc_get_plane_fifo_size(plane) - size;
5901+
5902+ dispc_setup_plane_fifo(plane, low, high);
5903+}
5904+
5905+static int default_wait_vsync(struct omap_display *display)
5906+{
5907+ unsigned long timeout = msecs_to_jiffies(500);
5908+ u32 irq;
5909+
5910+ if (display->type == OMAP_DISPLAY_TYPE_VENC)
5911+ irq = DISPC_IRQ_EVSYNC_ODD;
5912+ else
5913+ irq = DISPC_IRQ_VSYNC;
5914+
5915+ return omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
5916+}
5917+
5918+static int default_get_recommended_bpp(struct omap_display *display)
5919+{
5920+ if (display->panel->recommended_bpp)
5921+ return display->panel->recommended_bpp;
5922+
5923+ switch (display->type) {
5924+ case OMAP_DISPLAY_TYPE_DPI:
5925+ if (display->hw_config.u.dpi.data_lines == 24)
5926+ return 24;
5927+ else
5928+ return 16;
5929+
5930+ case OMAP_DISPLAY_TYPE_DBI:
5931+ case OMAP_DISPLAY_TYPE_DSI:
5932+ if (display->ctrl->pixel_size == 24)
5933+ return 24;
5934+ else
5935+ return 16;
5936+ case OMAP_DISPLAY_TYPE_VENC:
5937+ case OMAP_DISPLAY_TYPE_SDI:
5938+ return 24;
5939+ return 24;
5940+ default:
5941+ BUG();
5942+ }
5943+}
5944+
5945+void dss_init_displays(struct platform_device *pdev)
5946+{
5947+ struct omap_dss_board_info *pdata = pdev->dev.platform_data;
5948+ int i, r;
5949+
5950+ INIT_LIST_HEAD(&display_list);
5951+
5952+ num_displays = 0;
5953+
5954+ for (i = 0; i < pdata->num_displays; ++i) {
5955+ struct omap_display *display;
5956+
5957+ switch (pdata->displays[i]->type) {
5958+ case OMAP_DISPLAY_TYPE_DPI:
5959+#ifdef CONFIG_OMAP2_DSS_RFBI
5960+ case OMAP_DISPLAY_TYPE_DBI:
5961+#endif
5962+#ifdef CONFIG_OMAP2_DSS_SDI
5963+ case OMAP_DISPLAY_TYPE_SDI:
5964+#endif
5965+#ifdef CONFIG_OMAP2_DSS_DSI
5966+ case OMAP_DISPLAY_TYPE_DSI:
5967+#endif
5968+#ifdef CONFIG_OMAP2_DSS_VENC
5969+ case OMAP_DISPLAY_TYPE_VENC:
5970+#endif
5971+ break;
5972+ default:
5973+ DSSERR("Support for display '%s' not compiled in.\n",
5974+ pdata->displays[i]->name);
5975+ continue;
5976+ }
5977+
5978+ display = kzalloc(sizeof(*display), GFP_KERNEL);
5979+
5980+ /*atomic_set(&display->ref_count, 0);*/
5981+ display->ref_count = 0;
5982+
5983+ display->hw_config = *pdata->displays[i];
5984+ display->type = pdata->displays[i]->type;
5985+ display->name = pdata->displays[i]->name;
5986+
5987+ display->get_resolution = default_get_resolution;
5988+ display->get_recommended_bpp = default_get_recommended_bpp;
5989+ display->configure_overlay = default_configure_overlay;
5990+ display->wait_vsync = default_wait_vsync;
5991+
5992+ switch (display->type) {
5993+ case OMAP_DISPLAY_TYPE_DPI:
5994+ dpi_init_display(display);
5995+ break;
5996+#ifdef CONFIG_OMAP2_DSS_RFBI
5997+ case OMAP_DISPLAY_TYPE_DBI:
5998+ rfbi_init_display(display);
5999+ break;
6000+#endif
6001+#ifdef CONFIG_OMAP2_DSS_VENC
6002+ case OMAP_DISPLAY_TYPE_VENC:
6003+ venc_init_display(display);
6004+ break;
6005+#endif
6006+#ifdef CONFIG_OMAP2_DSS_SDI
6007+ case OMAP_DISPLAY_TYPE_SDI:
6008+ sdi_init_display(display);
6009+ break;
6010+#endif
6011+#ifdef CONFIG_OMAP2_DSS_DSI
6012+ case OMAP_DISPLAY_TYPE_DSI:
6013+ dsi_init_display(display);
6014+ break;
6015+#endif
6016+ default:
6017+ BUG();
6018+ }
6019+
6020+ r = kobject_init_and_add(&display->kobj, &display_ktype,
6021+ &pdev->dev.kobj, "display%d", num_displays);
6022+
6023+ if (r) {
6024+ DSSERR("failed to create sysfs file\n");
6025+ continue;
6026+ }
6027+
6028+ num_displays++;
6029+
6030+ list_add_tail(&display->list, &display_list);
6031+ }
6032+}
6033+
6034+void dss_uninit_displays(struct platform_device *pdev)
6035+{
6036+ struct omap_display *display;
6037+
6038+ while (!list_empty(&display_list)) {
6039+ display = list_first_entry(&display_list,
6040+ struct omap_display, list);
6041+ list_del(&display->list);
6042+ kobject_del(&display->kobj);
6043+ kobject_put(&display->kobj);
6044+ kfree(display);
6045+ }
6046+
6047+ num_displays = 0;
6048+}
6049+
6050+int dss_suspend_all_displays(void)
6051+{
6052+ int r;
6053+ struct omap_display *display;
6054+
6055+ list_for_each_entry(display, &display_list, list) {
6056+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE) {
6057+ display->activate_after_resume = 0;
6058+ continue;
6059+ }
6060+
6061+ if (!display->suspend) {
6062+ DSSERR("display '%s' doesn't implement suspend\n",
6063+ display->name);
6064+ r = -ENOSYS;
6065+ goto err;
6066+ }
6067+
6068+ r = display->suspend(display);
6069+
6070+ if (r)
6071+ goto err;
6072+
6073+ display->activate_after_resume = 1;
6074+ }
6075+
6076+ return 0;
6077+err:
6078+ /* resume all displays that were suspended */
6079+ dss_resume_all_displays();
6080+ return r;
6081+}
6082+
6083+int dss_resume_all_displays(void)
6084+{
6085+ int r;
6086+ struct omap_display *display;
6087+
6088+ list_for_each_entry(display, &display_list, list) {
6089+ if (display->activate_after_resume && display->resume) {
6090+ r = display->resume(display);
6091+ if (r)
6092+ return r;
6093+ }
6094+
6095+ display->activate_after_resume = 0;
6096+ }
6097+
6098+ return 0;
6099+}
6100+
6101+int omap_dss_get_num_displays(void)
6102+{
6103+ return num_displays;
6104+}
6105+EXPORT_SYMBOL(omap_dss_get_num_displays);
6106+
6107+struct omap_display *dss_get_display(int no)
6108+{
6109+ int i = 0;
6110+ struct omap_display *display;
6111+
6112+ list_for_each_entry(display, &display_list, list) {
6113+ if (i++ == no)
6114+ return display;
6115+ }
6116+
6117+ return NULL;
6118+}
6119+
6120+struct omap_display *omap_dss_get_display(int no)
6121+{
6122+ struct omap_display *display;
6123+
6124+ display = dss_get_display(no);
6125+
6126+ if (!display)
6127+ return NULL;
6128+
6129+ switch (display->type) {
6130+ case OMAP_DISPLAY_TYPE_VENC:
6131+ break;
6132+
6133+ case OMAP_DISPLAY_TYPE_DPI:
6134+ case OMAP_DISPLAY_TYPE_SDI:
6135+ if (display->panel == NULL)
6136+ return NULL;
6137+ break;
6138+
6139+ case OMAP_DISPLAY_TYPE_DBI:
6140+ case OMAP_DISPLAY_TYPE_DSI:
6141+ if (display->panel == NULL || display->ctrl == NULL)
6142+ return NULL;
6143+ break;
6144+
6145+ default:
6146+ return NULL;
6147+ }
6148+
6149+ if (display->ctrl) {
6150+ if (!try_module_get(display->ctrl->owner))
6151+ goto err0;
6152+
6153+ if (display->ctrl->init)
6154+ if (display->ctrl->init(display) != 0)
6155+ goto err1;
6156+ }
6157+
6158+ if (display->panel) {
6159+ if (!try_module_get(display->panel->owner))
6160+ goto err2;
6161+
6162+ if (display->panel->init)
6163+ if (display->panel->init(display) != 0)
6164+ goto err3;
6165+ }
6166+
6167+ display->ref_count++;
6168+ /*
6169+ if (atomic_cmpxchg(&display->ref_count, 0, 1) != 0)
6170+ return 0;
6171+*/
6172+
6173+ return display;
6174+err3:
6175+ if (display->panel)
6176+ module_put(display->panel->owner);
6177+err2:
6178+ if (display->ctrl && display->ctrl->cleanup)
6179+ display->ctrl->cleanup(display);
6180+err1:
6181+ if (display->ctrl)
6182+ module_put(display->ctrl->owner);
6183+err0:
6184+ return NULL;
6185+}
6186+EXPORT_SYMBOL(omap_dss_get_display);
6187+
6188+void omap_dss_put_display(struct omap_display *display)
6189+{
6190+ if (--display->ref_count > 0)
6191+ return;
6192+/*
6193+ if (atomic_cmpxchg(&display->ref_count, 1, 0) != 1)
6194+ return;
6195+*/
6196+ if (display->ctrl) {
6197+ if (display->ctrl->cleanup)
6198+ display->ctrl->cleanup(display);
6199+ module_put(display->ctrl->owner);
6200+ }
6201+
6202+ if (display->panel) {
6203+ if (display->panel->cleanup)
6204+ display->panel->cleanup(display);
6205+ module_put(display->panel->owner);
6206+ }
6207+}
6208+EXPORT_SYMBOL(omap_dss_put_display);
6209+
6210+void omap_dss_register_ctrl(struct omap_ctrl *ctrl)
6211+{
6212+ struct omap_display *display;
6213+
6214+ list_for_each_entry(display, &display_list, list) {
6215+ if (display->hw_config.ctrl_name &&
6216+ strcmp(display->hw_config.ctrl_name, ctrl->name) == 0) {
6217+ display->ctrl = ctrl;
6218+ DSSDBG("ctrl '%s' registered\n", ctrl->name);
6219+ }
6220+ }
6221+}
6222+EXPORT_SYMBOL(omap_dss_register_ctrl);
6223+
6224+void omap_dss_register_panel(struct omap_panel *panel)
6225+{
6226+ struct omap_display *display;
6227+
6228+ list_for_each_entry(display, &display_list, list) {
6229+ if (display->hw_config.panel_name &&
6230+ strcmp(display->hw_config.panel_name, panel->name) == 0) {
6231+ display->panel = panel;
6232+ DSSDBG("panel '%s' registered\n", panel->name);
6233+ }
6234+ }
6235+}
6236+EXPORT_SYMBOL(omap_dss_register_panel);
6237+
6238+void omap_dss_unregister_ctrl(struct omap_ctrl *ctrl)
6239+{
6240+ struct omap_display *display;
6241+
6242+ list_for_each_entry(display, &display_list, list) {
6243+ if (display->hw_config.ctrl_name &&
6244+ strcmp(display->hw_config.ctrl_name, ctrl->name) == 0)
6245+ display->ctrl = NULL;
6246+ }
6247+}
6248+EXPORT_SYMBOL(omap_dss_unregister_ctrl);
6249+
6250+void omap_dss_unregister_panel(struct omap_panel *panel)
6251+{
6252+ struct omap_display *display;
6253+
6254+ list_for_each_entry(display, &display_list, list) {
6255+ if (display->hw_config.panel_name &&
6256+ strcmp(display->hw_config.panel_name, panel->name) == 0)
6257+ display->panel = NULL;
6258+ }
6259+}
6260+EXPORT_SYMBOL(omap_dss_unregister_panel);
6261diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
6262new file mode 100644
6263index 0000000..71fffca
6264--- /dev/null
6265+++ b/drivers/video/omap2/dss/dpi.c
6266@@ -0,0 +1,393 @@
6267+/*
6268+ * linux/drivers/video/omap2/dss/dpi.c
6269+ *
6270+ * Copyright (C) 2009 Nokia Corporation
6271+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6272+ *
6273+ * Some code and ideas taken from drivers/video/omap/ driver
6274+ * by Imre Deak.
6275+ *
6276+ * This program is free software; you can redistribute it and/or modify it
6277+ * under the terms of the GNU General Public License version 2 as published by
6278+ * the Free Software Foundation.
6279+ *
6280+ * This program is distributed in the hope that it will be useful, but WITHOUT
6281+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6282+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
6283+ * more details.
6284+ *
6285+ * You should have received a copy of the GNU General Public License along with
6286+ * this program. If not, see <http://www.gnu.org/licenses/>.
6287+ */
6288+
6289+#include <linux/kernel.h>
6290+#include <linux/clk.h>
6291+#include <linux/delay.h>
6292+#include <linux/errno.h>
6293+
6294+#include <mach/board.h>
6295+#include <mach/display.h>
6296+#include <mach/cpu.h>
6297+
6298+#include "dss.h"
6299+
6300+static struct {
6301+ int update_enabled;
6302+} dpi;
6303+
6304+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
6305+static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
6306+ unsigned long *fck, int *lck_div, int *pck_div)
6307+{
6308+ struct dsi_clock_info cinfo;
6309+ int r;
6310+
6311+ r = dsi_pll_calc_pck(is_tft, pck_req, &cinfo);
6312+ if (r)
6313+ return r;
6314+
6315+ r = dsi_pll_program(&cinfo);
6316+ if (r)
6317+ return r;
6318+
6319+ dss_select_clk_source(0, 1);
6320+
6321+ dispc_set_lcd_divisor(cinfo.lck_div, cinfo.pck_div);
6322+
6323+ *fck = cinfo.dsi1_pll_fclk;
6324+ *lck_div = cinfo.lck_div;
6325+ *pck_div = cinfo.pck_div;
6326+
6327+ return 0;
6328+}
6329+#else
6330+static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
6331+ unsigned long *fck, int *lck_div, int *pck_div)
6332+{
6333+ struct dispc_clock_info cinfo;
6334+ int r;
6335+
6336+ r = dispc_calc_clock_div(is_tft, pck_req, &cinfo);
6337+ if (r)
6338+ return r;
6339+
6340+ r = dispc_set_clock_div(&cinfo);
6341+ if (r)
6342+ return r;
6343+
6344+ *fck = cinfo.fck;
6345+ *lck_div = cinfo.lck_div;
6346+ *pck_div = cinfo.pck_div;
6347+
6348+ return 0;
6349+}
6350+#endif
6351+
6352+static int dpi_set_mode(struct omap_display *display)
6353+{
6354+ struct omap_panel *panel = display->panel;
6355+ int lck_div, pck_div;
6356+ unsigned long fck;
6357+ unsigned long pck;
6358+ bool is_tft;
6359+ int r = 0;
6360+
6361+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
6362+
6363+ dispc_set_pol_freq(panel);
6364+
6365+ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
6366+
6367+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
6368+ r = dpi_set_dsi_clk(is_tft, panel->timings.pixel_clock * 1000,
6369+ &fck, &lck_div, &pck_div);
6370+#else
6371+ r = dpi_set_dispc_clk(is_tft, panel->timings.pixel_clock * 1000,
6372+ &fck, &lck_div, &pck_div);
6373+#endif
6374+ if (r)
6375+ goto err0;
6376+
6377+ pck = fck / lck_div / pck_div / 1000;
6378+
6379+ if (pck != panel->timings.pixel_clock) {
6380+ DSSWARN("Could not find exact pixel clock. "
6381+ "Requested %d kHz, got %lu kHz\n",
6382+ panel->timings.pixel_clock, pck);
6383+
6384+ panel->timings.pixel_clock = pck;
6385+ }
6386+
6387+ dispc_set_lcd_timings(&panel->timings);
6388+
6389+err0:
6390+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
6391+ return r;
6392+}
6393+
6394+static int dpi_basic_init(struct omap_display *display)
6395+{
6396+ bool is_tft;
6397+
6398+ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
6399+
6400+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
6401+ dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT :
6402+ OMAP_DSS_LCD_DISPLAY_STN);
6403+ dispc_set_tft_data_lines(display->hw_config.u.dpi.data_lines);
6404+
6405+ return 0;
6406+}
6407+
6408+static int dpi_display_enable(struct omap_display *display)
6409+{
6410+ struct omap_panel *panel = display->panel;
6411+ int r;
6412+
6413+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
6414+ DSSERR("display already enabled\n");
6415+ return -EINVAL;
6416+ }
6417+
6418+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
6419+
6420+ r = dpi_basic_init(display);
6421+ if (r)
6422+ goto err0;
6423+
6424+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
6425+ dss_clk_enable(DSS_CLK_FCK2);
6426+ r = dsi_pll_init(0, 1);
6427+ if (r)
6428+ goto err1;
6429+#endif
6430+ r = dpi_set_mode(display);
6431+ if (r)
6432+ goto err2;
6433+
6434+ mdelay(2);
6435+
6436+ dispc_enable_lcd_out(1);
6437+
6438+ r = panel->enable(display);
6439+ if (r)
6440+ goto err3;
6441+
6442+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
6443+
6444+ return 0;
6445+
6446+err3:
6447+ dispc_enable_lcd_out(0);
6448+err2:
6449+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
6450+ dsi_pll_uninit();
6451+err1:
6452+ dss_clk_disable(DSS_CLK_FCK2);
6453+#endif
6454+err0:
6455+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
6456+ return r;
6457+}
6458+
6459+static int dpi_display_resume(struct omap_display *display);
6460+
6461+static void dpi_display_disable(struct omap_display *display)
6462+{
6463+ if (display->state == OMAP_DSS_DISPLAY_DISABLED)
6464+ return;
6465+
6466+ if (display->state == OMAP_DSS_DISPLAY_SUSPENDED)
6467+ dpi_display_resume(display);
6468+
6469+ display->panel->disable(display);
6470+
6471+ dispc_enable_lcd_out(0);
6472+
6473+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
6474+ dss_select_clk_source(0, 0);
6475+ dsi_pll_uninit();
6476+ dss_clk_disable(DSS_CLK_FCK2);
6477+#endif
6478+
6479+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
6480+
6481+ display->state = OMAP_DSS_DISPLAY_DISABLED;
6482+}
6483+
6484+static int dpi_display_suspend(struct omap_display *display)
6485+{
6486+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
6487+ return -EINVAL;
6488+
6489+ DSSDBG("dpi_display_suspend\n");
6490+
6491+ if (display->panel->suspend)
6492+ display->panel->suspend(display);
6493+
6494+ dispc_enable_lcd_out(0);
6495+
6496+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
6497+
6498+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
6499+
6500+ return 0;
6501+}
6502+
6503+static int dpi_display_resume(struct omap_display *display)
6504+{
6505+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
6506+ return -EINVAL;
6507+
6508+ DSSDBG("dpi_display_resume\n");
6509+
6510+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
6511+
6512+ dispc_enable_lcd_out(1);
6513+
6514+ if (display->panel->resume)
6515+ display->panel->resume(display);
6516+
6517+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
6518+
6519+ return 0;
6520+}
6521+
6522+static void dpi_set_timings(struct omap_display *display,
6523+ struct omap_video_timings *timings)
6524+{
6525+ DSSDBG("dpi_set_timings\n");
6526+ display->panel->timings = *timings;
6527+ if (display->state == OMAP_DSS_DISPLAY_ACTIVE) {
6528+ dpi_set_mode(display);
6529+ dispc_go(OMAP_DSS_CHANNEL_LCD);
6530+ }
6531+}
6532+
6533+static int dpi_check_timings(struct omap_display *display,
6534+ struct omap_video_timings *timings)
6535+{
6536+ bool is_tft;
6537+ int r;
6538+ int lck_div, pck_div;
6539+ unsigned long fck;
6540+ unsigned long pck;
6541+
6542+ if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
6543+ if (timings->hsw < 1 || timings->hsw > 64 ||
6544+ timings->hfp < 1 || timings->hfp > 256 ||
6545+ timings->hbp < 1 || timings->hbp > 256) {
6546+ return -EINVAL;
6547+ }
6548+
6549+ if (timings->vsw < 1 || timings->vsw > 64 ||
6550+ timings->vfp > 255 || timings->vbp > 255) {
6551+ return -EINVAL;
6552+ }
6553+ } else {
6554+ if (timings->hsw < 1 || timings->hsw > 256 ||
6555+ timings->hfp < 1 || timings->hfp > 4096 ||
6556+ timings->hbp < 1 || timings->hbp > 4096) {
6557+ return -EINVAL;
6558+ }
6559+
6560+ if (timings->vsw < 1 || timings->vsw > 64 ||
6561+ timings->vfp > 4095 || timings->vbp > 4095) {
6562+ return -EINVAL;
6563+ }
6564+ }
6565+
6566+ if (timings->pixel_clock == 0)
6567+ return -EINVAL;
6568+
6569+ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
6570+
6571+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
6572+ {
6573+ struct dsi_clock_info cinfo;
6574+ r = dsi_pll_calc_pck(is_tft, timings->pixel_clock * 1000,
6575+ &cinfo);
6576+
6577+ if (r)
6578+ return r;
6579+
6580+ fck = cinfo.dsi1_pll_fclk;
6581+ lck_div = cinfo.lck_div;
6582+ pck_div = cinfo.pck_div;
6583+ }
6584+#else
6585+ {
6586+ struct dispc_clock_info cinfo;
6587+ r = dispc_calc_clock_div(is_tft, timings->pixel_clock * 1000,
6588+ &cinfo);
6589+
6590+ if (r)
6591+ return r;
6592+
6593+ fck = cinfo.fck;
6594+ lck_div = cinfo.lck_div;
6595+ pck_div = cinfo.pck_div;
6596+ }
6597+#endif
6598+
6599+ pck = fck / lck_div / pck_div / 1000;
6600+
6601+ timings->pixel_clock = pck;
6602+
6603+ return 0;
6604+}
6605+
6606+static void dpi_get_timings(struct omap_display *display,
6607+ struct omap_video_timings *timings)
6608+{
6609+ *timings = display->panel->timings;
6610+}
6611+
6612+static int dpi_display_set_update_mode(struct omap_display *display,
6613+ enum omap_dss_update_mode mode)
6614+{
6615+ if (mode == OMAP_DSS_UPDATE_MANUAL)
6616+ return -EINVAL;
6617+
6618+ if (mode == OMAP_DSS_UPDATE_DISABLED) {
6619+ dispc_enable_lcd_out(0);
6620+ dpi.update_enabled = 0;
6621+ } else {
6622+ dispc_enable_lcd_out(1);
6623+ dpi.update_enabled = 1;
6624+ }
6625+
6626+ return 0;
6627+}
6628+
6629+static enum omap_dss_update_mode dpi_display_get_update_mode(
6630+ struct omap_display *display)
6631+{
6632+ return dpi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
6633+ OMAP_DSS_UPDATE_DISABLED;
6634+}
6635+
6636+void dpi_init_display(struct omap_display *display)
6637+{
6638+ DSSDBG("DPI init_display\n");
6639+
6640+ display->enable = dpi_display_enable;
6641+ display->disable = dpi_display_disable;
6642+ display->suspend = dpi_display_suspend;
6643+ display->resume = dpi_display_resume;
6644+ display->set_timings = dpi_set_timings;
6645+ display->check_timings = dpi_check_timings;
6646+ display->get_timings = dpi_get_timings;
6647+ display->set_update_mode = dpi_display_set_update_mode;
6648+ display->get_update_mode = dpi_display_get_update_mode;
6649+}
6650+
6651+int dpi_init(void)
6652+{
6653+ return 0;
6654+}
6655+
6656+void dpi_exit(void)
6657+{
6658+}
6659+
6660diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
6661new file mode 100644
6662index 0000000..4442931
6663--- /dev/null
6664+++ b/drivers/video/omap2/dss/dsi.c
6665@@ -0,0 +1,3752 @@
6666+/*
6667+ * linux/drivers/video/omap2/dss/dsi.c
6668+ *
6669+ * Copyright (C) 2009 Nokia Corporation
6670+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6671+ *
6672+ * This program is free software; you can redistribute it and/or modify it
6673+ * under the terms of the GNU General Public License version 2 as published by
6674+ * the Free Software Foundation.
6675+ *
6676+ * This program is distributed in the hope that it will be useful, but WITHOUT
6677+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6678+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
6679+ * more details.
6680+ *
6681+ * You should have received a copy of the GNU General Public License along with
6682+ * this program. If not, see <http://www.gnu.org/licenses/>.
6683+ */
6684+
6685+#define DSS_SUBSYS_NAME "DSI"
6686+
6687+#include <linux/kernel.h>
6688+#include <linux/io.h>
6689+#include <linux/clk.h>
6690+#include <linux/device.h>
6691+#include <linux/err.h>
6692+#include <linux/interrupt.h>
6693+#include <linux/delay.h>
6694+#include <linux/workqueue.h>
6695+#include <linux/mutex.h>
6696+#include <linux/seq_file.h>
6697+#include <linux/kfifo.h>
6698+
6699+#include <mach/board.h>
6700+#include <mach/display.h>
6701+#include <mach/clock.h>
6702+
6703+#include "dss.h"
6704+
6705+/*#define VERBOSE_IRQ*/
6706+
6707+#define DSI_BASE 0x4804FC00
6708+
6709+struct dsi_reg { u16 idx; };
6710+
6711+#define DSI_REG(idx) ((const struct dsi_reg) { idx })
6712+
6713+#define DSI_SZ_REGS SZ_1K
6714+/* DSI Protocol Engine */
6715+
6716+#define DSI_REVISION DSI_REG(0x0000)
6717+#define DSI_SYSCONFIG DSI_REG(0x0010)
6718+#define DSI_SYSSTATUS DSI_REG(0x0014)
6719+#define DSI_IRQSTATUS DSI_REG(0x0018)
6720+#define DSI_IRQENABLE DSI_REG(0x001C)
6721+#define DSI_CTRL DSI_REG(0x0040)
6722+#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
6723+#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
6724+#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
6725+#define DSI_CLK_CTRL DSI_REG(0x0054)
6726+#define DSI_TIMING1 DSI_REG(0x0058)
6727+#define DSI_TIMING2 DSI_REG(0x005C)
6728+#define DSI_VM_TIMING1 DSI_REG(0x0060)
6729+#define DSI_VM_TIMING2 DSI_REG(0x0064)
6730+#define DSI_VM_TIMING3 DSI_REG(0x0068)
6731+#define DSI_CLK_TIMING DSI_REG(0x006C)
6732+#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
6733+#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
6734+#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
6735+#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
6736+#define DSI_VM_TIMING4 DSI_REG(0x0080)
6737+#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
6738+#define DSI_VM_TIMING5 DSI_REG(0x0088)
6739+#define DSI_VM_TIMING6 DSI_REG(0x008C)
6740+#define DSI_VM_TIMING7 DSI_REG(0x0090)
6741+#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
6742+#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
6743+#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
6744+#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
6745+#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
6746+#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
6747+#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
6748+#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
6749+
6750+/* DSIPHY_SCP */
6751+
6752+#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
6753+#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
6754+#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
6755+#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
6756+
6757+/* DSI_PLL_CTRL_SCP */
6758+
6759+#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
6760+#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
6761+#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
6762+#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
6763+#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
6764+
6765+#define REG_GET(idx, start, end) \
6766+ FLD_GET(dsi_read_reg(idx), start, end)
6767+
6768+#define REG_FLD_MOD(idx, val, start, end) \
6769+ dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
6770+
6771+/* Global interrupts */
6772+#define DSI_IRQ_VC0 (1 << 0)
6773+#define DSI_IRQ_VC1 (1 << 1)
6774+#define DSI_IRQ_VC2 (1 << 2)
6775+#define DSI_IRQ_VC3 (1 << 3)
6776+#define DSI_IRQ_WAKEUP (1 << 4)
6777+#define DSI_IRQ_RESYNC (1 << 5)
6778+#define DSI_IRQ_PLL_LOCK (1 << 7)
6779+#define DSI_IRQ_PLL_UNLOCK (1 << 8)
6780+#define DSI_IRQ_PLL_RECALL (1 << 9)
6781+#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
6782+#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
6783+#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
6784+#define DSI_IRQ_TE_TRIGGER (1 << 16)
6785+#define DSI_IRQ_ACK_TRIGGER (1 << 17)
6786+#define DSI_IRQ_SYNC_LOST (1 << 18)
6787+#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
6788+#define DSI_IRQ_TA_TIMEOUT (1 << 20)
6789+#define DSI_IRQ_ERROR_MASK \
6790+ (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
6791+ DSI_IRQ_TA_TIMEOUT)
6792+#define DSI_IRQ_CHANNEL_MASK 0xf
6793+
6794+/* Virtual channel interrupts */
6795+#define DSI_VC_IRQ_CS (1 << 0)
6796+#define DSI_VC_IRQ_ECC_CORR (1 << 1)
6797+#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
6798+#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
6799+#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
6800+#define DSI_VC_IRQ_BTA (1 << 5)
6801+#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
6802+#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
6803+#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
6804+#define DSI_VC_IRQ_ERROR_MASK \
6805+ (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
6806+ DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
6807+ DSI_VC_IRQ_FIFO_TX_UDF)
6808+
6809+/* ComplexIO interrupts */
6810+#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
6811+#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
6812+#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
6813+#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
6814+#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
6815+#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
6816+#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
6817+#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
6818+#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
6819+#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
6820+#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
6821+#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
6822+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
6823+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
6824+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
6825+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
6826+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
6827+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
6828+#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
6829+#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
6830+
6831+#define DSI_DT_DCS_SHORT_WRITE_0 0x05
6832+#define DSI_DT_DCS_SHORT_WRITE_1 0x15
6833+#define DSI_DT_DCS_READ 0x06
6834+#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
6835+#define DSI_DT_NULL_PACKET 0x09
6836+#define DSI_DT_DCS_LONG_WRITE 0x39
6837+
6838+#define DSI_DT_RX_ACK_WITH_ERR 0x02
6839+#define DSI_DT_RX_DCS_LONG_READ 0x1c
6840+#define DSI_DT_RX_SHORT_READ_1 0x21
6841+#define DSI_DT_RX_SHORT_READ_2 0x22
6842+
6843+#define FINT_MAX 2100000
6844+#define FINT_MIN 750000
6845+#define REGN_MAX (1 << 7)
6846+#define REGM_MAX ((1 << 11) - 1)
6847+#define REGM3_MAX (1 << 4)
6848+#define REGM4_MAX (1 << 4)
6849+
6850+enum fifo_size {
6851+ DSI_FIFO_SIZE_0 = 0,
6852+ DSI_FIFO_SIZE_32 = 1,
6853+ DSI_FIFO_SIZE_64 = 2,
6854+ DSI_FIFO_SIZE_96 = 3,
6855+ DSI_FIFO_SIZE_128 = 4,
6856+};
6857+
6858+#define DSI_CMD_FIFO_LEN 16
6859+
6860+struct dsi_cmd_update {
6861+ int bytespp;
6862+ u16 x;
6863+ u16 y;
6864+ u16 w;
6865+ u16 h;
6866+};
6867+
6868+struct dsi_cmd_mem_read {
6869+ void *buf;
6870+ size_t size;
6871+ u16 x;
6872+ u16 y;
6873+ u16 w;
6874+ u16 h;
6875+ size_t *ret_size;
6876+ struct completion *completion;
6877+};
6878+
6879+struct dsi_cmd_test {
6880+ int test_num;
6881+ int *result;
6882+ struct completion *completion;
6883+};
6884+
6885+enum dsi_cmd {
6886+ DSI_CMD_UPDATE,
6887+ DSI_CMD_AUTOUPDATE,
6888+ DSI_CMD_SYNC,
6889+ DSI_CMD_MEM_READ,
6890+ DSI_CMD_TEST,
6891+ DSI_CMD_SET_TE,
6892+ DSI_CMD_SET_UPDATE_MODE,
6893+ DSI_CMD_SET_ROTATE,
6894+ DSI_CMD_SET_MIRROR,
6895+};
6896+
6897+struct dsi_cmd_item {
6898+ struct omap_display *display;
6899+
6900+ enum dsi_cmd cmd;
6901+
6902+ union {
6903+ struct dsi_cmd_update r;
6904+ struct completion *sync;
6905+ struct dsi_cmd_mem_read mem_read;
6906+ struct dsi_cmd_test test;
6907+ int te;
6908+ enum omap_dss_update_mode update_mode;
6909+ int rotate;
6910+ int mirror;
6911+ } u;
6912+};
6913+
6914+static struct
6915+{
6916+ void __iomem *base;
6917+
6918+ unsigned long dsi1_pll_fclk; /* Hz */
6919+ unsigned long dsi2_pll_fclk; /* Hz */
6920+ unsigned long dsiphy; /* Hz */
6921+ unsigned long ddr_clk; /* Hz */
6922+
6923+ struct {
6924+ struct omap_display *display;
6925+ enum fifo_size fifo_size;
6926+ int dest_per; /* destination peripheral 0-3 */
6927+ } vc[4];
6928+
6929+ struct mutex lock;
6930+
6931+ unsigned pll_locked;
6932+
6933+ struct completion bta_completion;
6934+
6935+ struct work_struct framedone_work;
6936+ struct work_struct process_work;
6937+ struct workqueue_struct *workqueue;
6938+
6939+ enum omap_dss_update_mode user_update_mode;
6940+ enum omap_dss_update_mode target_update_mode;
6941+ enum omap_dss_update_mode update_mode;
6942+ int use_te;
6943+ int framedone_scheduled; /* helps to catch strange framedone bugs */
6944+
6945+ unsigned long cache_req_pck;
6946+ unsigned long cache_clk_freq;
6947+ struct dsi_clock_info cache_cinfo;
6948+
6949+ struct kfifo *cmd_fifo;
6950+ spinlock_t cmd_lock;
6951+ struct completion cmd_done;
6952+ atomic_t cmd_fifo_full;
6953+ atomic_t cmd_pending;
6954+
6955+ bool autoupdate_setup;
6956+
6957+#ifdef DEBUG
6958+ ktime_t perf_setup_time;
6959+ ktime_t perf_start_time;
6960+ int perf_measure_frames;
6961+
6962+ struct {
6963+ int x, y, w, h;
6964+ int bytespp;
6965+ } update_region;
6966+
6967+#endif
6968+ int debug_process;
6969+ int debug_read;
6970+ int debug_write;
6971+} dsi;
6972+
6973+#ifdef DEBUG
6974+static unsigned int dsi_perf;
6975+module_param_named(dsi_perf, dsi_perf, bool, 0644);
6976+#endif
6977+
6978+static void dsi_process_cmd_fifo(struct work_struct *work);
6979+static void dsi_push_update(struct omap_display *display,
6980+ int x, int y, int w, int h);
6981+static void dsi_push_autoupdate(struct omap_display *display);
6982+
6983+static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
6984+{
6985+ __raw_writel(val, dsi.base + idx.idx);
6986+}
6987+
6988+static inline u32 dsi_read_reg(const struct dsi_reg idx)
6989+{
6990+ return __raw_readl(dsi.base + idx.idx);
6991+}
6992+
6993+
6994+void dsi_save_context(void)
6995+{
6996+}
6997+
6998+void dsi_restore_context(void)
6999+{
7000+}
7001+
7002+static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
7003+ int value)
7004+{
7005+ int t = 100000;
7006+
7007+ while (REG_GET(idx, bitnum, bitnum) != value) {
7008+ if (--t == 0)
7009+ return !value;
7010+ }
7011+
7012+ return value;
7013+}
7014+
7015+#ifdef DEBUG
7016+static void perf_mark_setup(void)
7017+{
7018+ dsi.perf_setup_time = ktime_get();
7019+}
7020+
7021+static void perf_mark_start(void)
7022+{
7023+ dsi.perf_start_time = ktime_get();
7024+}
7025+
7026+static void perf_show(const char *name)
7027+{
7028+ ktime_t t, setup_time, trans_time;
7029+ u32 total_bytes;
7030+ u32 setup_us, trans_us, total_us;
7031+ const int numframes = 100;
7032+ static u32 s_trans_us, s_min_us = 0xffffffff, s_max_us;
7033+
7034+ if (!dsi_perf)
7035+ return;
7036+
7037+ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
7038+ return;
7039+
7040+ t = ktime_get();
7041+
7042+ setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
7043+ setup_us = (u32)ktime_to_us(setup_time);
7044+ if (setup_us == 0)
7045+ setup_us = 1;
7046+
7047+ trans_time = ktime_sub(t, dsi.perf_start_time);
7048+ trans_us = (u32)ktime_to_us(trans_time);
7049+ if (trans_us == 0)
7050+ trans_us = 1;
7051+
7052+ total_us = setup_us + trans_us;
7053+
7054+ total_bytes = dsi.update_region.w *
7055+ dsi.update_region.h *
7056+ dsi.update_region.bytespp;
7057+
7058+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
7059+ dsi.perf_measure_frames++;
7060+
7061+ if (trans_us < s_min_us)
7062+ s_min_us = trans_us;
7063+
7064+ if (trans_us > s_max_us)
7065+ s_max_us = trans_us;
7066+
7067+ s_trans_us += trans_us;
7068+
7069+ if (dsi.perf_measure_frames < numframes)
7070+ return;
7071+
7072+ DSSINFO("%s update: %d frames in %u us "
7073+ "(min/max/avg %u/%u/%u), %u fps\n",
7074+ name, numframes,
7075+ s_trans_us,
7076+ s_min_us,
7077+ s_max_us,
7078+ s_trans_us / numframes,
7079+ 1000*1000 / (s_trans_us / numframes));
7080+
7081+ dsi.perf_measure_frames = 0;
7082+ s_trans_us = 0;
7083+ s_min_us = 0xffffffff;
7084+ s_max_us = 0;
7085+ } else {
7086+ DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, "
7087+ "%u kbytes/sec\n",
7088+ name,
7089+ setup_us,
7090+ trans_us,
7091+ total_us,
7092+ 1000*1000 / total_us,
7093+ total_bytes,
7094+ total_bytes * 1000 / total_us);
7095+ }
7096+}
7097+#else
7098+#define perf_mark_setup()
7099+#define perf_mark_start()
7100+#define perf_show(x)
7101+#endif
7102+
7103+static void print_irq_status(u32 status)
7104+{
7105+#ifndef VERBOSE_IRQ
7106+ if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
7107+ return;
7108+#endif
7109+ printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
7110+
7111+#define PIS(x) \
7112+ if (status & DSI_IRQ_##x) \
7113+ printk(#x " ");
7114+#ifdef VERBOSE_IRQ
7115+ PIS(VC0);
7116+ PIS(VC1);
7117+ PIS(VC2);
7118+ PIS(VC3);
7119+#endif
7120+ PIS(WAKEUP);
7121+ PIS(RESYNC);
7122+ PIS(PLL_LOCK);
7123+ PIS(PLL_UNLOCK);
7124+ PIS(PLL_RECALL);
7125+ PIS(COMPLEXIO_ERR);
7126+ PIS(HS_TX_TIMEOUT);
7127+ PIS(LP_RX_TIMEOUT);
7128+ PIS(TE_TRIGGER);
7129+ PIS(ACK_TRIGGER);
7130+ PIS(SYNC_LOST);
7131+ PIS(LDO_POWER_GOOD);
7132+ PIS(TA_TIMEOUT);
7133+#undef PIS
7134+
7135+ printk("\n");
7136+}
7137+
7138+static void print_irq_status_vc(int channel, u32 status)
7139+{
7140+#ifndef VERBOSE_IRQ
7141+ if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
7142+ return;
7143+#endif
7144+ printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
7145+
7146+#define PIS(x) \
7147+ if (status & DSI_VC_IRQ_##x) \
7148+ printk(#x " ");
7149+ PIS(CS);
7150+ PIS(ECC_CORR);
7151+#ifdef VERBOSE_IRQ
7152+ PIS(PACKET_SENT);
7153+#endif
7154+ PIS(FIFO_TX_OVF);
7155+ PIS(FIFO_RX_OVF);
7156+ PIS(BTA);
7157+ PIS(ECC_NO_CORR);
7158+ PIS(FIFO_TX_UDF);
7159+ PIS(PP_BUSY_CHANGE);
7160+#undef PIS
7161+ printk("\n");
7162+}
7163+
7164+static void print_irq_status_cio(u32 status)
7165+{
7166+ printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
7167+
7168+#define PIS(x) \
7169+ if (status & DSI_CIO_IRQ_##x) \
7170+ printk(#x " ");
7171+ PIS(ERRSYNCESC1);
7172+ PIS(ERRSYNCESC2);
7173+ PIS(ERRSYNCESC3);
7174+ PIS(ERRESC1);
7175+ PIS(ERRESC2);
7176+ PIS(ERRESC3);
7177+ PIS(ERRCONTROL1);
7178+ PIS(ERRCONTROL2);
7179+ PIS(ERRCONTROL3);
7180+ PIS(STATEULPS1);
7181+ PIS(STATEULPS2);
7182+ PIS(STATEULPS3);
7183+ PIS(ERRCONTENTIONLP0_1);
7184+ PIS(ERRCONTENTIONLP1_1);
7185+ PIS(ERRCONTENTIONLP0_2);
7186+ PIS(ERRCONTENTIONLP1_2);
7187+ PIS(ERRCONTENTIONLP0_3);
7188+ PIS(ERRCONTENTIONLP1_3);
7189+ PIS(ULPSACTIVENOT_ALL0);
7190+ PIS(ULPSACTIVENOT_ALL1);
7191+#undef PIS
7192+
7193+ printk("\n");
7194+}
7195+
7196+static int debug_irq;
7197+
7198+/* called from dss */
7199+void dsi_irq_handler(void)
7200+{
7201+ u32 irqstatus, vcstatus, ciostatus;
7202+ int i;
7203+
7204+ irqstatus = dsi_read_reg(DSI_IRQSTATUS);
7205+
7206+ if (irqstatus & DSI_IRQ_ERROR_MASK) {
7207+ DSSERR("DSI error, irqstatus %x\n", irqstatus);
7208+ print_irq_status(irqstatus);
7209+ } else if (debug_irq) {
7210+ print_irq_status(irqstatus);
7211+ }
7212+
7213+ for (i = 0; i < 4; ++i) {
7214+ if ((irqstatus & (1<<i)) == 0)
7215+ continue;
7216+
7217+ vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
7218+
7219+ if (vcstatus & DSI_VC_IRQ_BTA)
7220+ complete(&dsi.bta_completion);
7221+
7222+ if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
7223+ DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
7224+ i, vcstatus);
7225+ print_irq_status_vc(i, vcstatus);
7226+ } else if (debug_irq) {
7227+ print_irq_status_vc(i, vcstatus);
7228+ }
7229+
7230+ dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
7231+ }
7232+
7233+ if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
7234+ ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
7235+
7236+ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
7237+
7238+ DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
7239+ print_irq_status_cio(ciostatus);
7240+ }
7241+
7242+ dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
7243+}
7244+
7245+
7246+static void _dsi_initialize_irq(void)
7247+{
7248+ u32 l;
7249+ int i;
7250+
7251+ /* disable all interrupts */
7252+ dsi_write_reg(DSI_IRQENABLE, 0);
7253+ for (i = 0; i < 4; ++i)
7254+ dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
7255+ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
7256+
7257+ /* clear interrupt status */
7258+ l = dsi_read_reg(DSI_IRQSTATUS);
7259+ dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
7260+
7261+ for (i = 0; i < 4; ++i) {
7262+ l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
7263+ dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
7264+ }
7265+
7266+ l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
7267+ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
7268+
7269+ /* enable error irqs */
7270+ l = DSI_IRQ_ERROR_MASK;
7271+ dsi_write_reg(DSI_IRQENABLE, l);
7272+
7273+ l = DSI_VC_IRQ_ERROR_MASK;
7274+ for (i = 0; i < 4; ++i)
7275+ dsi_write_reg(DSI_VC_IRQENABLE(i), l);
7276+
7277+ /* XXX zonda responds incorrectly, causing control error:
7278+ Exit from LP-ESC mode to LP11 uses wrong transition states on the
7279+ data lines LP0 and LN0. */
7280+ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
7281+ -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
7282+}
7283+
7284+static void dsi_vc_enable_bta_irq(int channel)
7285+{
7286+ u32 l;
7287+
7288+ l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
7289+ l |= DSI_VC_IRQ_BTA;
7290+ dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
7291+}
7292+
7293+static void dsi_vc_disable_bta_irq(int channel)
7294+{
7295+ u32 l;
7296+
7297+ l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
7298+ l &= ~DSI_VC_IRQ_BTA;
7299+ dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
7300+}
7301+
7302+/* DSI func clock. this could also be DSI2_PLL_FCLK */
7303+static inline void enable_clocks(bool enable)
7304+{
7305+ if (enable)
7306+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
7307+ else
7308+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
7309+}
7310+
7311+/* source clock for DSI PLL. this could also be PCLKFREE */
7312+static inline void dsi_enable_pll_clock(bool enable)
7313+{
7314+ if (enable)
7315+ dss_clk_enable(DSS_CLK_FCK2);
7316+ else
7317+ dss_clk_disable(DSS_CLK_FCK2);
7318+
7319+ if (enable && dsi.pll_locked) {
7320+ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
7321+ DSSERR("cannot lock PLL when enabling clocks\n");
7322+ }
7323+}
7324+
7325+#ifdef DEBUG
7326+static void _dsi_print_reset_status(void)
7327+{
7328+ u32 l;
7329+
7330+ if (!dss_debug)
7331+ return;
7332+
7333+ /* A dummy read using the SCP interface to any DSIPHY register is
7334+ * required after DSIPHY reset to complete the reset of the DSI complex
7335+ * I/O. */
7336+ l = dsi_read_reg(DSI_DSIPHY_CFG5);
7337+
7338+ printk(KERN_DEBUG "DSI resets: ");
7339+
7340+ l = dsi_read_reg(DSI_PLL_STATUS);
7341+ printk("PLL (%d) ", FLD_GET(l, 0, 0));
7342+
7343+ l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
7344+ printk("CIO (%d) ", FLD_GET(l, 29, 29));
7345+
7346+ l = dsi_read_reg(DSI_DSIPHY_CFG5);
7347+ printk("PHY (%x, %d, %d, %d)\n",
7348+ FLD_GET(l, 28, 26),
7349+ FLD_GET(l, 29, 29),
7350+ FLD_GET(l, 30, 30),
7351+ FLD_GET(l, 31, 31));
7352+}
7353+#else
7354+#define _dsi_print_reset_status()
7355+#endif
7356+
7357+static inline int dsi_if_enable(bool enable)
7358+{
7359+ DSSDBG("dsi_if_enable(%d)\n", enable);
7360+
7361+ enable = enable ? 1 : 0;
7362+ REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
7363+
7364+ if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
7365+ DSSERR("Failed to set dsi_if_enable to %d\n", enable);
7366+ return -EIO;
7367+ }
7368+
7369+ return 0;
7370+}
7371+
7372+static unsigned long dsi_fclk_rate(void)
7373+{
7374+ unsigned long r;
7375+
7376+ if (dss_get_dsi_clk_source() == 0) {
7377+ /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
7378+ r = dss_clk_get_rate(DSS_CLK_FCK1);
7379+ } else {
7380+ /* DSI FCLK source is DSI2_PLL_FCLK */
7381+ r = dsi.dsi2_pll_fclk;
7382+ }
7383+
7384+ return r;
7385+}
7386+
7387+static int dsi_set_lp_clk_divisor(void)
7388+{
7389+ int n;
7390+ unsigned long dsi_fclk;
7391+ unsigned long mhz;
7392+
7393+ /* LP_CLK_DIVISOR, DSI fclk/n, should be 20MHz - 32kHz */
7394+
7395+ dsi_fclk = dsi_fclk_rate();
7396+
7397+ for (n = 1; n < (1 << 13) - 1; ++n) {
7398+ mhz = dsi_fclk / n;
7399+ if (mhz <= 20*1000*1000)
7400+ break;
7401+ }
7402+
7403+ if (n == (1 << 13) - 1) {
7404+ DSSERR("Failed to find LP_CLK_DIVISOR\n");
7405+ return -EINVAL;
7406+ }
7407+
7408+ DSSDBG("LP_CLK_DIV %d, LP_CLK %ld\n", n, mhz);
7409+
7410+ REG_FLD_MOD(DSI_CLK_CTRL, n, 12, 0); /* LP_CLK_DIVISOR */
7411+ if (dsi_fclk > 30*1000*1000)
7412+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */
7413+
7414+ return 0;
7415+}
7416+
7417+
7418+enum dsi_pll_power_state {
7419+ DSI_PLL_POWER_OFF = 0x0,
7420+ DSI_PLL_POWER_ON_HSCLK = 0x1,
7421+ DSI_PLL_POWER_ON_ALL = 0x2,
7422+ DSI_PLL_POWER_ON_DIV = 0x3,
7423+};
7424+
7425+static int dsi_pll_power(enum dsi_pll_power_state state)
7426+{
7427+ int t = 0;
7428+
7429+ REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
7430+
7431+ /* PLL_PWR_STATUS */
7432+ while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
7433+ udelay(1);
7434+ if (t++ > 1000) {
7435+ DSSERR("Failed to set DSI PLL power mode to %d\n",
7436+ state);
7437+ return -ENODEV;
7438+ }
7439+ }
7440+
7441+ return 0;
7442+}
7443+
7444+int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck,
7445+ struct dsi_clock_info *cinfo)
7446+{
7447+ struct dsi_clock_info cur, best;
7448+ int min_fck_per_pck;
7449+ int match = 0;
7450+
7451+ if (req_pck == dsi.cache_req_pck &&
7452+ dsi.cache_cinfo.clkin == dss_clk_get_rate(DSS_CLK_FCK2)) {
7453+ DSSDBG("DSI clock info found from cache\n");
7454+ *cinfo = dsi.cache_cinfo;
7455+ return 0;
7456+ }
7457+
7458+ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
7459+
7460+ if (min_fck_per_pck &&
7461+ req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
7462+ DSSERR("Requested pixel clock not possible with the current "
7463+ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
7464+ "the constraint off.\n");
7465+ min_fck_per_pck = 0;
7466+ }
7467+
7468+ DSSDBG("dsi_pll_calc\n");
7469+
7470+retry:
7471+ memset(&best, 0, sizeof(best));
7472+
7473+ memset(&cur, 0, sizeof(cur));
7474+ cur.clkin = dss_clk_get_rate(DSS_CLK_FCK2);
7475+ cur.use_dss2_fck = 1;
7476+ cur.highfreq = 0;
7477+
7478+ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
7479+ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
7480+ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
7481+ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
7482+ if (cur.highfreq == 0)
7483+ cur.fint = cur.clkin / cur.regn;
7484+ else
7485+ cur.fint = cur.clkin / (2 * cur.regn);
7486+
7487+ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
7488+ continue;
7489+
7490+ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
7491+ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
7492+ unsigned long a, b;
7493+
7494+ a = 2 * cur.regm * (cur.clkin/1000);
7495+ b = cur.regn * (cur.highfreq + 1);
7496+ cur.dsiphy = a / b * 1000;
7497+
7498+ if (cur.dsiphy > 1800 * 1000 * 1000)
7499+ break;
7500+
7501+ /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
7502+ for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
7503+ ++cur.regm3) {
7504+ cur.dsi1_pll_fclk = cur.dsiphy / cur.regm3;
7505+
7506+ /* this will narrow down the search a bit,
7507+ * but still give pixclocks below what was
7508+ * requested */
7509+ if (cur.dsi1_pll_fclk < req_pck)
7510+ break;
7511+
7512+ if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
7513+ continue;
7514+
7515+ if (min_fck_per_pck &&
7516+ cur.dsi1_pll_fclk <
7517+ req_pck * min_fck_per_pck)
7518+ continue;
7519+
7520+ match = 1;
7521+
7522+ find_lck_pck_divs(is_tft, req_pck,
7523+ cur.dsi1_pll_fclk,
7524+ &cur.lck_div,
7525+ &cur.pck_div);
7526+
7527+ cur.lck = cur.dsi1_pll_fclk / cur.lck_div;
7528+ cur.pck = cur.lck / cur.pck_div;
7529+
7530+ if (abs(cur.pck - req_pck) <
7531+ abs(best.pck - req_pck)) {
7532+ best = cur;
7533+
7534+ if (cur.pck == req_pck)
7535+ goto found;
7536+ }
7537+ }
7538+ }
7539+ }
7540+found:
7541+ if (!match) {
7542+ if (min_fck_per_pck) {
7543+ DSSERR("Could not find suitable clock settings.\n"
7544+ "Turning FCK/PCK constraint off and"
7545+ "trying again.\n");
7546+ min_fck_per_pck = 0;
7547+ goto retry;
7548+ }
7549+
7550+ DSSERR("Could not find suitable clock settings.\n");
7551+
7552+ return -EINVAL;
7553+ }
7554+
7555+ /* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
7556+ best.regm4 = best.dsiphy / 48000000;
7557+ if (best.regm4 > REGM4_MAX)
7558+ best.regm4 = REGM4_MAX;
7559+ else if (best.regm4 == 0)
7560+ best.regm4 = 1;
7561+ best.dsi2_pll_fclk = best.dsiphy / best.regm4;
7562+
7563+ if (cinfo)
7564+ *cinfo = best;
7565+
7566+ dsi.cache_req_pck = req_pck;
7567+ dsi.cache_clk_freq = 0;
7568+ dsi.cache_cinfo = best;
7569+
7570+ return 0;
7571+}
7572+
7573+static int dsi_pll_calc_ddrfreq(unsigned long clk_freq,
7574+ struct dsi_clock_info *cinfo)
7575+{
7576+ struct dsi_clock_info cur, best;
7577+ const bool use_dss2_fck = 1;
7578+ unsigned long datafreq;
7579+
7580+ DSSDBG("dsi_pll_calc_ddrfreq\n");
7581+
7582+ if (clk_freq == dsi.cache_clk_freq &&
7583+ dsi.cache_cinfo.clkin == dss_clk_get_rate(DSS_CLK_FCK2)) {
7584+ DSSDBG("DSI clock info found from cache\n");
7585+ *cinfo = dsi.cache_cinfo;
7586+ return 0;
7587+ }
7588+
7589+ datafreq = clk_freq * 4;
7590+
7591+ memset(&best, 0, sizeof(best));
7592+
7593+ memset(&cur, 0, sizeof(cur));
7594+ cur.use_dss2_fck = use_dss2_fck;
7595+ if (use_dss2_fck) {
7596+ cur.clkin = dss_clk_get_rate(DSS_CLK_FCK2);
7597+ cur.highfreq = 0;
7598+ } else {
7599+ cur.clkin = dispc_pclk_rate();
7600+ if (cur.clkin < 32000000)
7601+ cur.highfreq = 0;
7602+ else
7603+ cur.highfreq = 1;
7604+ }
7605+
7606+ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
7607+ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
7608+ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
7609+ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
7610+ if (cur.highfreq == 0)
7611+ cur.fint = cur.clkin / cur.regn;
7612+ else
7613+ cur.fint = cur.clkin / (2 * cur.regn);
7614+
7615+ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
7616+ continue;
7617+
7618+ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
7619+ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
7620+ unsigned long a, b;
7621+
7622+ a = 2 * cur.regm * (cur.clkin/1000);
7623+ b = cur.regn * (cur.highfreq + 1);
7624+ cur.dsiphy = a / b * 1000;
7625+
7626+ if (cur.dsiphy > 1800 * 1000 * 1000)
7627+ break;
7628+
7629+ if (abs(cur.dsiphy - datafreq) <
7630+ abs(best.dsiphy - datafreq)) {
7631+ best = cur;
7632+ /* DSSDBG("best %ld\n", best.dsiphy); */
7633+ }
7634+
7635+ if (cur.dsiphy == datafreq)
7636+ goto found;
7637+ }
7638+ }
7639+found:
7640+ /* DSI1_PLL_FCLK (regm3) is not used. Set it to something sane. */
7641+ best.regm3 = best.dsiphy / 48000000;
7642+ if (best.regm3 > REGM3_MAX)
7643+ best.regm3 = REGM3_MAX;
7644+ else if (best.regm3 == 0)
7645+ best.regm3 = 1;
7646+ best.dsi1_pll_fclk = best.dsiphy / best.regm3;
7647+
7648+ /* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
7649+ best.regm4 = best.dsiphy / 48000000;
7650+ if (best.regm4 > REGM4_MAX)
7651+ best.regm4 = REGM4_MAX;
7652+ else if (best.regm4 == 0)
7653+ best.regm4 = 1;
7654+ best.dsi2_pll_fclk = best.dsiphy / best.regm4;
7655+
7656+ if (cinfo)
7657+ *cinfo = best;
7658+
7659+ dsi.cache_clk_freq = clk_freq;
7660+ dsi.cache_req_pck = 0;
7661+ dsi.cache_cinfo = best;
7662+
7663+ return 0;
7664+}
7665+
7666+int dsi_pll_program(struct dsi_clock_info *cinfo)
7667+{
7668+ int r = 0;
7669+ u32 l;
7670+
7671+ DSSDBG("dsi_pll_program\n");
7672+
7673+ dsi.dsiphy = cinfo->dsiphy;
7674+ dsi.ddr_clk = dsi.dsiphy / 4;
7675+ dsi.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
7676+ dsi.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
7677+
7678+ DSSDBG("DSI Fint %ld\n", cinfo->fint);
7679+
7680+ DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
7681+ cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
7682+ cinfo->clkin,
7683+ cinfo->highfreq);
7684+
7685+ /* DSIPHY == CLKIN4DDR */
7686+ DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n",
7687+ cinfo->regm,
7688+ cinfo->regn,
7689+ cinfo->clkin,
7690+ cinfo->highfreq + 1,
7691+ cinfo->dsiphy);
7692+
7693+ DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
7694+ dsi.dsiphy / 1000 / 1000 / 2);
7695+
7696+ DSSDBG("Clock lane freq %ld Hz\n", dsi.ddr_clk);
7697+
7698+ DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
7699+ cinfo->regm3, cinfo->dsi1_pll_fclk);
7700+ DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
7701+ cinfo->regm4, cinfo->dsi2_pll_fclk);
7702+
7703+ REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
7704+
7705+ l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
7706+ l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
7707+ l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
7708+ l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
7709+ l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19); /* DSI_CLOCK_DIV */
7710+ l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23); /* DSIPROTO_CLOCK_DIV */
7711+ dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
7712+
7713+ l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
7714+ l = FLD_MOD(l, 7, 4, 1); /* DSI_PLL_FREQSEL */
7715+ /* DSI_PLL_CLKSEL */
7716+ l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11);
7717+ l = FLD_MOD(l, cinfo->highfreq, 12, 12); /* DSI_PLL_HIGHFREQ */
7718+ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
7719+ l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
7720+ l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
7721+ dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
7722+
7723+ REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
7724+
7725+ if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
7726+ DSSERR("dsi pll go bit not going down.\n");
7727+ r = -EIO;
7728+ goto err;
7729+ }
7730+
7731+ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
7732+ DSSERR("cannot lock PLL\n");
7733+ r = -EIO;
7734+ goto err;
7735+ }
7736+
7737+ dsi.pll_locked = 1;
7738+
7739+ l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
7740+ l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
7741+ l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
7742+ l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
7743+ l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
7744+ l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
7745+ l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
7746+ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
7747+ l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
7748+ l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
7749+ l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
7750+ l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
7751+ l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
7752+ l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
7753+ l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
7754+ dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
7755+
7756+ DSSDBG("PLL config done\n");
7757+err:
7758+ return r;
7759+}
7760+
7761+int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
7762+{
7763+ int r = 0;
7764+ enum dsi_pll_power_state pwstate;
7765+ struct dispc_clock_info cinfo;
7766+
7767+ DSSDBG("PLL init\n");
7768+
7769+ enable_clocks(1);
7770+ dsi_enable_pll_clock(1);
7771+
7772+ /* configure dispc fck and pixel clock to something sane */
7773+ r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
7774+ if (r)
7775+ goto err0;
7776+
7777+ r = dispc_set_clock_div(&cinfo);
7778+ if (r) {
7779+ DSSERR("Failed to set basic clocks\n");
7780+ goto err0;
7781+ }
7782+
7783+ r = dss_dsi_power_up();
7784+ if (r)
7785+ goto err0;
7786+
7787+ /* PLL does not come out of reset without this... */
7788+ dispc_pck_free_enable(1);
7789+
7790+ if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
7791+ DSSERR("PLL not coming out of reset.\n");
7792+ r = -ENODEV;
7793+ goto err1;
7794+ }
7795+
7796+ /* ... but if left on, we get problems when planes do not
7797+ * fill the whole display. No idea about this XXX */
7798+ dispc_pck_free_enable(0);
7799+
7800+ if (enable_hsclk && enable_hsdiv)
7801+ pwstate = DSI_PLL_POWER_ON_ALL;
7802+ else if (enable_hsclk)
7803+ pwstate = DSI_PLL_POWER_ON_HSCLK;
7804+ else if (enable_hsdiv)
7805+ pwstate = DSI_PLL_POWER_ON_DIV;
7806+ else
7807+ pwstate = DSI_PLL_POWER_OFF;
7808+
7809+ r = dsi_pll_power(pwstate);
7810+
7811+ if (r)
7812+ goto err1;
7813+
7814+ DSSDBG("PLL init done\n");
7815+
7816+ return 0;
7817+err1:
7818+ dss_dsi_power_down();
7819+err0:
7820+ enable_clocks(0);
7821+ dsi_enable_pll_clock(0);
7822+ return r;
7823+}
7824+
7825+void dsi_pll_uninit(void)
7826+{
7827+ enable_clocks(0);
7828+ dsi_enable_pll_clock(0);
7829+
7830+ dsi.pll_locked = 0;
7831+ dsi_pll_power(DSI_PLL_POWER_OFF);
7832+ dss_dsi_power_down();
7833+ DSSDBG("PLL uninit done\n");
7834+}
7835+
7836+unsigned long dsi_get_dsi1_pll_rate(void)
7837+{
7838+ return dsi.dsi1_pll_fclk;
7839+}
7840+
7841+unsigned long dsi_get_dsi2_pll_rate(void)
7842+{
7843+ return dsi.dsi2_pll_fclk;
7844+}
7845+
7846+void dsi_dump_clocks(struct seq_file *s)
7847+{
7848+ int clksel;
7849+
7850+ enable_clocks(1);
7851+
7852+ clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
7853+
7854+ seq_printf(s, "- dsi -\n");
7855+
7856+ seq_printf(s, "dsi fclk source = %s\n",
7857+ dss_get_dsi_clk_source() == 0 ?
7858+ "dss1_alwon_fclk" : "dsi2_pll_fclk");
7859+
7860+ seq_printf(s, "dsi pll source = %s\n",
7861+ clksel == 0 ?
7862+ "dss2_alwon_fclk" : "pclkfree");
7863+
7864+ seq_printf(s, "DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n",
7865+ dsi.dsiphy, dsi.ddr_clk);
7866+
7867+ seq_printf(s, "dsi1_pll_fck\t%lu (%s)\n"
7868+ "dsi2_pll_fck\t%lu (%s)\n",
7869+ dsi.dsi1_pll_fclk,
7870+ dss_get_dispc_clk_source() == 0 ? "off" : "on",
7871+ dsi.dsi2_pll_fclk,
7872+ dss_get_dsi_clk_source() == 0 ? "off" : "on");
7873+
7874+ enable_clocks(0);
7875+}
7876+
7877+void dsi_dump_regs(struct seq_file *s)
7878+{
7879+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
7880+
7881+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
7882+
7883+ DUMPREG(DSI_REVISION);
7884+ DUMPREG(DSI_SYSCONFIG);
7885+ DUMPREG(DSI_SYSSTATUS);
7886+ DUMPREG(DSI_IRQSTATUS);
7887+ DUMPREG(DSI_IRQENABLE);
7888+ DUMPREG(DSI_CTRL);
7889+ DUMPREG(DSI_COMPLEXIO_CFG1);
7890+ DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
7891+ DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
7892+ DUMPREG(DSI_CLK_CTRL);
7893+ DUMPREG(DSI_TIMING1);
7894+ DUMPREG(DSI_TIMING2);
7895+ DUMPREG(DSI_VM_TIMING1);
7896+ DUMPREG(DSI_VM_TIMING2);
7897+ DUMPREG(DSI_VM_TIMING3);
7898+ DUMPREG(DSI_CLK_TIMING);
7899+ DUMPREG(DSI_TX_FIFO_VC_SIZE);
7900+ DUMPREG(DSI_RX_FIFO_VC_SIZE);
7901+ DUMPREG(DSI_COMPLEXIO_CFG2);
7902+ DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
7903+ DUMPREG(DSI_VM_TIMING4);
7904+ DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
7905+ DUMPREG(DSI_VM_TIMING5);
7906+ DUMPREG(DSI_VM_TIMING6);
7907+ DUMPREG(DSI_VM_TIMING7);
7908+ DUMPREG(DSI_STOPCLK_TIMING);
7909+
7910+ DUMPREG(DSI_VC_CTRL(0));
7911+ DUMPREG(DSI_VC_TE(0));
7912+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
7913+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
7914+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
7915+ DUMPREG(DSI_VC_IRQSTATUS(0));
7916+ DUMPREG(DSI_VC_IRQENABLE(0));
7917+
7918+ DUMPREG(DSI_VC_CTRL(1));
7919+ DUMPREG(DSI_VC_TE(1));
7920+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
7921+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
7922+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
7923+ DUMPREG(DSI_VC_IRQSTATUS(1));
7924+ DUMPREG(DSI_VC_IRQENABLE(1));
7925+
7926+ DUMPREG(DSI_VC_CTRL(2));
7927+ DUMPREG(DSI_VC_TE(2));
7928+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
7929+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
7930+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
7931+ DUMPREG(DSI_VC_IRQSTATUS(2));
7932+ DUMPREG(DSI_VC_IRQENABLE(2));
7933+
7934+ DUMPREG(DSI_VC_CTRL(3));
7935+ DUMPREG(DSI_VC_TE(3));
7936+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
7937+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
7938+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
7939+ DUMPREG(DSI_VC_IRQSTATUS(3));
7940+ DUMPREG(DSI_VC_IRQENABLE(3));
7941+
7942+ DUMPREG(DSI_DSIPHY_CFG0);
7943+ DUMPREG(DSI_DSIPHY_CFG1);
7944+ DUMPREG(DSI_DSIPHY_CFG2);
7945+ DUMPREG(DSI_DSIPHY_CFG5);
7946+
7947+ DUMPREG(DSI_PLL_CONTROL);
7948+ DUMPREG(DSI_PLL_STATUS);
7949+ DUMPREG(DSI_PLL_GO);
7950+ DUMPREG(DSI_PLL_CONFIGURATION1);
7951+ DUMPREG(DSI_PLL_CONFIGURATION2);
7952+
7953+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
7954+#undef DUMPREG
7955+}
7956+
7957+enum dsi_complexio_power_state {
7958+ DSI_COMPLEXIO_POWER_OFF = 0x0,
7959+ DSI_COMPLEXIO_POWER_ON = 0x1,
7960+ DSI_COMPLEXIO_POWER_ULPS = 0x2,
7961+};
7962+
7963+static int dsi_complexio_power(enum dsi_complexio_power_state state)
7964+{
7965+ int t = 0;
7966+
7967+ /* PWR_CMD */
7968+ REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
7969+
7970+ /* PWR_STATUS */
7971+ while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
7972+ udelay(1);
7973+ if (t++ > 1000) {
7974+ DSSERR("failed to set complexio power state to "
7975+ "%d\n", state);
7976+ return -ENODEV;
7977+ }
7978+ }
7979+
7980+ return 0;
7981+}
7982+
7983+static void dsi_complexio_config(struct omap_display *display)
7984+{
7985+ u32 r;
7986+
7987+ int clk_lane = display->hw_config.u.dsi.clk_lane;
7988+ int data1_lane = display->hw_config.u.dsi.data1_lane;
7989+ int data2_lane = display->hw_config.u.dsi.data2_lane;
7990+ int clk_pol = display->hw_config.u.dsi.clk_pol;
7991+ int data1_pol = display->hw_config.u.dsi.data1_pol;
7992+ int data2_pol = display->hw_config.u.dsi.data2_pol;
7993+
7994+ r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
7995+ r = FLD_MOD(r, clk_lane, 2, 0);
7996+ r = FLD_MOD(r, clk_pol, 3, 3);
7997+ r = FLD_MOD(r, data1_lane, 6, 4);
7998+ r = FLD_MOD(r, data1_pol, 7, 7);
7999+ r = FLD_MOD(r, data2_lane, 10, 8);
8000+ r = FLD_MOD(r, data2_pol, 11, 11);
8001+ dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
8002+
8003+ /* The configuration of the DSI complex I/O (number of data lanes,
8004+ position, differential order) should not be changed while
8005+ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
8006+ the hardware to take into account a new configuration of the complex
8007+ I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
8008+ follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
8009+ then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
8010+ DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
8011+ DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
8012+ DSI complex I/O configuration is unknown. */
8013+
8014+ /*
8015+ REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
8016+ REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
8017+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
8018+ REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
8019+ */
8020+}
8021+
8022+static inline unsigned ns2ddr(unsigned ns)
8023+{
8024+ /* convert time in ns to ddr ticks, rounding up */
8025+ return (ns * (dsi.ddr_clk/1000/1000) + 999) / 1000;
8026+}
8027+
8028+static inline unsigned ddr2ns(unsigned ddr)
8029+{
8030+ return ddr * 1000 * 1000 / (dsi.ddr_clk / 1000);
8031+}
8032+
8033+static void dsi_complexio_timings(void)
8034+{
8035+ u32 r;
8036+ u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
8037+ u32 tlpx_half, tclk_trail, tclk_zero;
8038+ u32 tclk_prepare;
8039+
8040+ /* calculate timings */
8041+
8042+ /* 1 * DDR_CLK = 2 * UI */
8043+
8044+ /* min 40ns + 4*UI max 85ns + 6*UI */
8045+ ths_prepare = ns2ddr(59) + 2;
8046+
8047+ /* min 145ns + 10*UI */
8048+ ths_prepare_ths_zero = ns2ddr(145) + 5;
8049+
8050+ /* min max(8*UI, 60ns+4*UI) */
8051+ ths_trail = max((unsigned)4, ns2ddr(60) + 2);
8052+
8053+ /* min 100ns */
8054+ ths_exit = ns2ddr(100);
8055+
8056+ /* tlpx min 50n */
8057+ tlpx_half = ns2ddr(25);
8058+
8059+ /* min 60ns */
8060+ tclk_trail = ns2ddr(60);
8061+
8062+ /* min 38ns, max 95ns */
8063+ tclk_prepare = ns2ddr(38);
8064+
8065+ /* min tclk-prepare + tclk-zero = 300ns */
8066+ tclk_zero = ns2ddr(300 - 38);
8067+
8068+ DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
8069+ ths_prepare, ddr2ns(ths_prepare),
8070+ ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
8071+ DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
8072+ ths_trail, ddr2ns(ths_trail),
8073+ ths_exit, ddr2ns(ths_exit));
8074+
8075+ DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
8076+ "tclk_zero %u (%uns)\n",
8077+ tlpx_half, ddr2ns(tlpx_half),
8078+ tclk_trail, ddr2ns(tclk_trail),
8079+ tclk_zero, ddr2ns(tclk_zero));
8080+ DSSDBG("tclk_prepare %u (%uns)\n",
8081+ tclk_prepare, ddr2ns(tclk_prepare));
8082+
8083+ /* program timings */
8084+
8085+ r = dsi_read_reg(DSI_DSIPHY_CFG0);
8086+ r = FLD_MOD(r, ths_prepare, 31, 24);
8087+ r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
8088+ r = FLD_MOD(r, ths_trail, 15, 8);
8089+ r = FLD_MOD(r, ths_exit, 7, 0);
8090+ dsi_write_reg(DSI_DSIPHY_CFG0, r);
8091+
8092+ r = dsi_read_reg(DSI_DSIPHY_CFG1);
8093+ r = FLD_MOD(r, tlpx_half, 22, 16);
8094+ r = FLD_MOD(r, tclk_trail, 15, 8);
8095+ r = FLD_MOD(r, tclk_zero, 7, 0);
8096+ dsi_write_reg(DSI_DSIPHY_CFG1, r);
8097+
8098+ r = dsi_read_reg(DSI_DSIPHY_CFG2);
8099+ r = FLD_MOD(r, tclk_prepare, 7, 0);
8100+ dsi_write_reg(DSI_DSIPHY_CFG2, r);
8101+}
8102+
8103+
8104+static int dsi_complexio_init(struct omap_display *display)
8105+{
8106+ int r = 0;
8107+
8108+ DSSDBG("dsi_complexio_init\n");
8109+
8110+ /* CIO_CLK_ICG, enable L3 clk to CIO */
8111+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
8112+
8113+ /* A dummy read using the SCP interface to any DSIPHY register is
8114+ * required after DSIPHY reset to complete the reset of the DSI complex
8115+ * I/O. */
8116+ dsi_read_reg(DSI_DSIPHY_CFG5);
8117+
8118+ if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
8119+ DSSERR("ComplexIO PHY not coming out of reset.\n");
8120+ r = -ENODEV;
8121+ goto err;
8122+ }
8123+
8124+ dsi_complexio_config(display);
8125+
8126+ r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
8127+
8128+ if (r)
8129+ goto err;
8130+
8131+ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
8132+ DSSERR("ComplexIO not coming out of reset.\n");
8133+ r = -ENODEV;
8134+ goto err;
8135+ }
8136+
8137+ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
8138+ DSSERR("ComplexIO LDO power down.\n");
8139+ r = -ENODEV;
8140+ goto err;
8141+ }
8142+
8143+ dsi_complexio_timings();
8144+
8145+ /*
8146+ The configuration of the DSI complex I/O (number of data lanes,
8147+ position, differential order) should not be changed while
8148+ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
8149+ hardware to recognize a new configuration of the complex I/O (done
8150+ in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
8151+ this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
8152+ reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
8153+ LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
8154+ bit to 1. If the sequence is not followed, the DSi complex I/O
8155+ configuration is undetermined.
8156+ */
8157+ dsi_if_enable(1);
8158+ dsi_if_enable(0);
8159+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
8160+ dsi_if_enable(1);
8161+ dsi_if_enable(0);
8162+
8163+ DSSDBG("CIO init done\n");
8164+err:
8165+ return r;
8166+}
8167+
8168+static void dsi_complexio_uninit(void)
8169+{
8170+ dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
8171+}
8172+
8173+static int _dsi_wait_reset(void)
8174+{
8175+ int i = 0;
8176+
8177+ while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
8178+ if (i++ > 5) {
8179+ DSSERR("soft reset failed\n");
8180+ return -ENODEV;
8181+ }
8182+ udelay(1);
8183+ }
8184+
8185+ return 0;
8186+}
8187+
8188+static int _dsi_reset(void)
8189+{
8190+ /* Soft reset */
8191+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
8192+ return _dsi_wait_reset();
8193+}
8194+
8195+
8196+static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
8197+ enum fifo_size size3, enum fifo_size size4)
8198+{
8199+ u32 r = 0;
8200+ int add = 0;
8201+ int i;
8202+
8203+ dsi.vc[0].fifo_size = size1;
8204+ dsi.vc[1].fifo_size = size2;
8205+ dsi.vc[2].fifo_size = size3;
8206+ dsi.vc[3].fifo_size = size4;
8207+
8208+ for (i = 0; i < 4; i++) {
8209+ u8 v;
8210+ int size = dsi.vc[i].fifo_size;
8211+
8212+ if (add + size > 4) {
8213+ DSSERR("Illegal FIFO configuration\n");
8214+ BUG();
8215+ }
8216+
8217+ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
8218+ r |= v << (8 * i);
8219+ /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
8220+ add += size;
8221+ }
8222+
8223+ dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
8224+}
8225+
8226+static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
8227+ enum fifo_size size3, enum fifo_size size4)
8228+{
8229+ u32 r = 0;
8230+ int add = 0;
8231+ int i;
8232+
8233+ dsi.vc[0].fifo_size = size1;
8234+ dsi.vc[1].fifo_size = size2;
8235+ dsi.vc[2].fifo_size = size3;
8236+ dsi.vc[3].fifo_size = size4;
8237+
8238+ for (i = 0; i < 4; i++) {
8239+ u8 v;
8240+ int size = dsi.vc[i].fifo_size;
8241+
8242+ if (add + size > 4) {
8243+ DSSERR("Illegal FIFO configuration\n");
8244+ BUG();
8245+ }
8246+
8247+ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
8248+ r |= v << (8 * i);
8249+ /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
8250+ add += size;
8251+ }
8252+
8253+ dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
8254+}
8255+
8256+static int dsi_force_tx_stop_mode_io(void)
8257+{
8258+ u32 r;
8259+
8260+ r = dsi_read_reg(DSI_TIMING1);
8261+ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
8262+ dsi_write_reg(DSI_TIMING1, r);
8263+
8264+ if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
8265+ DSSERR("TX_STOP bit not going down\n");
8266+ return -EIO;
8267+ }
8268+
8269+ return 0;
8270+}
8271+
8272+static void dsi_vc_print_status(int channel)
8273+{
8274+ u32 r;
8275+
8276+ r = dsi_read_reg(DSI_VC_CTRL(channel));
8277+ DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
8278+ "TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
8279+ channel,
8280+ FLD_GET(r, 5, 5),
8281+ FLD_GET(r, 6, 6),
8282+ FLD_GET(r, 15, 15),
8283+ FLD_GET(r, 16, 16),
8284+ FLD_GET(r, 20, 20));
8285+
8286+ r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS);
8287+ DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);
8288+}
8289+
8290+static void dsi_vc_config(int channel)
8291+{
8292+ u32 r;
8293+
8294+ DSSDBG("dsi_vc_config %d\n", channel);
8295+
8296+ r = dsi_read_reg(DSI_VC_CTRL(channel));
8297+
8298+ r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
8299+ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
8300+ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
8301+ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
8302+ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
8303+ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
8304+ r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
8305+
8306+ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
8307+ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
8308+
8309+ dsi_write_reg(DSI_VC_CTRL(channel), r);
8310+}
8311+
8312+static void dsi_vc_config_vp(int channel)
8313+{
8314+ u32 r;
8315+
8316+ DSSDBG("dsi_vc_config_vp\n");
8317+
8318+ r = dsi_read_reg(DSI_VC_CTRL(channel));
8319+
8320+ r = FLD_MOD(r, 1, 1, 1); /* SOURCE, 1 = video port */
8321+ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
8322+ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
8323+ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
8324+ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
8325+ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
8326+ r = FLD_MOD(r, 1, 9, 9); /* MODE_SPEED, high speed on/off */
8327+
8328+ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
8329+ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
8330+
8331+ dsi_write_reg(DSI_VC_CTRL(channel), r);
8332+}
8333+
8334+
8335+static int dsi_vc_enable(int channel, bool enable)
8336+{
8337+ DSSDBG("dsi_vc_enable channel %d, enable %d\n", channel, enable);
8338+
8339+ enable = enable ? 1 : 0;
8340+
8341+ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
8342+
8343+ if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
8344+ DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
8345+ return -EIO;
8346+ }
8347+
8348+ return 0;
8349+}
8350+
8351+static void dsi_vc_enable_hs(int channel, bool enable)
8352+{
8353+ DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
8354+
8355+ dsi_vc_enable(channel, 0);
8356+ dsi_if_enable(0);
8357+
8358+ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
8359+
8360+ dsi_vc_enable(channel, 1);
8361+ dsi_if_enable(1);
8362+
8363+ dsi_force_tx_stop_mode_io();
8364+}
8365+
8366+static void dsi_vc_flush_long_data(int channel)
8367+{
8368+ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
8369+ u32 val;
8370+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
8371+ DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
8372+ (val >> 0) & 0xff,
8373+ (val >> 8) & 0xff,
8374+ (val >> 16) & 0xff,
8375+ (val >> 24) & 0xff);
8376+ }
8377+}
8378+
8379+static void dsi_show_rx_ack_with_err(u16 err)
8380+{
8381+ DSSERR("\tACK with ERROR (%#x):\n", err);
8382+ if (err & (1 << 0))
8383+ DSSERR("\t\tSoT Error\n");
8384+ if (err & (1 << 1))
8385+ DSSERR("\t\tSoT Sync Error\n");
8386+ if (err & (1 << 2))
8387+ DSSERR("\t\tEoT Sync Error\n");
8388+ if (err & (1 << 3))
8389+ DSSERR("\t\tEscape Mode Entry Command Error\n");
8390+ if (err & (1 << 4))
8391+ DSSERR("\t\tLP Transmit Sync Error\n");
8392+ if (err & (1 << 5))
8393+ DSSERR("\t\tHS Receive Timeout Error\n");
8394+ if (err & (1 << 6))
8395+ DSSERR("\t\tFalse Control Error\n");
8396+ if (err & (1 << 7))
8397+ DSSERR("\t\t(reserved7)\n");
8398+ if (err & (1 << 8))
8399+ DSSERR("\t\tECC Error, single-bit (corrected)\n");
8400+ if (err & (1 << 9))
8401+ DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
8402+ if (err & (1 << 10))
8403+ DSSERR("\t\tChecksum Error\n");
8404+ if (err & (1 << 11))
8405+ DSSERR("\t\tData type not recognized\n");
8406+ if (err & (1 << 12))
8407+ DSSERR("\t\tInvalid VC ID\n");
8408+ if (err & (1 << 13))
8409+ DSSERR("\t\tInvalid Transmission Length\n");
8410+ if (err & (1 << 14))
8411+ DSSERR("\t\t(reserved14)\n");
8412+ if (err & (1 << 15))
8413+ DSSERR("\t\tDSI Protocol Violation\n");
8414+}
8415+
8416+static u16 dsi_vc_flush_receive_data(int channel)
8417+{
8418+ /* RX_FIFO_NOT_EMPTY */
8419+ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
8420+ u32 val;
8421+ u8 dt;
8422+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
8423+ DSSDBG("\trawval %#08x\n", val);
8424+ dt = FLD_GET(val, 5, 0);
8425+ if (dt == DSI_DT_RX_ACK_WITH_ERR) {
8426+ u16 err = FLD_GET(val, 23, 8);
8427+ dsi_show_rx_ack_with_err(err);
8428+ } else if (dt == DSI_DT_RX_SHORT_READ_1) {
8429+ DSSDBG("\tDCS short response, 1 byte: %#x\n",
8430+ FLD_GET(val, 23, 8));
8431+ } else if (dt == DSI_DT_RX_SHORT_READ_2) {
8432+ DSSDBG("\tDCS short response, 2 byte: %#x\n",
8433+ FLD_GET(val, 23, 8));
8434+ } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
8435+ DSSDBG("\tDCS long response, len %d\n",
8436+ FLD_GET(val, 23, 8));
8437+ dsi_vc_flush_long_data(channel);
8438+ } else {
8439+ DSSERR("\tunknown datatype 0x%02x\n", dt);
8440+ }
8441+ }
8442+ return 0;
8443+}
8444+
8445+static int dsi_vc_send_bta(int channel)
8446+{
8447+ unsigned long tmo;
8448+
8449+ /*DSSDBG("dsi_vc_send_bta_sync %d\n", channel); */
8450+
8451+ if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
8452+ DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
8453+ dsi_vc_flush_receive_data(channel);
8454+ }
8455+
8456+ REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
8457+
8458+ tmo = jiffies + msecs_to_jiffies(10);
8459+ while (REG_GET(DSI_VC_CTRL(channel), 6, 6) == 1) {
8460+ if (time_after(jiffies, tmo)) {
8461+ DSSERR("Failed to send BTA\n");
8462+ return -EIO;
8463+ }
8464+ }
8465+
8466+ return 0;
8467+}
8468+
8469+static int dsi_vc_send_bta_sync(int channel)
8470+{
8471+ int r = 0;
8472+
8473+ init_completion(&dsi.bta_completion);
8474+
8475+ dsi_vc_enable_bta_irq(channel);
8476+
8477+ r = dsi_vc_send_bta(channel);
8478+ if (r)
8479+ goto err;
8480+
8481+ if (wait_for_completion_timeout(&dsi.bta_completion,
8482+ msecs_to_jiffies(500)) == 0) {
8483+ DSSERR("Failed to receive BTA\n");
8484+ r = -EIO;
8485+ goto err;
8486+ }
8487+err:
8488+ dsi_vc_disable_bta_irq(channel);
8489+
8490+ return r;
8491+}
8492+
8493+static inline void dsi_vc_write_long_header(int channel, u8 data_type,
8494+ u16 len, u8 ecc)
8495+{
8496+ u32 val;
8497+ u8 data_id;
8498+
8499+ /*data_id = data_type | channel << 6; */
8500+ data_id = data_type | dsi.vc[channel].dest_per << 6;
8501+
8502+ val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
8503+ FLD_VAL(ecc, 31, 24);
8504+
8505+ dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
8506+}
8507+
8508+static inline void dsi_vc_write_long_payload(int channel,
8509+ u8 b1, u8 b2, u8 b3, u8 b4)
8510+{
8511+ u32 val;
8512+
8513+ val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
8514+
8515+/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
8516+ b1, b2, b3, b4, val); */
8517+
8518+ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
8519+}
8520+
8521+static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
8522+ u8 ecc)
8523+{
8524+ /*u32 val; */
8525+ int i;
8526+ u8 *p;
8527+ int r = 0;
8528+ u8 b1, b2, b3, b4;
8529+
8530+ if (dsi.debug_write)
8531+ DSSDBG("dsi_vc_send_long, %d bytes\n", len);
8532+
8533+ /* len + header */
8534+ if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
8535+ DSSERR("unable to send long packet: packet too long.\n");
8536+ return -EINVAL;
8537+ }
8538+
8539+ dsi_vc_write_long_header(channel, data_type, len, ecc);
8540+
8541+ /*dsi_vc_print_status(0); */
8542+
8543+ p = data;
8544+ for (i = 0; i < len >> 2; i++) {
8545+ if (dsi.debug_write)
8546+ DSSDBG("\tsending full packet %d\n", i);
8547+ /*dsi_vc_print_status(0); */
8548+
8549+ b1 = *p++;
8550+ b2 = *p++;
8551+ b3 = *p++;
8552+ b4 = *p++;
8553+
8554+ dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
8555+ }
8556+
8557+ i = len % 4;
8558+ if (i) {
8559+ b1 = 0; b2 = 0; b3 = 0;
8560+
8561+ if (dsi.debug_write)
8562+ DSSDBG("\tsending remainder bytes %d\n", i);
8563+
8564+ switch (i) {
8565+ case 3:
8566+ b1 = *p++;
8567+ b2 = *p++;
8568+ b3 = *p++;
8569+ break;
8570+ case 2:
8571+ b1 = *p++;
8572+ b2 = *p++;
8573+ break;
8574+ case 1:
8575+ b1 = *p++;
8576+ break;
8577+ }
8578+
8579+ dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
8580+ }
8581+
8582+ return r;
8583+}
8584+
8585+static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
8586+{
8587+ u32 r;
8588+ u8 data_id;
8589+
8590+ if (dsi.debug_write)
8591+ DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
8592+ channel,
8593+ data_type, data & 0xff, (data >> 8) & 0xff);
8594+
8595+ if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
8596+ DSSERR("ERROR FIFO FULL, aborting transfer\n");
8597+ return -EINVAL;
8598+ }
8599+
8600+ data_id = data_type | channel << 6;
8601+
8602+ r = (data_id << 0) | (data << 8) | (ecc << 24);
8603+
8604+ dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
8605+
8606+ return 0;
8607+}
8608+
8609+int dsi_vc_send_null(int channel)
8610+{
8611+ u8 nullpkg[] = {0, 0, 0, 0};
8612+ return dsi_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
8613+}
8614+EXPORT_SYMBOL(dsi_vc_send_null);
8615+
8616+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
8617+{
8618+ int r;
8619+
8620+ BUG_ON(len == 0);
8621+
8622+ if (len == 1) {
8623+ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
8624+ data[0], 0);
8625+ } else if (len == 2) {
8626+ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
8627+ data[0] | (data[1] << 8), 0);
8628+ } else {
8629+ /* 0x39 = DCS Long Write */
8630+ r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
8631+ data, len, 0);
8632+ }
8633+
8634+ return r;
8635+}
8636+EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
8637+
8638+int dsi_vc_dcs_write(int channel, u8 *data, int len)
8639+{
8640+ int r;
8641+
8642+ r = dsi_vc_dcs_write_nosync(channel, data, len);
8643+ if (r)
8644+ return r;
8645+
8646+ /* Some devices need time to process the msg in low power mode.
8647+ This also makes the write synchronous, and checks that
8648+ the peripheral is still alive */
8649+ r = dsi_vc_send_bta_sync(channel);
8650+
8651+ return r;
8652+}
8653+EXPORT_SYMBOL(dsi_vc_dcs_write);
8654+
8655+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
8656+{
8657+ u32 val;
8658+ u8 dt;
8659+ int r;
8660+
8661+ if (dsi.debug_read)
8662+ DSSDBG("dsi_vc_dcs_read\n");
8663+
8664+ r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
8665+ if (r)
8666+ return r;
8667+
8668+ r = dsi_vc_send_bta_sync(channel);
8669+ if (r)
8670+ return r;
8671+
8672+ if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) { /* RX_FIFO_NOT_EMPTY */
8673+ DSSERR("RX fifo empty when trying to read.\n");
8674+ return -EIO;
8675+ }
8676+
8677+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
8678+ if (dsi.debug_read)
8679+ DSSDBG("\theader: %08x\n", val);
8680+ dt = FLD_GET(val, 5, 0);
8681+ if (dt == DSI_DT_RX_ACK_WITH_ERR) {
8682+ u16 err = FLD_GET(val, 23, 8);
8683+ dsi_show_rx_ack_with_err(err);
8684+ return -1;
8685+
8686+ } else if (dt == DSI_DT_RX_SHORT_READ_1) {
8687+ u8 data = FLD_GET(val, 15, 8);
8688+ if (dsi.debug_read)
8689+ DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
8690+
8691+ if (buflen < 1)
8692+ return -1;
8693+
8694+ buf[0] = data;
8695+
8696+ return 1;
8697+ } else if (dt == DSI_DT_RX_SHORT_READ_2) {
8698+ u16 data = FLD_GET(val, 23, 8);
8699+ if (dsi.debug_read)
8700+ DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
8701+
8702+ if (buflen < 2)
8703+ return -1;
8704+
8705+ buf[0] = data & 0xff;
8706+ buf[1] = (data >> 8) & 0xff;
8707+
8708+ return 2;
8709+ } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
8710+ int w;
8711+ int len = FLD_GET(val, 23, 8);
8712+ if (dsi.debug_read)
8713+ DSSDBG("\tDCS long response, len %d\n", len);
8714+
8715+ if (len > buflen)
8716+ return -1;
8717+
8718+ /* two byte checksum ends the packet, not included in len */
8719+ for (w = 0; w < len + 2;) {
8720+ int b;
8721+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
8722+ if (dsi.debug_read)
8723+ DSSDBG("\t\t%02x %02x %02x %02x\n",
8724+ (val >> 0) & 0xff,
8725+ (val >> 8) & 0xff,
8726+ (val >> 16) & 0xff,
8727+ (val >> 24) & 0xff);
8728+
8729+ for (b = 0; b < 4; ++b) {
8730+ if (w < len)
8731+ buf[w] = (val >> (b * 8)) & 0xff;
8732+ /* we discard the 2 byte checksum */
8733+ ++w;
8734+ }
8735+ }
8736+
8737+ return len;
8738+
8739+ } else {
8740+ DSSERR("\tunknown datatype 0x%02x\n", dt);
8741+ return -1;
8742+ }
8743+}
8744+EXPORT_SYMBOL(dsi_vc_dcs_read);
8745+
8746+
8747+int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
8748+{
8749+ return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
8750+ len, 0);
8751+}
8752+EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
8753+
8754+
8755+static int dsi_set_lp_rx_timeout(int ns, int x4, int x16)
8756+{
8757+ u32 r;
8758+ unsigned long fck;
8759+ int ticks;
8760+
8761+ /* ticks in DSI_FCK */
8762+
8763+ fck = dsi_fclk_rate();
8764+ ticks = (fck / 1000 / 1000) * ns / 1000;
8765+
8766+ if (ticks > 0x1fff) {
8767+ DSSERR("LP_TX_TO too high\n");
8768+ return -EINVAL;
8769+ }
8770+
8771+ r = dsi_read_reg(DSI_TIMING2);
8772+ r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
8773+ r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */
8774+ r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */
8775+ r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
8776+ dsi_write_reg(DSI_TIMING2, r);
8777+
8778+ DSSDBG("LP_RX_TO %ld ns (%#x ticks)\n",
8779+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
8780+ (fck / 1000 / 1000),
8781+ ticks);
8782+
8783+ return 0;
8784+}
8785+
8786+static int dsi_set_ta_timeout(int ns, int x8, int x16)
8787+{
8788+ u32 r;
8789+ unsigned long fck;
8790+ int ticks;
8791+
8792+ /* ticks in DSI_FCK */
8793+
8794+ fck = dsi_fclk_rate();
8795+ ticks = (fck / 1000 / 1000) * ns / 1000;
8796+
8797+ if (ticks > 0x1fff) {
8798+ DSSERR("TA_TO too high\n");
8799+ return -EINVAL;
8800+ }
8801+
8802+ r = dsi_read_reg(DSI_TIMING1);
8803+ r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
8804+ r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */
8805+ r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */
8806+ r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
8807+ dsi_write_reg(DSI_TIMING1, r);
8808+
8809+ DSSDBG("TA_TO %ld ns (%#x ticks)\n",
8810+ (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
8811+ (fck / 1000 / 1000),
8812+ ticks);
8813+
8814+ return 0;
8815+}
8816+
8817+static int dsi_set_stop_state_counter(int ns, int x4, int x16)
8818+{
8819+ u32 r;
8820+ unsigned long fck;
8821+ int ticks;
8822+
8823+ /* ticks in DSI_FCK */
8824+
8825+ fck = dsi_fclk_rate();
8826+ ticks = (fck / 1000 / 1000) * ns / 1000;
8827+
8828+ if (ticks > 0x1fff) {
8829+ DSSERR("STOP_STATE_COUNTER_IO too high\n");
8830+ return -EINVAL;
8831+ }
8832+
8833+ r = dsi_read_reg(DSI_TIMING1);
8834+ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
8835+ r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */
8836+ r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */
8837+ r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
8838+ dsi_write_reg(DSI_TIMING1, r);
8839+
8840+ DSSDBG("STOP_STATE_COUNTER %ld ns (%#x ticks)\n",
8841+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
8842+ (fck / 1000 / 1000),
8843+ ticks);
8844+
8845+ return 0;
8846+}
8847+
8848+static int dsi_set_hs_tx_timeout(int ns, int x4, int x16)
8849+{
8850+ u32 r;
8851+ unsigned long fck;
8852+ int ticks;
8853+
8854+ /* ticks in TxByteClkHS */
8855+
8856+ fck = dsi.ddr_clk / 4;
8857+ ticks = (fck / 1000 / 1000) * ns / 1000;
8858+
8859+ if (ticks > 0x1fff) {
8860+ DSSERR("HS_TX_TO too high\n");
8861+ return -EINVAL;
8862+ }
8863+
8864+ r = dsi_read_reg(DSI_TIMING2);
8865+ r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
8866+ r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */
8867+ r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */
8868+ r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
8869+ dsi_write_reg(DSI_TIMING2, r);
8870+
8871+ DSSDBG("HS_TX_TO %ld ns (%#x ticks)\n",
8872+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
8873+ (fck / 1000 / 1000),
8874+ ticks);
8875+
8876+ return 0;
8877+}
8878+static int dsi_proto_config(struct omap_display *display)
8879+{
8880+ u32 r;
8881+ int buswidth = 0;
8882+
8883+ dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
8884+ DSI_FIFO_SIZE_0,
8885+ DSI_FIFO_SIZE_0,
8886+ DSI_FIFO_SIZE_0);
8887+
8888+ dsi_config_rx_fifo(DSI_FIFO_SIZE_128,
8889+ DSI_FIFO_SIZE_0,
8890+ DSI_FIFO_SIZE_0,
8891+ DSI_FIFO_SIZE_0);
8892+
8893+ /* XXX what values for the timeouts? */
8894+ dsi_set_stop_state_counter(1000, 0, 0);
8895+
8896+ dsi_set_ta_timeout(50000, 1, 1);
8897+
8898+ /* 3000ns * 16 */
8899+ dsi_set_lp_rx_timeout(3000, 0, 1);
8900+
8901+ /* 10000ns * 4 */
8902+ dsi_set_hs_tx_timeout(10000, 1, 0);
8903+
8904+ switch (display->ctrl->pixel_size) {
8905+ case 16:
8906+ buswidth = 0;
8907+ break;
8908+ case 18:
8909+ buswidth = 1;
8910+ break;
8911+ case 24:
8912+ buswidth = 2;
8913+ break;
8914+ default:
8915+ BUG();
8916+ }
8917+
8918+ r = dsi_read_reg(DSI_CTRL);
8919+ r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
8920+ r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
8921+ r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
8922+ /* XXX what should the ratio be */
8923+ r = FLD_MOD(r, 0, 4, 4); /* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
8924+ r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
8925+ r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
8926+ r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
8927+ r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
8928+ r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
8929+ r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
8930+ r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
8931+
8932+ dsi_write_reg(DSI_CTRL, r);
8933+
8934+ /* we configure vc0 for L4 communication, and
8935+ * vc1 for dispc */
8936+ dsi_vc_config(0);
8937+ dsi_vc_config_vp(1);
8938+
8939+ /* set all vc targets to peripheral 0 */
8940+ dsi.vc[0].dest_per = 0;
8941+ dsi.vc[1].dest_per = 0;
8942+ dsi.vc[2].dest_per = 0;
8943+ dsi.vc[3].dest_per = 0;
8944+
8945+ return 0;
8946+}
8947+
8948+static void dsi_proto_timings(void)
8949+{
8950+ int tlpx_half, tclk_zero, tclk_prepare, tclk_trail;
8951+ int tclk_pre, tclk_post;
8952+ int ddr_clk_pre, ddr_clk_post;
8953+ u32 r;
8954+
8955+ r = dsi_read_reg(DSI_DSIPHY_CFG1);
8956+ tlpx_half = FLD_GET(r, 22, 16);
8957+ tclk_trail = FLD_GET(r, 15, 8);
8958+ tclk_zero = FLD_GET(r, 7, 0);
8959+
8960+ r = dsi_read_reg(DSI_DSIPHY_CFG2);
8961+ tclk_prepare = FLD_GET(r, 7, 0);
8962+
8963+ /* min 8*UI */
8964+ tclk_pre = 20;
8965+ /* min 60ns + 52*UI */
8966+ tclk_post = ns2ddr(60) + 26;
8967+
8968+ ddr_clk_pre = (tclk_pre + tlpx_half*2 + tclk_zero + tclk_prepare) / 4;
8969+ ddr_clk_post = (tclk_post + tclk_trail) / 4;
8970+
8971+ r = dsi_read_reg(DSI_CLK_TIMING);
8972+ r = FLD_MOD(r, ddr_clk_pre, 15, 8);
8973+ r = FLD_MOD(r, ddr_clk_post, 7, 0);
8974+ dsi_write_reg(DSI_CLK_TIMING, r);
8975+
8976+ DSSDBG("ddr_clk_pre %d, ddr_clk_post %d\n",
8977+ ddr_clk_pre,
8978+ ddr_clk_post);
8979+}
8980+
8981+
8982+#define DSI_DECL_VARS \
8983+ int __dsi_cb = 0; u32 __dsi_cv = 0;
8984+
8985+#define DSI_FLUSH(ch) \
8986+ if (__dsi_cb > 0) { \
8987+ /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
8988+ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
8989+ __dsi_cb = __dsi_cv = 0; \
8990+ }
8991+
8992+#define DSI_PUSH(ch, data) \
8993+ do { \
8994+ __dsi_cv |= (data) << (__dsi_cb * 8); \
8995+ /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
8996+ if (++__dsi_cb > 3) \
8997+ DSI_FLUSH(ch); \
8998+ } while (0)
8999+
9000+static int dsi_update_screen_l4(struct omap_display *display,
9001+ int x, int y, int w, int h)
9002+{
9003+ /* Note: supports only 24bit colors in 32bit container */
9004+ int first = 1;
9005+ int fifo_stalls = 0;
9006+ int max_dsi_packet_size;
9007+ int max_data_per_packet;
9008+ int max_pixels_per_packet;
9009+ int pixels_left;
9010+ int bytespp = 3;
9011+ int scr_width;
9012+ u32 __iomem *data;
9013+ int start_offset;
9014+ int horiz_inc;
9015+ int current_x;
9016+ struct omap_overlay *ovl;
9017+
9018+ debug_irq = 0;
9019+
9020+ DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
9021+ x, y, w, h);
9022+
9023+ ovl = display->manager->overlays[0];
9024+
9025+ if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
9026+ return -EINVAL;
9027+
9028+ if (display->ctrl->pixel_size != 24)
9029+ return -EINVAL;
9030+
9031+ scr_width = ovl->info.screen_width;
9032+ data = ovl->info.vaddr;
9033+
9034+ start_offset = scr_width * y + x;
9035+ horiz_inc = scr_width - w;
9036+ current_x = x;
9037+
9038+ /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
9039+ * in fifo */
9040+
9041+ /* When using CPU, max long packet size is TX buffer size */
9042+ max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
9043+
9044+ /* we seem to get better perf if we divide the tx fifo to half,
9045+ and while the other half is being sent, we fill the other half
9046+ max_dsi_packet_size /= 2; */
9047+
9048+ max_data_per_packet = max_dsi_packet_size - 4 - 1;
9049+
9050+ max_pixels_per_packet = max_data_per_packet / bytespp;
9051+
9052+ DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
9053+
9054+ display->ctrl->setup_update(display, x, y, w, h);
9055+
9056+ pixels_left = w * h;
9057+
9058+ DSSDBG("total pixels %d\n", pixels_left);
9059+
9060+ data += start_offset;
9061+
9062+#ifdef DEBUG
9063+ dsi.update_region.x = x;
9064+ dsi.update_region.y = y;
9065+ dsi.update_region.w = w;
9066+ dsi.update_region.h = h;
9067+ dsi.update_region.bytespp = bytespp;
9068+#endif
9069+
9070+ perf_mark_start();
9071+
9072+ while (pixels_left > 0) {
9073+ /* 0x2c = write_memory_start */
9074+ /* 0x3c = write_memory_continue */
9075+ u8 dcs_cmd = first ? 0x2c : 0x3c;
9076+ int pixels;
9077+ DSI_DECL_VARS;
9078+ first = 0;
9079+
9080+#if 1
9081+ /* using fifo not empty */
9082+ /* TX_FIFO_NOT_EMPTY */
9083+ while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
9084+ udelay(1);
9085+ fifo_stalls++;
9086+ if (fifo_stalls > 0xfffff) {
9087+ DSSERR("fifo stalls overflow, pixels left %d\n",
9088+ pixels_left);
9089+ dsi_if_enable(0);
9090+ return -EIO;
9091+ }
9092+ }
9093+#elif 1
9094+ /* using fifo emptiness */
9095+ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
9096+ max_dsi_packet_size) {
9097+ fifo_stalls++;
9098+ if (fifo_stalls > 0xfffff) {
9099+ DSSERR("fifo stalls overflow, pixels left %d\n",
9100+ pixels_left);
9101+ dsi_if_enable(0);
9102+ return -EIO;
9103+ }
9104+ }
9105+#else
9106+ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
9107+ fifo_stalls++;
9108+ if (fifo_stalls > 0xfffff) {
9109+ DSSERR("fifo stalls overflow, pixels left %d\n",
9110+ pixels_left);
9111+ dsi_if_enable(0);
9112+ return -EIO;
9113+ }
9114+ }
9115+#endif
9116+ pixels = min(max_pixels_per_packet, pixels_left);
9117+
9118+ pixels_left -= pixels;
9119+
9120+ dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
9121+ 1 + pixels * bytespp, 0);
9122+
9123+ DSI_PUSH(0, dcs_cmd);
9124+
9125+ while (pixels-- > 0) {
9126+ u32 pix = __raw_readl(data++);
9127+
9128+ DSI_PUSH(0, (pix >> 16) & 0xff);
9129+ DSI_PUSH(0, (pix >> 8) & 0xff);
9130+ DSI_PUSH(0, (pix >> 0) & 0xff);
9131+
9132+ current_x++;
9133+ if (current_x == x+w) {
9134+ current_x = x;
9135+ data += horiz_inc;
9136+ }
9137+ }
9138+
9139+ DSI_FLUSH(0);
9140+ }
9141+
9142+ perf_show("L4");
9143+
9144+ return 0;
9145+}
9146+
9147+#if 0
9148+static void dsi_clear_screen_l4(struct omap_display *display,
9149+ int x, int y, int w, int h)
9150+{
9151+ int first = 1;
9152+ int fifo_stalls = 0;
9153+ int max_dsi_packet_size;
9154+ int max_data_per_packet;
9155+ int max_pixels_per_packet;
9156+ int pixels_left;
9157+ int bytespp = 3;
9158+ int pixnum;
9159+
9160+ debug_irq = 0;
9161+
9162+ DSSDBG("dsi_clear_screen_l4 (%d,%d %dx%d)\n",
9163+ x, y, w, h);
9164+
9165+ if (display->ctrl->bpp != 24)
9166+ return -EINVAL;
9167+
9168+ /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp)
9169+ * bytes in fifo */
9170+
9171+ /* When using CPU, max long packet size is TX buffer size */
9172+ max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
9173+
9174+ max_data_per_packet = max_dsi_packet_size - 4 - 1;
9175+
9176+ max_pixels_per_packet = max_data_per_packet / bytespp;
9177+
9178+ enable_clocks(1);
9179+
9180+ display->ctrl->setup_update(display, x, y, w, h);
9181+
9182+ pixels_left = w * h;
9183+
9184+ dsi.update_region.x = x;
9185+ dsi.update_region.y = y;
9186+ dsi.update_region.w = w;
9187+ dsi.update_region.h = h;
9188+ dsi.update_region.bytespp = bytespp;
9189+
9190+ start_measuring();
9191+
9192+ pixnum = 0;
9193+
9194+ while (pixels_left > 0) {
9195+ /* 0x2c = write_memory_start */
9196+ /* 0x3c = write_memory_continue */
9197+ u8 dcs_cmd = first ? 0x2c : 0x3c;
9198+ int pixels;
9199+ DSI_DECL_VARS;
9200+ first = 0;
9201+
9202+ /* TX_FIFO_NOT_EMPTY */
9203+ while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
9204+ fifo_stalls++;
9205+ if (fifo_stalls > 0xfffff) {
9206+ DSSERR("fifo stalls overflow\n");
9207+ dsi_if_enable(0);
9208+ enable_clocks(0);
9209+ return;
9210+ }
9211+ }
9212+
9213+ pixels = min(max_pixels_per_packet, pixels_left);
9214+
9215+ pixels_left -= pixels;
9216+
9217+ dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
9218+ 1 + pixels * bytespp, 0);
9219+
9220+ DSI_PUSH(0, dcs_cmd);
9221+
9222+ while (pixels-- > 0) {
9223+ u32 pix;
9224+
9225+ pix = 0x000000;
9226+
9227+ DSI_PUSH(0, (pix >> 16) & 0xff);
9228+ DSI_PUSH(0, (pix >> 8) & 0xff);
9229+ DSI_PUSH(0, (pix >> 0) & 0xff);
9230+ }
9231+
9232+ DSI_FLUSH(0);
9233+ }
9234+
9235+ enable_clocks(0);
9236+
9237+ end_measuring("L4 CLEAR");
9238+}
9239+#endif
9240+
9241+static void dsi_setup_update_dispc(struct omap_display *display,
9242+ u16 x, u16 y, u16 w, u16 h)
9243+{
9244+ DSSDBG("dsi_setup_update_dispc(%d,%d %dx%d)\n",
9245+ x, y, w, h);
9246+
9247+#ifdef DEBUG
9248+ dsi.update_region.x = x;
9249+ dsi.update_region.y = y;
9250+ dsi.update_region.w = w;
9251+ dsi.update_region.h = h;
9252+ dsi.update_region.bytespp = 3; // XXX
9253+#endif
9254+
9255+ dispc_setup_partial_planes(display, &x, &y, &w, &h);
9256+
9257+ dispc_set_lcd_size(w, h);
9258+}
9259+
9260+static void dsi_setup_autoupdate_dispc(struct omap_display *display)
9261+{
9262+ u16 w, h;
9263+
9264+ display->get_resolution(display, &w, &h);
9265+
9266+#ifdef DEBUG
9267+ dsi.update_region.x = 0;
9268+ dsi.update_region.y = 0;
9269+ dsi.update_region.w = w;
9270+ dsi.update_region.h = h;
9271+ dsi.update_region.bytespp = 3; // XXX
9272+#endif
9273+
9274+ /* the overlay settings may not have been applied, if we were in manual
9275+ * mode earlier, so do it here */
9276+ display->manager->apply(display->manager);
9277+
9278+ dispc_set_lcd_size(w, h);
9279+
9280+ dsi.autoupdate_setup = 0;
9281+}
9282+
9283+static void dsi_update_screen_dispc(struct omap_display *display,
9284+ u16 x, u16 y, u16 w, u16 h)
9285+{
9286+ int bytespp = 3;
9287+ int total_len;
9288+ int line_packet_len;
9289+ u32 l;
9290+
9291+ if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
9292+ DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
9293+ x, y, w, h);
9294+
9295+ /* TODO: one packet could be longer, I think? Max is the line buffer */
9296+ line_packet_len = w * bytespp + 1; /* 1 byte for DCS cmd */
9297+ total_len = line_packet_len * h;
9298+
9299+ display->ctrl->setup_update(display, x, y, w, h);
9300+
9301+ if (0)
9302+ dsi_vc_print_status(1);
9303+
9304+ perf_mark_start();
9305+
9306+ l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
9307+ dsi_write_reg(DSI_VC_TE(1), l);
9308+
9309+ dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, line_packet_len, 0);
9310+
9311+ if (dsi.use_te)
9312+ l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
9313+ else
9314+ l = FLD_MOD(l, 1, 31, 31); /* TE_START */
9315+ dsi_write_reg(DSI_VC_TE(1), l);
9316+
9317+ dispc_enable_lcd_out(1);
9318+
9319+ if (dsi.use_te)
9320+ dsi_vc_send_bta(1);
9321+}
9322+
9323+static void framedone_callback(void *data, u32 mask)
9324+{
9325+ if (dsi.framedone_scheduled) {
9326+ DSSERR("Framedone already scheduled. Bogus FRAMEDONE IRQ?\n");
9327+ return;
9328+ }
9329+
9330+ dsi.framedone_scheduled = 1;
9331+
9332+ /* We get FRAMEDONE when DISPC has finished sending pixels and turns
9333+ * itself off. However, DSI still has the pixels in its buffers, and
9334+ * is sending the data. Thus we have to wait until we can do a new
9335+ * transfer or turn the clocks off. We do that in a separate work
9336+ * func. */
9337+ queue_work(dsi.workqueue, &dsi.framedone_work);
9338+}
9339+
9340+static void framedone_worker(struct work_struct *work)
9341+{
9342+ u32 l;
9343+ unsigned long tmo;
9344+ int i = 0;
9345+
9346+ l = REG_GET(DSI_VC_TE(1), 23, 0); /* TE_SIZE */
9347+
9348+ /* There shouldn't be much stuff in DSI buffers, if any, so we'll
9349+ * just busyloop */
9350+ if (l > 0) {
9351+ tmo = jiffies + msecs_to_jiffies(50);
9352+ while (REG_GET(DSI_VC_TE(1), 23, 0) > 0) { /* TE_SIZE */
9353+ i++;
9354+ if (time_after(jiffies, tmo)) {
9355+ DSSERR("timeout waiting TE_SIZE to zero\n");
9356+ break;
9357+ }
9358+ cpu_relax();
9359+ }
9360+ }
9361+
9362+ if (REG_GET(DSI_VC_TE(1), 30, 30))
9363+ DSSERR("TE_EN not zero\n");
9364+
9365+ if (REG_GET(DSI_VC_TE(1), 31, 31))
9366+ DSSERR("TE_START not zero\n");
9367+
9368+ perf_show("DISPC");
9369+
9370+ if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
9371+ DSSDBG("FRAMEDONE\n");
9372+
9373+#if 0
9374+ if (l)
9375+ DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
9376+#else
9377+ if (l > 1024*3)
9378+ DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
9379+#endif
9380+
9381+#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
9382+ dispc_fake_vsync_irq();
9383+#endif
9384+ dsi.framedone_scheduled = 0;
9385+
9386+ /* XXX check that fifo is not full. otherwise we would sleep and never
9387+ * get to process_cmd_fifo below */
9388+ /* We check for target_update_mode, not update_mode. No reason to push
9389+ * new updates if we're turning auto update off */
9390+ if (dsi.target_update_mode == OMAP_DSS_UPDATE_AUTO)
9391+ dsi_push_autoupdate(dsi.vc[1].display);
9392+
9393+ atomic_set(&dsi.cmd_pending, 0);
9394+ dsi_process_cmd_fifo(NULL);
9395+}
9396+
9397+static void dsi_start_auto_update(struct omap_display *display)
9398+{
9399+ DSSDBG("starting auto update\n");
9400+
9401+ dsi.autoupdate_setup = 1;
9402+
9403+ dsi_push_autoupdate(display);
9404+}
9405+
9406+
9407+
9408+
9409+
9410+
9411+
9412+
9413+
9414+
9415+
9416+
9417+
9418+/* FIFO functions */
9419+
9420+static void dsi_signal_fifo_waiters(void)
9421+{
9422+ if (atomic_read(&dsi.cmd_fifo_full) > 0) {
9423+ DSSDBG("SIGNALING: Fifo not full for waiter!\n");
9424+ complete(&dsi.cmd_done);
9425+ atomic_dec(&dsi.cmd_fifo_full);
9426+ }
9427+}
9428+
9429+/* returns 1 for async op, and 0 for sync op */
9430+static int dsi_do_update(struct omap_display *display,
9431+ struct dsi_cmd_update *upd)
9432+{
9433+ int r;
9434+ u16 x = upd->x, y = upd->y, w = upd->w, h = upd->h;
9435+ u16 dw, dh;
9436+
9437+ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
9438+ return 0;
9439+
9440+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
9441+ return 0;
9442+
9443+ display->get_resolution(display, &dw, &dh);
9444+ if (x > dw || y > dh)
9445+ return 0;
9446+
9447+ if (x + w > dw)
9448+ w = dw - x;
9449+
9450+ if (y + h > dh)
9451+ h = dh - y;
9452+
9453+ DSSDBGF("%d,%d %dx%d", x, y, w, h);
9454+
9455+ perf_mark_setup();
9456+
9457+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
9458+ dsi_setup_update_dispc(display, x, y, w, h);
9459+ dsi_update_screen_dispc(display, x, y, w, h);
9460+ return 1;
9461+ } else {
9462+ r = dsi_update_screen_l4(display, x, y, w, h);
9463+ if (r)
9464+ DSSERR("L4 update failed\n");
9465+ return 0;
9466+ }
9467+}
9468+
9469+/* returns 1 for async op, and 0 for sync op */
9470+static int dsi_do_autoupdate(struct omap_display *display)
9471+{
9472+ int r;
9473+ u16 w, h;
9474+
9475+ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
9476+ return 0;
9477+
9478+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
9479+ return 0;
9480+
9481+ display->get_resolution(display, &w, &h);
9482+
9483+ perf_mark_setup();
9484+
9485+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
9486+ if (dsi.autoupdate_setup)
9487+ dsi_setup_autoupdate_dispc(display);
9488+ dsi_update_screen_dispc(display, 0, 0, w, h);
9489+ return 1;
9490+ } else {
9491+ r = dsi_update_screen_l4(display, 0, 0, w, h);
9492+ if (r)
9493+ DSSERR("L4 update failed\n");
9494+ return 0;
9495+ }
9496+}
9497+
9498+static void dsi_do_cmd_mem_read(struct omap_display *display,
9499+ struct dsi_cmd_mem_read *mem_read)
9500+{
9501+ int r;
9502+ r = display->ctrl->memory_read(display,
9503+ mem_read->buf,
9504+ mem_read->size,
9505+ mem_read->x,
9506+ mem_read->y,
9507+ mem_read->w,
9508+ mem_read->h);
9509+
9510+ *mem_read->ret_size = (size_t)r;
9511+ complete(mem_read->completion);
9512+}
9513+
9514+static void dsi_do_cmd_test(struct omap_display *display,
9515+ struct dsi_cmd_test *test)
9516+{
9517+ int r = 0;
9518+
9519+ DSSDBGF("");
9520+
9521+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
9522+ return;
9523+
9524+ /* run test first in low speed mode */
9525+ dsi_vc_enable_hs(0, 0);
9526+
9527+ if (display->ctrl->run_test) {
9528+ r = display->ctrl->run_test(display, test->test_num);
9529+ if (r)
9530+ goto end;
9531+ }
9532+
9533+ if (display->panel->run_test) {
9534+ r = display->panel->run_test(display, test->test_num);
9535+ if (r)
9536+ goto end;
9537+ }
9538+
9539+ /* then in high speed */
9540+ dsi_vc_enable_hs(0, 1);
9541+
9542+ if (display->ctrl->run_test) {
9543+ r = display->ctrl->run_test(display, test->test_num);
9544+ if (r)
9545+ goto end;
9546+ }
9547+
9548+ if (display->panel->run_test)
9549+ r = display->panel->run_test(display, test->test_num);
9550+
9551+end:
9552+ dsi_vc_enable_hs(0, 1);
9553+
9554+ *test->result = r;
9555+ complete(test->completion);
9556+
9557+ DSSDBG("test end\n");
9558+}
9559+
9560+static void dsi_do_cmd_set_te(struct omap_display *display, bool enable)
9561+{
9562+ dsi.use_te = enable;
9563+
9564+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
9565+ return;
9566+
9567+ display->ctrl->enable_te(display, enable);
9568+
9569+ if (enable) {
9570+ /* disable LP_RX_TO, so that we can receive TE.
9571+ * Time to wait for TE is longer than the timer allows */
9572+ REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
9573+ } else {
9574+ REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
9575+ }
9576+}
9577+
9578+static void dsi_do_cmd_set_update_mode(struct omap_display *display,
9579+ enum omap_dss_update_mode mode)
9580+{
9581+ dsi.update_mode = mode;
9582+
9583+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
9584+ return;
9585+
9586+ if (mode == OMAP_DSS_UPDATE_AUTO)
9587+ dsi_start_auto_update(display);
9588+}
9589+
9590+static void dsi_process_cmd_fifo(struct work_struct *work)
9591+{
9592+ int len;
9593+ struct dsi_cmd_item p;
9594+ unsigned long flags;
9595+ struct omap_display *display;
9596+ int exit = 0;
9597+
9598+ if (dsi.debug_process)
9599+ DSSDBGF("");
9600+
9601+ if (atomic_cmpxchg(&dsi.cmd_pending, 0, 1) == 1) {
9602+ if (dsi.debug_process)
9603+ DSSDBG("cmd pending, skip process\n");
9604+ return;
9605+ }
9606+
9607+ while (!exit) {
9608+ spin_lock_irqsave(dsi.cmd_fifo->lock, flags);
9609+
9610+ len = __kfifo_get(dsi.cmd_fifo, (unsigned char *)&p,
9611+ sizeof(p));
9612+ if (len == 0) {
9613+ if (dsi.debug_process)
9614+ DSSDBG("nothing more in fifo, atomic clear\n");
9615+ atomic_set(&dsi.cmd_pending, 0);
9616+ spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
9617+ break;
9618+ }
9619+
9620+ spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
9621+
9622+ BUG_ON(len != sizeof(p));
9623+
9624+ display = p.display;
9625+
9626+ if (dsi.debug_process)
9627+ DSSDBG("processing cmd %d\n", p.cmd);
9628+
9629+ switch (p.cmd) {
9630+ case DSI_CMD_UPDATE:
9631+ if (dsi_do_update(display, &p.u.r)) {
9632+ if (dsi.debug_process)
9633+ DSSDBG("async update\n");
9634+ exit = 1;
9635+ } else {
9636+ if (dsi.debug_process)
9637+ DSSDBG("sync update\n");
9638+ }
9639+ break;
9640+
9641+ case DSI_CMD_AUTOUPDATE:
9642+ if (dsi_do_autoupdate(display)) {
9643+ if (dsi.debug_process)
9644+ DSSDBG("async autoupdate\n");
9645+ exit = 1;
9646+ } else {
9647+ if (dsi.debug_process)
9648+ DSSDBG("sync autoupdate\n");
9649+ }
9650+ break;
9651+
9652+ case DSI_CMD_SYNC:
9653+ if (dsi.debug_process)
9654+ DSSDBG("Signaling SYNC done!\n");
9655+ complete(p.u.sync);
9656+ break;
9657+
9658+ case DSI_CMD_MEM_READ:
9659+ dsi_do_cmd_mem_read(display, &p.u.mem_read);
9660+ break;
9661+
9662+ case DSI_CMD_TEST:
9663+ dsi_do_cmd_test(display, &p.u.test);
9664+ break;
9665+
9666+ case DSI_CMD_SET_TE:
9667+ dsi_do_cmd_set_te(display, p.u.te);
9668+ break;
9669+
9670+ case DSI_CMD_SET_UPDATE_MODE:
9671+ dsi_do_cmd_set_update_mode(display, p.u.update_mode);
9672+ break;
9673+
9674+ case DSI_CMD_SET_ROTATE:
9675+ display->ctrl->set_rotate(display, p.u.rotate);
9676+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
9677+ dsi.autoupdate_setup = 1;
9678+ break;
9679+
9680+ case DSI_CMD_SET_MIRROR:
9681+ display->ctrl->set_mirror(display, p.u.mirror);
9682+ break;
9683+
9684+ default:
9685+ BUG();
9686+ }
9687+ }
9688+
9689+ if (dsi.debug_process)
9690+ DSSDBG("exit dsi_process_cmd_fifo\n");
9691+
9692+ dsi_signal_fifo_waiters();
9693+}
9694+
9695+static void dsi_push_cmd(struct dsi_cmd_item *p)
9696+{
9697+ int ret;
9698+
9699+ if (dsi.debug_process)
9700+ DSSDBGF("");
9701+
9702+ while (1) {
9703+ unsigned long flags;
9704+ unsigned avail, used;
9705+
9706+ spin_lock_irqsave(dsi.cmd_fifo->lock, flags);
9707+ used = __kfifo_len(dsi.cmd_fifo) / sizeof(struct dsi_cmd_item);
9708+ avail = DSI_CMD_FIFO_LEN - used;
9709+
9710+ if (dsi.debug_process)
9711+ DSSDBG("%u/%u items left in fifo\n", avail, used);
9712+
9713+ if (avail == 0) {
9714+ if (dsi.debug_process)
9715+ DSSDBG("cmd fifo full, waiting...\n");
9716+ spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
9717+ atomic_inc(&dsi.cmd_fifo_full);
9718+ wait_for_completion(&dsi.cmd_done);
9719+ if (dsi.debug_process)
9720+ DSSDBG("cmd fifo not full, woke up\n");
9721+ continue;
9722+ }
9723+
9724+ ret = __kfifo_put(dsi.cmd_fifo, (unsigned char *)p,
9725+ sizeof(*p));
9726+
9727+ spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
9728+
9729+ BUG_ON(ret != sizeof(*p));
9730+
9731+ break;
9732+ }
9733+
9734+ queue_work(dsi.workqueue, &dsi.process_work);
9735+}
9736+
9737+static void dsi_push_update(struct omap_display *display,
9738+ int x, int y, int w, int h)
9739+{
9740+ struct dsi_cmd_item p;
9741+
9742+ p.display = display;
9743+ p.cmd = DSI_CMD_UPDATE;
9744+
9745+ p.u.r.x = x;
9746+ p.u.r.y = y;
9747+ p.u.r.w = w;
9748+ p.u.r.h = h;
9749+
9750+ DSSDBG("pushing UPDATE %d,%d %dx%d\n", x, y, w, h);
9751+
9752+ dsi_push_cmd(&p);
9753+}
9754+
9755+static void dsi_push_autoupdate(struct omap_display *display)
9756+{
9757+ struct dsi_cmd_item p;
9758+
9759+ p.display = display;
9760+ p.cmd = DSI_CMD_AUTOUPDATE;
9761+
9762+ dsi_push_cmd(&p);
9763+}
9764+
9765+static void dsi_push_sync(struct omap_display *display,
9766+ struct completion *sync_comp)
9767+{
9768+ struct dsi_cmd_item p;
9769+
9770+ p.display = display;
9771+ p.cmd = DSI_CMD_SYNC;
9772+ p.u.sync = sync_comp;
9773+
9774+ DSSDBG("pushing SYNC\n");
9775+
9776+ dsi_push_cmd(&p);
9777+}
9778+
9779+static void dsi_push_mem_read(struct omap_display *display,
9780+ struct dsi_cmd_mem_read *mem_read)
9781+{
9782+ struct dsi_cmd_item p;
9783+
9784+ p.display = display;
9785+ p.cmd = DSI_CMD_MEM_READ;
9786+ p.u.mem_read = *mem_read;
9787+
9788+ DSSDBG("pushing MEM_READ\n");
9789+
9790+ dsi_push_cmd(&p);
9791+}
9792+
9793+static void dsi_push_test(struct omap_display *display, int test_num,
9794+ int *result, struct completion *completion)
9795+{
9796+ struct dsi_cmd_item p;
9797+
9798+ p.display = display;
9799+ p.cmd = DSI_CMD_TEST;
9800+ p.u.test.test_num = test_num;
9801+ p.u.test.result = result;
9802+ p.u.test.completion = completion;
9803+
9804+ DSSDBG("pushing TEST\n");
9805+
9806+ dsi_push_cmd(&p);
9807+}
9808+
9809+static void dsi_push_set_te(struct omap_display *display, bool enable)
9810+{
9811+ struct dsi_cmd_item p;
9812+
9813+ p.display = display;
9814+ p.cmd = DSI_CMD_SET_TE;
9815+ p.u.te = enable;
9816+
9817+ DSSDBG("pushing SET_TE\n");
9818+
9819+ dsi_push_cmd(&p);
9820+}
9821+
9822+static void dsi_push_set_update_mode(struct omap_display *display,
9823+ enum omap_dss_update_mode mode)
9824+{
9825+ struct dsi_cmd_item p;
9826+
9827+ p.display = display;
9828+ p.cmd = DSI_CMD_SET_UPDATE_MODE;
9829+ p.u.update_mode = mode;
9830+
9831+ DSSDBG("pushing SET_UPDATE_MODE\n");
9832+
9833+ dsi_push_cmd(&p);
9834+}
9835+
9836+static void dsi_push_set_rotate(struct omap_display *display, int rotate)
9837+{
9838+ struct dsi_cmd_item p;
9839+
9840+ p.display = display;
9841+ p.cmd = DSI_CMD_SET_ROTATE;
9842+ p.u.rotate = rotate;
9843+
9844+ DSSDBG("pushing SET_ROTATE\n");
9845+
9846+ dsi_push_cmd(&p);
9847+}
9848+
9849+static void dsi_push_set_mirror(struct omap_display *display, int mirror)
9850+{
9851+ struct dsi_cmd_item p;
9852+
9853+ p.display = display;
9854+ p.cmd = DSI_CMD_SET_MIRROR;
9855+ p.u.mirror = mirror;
9856+
9857+ DSSDBG("pushing SET_MIRROR\n");
9858+
9859+ dsi_push_cmd(&p);
9860+}
9861+
9862+static int dsi_wait_sync(struct omap_display *display)
9863+{
9864+ long wait = msecs_to_jiffies(60000);
9865+ struct completion compl;
9866+
9867+ DSSDBGF("");
9868+
9869+ init_completion(&compl);
9870+ dsi_push_sync(display, &compl);
9871+
9872+ DSSDBG("Waiting for SYNC to happen...\n");
9873+ wait = wait_for_completion_timeout(&compl, wait);
9874+ DSSDBG("Released from SYNC\n");
9875+
9876+ if (wait == 0) {
9877+ DSSERR("timeout waiting sync\n");
9878+ return -ETIME;
9879+ }
9880+
9881+ return 0;
9882+}
9883+
9884+
9885+
9886+
9887+
9888+
9889+
9890+
9891+
9892+
9893+
9894+
9895+/* Display funcs */
9896+
9897+static int dsi_display_init_dispc(struct omap_display *display)
9898+{
9899+ int r;
9900+
9901+ r = omap_dispc_register_isr(framedone_callback, NULL,
9902+ DISPC_IRQ_FRAMEDONE);
9903+ if (r) {
9904+ DSSERR("can't get FRAMEDONE irq\n");
9905+ return r;
9906+ }
9907+
9908+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
9909+
9910+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
9911+ dispc_enable_fifohandcheck(1);
9912+
9913+ dispc_set_tft_data_lines(display->ctrl->pixel_size);
9914+
9915+ {
9916+ struct omap_video_timings timings = {
9917+ .hsw = 1,
9918+ .hfp = 1,
9919+ .hbp = 1,
9920+ .vsw = 1,
9921+ .vfp = 0,
9922+ .vbp = 0,
9923+ };
9924+
9925+ dispc_set_lcd_timings(&timings);
9926+ }
9927+
9928+ return 0;
9929+}
9930+
9931+static void dsi_display_uninit_dispc(struct omap_display *display)
9932+{
9933+ omap_dispc_unregister_isr(framedone_callback, NULL,
9934+ DISPC_IRQ_FRAMEDONE);
9935+}
9936+
9937+static int dsi_display_init_dsi(struct omap_display *display)
9938+{
9939+ struct dsi_clock_info cinfo;
9940+ int r;
9941+
9942+ _dsi_print_reset_status();
9943+
9944+ r = dsi_pll_init(1, 0);
9945+ if (r)
9946+ goto err0;
9947+
9948+ r = dsi_pll_calc_ddrfreq(display->hw_config.u.dsi.ddr_clk_hz, &cinfo);
9949+ if (r)
9950+ goto err1;
9951+
9952+ r = dsi_pll_program(&cinfo);
9953+ if (r)
9954+ goto err1;
9955+
9956+ DSSDBG("PLL OK\n");
9957+
9958+ r = dsi_complexio_init(display);
9959+ if (r)
9960+ goto err1;
9961+
9962+ _dsi_print_reset_status();
9963+
9964+ dsi_proto_timings();
9965+ dsi_set_lp_clk_divisor();
9966+
9967+ if (1)
9968+ _dsi_print_reset_status();
9969+
9970+ r = dsi_proto_config(display);
9971+ if (r)
9972+ goto err2;
9973+
9974+ /* enable interface */
9975+ dsi_vc_enable(0, 1);
9976+ dsi_vc_enable(1, 1);
9977+ dsi_if_enable(1);
9978+ dsi_force_tx_stop_mode_io();
9979+
9980+ if (display->ctrl && display->ctrl->enable) {
9981+ r = display->ctrl->enable(display);
9982+ if (r)
9983+ goto err3;
9984+ }
9985+
9986+ if (display->panel && display->panel->enable) {
9987+ r = display->panel->enable(display);
9988+ if (r)
9989+ goto err4;
9990+ }
9991+
9992+ /* enable high-speed after initial config */
9993+ dsi_vc_enable_hs(0, 1);
9994+
9995+ return 0;
9996+err4:
9997+ if (display->ctrl && display->ctrl->disable)
9998+ display->ctrl->disable(display);
9999+err3:
10000+ dsi_if_enable(0);
10001+err2:
10002+ dsi_complexio_uninit();
10003+err1:
10004+ dsi_pll_uninit();
10005+err0:
10006+ return r;
10007+}
10008+
10009+static void dsi_display_uninit_dsi(struct omap_display *display)
10010+{
10011+ if (display->panel && display->panel->disable)
10012+ display->panel->disable(display);
10013+ if (display->ctrl && display->ctrl->disable)
10014+ display->ctrl->disable(display);
10015+
10016+ dsi_complexio_uninit();
10017+ dsi_pll_uninit();
10018+}
10019+
10020+static int dsi_core_init(void)
10021+{
10022+ /* Autoidle */
10023+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
10024+
10025+ /* ENWAKEUP */
10026+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
10027+
10028+ /* SIDLEMODE smart-idle */
10029+ REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
10030+
10031+ _dsi_initialize_irq();
10032+
10033+ return 0;
10034+}
10035+
10036+static int dsi_display_enable(struct omap_display *display)
10037+{
10038+ int r = 0;
10039+
10040+ DSSDBG("dsi_display_enable\n");
10041+
10042+ mutex_lock(&dsi.lock);
10043+
10044+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
10045+ DSSERR("display already enabled\n");
10046+ r = -EINVAL;
10047+ goto err0;
10048+ }
10049+
10050+ enable_clocks(1);
10051+ dsi_enable_pll_clock(1);
10052+
10053+ r = _dsi_reset();
10054+ if (r)
10055+ return r;
10056+
10057+ dsi_core_init();
10058+
10059+ r = dsi_display_init_dispc(display);
10060+ if (r)
10061+ goto err1;
10062+
10063+ r = dsi_display_init_dsi(display);
10064+ if (r)
10065+ goto err2;
10066+
10067+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
10068+
10069+ if (dsi.use_te)
10070+ dsi_push_set_te(display, 1);
10071+
10072+ dsi_push_set_update_mode(display, dsi.user_update_mode);
10073+ dsi.target_update_mode = dsi.user_update_mode;
10074+
10075+ mutex_unlock(&dsi.lock);
10076+
10077+ return dsi_wait_sync(display);
10078+
10079+err2:
10080+ dsi_display_uninit_dispc(display);
10081+err1:
10082+ enable_clocks(0);
10083+ dsi_enable_pll_clock(0);
10084+err0:
10085+ mutex_unlock(&dsi.lock);
10086+ DSSDBG("dsi_display_enable FAILED\n");
10087+ return r;
10088+}
10089+
10090+static void dsi_display_disable(struct omap_display *display)
10091+{
10092+ DSSDBG("dsi_display_disable\n");
10093+
10094+ mutex_lock(&dsi.lock);
10095+
10096+ if (display->state == OMAP_DSS_DISPLAY_DISABLED ||
10097+ display->state == OMAP_DSS_DISPLAY_SUSPENDED)
10098+ goto end;
10099+
10100+ if (dsi.target_update_mode != OMAP_DSS_UPDATE_DISABLED) {
10101+ dsi_push_set_update_mode(display, OMAP_DSS_UPDATE_DISABLED);
10102+ dsi.target_update_mode = OMAP_DSS_UPDATE_DISABLED;
10103+ }
10104+
10105+ dsi_wait_sync(display);
10106+
10107+ display->state = OMAP_DSS_DISPLAY_DISABLED;
10108+
10109+ dsi_display_uninit_dispc(display);
10110+
10111+ dsi_display_uninit_dsi(display);
10112+
10113+ enable_clocks(0);
10114+ dsi_enable_pll_clock(0);
10115+end:
10116+ mutex_unlock(&dsi.lock);
10117+}
10118+
10119+static int dsi_display_suspend(struct omap_display *display)
10120+{
10121+ DSSDBG("dsi_display_suspend\n");
10122+
10123+ dsi_display_disable(display);
10124+
10125+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
10126+
10127+ return 0;
10128+}
10129+
10130+static int dsi_display_resume(struct omap_display *display)
10131+{
10132+ DSSDBG("dsi_display_resume\n");
10133+
10134+ display->state = OMAP_DSS_DISPLAY_DISABLED;
10135+ return dsi_display_enable(display);
10136+}
10137+
10138+static int dsi_display_update(struct omap_display *display,
10139+ u16 x, u16 y, u16 w, u16 h)
10140+{
10141+ DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x, y, w, h);
10142+
10143+ if (w == 0 || h == 0)
10144+ return 0;
10145+
10146+ mutex_lock(&dsi.lock);
10147+
10148+ if (dsi.target_update_mode == OMAP_DSS_UPDATE_MANUAL)
10149+ dsi_push_update(display, x, y, w, h);
10150+ /* XXX else return error? */
10151+
10152+ mutex_unlock(&dsi.lock);
10153+
10154+ return 0;
10155+}
10156+
10157+static int dsi_display_sync(struct omap_display *display)
10158+{
10159+ DSSDBGF("");
10160+ return dsi_wait_sync(display);
10161+}
10162+
10163+static int dsi_display_set_update_mode(struct omap_display *display,
10164+ enum omap_dss_update_mode mode)
10165+{
10166+ DSSDBGF("%d", mode);
10167+
10168+ mutex_lock(&dsi.lock);
10169+
10170+ if (dsi.target_update_mode != mode) {
10171+ dsi_push_set_update_mode(display, mode);
10172+
10173+ dsi.target_update_mode = mode;
10174+ dsi.user_update_mode = mode;
10175+ }
10176+
10177+ mutex_unlock(&dsi.lock);
10178+
10179+ return dsi_wait_sync(display);
10180+}
10181+
10182+static enum omap_dss_update_mode dsi_display_get_update_mode(
10183+ struct omap_display *display)
10184+{
10185+ return dsi.update_mode;
10186+}
10187+
10188+static int dsi_display_enable_te(struct omap_display *display, bool enable)
10189+{
10190+ DSSDBGF("%d", enable);
10191+
10192+ if (!display->ctrl->enable_te)
10193+ return -ENOENT;
10194+
10195+ dsi_push_set_te(display, enable);
10196+
10197+ return dsi_wait_sync(display);
10198+}
10199+
10200+static int dsi_display_get_te(struct omap_display *display)
10201+{
10202+ return dsi.use_te;
10203+}
10204+
10205+
10206+
10207+static int dsi_display_set_rotate(struct omap_display *display, u8 rotate)
10208+{
10209+ DSSDBGF("%d", rotate);
10210+
10211+ if (!display->ctrl->set_rotate || !display->ctrl->get_rotate)
10212+ return -EINVAL;
10213+
10214+ dsi_push_set_rotate(display, rotate);
10215+
10216+ return dsi_wait_sync(display);
10217+}
10218+
10219+static u8 dsi_display_get_rotate(struct omap_display *display)
10220+{
10221+ if (!display->ctrl->set_rotate || !display->ctrl->get_rotate)
10222+ return 0;
10223+
10224+ return display->ctrl->get_rotate(display);
10225+}
10226+
10227+static int dsi_display_set_mirror(struct omap_display *display, bool mirror)
10228+{
10229+ DSSDBGF("%d", mirror);
10230+
10231+ if (!display->ctrl->set_mirror || !display->ctrl->get_mirror)
10232+ return -EINVAL;
10233+
10234+ dsi_push_set_mirror(display, mirror);
10235+
10236+ return dsi_wait_sync(display);
10237+}
10238+
10239+static bool dsi_display_get_mirror(struct omap_display *display)
10240+{
10241+ if (!display->ctrl->set_mirror || !display->ctrl->get_mirror)
10242+ return 0;
10243+
10244+ return display->ctrl->get_mirror(display);
10245+}
10246+
10247+static int dsi_display_run_test(struct omap_display *display, int test_num)
10248+{
10249+ long wait = msecs_to_jiffies(60000);
10250+ struct completion compl;
10251+ int result;
10252+
10253+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
10254+ return -EIO;
10255+
10256+ DSSDBGF("%d", test_num);
10257+
10258+ init_completion(&compl);
10259+
10260+ dsi_push_test(display, test_num, &result, &compl);
10261+
10262+ DSSDBG("Waiting for SYNC to happen...\n");
10263+ wait = wait_for_completion_timeout(&compl, wait);
10264+ DSSDBG("Released from SYNC\n");
10265+
10266+ if (wait == 0) {
10267+ DSSERR("timeout waiting test sync\n");
10268+ return -ETIME;
10269+ }
10270+
10271+ return result;
10272+}
10273+
10274+static int dsi_display_memory_read(struct omap_display *display,
10275+ void *buf, size_t size,
10276+ u16 x, u16 y, u16 w, u16 h)
10277+{
10278+ long wait = msecs_to_jiffies(60000);
10279+ struct completion compl;
10280+ struct dsi_cmd_mem_read mem_read;
10281+ size_t ret_size;
10282+
10283+ DSSDBGF("");
10284+
10285+ if (!display->ctrl->memory_read)
10286+ return -EINVAL;
10287+
10288+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
10289+ return -EIO;
10290+
10291+ init_completion(&compl);
10292+
10293+ mem_read.x = x;
10294+ mem_read.y = y;
10295+ mem_read.w = w;
10296+ mem_read.h = h;
10297+ mem_read.buf = buf;
10298+ mem_read.size = size;
10299+ mem_read.ret_size = &ret_size;
10300+ mem_read.completion = &compl;
10301+
10302+ dsi_push_mem_read(display, &mem_read);
10303+
10304+ DSSDBG("Waiting for SYNC to happen...\n");
10305+ wait = wait_for_completion_timeout(&compl, wait);
10306+ DSSDBG("Released from SYNC\n");
10307+
10308+ if (wait == 0) {
10309+ DSSERR("timeout waiting mem read sync\n");
10310+ return -ETIME;
10311+ }
10312+
10313+ return ret_size;
10314+}
10315+
10316+static void dsi_configure_overlay(struct omap_overlay *ovl)
10317+{
10318+ unsigned low, high, size;
10319+ enum omap_burst_size burst;
10320+ enum omap_plane plane = ovl->id;
10321+
10322+ burst = OMAP_DSS_BURST_16x32;
10323+ size = 16 * 32 / 8;
10324+
10325+ dispc_set_burst_size(plane, burst);
10326+
10327+ high = dispc_get_plane_fifo_size(plane) - size;
10328+ low = 0;
10329+ dispc_setup_plane_fifo(plane, low, high);
10330+}
10331+
10332+void dsi_init_display(struct omap_display *display)
10333+{
10334+ DSSDBG("DSI init\n");
10335+
10336+ display->enable = dsi_display_enable;
10337+ display->disable = dsi_display_disable;
10338+ display->suspend = dsi_display_suspend;
10339+ display->resume = dsi_display_resume;
10340+ display->update = dsi_display_update;
10341+ display->sync = dsi_display_sync;
10342+ display->set_update_mode = dsi_display_set_update_mode;
10343+ display->get_update_mode = dsi_display_get_update_mode;
10344+ display->enable_te = dsi_display_enable_te;
10345+ display->get_te = dsi_display_get_te;
10346+
10347+ display->get_rotate = dsi_display_get_rotate;
10348+ display->set_rotate = dsi_display_set_rotate;
10349+
10350+ display->get_mirror = dsi_display_get_mirror;
10351+ display->set_mirror = dsi_display_set_mirror;
10352+
10353+ display->run_test = dsi_display_run_test;
10354+ display->memory_read = dsi_display_memory_read;
10355+
10356+ display->configure_overlay = dsi_configure_overlay;
10357+
10358+ display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
10359+
10360+ dsi.vc[0].display = display;
10361+ dsi.vc[1].display = display;
10362+}
10363+
10364+int dsi_init(void)
10365+{
10366+ u32 rev;
10367+
10368+ spin_lock_init(&dsi.cmd_lock);
10369+ dsi.cmd_fifo = kfifo_alloc(
10370+ DSI_CMD_FIFO_LEN * sizeof(struct dsi_cmd_item),
10371+ GFP_KERNEL,
10372+ &dsi.cmd_lock);
10373+
10374+ init_completion(&dsi.cmd_done);
10375+ atomic_set(&dsi.cmd_fifo_full, 0);
10376+ atomic_set(&dsi.cmd_pending, 0);
10377+
10378+ init_completion(&dsi.bta_completion);
10379+
10380+ dsi.workqueue = create_singlethread_workqueue("dsi");
10381+ INIT_WORK(&dsi.framedone_work, framedone_worker);
10382+ INIT_WORK(&dsi.process_work, dsi_process_cmd_fifo);
10383+
10384+ mutex_init(&dsi.lock);
10385+
10386+ dsi.target_update_mode = OMAP_DSS_UPDATE_DISABLED;
10387+ dsi.user_update_mode = OMAP_DSS_UPDATE_DISABLED;
10388+
10389+ dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
10390+ if (!dsi.base) {
10391+ DSSERR("can't ioremap DSI\n");
10392+ return -ENOMEM;
10393+ }
10394+
10395+ enable_clocks(1);
10396+
10397+ rev = dsi_read_reg(DSI_REVISION);
10398+ printk(KERN_INFO "OMAP DSI rev %d.%d\n",
10399+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
10400+
10401+ enable_clocks(0);
10402+
10403+ return 0;
10404+}
10405+
10406+void dsi_exit(void)
10407+{
10408+ flush_workqueue(dsi.workqueue);
10409+ destroy_workqueue(dsi.workqueue);
10410+
10411+ iounmap(dsi.base);
10412+
10413+ kfifo_free(dsi.cmd_fifo);
10414+
10415+ DSSDBG("omap_dsi_exit\n");
10416+}
10417+
10418diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
10419new file mode 100644
10420index 0000000..adc1f34
10421--- /dev/null
10422+++ b/drivers/video/omap2/dss/dss.c
10423@@ -0,0 +1,345 @@
10424+/*
10425+ * linux/drivers/video/omap2/dss/dss.c
10426+ *
10427+ * Copyright (C) 2009 Nokia Corporation
10428+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
10429+ *
10430+ * Some code and ideas taken from drivers/video/omap/ driver
10431+ * by Imre Deak.
10432+ *
10433+ * This program is free software; you can redistribute it and/or modify it
10434+ * under the terms of the GNU General Public License version 2 as published by
10435+ * the Free Software Foundation.
10436+ *
10437+ * This program is distributed in the hope that it will be useful, but WITHOUT
10438+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10439+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
10440+ * more details.
10441+ *
10442+ * You should have received a copy of the GNU General Public License along with
10443+ * this program. If not, see <http://www.gnu.org/licenses/>.
10444+ */
10445+
10446+#define DSS_SUBSYS_NAME "DSS"
10447+
10448+#include <linux/kernel.h>
10449+#include <linux/io.h>
10450+#include <linux/err.h>
10451+#include <linux/delay.h>
10452+#include <linux/interrupt.h>
10453+#include <linux/seq_file.h>
10454+
10455+#include <mach/display.h>
10456+#include "dss.h"
10457+
10458+#define DSS_BASE 0x48050000
10459+
10460+#define DSS_SZ_REGS SZ_512
10461+
10462+struct dss_reg {
10463+ u16 idx;
10464+};
10465+
10466+#define DSS_REG(idx) ((const struct dss_reg) { idx })
10467+
10468+#define DSS_REVISION DSS_REG(0x0000)
10469+#define DSS_SYSCONFIG DSS_REG(0x0010)
10470+#define DSS_SYSSTATUS DSS_REG(0x0014)
10471+#define DSS_IRQSTATUS DSS_REG(0x0018)
10472+#define DSS_CONTROL DSS_REG(0x0040)
10473+#define DSS_SDI_CONTROL DSS_REG(0x0044)
10474+#define DSS_PLL_CONTROL DSS_REG(0x0048)
10475+#define DSS_SDI_STATUS DSS_REG(0x005C)
10476+
10477+#define REG_GET(idx, start, end) \
10478+ FLD_GET(dss_read_reg(idx), start, end)
10479+
10480+#define REG_FLD_MOD(idx, val, start, end) \
10481+ dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
10482+
10483+static struct {
10484+ void __iomem *base;
10485+
10486+ u32 ctx[DSS_SZ_REGS / sizeof(u32)];
10487+} dss;
10488+
10489+static int _omap_dss_wait_reset(void);
10490+
10491+static inline void dss_write_reg(const struct dss_reg idx, u32 val)
10492+{
10493+ __raw_writel(val, dss.base + idx.idx);
10494+}
10495+
10496+static inline u32 dss_read_reg(const struct dss_reg idx)
10497+{
10498+ return __raw_readl(dss.base + idx.idx);
10499+}
10500+
10501+#define SR(reg) \
10502+ dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
10503+#define RR(reg) \
10504+ dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
10505+
10506+void dss_save_context(void)
10507+{
10508+ if (cpu_is_omap24xx())
10509+ return;
10510+
10511+ SR(SYSCONFIG);
10512+ SR(CONTROL);
10513+
10514+#ifdef CONFIG_OMAP2_DSS_SDI
10515+ SR(SDI_CONTROL);
10516+ SR(PLL_CONTROL);
10517+#endif
10518+}
10519+
10520+void dss_restore_context(void)
10521+{
10522+ if (_omap_dss_wait_reset())
10523+ DSSERR("DSS not coming out of reset after sleep\n");
10524+
10525+ RR(SYSCONFIG);
10526+ RR(CONTROL);
10527+
10528+#ifdef CONFIG_OMAP2_DSS_SDI
10529+ RR(SDI_CONTROL);
10530+ RR(PLL_CONTROL);
10531+#endif
10532+}
10533+
10534+#undef SR
10535+#undef RR
10536+
10537+void dss_sdi_init(u8 datapairs)
10538+{
10539+ u32 l;
10540+
10541+ BUG_ON(datapairs > 3 || datapairs < 1);
10542+
10543+ l = dss_read_reg(DSS_SDI_CONTROL);
10544+ l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
10545+ l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
10546+ l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
10547+ dss_write_reg(DSS_SDI_CONTROL, l);
10548+
10549+ l = dss_read_reg(DSS_PLL_CONTROL);
10550+ l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
10551+ l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
10552+ l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
10553+ dss_write_reg(DSS_PLL_CONTROL, l);
10554+}
10555+
10556+void dss_sdi_enable(void)
10557+{
10558+ dispc_pck_free_enable(1);
10559+
10560+ /* Reset SDI PLL */
10561+ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
10562+ udelay(1); /* wait 2x PCLK */
10563+
10564+ /* Lock SDI PLL */
10565+ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
10566+
10567+ /* Waiting for PLL lock request to complete */
10568+ while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6))
10569+ ;
10570+
10571+ /* Clearing PLL_GO bit */
10572+ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
10573+
10574+ /* Waiting for PLL to lock */
10575+ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5)))
10576+ ;
10577+
10578+ dispc_lcd_enable_signal(1);
10579+
10580+ /* Waiting for SDI reset to complete */
10581+ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2)))
10582+ ;
10583+}
10584+
10585+void dss_sdi_disable(void)
10586+{
10587+ dispc_lcd_enable_signal(0);
10588+
10589+ dispc_pck_free_enable(0);
10590+
10591+ /* Reset SDI PLL */
10592+ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
10593+}
10594+
10595+void dss_dump_regs(struct seq_file *s)
10596+{
10597+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
10598+
10599+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
10600+
10601+ DUMPREG(DSS_REVISION);
10602+ DUMPREG(DSS_SYSCONFIG);
10603+ DUMPREG(DSS_SYSSTATUS);
10604+ DUMPREG(DSS_IRQSTATUS);
10605+ DUMPREG(DSS_CONTROL);
10606+ DUMPREG(DSS_SDI_CONTROL);
10607+ DUMPREG(DSS_PLL_CONTROL);
10608+ DUMPREG(DSS_SDI_STATUS);
10609+
10610+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
10611+#undef DUMPREG
10612+}
10613+
10614+void dss_select_clk_source(bool dsi, bool dispc)
10615+{
10616+ u32 r;
10617+ r = dss_read_reg(DSS_CONTROL);
10618+ r = FLD_MOD(r, dsi, 1, 1); /* DSI_CLK_SWITCH */
10619+ r = FLD_MOD(r, dispc, 0, 0); /* DISPC_CLK_SWITCH */
10620+ dss_write_reg(DSS_CONTROL, r);
10621+}
10622+
10623+int dss_get_dsi_clk_source(void)
10624+{
10625+ return FLD_GET(dss_read_reg(DSS_CONTROL), 1, 1);
10626+}
10627+
10628+int dss_get_dispc_clk_source(void)
10629+{
10630+ return FLD_GET(dss_read_reg(DSS_CONTROL), 0, 0);
10631+}
10632+
10633+static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
10634+{
10635+ dispc_irq_handler();
10636+
10637+ return IRQ_HANDLED;
10638+}
10639+
10640+static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
10641+{
10642+ u32 irqstatus;
10643+
10644+ irqstatus = dss_read_reg(DSS_IRQSTATUS);
10645+
10646+ if (irqstatus & (1<<0)) /* DISPC_IRQ */
10647+ dispc_irq_handler();
10648+#ifdef CONFIG_OMAP2_DSS_DSI
10649+ if (irqstatus & (1<<1)) /* DSI_IRQ */
10650+ dsi_irq_handler();
10651+#endif
10652+
10653+ return IRQ_HANDLED;
10654+}
10655+
10656+static int _omap_dss_wait_reset(void)
10657+{
10658+ unsigned timeout = 1000;
10659+
10660+ while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
10661+ udelay(1);
10662+ if (!--timeout) {
10663+ DSSERR("soft reset failed\n");
10664+ return -ENODEV;
10665+ }
10666+ }
10667+
10668+ return 0;
10669+}
10670+
10671+static int _omap_dss_reset(void)
10672+{
10673+ /* Soft reset */
10674+ REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
10675+ return _omap_dss_wait_reset();
10676+}
10677+
10678+void dss_set_venc_output(enum omap_dss_venc_type type)
10679+{
10680+ int l = 0;
10681+
10682+ if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
10683+ l = 0;
10684+ else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
10685+ l = 1;
10686+ else
10687+ BUG();
10688+
10689+ /* venc out selection. 0 = comp, 1 = svideo */
10690+ REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
10691+}
10692+
10693+void dss_set_dac_pwrdn_bgz(bool enable)
10694+{
10695+ REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
10696+}
10697+
10698+int dss_init(bool skip_init)
10699+{
10700+ int r;
10701+ u32 rev;
10702+
10703+ dss.base = ioremap(DSS_BASE, DSS_SZ_REGS);
10704+ if (!dss.base) {
10705+ DSSERR("can't ioremap DSS\n");
10706+ r = -ENOMEM;
10707+ goto fail0;
10708+ }
10709+
10710+ if (!skip_init) {
10711+ /* We need to wait here a bit, otherwise we sometimes start to
10712+ * get synclost errors, and after that only power cycle will
10713+ * restore DSS functionality. I have no idea why this happens.
10714+ * And we have to wait _before_ resetting the DSS, but after
10715+ * enabling clocks.
10716+ */
10717+ msleep(50);
10718+
10719+ _omap_dss_reset();
10720+
10721+ }
10722+ else
10723+ printk("DSS SKIP RESET\n");
10724+
10725+ /* autoidle */
10726+ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
10727+
10728+ /* Select DPLL */
10729+ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
10730+
10731+#ifdef CONFIG_OMAP2_DSS_VENC
10732+ REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
10733+ REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
10734+ REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
10735+#endif
10736+
10737+ r = request_irq(INT_24XX_DSS_IRQ,
10738+ cpu_is_omap24xx()
10739+ ? dss_irq_handler_omap2
10740+ : dss_irq_handler_omap3,
10741+ 0, "OMAP DSS", NULL);
10742+
10743+ if (r < 0) {
10744+ DSSERR("omap2 dss: request_irq failed\n");
10745+ goto fail1;
10746+ }
10747+
10748+ dss_save_context();
10749+
10750+ rev = dss_read_reg(DSS_REVISION);
10751+ printk(KERN_INFO "OMAP DSS rev %d.%d\n",
10752+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
10753+
10754+ return 0;
10755+
10756+fail1:
10757+ iounmap(dss.base);
10758+fail0:
10759+ return r;
10760+}
10761+
10762+void dss_exit(void)
10763+{
10764+ free_irq(INT_24XX_DSS_IRQ, NULL);
10765+
10766+ iounmap(dss.base);
10767+}
10768+
10769diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
10770new file mode 100644
10771index 0000000..bac5ece
10772--- /dev/null
10773+++ b/drivers/video/omap2/dss/dss.h
10774@@ -0,0 +1,331 @@
10775+/*
10776+ * linux/drivers/video/omap2/dss/dss.h
10777+ *
10778+ * Copyright (C) 2009 Nokia Corporation
10779+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
10780+ *
10781+ * Some code and ideas taken from drivers/video/omap/ driver
10782+ * by Imre Deak.
10783+ *
10784+ * This program is free software; you can redistribute it and/or modify it
10785+ * under the terms of the GNU General Public License version 2 as published by
10786+ * the Free Software Foundation.
10787+ *
10788+ * This program is distributed in the hope that it will be useful, but WITHOUT
10789+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10790+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
10791+ * more details.
10792+ *
10793+ * You should have received a copy of the GNU General Public License along with
10794+ * this program. If not, see <http://www.gnu.org/licenses/>.
10795+ */
10796+
10797+#ifndef __OMAP2_DSS_H
10798+#define __OMAP2_DSS_H
10799+
10800+#ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
10801+#define DEBUG
10802+#endif
10803+
10804+#ifdef DEBUG
10805+extern unsigned int dss_debug;
10806+#ifdef DSS_SUBSYS_NAME
10807+#define DSSDBG(format, ...) \
10808+ if (dss_debug) \
10809+ printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
10810+ ## __VA_ARGS__)
10811+#else
10812+#define DSSDBG(format, ...) \
10813+ if (dss_debug) \
10814+ printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
10815+#endif
10816+
10817+#ifdef DSS_SUBSYS_NAME
10818+#define DSSDBGF(format, ...) \
10819+ if (dss_debug) \
10820+ printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
10821+ ": %s(" format ")\n", \
10822+ __func__, \
10823+ ## __VA_ARGS__)
10824+#else
10825+#define DSSDBGF(format, ...) \
10826+ if (dss_debug) \
10827+ printk(KERN_DEBUG "omapdss: " \
10828+ ": %s(" format ")\n", \
10829+ __func__, \
10830+ ## __VA_ARGS__)
10831+#endif
10832+
10833+#else /* DEBUG */
10834+#define DSSDBG(format, ...)
10835+#define DSSDBGF(format, ...)
10836+#endif
10837+
10838+
10839+#ifdef DSS_SUBSYS_NAME
10840+#define DSSERR(format, ...) \
10841+ printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
10842+ ## __VA_ARGS__)
10843+#else
10844+#define DSSERR(format, ...) \
10845+ printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
10846+#endif
10847+
10848+#ifdef DSS_SUBSYS_NAME
10849+#define DSSINFO(format, ...) \
10850+ printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
10851+ ## __VA_ARGS__)
10852+#else
10853+#define DSSINFO(format, ...) \
10854+ printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
10855+#endif
10856+
10857+#ifdef DSS_SUBSYS_NAME
10858+#define DSSWARN(format, ...) \
10859+ printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
10860+ ## __VA_ARGS__)
10861+#else
10862+#define DSSWARN(format, ...) \
10863+ printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
10864+#endif
10865+
10866+/* OMAP TRM gives bitfields as start:end, where start is the higher bit
10867+ number. For example 7:0 */
10868+#define FLD_MASK(start, end) (((1 << (start - end + 1)) - 1) << (end))
10869+#define FLD_VAL(val, start, end) (((val) << end) & FLD_MASK(start, end))
10870+#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
10871+#define FLD_MOD(orig, val, start, end) \
10872+ (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
10873+
10874+#define DISPC_MAX_FCK 173000000
10875+
10876+enum omap_burst_size {
10877+ OMAP_DSS_BURST_4x32 = 0,
10878+ OMAP_DSS_BURST_8x32 = 1,
10879+ OMAP_DSS_BURST_16x32 = 2,
10880+};
10881+
10882+enum omap_parallel_interface_mode {
10883+ OMAP_DSS_PARALLELMODE_BYPASS, /* MIPI DPI */
10884+ OMAP_DSS_PARALLELMODE_RFBI, /* MIPI DBI */
10885+ OMAP_DSS_PARALLELMODE_DSI,
10886+};
10887+
10888+enum dss_clock {
10889+ DSS_CLK_ICK = 1 << 0,
10890+ DSS_CLK_FCK1 = 1 << 1,
10891+ DSS_CLK_FCK2 = 1 << 2,
10892+ DSS_CLK_54M = 1 << 3,
10893+ DSS_CLK_96M = 1 << 4,
10894+};
10895+
10896+struct dispc_clock_info {
10897+ /* rates that we get with dividers below */
10898+ unsigned long fck;
10899+ unsigned long lck;
10900+ unsigned long pck;
10901+
10902+ /* dividers */
10903+ u16 fck_div;
10904+ u16 lck_div;
10905+ u16 pck_div;
10906+};
10907+
10908+struct dsi_clock_info {
10909+ /* rates that we get with dividers below */
10910+ unsigned long fint;
10911+ unsigned long dsiphy;
10912+ unsigned long clkin;
10913+ unsigned long dsi1_pll_fclk;
10914+ unsigned long dsi2_pll_fclk;
10915+ unsigned long lck;
10916+ unsigned long pck;
10917+
10918+ /* dividers */
10919+ u16 regn;
10920+ u16 regm;
10921+ u16 regm3;
10922+ u16 regm4;
10923+
10924+ u16 lck_div;
10925+ u16 pck_div;
10926+
10927+ u8 highfreq;
10928+ bool use_dss2_fck;
10929+};
10930+
10931+struct seq_file;
10932+struct platform_device;
10933+
10934+/* core */
10935+void dss_clk_enable(enum dss_clock clks);
10936+void dss_clk_disable(enum dss_clock clks);
10937+unsigned long dss_clk_get_rate(enum dss_clock clk);
10938+int dss_need_ctx_restore(void);
10939+void dss_dump_clocks(struct seq_file *s);
10940+
10941+int dss_dsi_power_up(void);
10942+void dss_dsi_power_down(void);
10943+
10944+/* display */
10945+void dss_init_displays(struct platform_device *pdev);
10946+void dss_uninit_displays(struct platform_device *pdev);
10947+int dss_suspend_all_displays(void);
10948+int dss_resume_all_displays(void);
10949+struct omap_display *dss_get_display(int no);
10950+
10951+/* manager */
10952+int dss_init_overlay_managers(struct platform_device *pdev);
10953+void dss_uninit_overlay_managers(struct platform_device *pdev);
10954+
10955+/* overlay */
10956+void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name);
10957+void dss_uninit_overlays(struct platform_device *pdev);
10958+int dss_check_overlay(struct omap_overlay *ovl, struct omap_display *display);
10959+void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
10960+
10961+/* DSS */
10962+int dss_init(bool skip_init);
10963+void dss_exit(void);
10964+
10965+void dss_save_context(void);
10966+void dss_restore_context(void);
10967+
10968+void dss_dump_regs(struct seq_file *s);
10969+
10970+void dss_sdi_init(u8 datapairs);
10971+void dss_sdi_enable(void);
10972+void dss_sdi_disable(void);
10973+
10974+void dss_select_clk_source(bool dsi, bool dispc);
10975+int dss_get_dsi_clk_source(void);
10976+int dss_get_dispc_clk_source(void);
10977+void dss_set_venc_output(enum omap_dss_venc_type type);
10978+void dss_set_dac_pwrdn_bgz(bool enable);
10979+
10980+/* SDI */
10981+int sdi_init(bool skip_init);
10982+void sdi_exit(void);
10983+void sdi_init_display(struct omap_display *display);
10984+
10985+/* DSI */
10986+int dsi_init(void);
10987+void dsi_exit(void);
10988+
10989+void dsi_dump_clocks(struct seq_file *s);
10990+void dsi_dump_regs(struct seq_file *s);
10991+
10992+void dsi_save_context(void);
10993+void dsi_restore_context(void);
10994+
10995+void dsi_init_display(struct omap_display *display);
10996+void dsi_irq_handler(void);
10997+unsigned long dsi_get_dsi1_pll_rate(void);
10998+unsigned long dsi_get_dsi2_pll_rate(void);
10999+int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck,
11000+ struct dsi_clock_info *cinfo);
11001+int dsi_pll_program(struct dsi_clock_info *cinfo);
11002+int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv);
11003+void dsi_pll_uninit(void);
11004+
11005+/* DPI */
11006+int dpi_init(void);
11007+void dpi_exit(void);
11008+void dpi_init_display(struct omap_display *display);
11009+
11010+/* DISPC */
11011+int dispc_init(void);
11012+void dispc_exit(void);
11013+void dispc_dump_clocks(struct seq_file *s);
11014+void dispc_dump_regs(struct seq_file *s);
11015+void dispc_irq_handler(void);
11016+void dispc_fake_vsync_irq(void);
11017+
11018+void dispc_save_context(void);
11019+void dispc_restore_context(void);
11020+
11021+void dispc_lcd_enable_signal_polarity(bool act_high);
11022+void dispc_lcd_enable_signal(bool enable);
11023+void dispc_pck_free_enable(bool enable);
11024+void dispc_enable_fifohandcheck(bool enable);
11025+
11026+void dispc_set_lcd_size(u16 width, u16 height);
11027+void dispc_set_digit_size(u16 width, u16 height);
11028+u32 dispc_get_plane_fifo_size(enum omap_plane plane);
11029+void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
11030+void dispc_enable_fifomerge(bool enable);
11031+void dispc_set_burst_size(enum omap_plane plane,
11032+ enum omap_burst_size burst_size);
11033+
11034+void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
11035+void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
11036+void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
11037+void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
11038+
11039+int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
11040+ u32 paddr, u16 screen_width,
11041+ u16 pos_x, u16 pos_y,
11042+ u16 width, u16 height,
11043+ u16 out_width, u16 out_height,
11044+ enum omap_color_mode color_mode,
11045+ bool ilace,
11046+ u8 rotation, bool mirror);
11047+
11048+void dispc_go(enum omap_channel channel);
11049+void dispc_enable_lcd_out(bool enable);
11050+void dispc_enable_digit_out(bool enable);
11051+int dispc_enable_plane(enum omap_plane plane, bool enable);
11052+
11053+void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode);
11054+void dispc_set_tft_data_lines(u8 data_lines);
11055+void dispc_set_lcd_display_type(enum omap_lcd_display_type type);
11056+void dispc_set_loadmode(enum omap_dss_load_mode mode);
11057+
11058+void dispc_set_default_color(enum omap_channel channel, u32 color);
11059+u32 dispc_get_default_color(enum omap_channel channel);
11060+void dispc_set_trans_key(enum omap_channel ch,
11061+ enum omap_dss_color_key_type type,
11062+ u32 trans_key);
11063+void dispc_get_trans_key(enum omap_channel ch,
11064+ enum omap_dss_color_key_type *type,
11065+ u32 *trans_key);
11066+void dispc_enable_trans_key(enum omap_channel ch, bool enable);
11067+bool dispc_trans_key_enabled(enum omap_channel ch);
11068+
11069+void dispc_set_lcd_timings(struct omap_video_timings *timings);
11070+unsigned long dispc_fclk_rate(void);
11071+unsigned long dispc_pclk_rate(void);
11072+void dispc_set_pol_freq(struct omap_panel *panel);
11073+void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
11074+ u16 *lck_div, u16 *pck_div);
11075+int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
11076+ struct dispc_clock_info *cinfo);
11077+int dispc_set_clock_div(struct dispc_clock_info *cinfo);
11078+int dispc_get_clock_div(struct dispc_clock_info *cinfo);
11079+void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div);
11080+
11081+void dispc_setup_partial_planes(struct omap_display *display,
11082+ u16 *x, u16 *y, u16 *w, u16 *h);
11083+void dispc_draw_partial_planes(struct omap_display *display);
11084+
11085+
11086+/* VENC */
11087+int venc_init(void);
11088+void venc_exit(void);
11089+void venc_dump_regs(struct seq_file *s);
11090+void venc_init_display(struct omap_display *display);
11091+
11092+/* RFBI */
11093+int rfbi_init(void);
11094+void rfbi_exit(void);
11095+void rfbi_dump_regs(struct seq_file *s);
11096+
11097+int rfbi_configure(int rfbi_module, int bpp, int lines);
11098+void rfbi_enable_rfbi(bool enable);
11099+void rfbi_transfer_area(u16 width, u16 height,
11100+ void (callback)(void *data), void *data);
11101+void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
11102+unsigned long rfbi_get_max_tx_rate(void);
11103+void rfbi_init_display(struct omap_display *display);
11104+
11105+#endif
11106diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
11107new file mode 100644
11108index 0000000..b0fee80
11109--- /dev/null
11110+++ b/drivers/video/omap2/dss/manager.c
11111@@ -0,0 +1,576 @@
11112+/*
11113+ * linux/drivers/video/omap2/dss/manager.c
11114+ *
11115+ * Copyright (C) 2009 Nokia Corporation
11116+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
11117+ *
11118+ * Some code and ideas taken from drivers/video/omap/ driver
11119+ * by Imre Deak.
11120+ *
11121+ * This program is free software; you can redistribute it and/or modify it
11122+ * under the terms of the GNU General Public License version 2 as published by
11123+ * the Free Software Foundation.
11124+ *
11125+ * This program is distributed in the hope that it will be useful, but WITHOUT
11126+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11127+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11128+ * more details.
11129+ *
11130+ * You should have received a copy of the GNU General Public License along with
11131+ * this program. If not, see <http://www.gnu.org/licenses/>.
11132+ */
11133+
11134+#define DSS_SUBSYS_NAME "MANAGER"
11135+
11136+#include <linux/kernel.h>
11137+#include <linux/module.h>
11138+#include <linux/platform_device.h>
11139+
11140+#include <mach/display.h>
11141+
11142+#include "dss.h"
11143+
11144+static int num_managers;
11145+static struct list_head manager_list;
11146+
11147+static ssize_t manager_name_show(struct omap_overlay_manager *mgr, char *buf)
11148+{
11149+ return snprintf(buf, PAGE_SIZE, "%s\n", mgr->name);
11150+}
11151+
11152+static ssize_t manager_display_show(struct omap_overlay_manager *mgr, char *buf)
11153+{
11154+ return snprintf(buf, PAGE_SIZE, "%s\n",
11155+ mgr->display ? mgr->display->name : "<none>");
11156+}
11157+
11158+static ssize_t manager_display_store(struct omap_overlay_manager *mgr, const char *buf, size_t size)
11159+{
11160+ int r, i;
11161+ int len = size;
11162+ struct omap_display *display = NULL;
11163+
11164+ if (buf[size-1] == '\n')
11165+ --len;
11166+
11167+ if (len > 0) {
11168+ for (i = 0; i < omap_dss_get_num_displays(); ++i) {
11169+ display = dss_get_display(i);
11170+
11171+ if (strncmp(buf, display->name, len) == 0)
11172+ break;
11173+
11174+ display = NULL;
11175+ }
11176+ }
11177+
11178+ if (len > 0 && display == NULL)
11179+ return -EINVAL;
11180+
11181+ if (display)
11182+ DSSDBG("display %s found\n", display->name);
11183+
11184+ if (mgr->display) {
11185+ r = mgr->unset_display(mgr);
11186+ if (r) {
11187+ DSSERR("failed to unset display\n");
11188+ return r;
11189+ }
11190+ }
11191+
11192+ if (display) {
11193+ r = mgr->set_display(mgr, display);
11194+ if (r) {
11195+ DSSERR("failed to set manager\n");
11196+ return r;
11197+ }
11198+
11199+ r = mgr->apply(mgr);
11200+ if (r) {
11201+ DSSERR("failed to apply dispc config\n");
11202+ return r;
11203+ }
11204+ }
11205+
11206+ return size;
11207+}
11208+
11209+static ssize_t manager_default_color_show(struct omap_overlay_manager *mgr,
11210+ char *buf)
11211+{
11212+ u32 default_color;
11213+
11214+ default_color = dispc_get_default_color(mgr->id);
11215+ return snprintf(buf, PAGE_SIZE, "%d", default_color);
11216+}
11217+
11218+static ssize_t manager_default_color_store(struct omap_overlay_manager *mgr,
11219+ const char *buf, size_t size)
11220+{
11221+ u32 default_color;
11222+
11223+ if (sscanf(buf, "%d", &default_color) != 1)
11224+ return -EINVAL;
11225+ dispc_set_default_color(mgr->id, default_color);
11226+
11227+ return size;
11228+}
11229+
11230+static const char *color_key_type_str[] = {
11231+ "gfx-destination",
11232+ "video-source",
11233+};
11234+
11235+static ssize_t manager_color_key_type_show(struct omap_overlay_manager *mgr,
11236+ char *buf)
11237+{
11238+ enum omap_dss_color_key_type key_type;
11239+
11240+ dispc_get_trans_key(mgr->id, &key_type, NULL);
11241+ BUG_ON(key_type >= ARRAY_SIZE(color_key_type_str));
11242+
11243+ return snprintf(buf, PAGE_SIZE, "%s\n", color_key_type_str[key_type]);
11244+}
11245+
11246+static ssize_t manager_color_key_type_store(struct omap_overlay_manager *mgr,
11247+ const char *buf, size_t size)
11248+{
11249+ enum omap_dss_color_key_type key_type;
11250+ u32 key_value;
11251+
11252+ for (key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
11253+ key_type < ARRAY_SIZE(color_key_type_str); key_type++) {
11254+ if (sysfs_streq(buf, color_key_type_str[key_type]))
11255+ break;
11256+ }
11257+ if (key_type == ARRAY_SIZE(color_key_type_str))
11258+ return -EINVAL;
11259+ dispc_get_trans_key(mgr->id, NULL, &key_value);
11260+ dispc_set_trans_key(mgr->id, key_type, key_value);
11261+
11262+ return size;
11263+}
11264+
11265+static ssize_t manager_color_key_value_show(struct omap_overlay_manager *mgr,
11266+ char *buf)
11267+{
11268+ u32 key_value;
11269+
11270+ dispc_get_trans_key(mgr->id, NULL, &key_value);
11271+
11272+ return snprintf(buf, PAGE_SIZE, "%d\n", key_value);
11273+}
11274+
11275+static ssize_t manager_color_key_value_store(struct omap_overlay_manager *mgr,
11276+ const char *buf, size_t size)
11277+{
11278+ enum omap_dss_color_key_type key_type;
11279+ u32 key_value;
11280+
11281+ if (sscanf(buf, "%d", &key_value) != 1)
11282+ return -EINVAL;
11283+ dispc_get_trans_key(mgr->id, &key_type, NULL);
11284+ dispc_set_trans_key(mgr->id, key_type, key_value);
11285+
11286+ return size;
11287+}
11288+
11289+static ssize_t manager_color_key_enabled_show(struct omap_overlay_manager *mgr,
11290+ char *buf)
11291+{
11292+ return snprintf(buf, PAGE_SIZE, "%d\n",
11293+ dispc_trans_key_enabled(mgr->id));
11294+}
11295+
11296+static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
11297+ const char *buf, size_t size)
11298+{
11299+ int enable;
11300+
11301+ if (sscanf(buf, "%d", &enable) != 1)
11302+ return -EINVAL;
11303+
11304+ dispc_enable_trans_key(mgr->id, enable);
11305+
11306+ return size;
11307+}
11308+
11309+
11310+struct manager_attribute {
11311+ struct attribute attr;
11312+ ssize_t (*show)(struct omap_overlay_manager *, char *);
11313+ ssize_t (*store)(struct omap_overlay_manager *, const char *, size_t);
11314+};
11315+
11316+#define MANAGER_ATTR(_name, _mode, _show, _store) \
11317+ struct manager_attribute manager_attr_##_name = \
11318+ __ATTR(_name, _mode, _show, _store)
11319+
11320+static MANAGER_ATTR(name, S_IRUGO, manager_name_show, NULL);
11321+static MANAGER_ATTR(display, S_IRUGO|S_IWUSR,
11322+ manager_display_show, manager_display_store);
11323+static MANAGER_ATTR(default_color, S_IRUGO|S_IWUSR,
11324+ manager_default_color_show, manager_default_color_store);
11325+static MANAGER_ATTR(color_key_type, S_IRUGO|S_IWUSR,
11326+ manager_color_key_type_show, manager_color_key_type_store);
11327+static MANAGER_ATTR(color_key_value, S_IRUGO|S_IWUSR,
11328+ manager_color_key_value_show, manager_color_key_value_store);
11329+static MANAGER_ATTR(color_key_enabled, S_IRUGO|S_IWUSR,
11330+ manager_color_key_enabled_show, manager_color_key_enabled_store);
11331+
11332+static struct attribute *manager_sysfs_attrs[] = {
11333+ &manager_attr_name.attr,
11334+ &manager_attr_display.attr,
11335+ &manager_attr_default_color.attr,
11336+ &manager_attr_color_key_type.attr,
11337+ &manager_attr_color_key_value.attr,
11338+ &manager_attr_color_key_enabled.attr,
11339+ NULL
11340+};
11341+
11342+static ssize_t manager_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
11343+{
11344+ struct omap_overlay_manager *manager;
11345+ struct manager_attribute *manager_attr;
11346+
11347+ manager = container_of(kobj, struct omap_overlay_manager, kobj);
11348+ manager_attr = container_of(attr, struct manager_attribute, attr);
11349+
11350+ if (!manager_attr->show)
11351+ return -ENOENT;
11352+
11353+ return manager_attr->show(manager, buf);
11354+}
11355+
11356+static ssize_t manager_attr_store(struct kobject *kobj, struct attribute *attr,
11357+ const char *buf, size_t size)
11358+{
11359+ struct omap_overlay_manager *manager;
11360+ struct manager_attribute *manager_attr;
11361+
11362+ manager = container_of(kobj, struct omap_overlay_manager, kobj);
11363+ manager_attr = container_of(attr, struct manager_attribute, attr);
11364+
11365+ if (!manager_attr->store)
11366+ return -ENOENT;
11367+
11368+ return manager_attr->store(manager, buf, size);
11369+}
11370+
11371+static struct sysfs_ops manager_sysfs_ops = {
11372+ .show = manager_attr_show,
11373+ .store = manager_attr_store,
11374+};
11375+
11376+static struct kobj_type manager_ktype = {
11377+ .sysfs_ops = &manager_sysfs_ops,
11378+ .default_attrs = manager_sysfs_attrs,
11379+};
11380+
11381+static int omap_dss_set_display(struct omap_overlay_manager *mgr,
11382+ struct omap_display *display)
11383+{
11384+ int i;
11385+ int r;
11386+
11387+ if (display->manager) {
11388+ DSSERR("display '%s' already has a manager '%s'\n",
11389+ display->name, display->manager->name);
11390+ return -EINVAL;
11391+ }
11392+
11393+ if ((mgr->supported_displays & display->type) == 0) {
11394+ DSSERR("display '%s' does not support manager '%s'\n",
11395+ display->name, mgr->name);
11396+ return -EINVAL;
11397+ }
11398+
11399+ for (i = 0; i < mgr->num_overlays; i++) {
11400+ struct omap_overlay *ovl = mgr->overlays[i];
11401+
11402+ if (ovl->manager != mgr || !ovl->info.enabled)
11403+ continue;
11404+
11405+ r = dss_check_overlay(ovl, display);
11406+ if (r)
11407+ return r;
11408+ }
11409+
11410+ display->manager = mgr;
11411+ mgr->display = display;
11412+
11413+ return 0;
11414+}
11415+
11416+static int omap_dss_unset_display(struct omap_overlay_manager *mgr)
11417+{
11418+ if (!mgr->display) {
11419+ DSSERR("failed to unset display, display not set.\n");
11420+ return -EINVAL;
11421+ }
11422+
11423+ mgr->display->manager = NULL;
11424+ mgr->display = NULL;
11425+
11426+ return 0;
11427+}
11428+
11429+
11430+static int overlay_enabled(struct omap_overlay *ovl)
11431+{
11432+ return ovl->info.enabled && ovl->manager && ovl->manager->display;
11433+}
11434+
11435+/* We apply settings to both managers here so that we can use optimizations
11436+ * like fifomerge. Shadow registers can be changed first and the non-shadowed
11437+ * should be changed last, at the same time with GO */
11438+static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
11439+{
11440+ int i;
11441+ int ret = 0;
11442+ enum omap_dss_update_mode mode;
11443+ struct omap_display *display;
11444+ struct omap_overlay *ovl;
11445+ bool ilace = 0;
11446+ int outw, outh;
11447+ int r;
11448+ int num_planes_enabled = 0;
11449+
11450+ DSSDBG("omap_dss_mgr_apply(%s)\n", mgr->name);
11451+
11452+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
11453+
11454+ /* Configure normal overlay parameters and disable unused overlays */
11455+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
11456+ ovl = omap_dss_get_overlay(i);
11457+
11458+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
11459+ continue;
11460+
11461+ if (!overlay_enabled(ovl)) {
11462+ dispc_enable_plane(ovl->id, 0);
11463+ continue;
11464+ }
11465+
11466+ display = ovl->manager->display;
11467+
11468+ if (dss_check_overlay(ovl, display)) {
11469+ dispc_enable_plane(ovl->id, 0);
11470+ continue;
11471+ }
11472+
11473+ ++num_planes_enabled;
11474+
11475+ /* On a manual update display, in manual update mode, update()
11476+ * handles configuring planes */
11477+ mode = OMAP_DSS_UPDATE_AUTO;
11478+ if (display->get_update_mode)
11479+ mode = display->get_update_mode(mgr->display);
11480+
11481+ if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE &&
11482+ mode != OMAP_DSS_UPDATE_AUTO)
11483+ continue;
11484+
11485+ if (display->type == OMAP_DISPLAY_TYPE_VENC)
11486+ ilace = 1;
11487+
11488+ if (ovl->info.out_width == 0)
11489+ outw = ovl->info.width;
11490+ else
11491+ outw = ovl->info.out_width;
11492+
11493+ if (ovl->info.out_height == 0)
11494+ outh = ovl->info.height;
11495+ else
11496+ outh = ovl->info.out_height;
11497+
11498+ r = dispc_setup_plane(ovl->id, ovl->manager->id,
11499+ ovl->info.paddr,
11500+ ovl->info.screen_width,
11501+ ovl->info.pos_x,
11502+ ovl->info.pos_y,
11503+ ovl->info.width,
11504+ ovl->info.height,
11505+ outw,
11506+ outh,
11507+ ovl->info.color_mode,
11508+ ilace,
11509+ ovl->info.rotation,
11510+ ovl->info.mirror);
11511+
11512+ if (r) {
11513+ DSSERR("dispc_setup_plane failed for ovl %d\n",
11514+ ovl->id);
11515+ dispc_enable_plane(ovl->id, 0);
11516+ continue;
11517+ }
11518+
11519+ dispc_enable_plane(ovl->id, 1);
11520+ }
11521+
11522+ /* Enable fifo merge if possible */
11523+ dispc_enable_fifomerge(num_planes_enabled == 1);
11524+
11525+ /* Go through overlays again. This time we configure fifos. We have to
11526+ * do this after enabling/disabling fifomerge so that we have correct
11527+ * knowledge of fifo sizes */
11528+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
11529+ ovl = omap_dss_get_overlay(i);
11530+
11531+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
11532+ continue;
11533+
11534+ if (!overlay_enabled(ovl)) {
11535+ continue;
11536+ }
11537+
11538+ ovl->manager->display->configure_overlay(ovl);
11539+ }
11540+
11541+ /* Issue GO for managers */
11542+ list_for_each_entry(mgr, &manager_list, list) {
11543+ if (!(mgr->caps & OMAP_DSS_OVL_MGR_CAP_DISPC))
11544+ continue;
11545+
11546+ display = mgr->display;
11547+
11548+ if (!display)
11549+ continue;
11550+
11551+ /* We don't need GO with manual update display. LCD iface will
11552+ * always be turned off after frame, and new settings will
11553+ * be taken in to use at next update */
11554+ if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE)
11555+ continue;
11556+
11557+ dispc_go(mgr->id);
11558+ }
11559+
11560+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
11561+
11562+ return ret;
11563+}
11564+
11565+static void omap_dss_mgr_set_def_color(struct omap_overlay_manager *mgr,
11566+ u32 color)
11567+{
11568+ dispc_set_default_color(mgr->id, color);
11569+}
11570+
11571+static void omap_dss_mgr_set_trans_key(struct omap_overlay_manager *mgr,
11572+ enum omap_dss_color_key_type type,
11573+ u32 trans_key)
11574+{
11575+ dispc_set_trans_key(mgr->id, type, trans_key);
11576+}
11577+
11578+static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
11579+ bool enable)
11580+{
11581+ dispc_enable_trans_key(mgr->id, enable);
11582+}
11583+
11584+static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager)
11585+{
11586+ ++num_managers;
11587+ list_add_tail(&manager->list, &manager_list);
11588+}
11589+
11590+int dss_init_overlay_managers(struct platform_device *pdev)
11591+{
11592+ int i, r;
11593+
11594+ INIT_LIST_HEAD(&manager_list);
11595+
11596+ num_managers = 0;
11597+
11598+ for (i = 0; i < 2; ++i) {
11599+ struct omap_overlay_manager *mgr;
11600+ mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
11601+
11602+ BUG_ON(mgr == NULL);
11603+
11604+ switch (i) {
11605+ case 0:
11606+ mgr->name = "lcd";
11607+ mgr->id = OMAP_DSS_CHANNEL_LCD;
11608+ mgr->supported_displays =
11609+ OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
11610+ OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI;
11611+ break;
11612+ case 1:
11613+ mgr->name = "tv";
11614+ mgr->id = OMAP_DSS_CHANNEL_DIGIT;
11615+ mgr->supported_displays = OMAP_DISPLAY_TYPE_VENC;
11616+ break;
11617+ }
11618+
11619+ mgr->set_display = &omap_dss_set_display,
11620+ mgr->unset_display = &omap_dss_unset_display,
11621+ mgr->apply = &omap_dss_mgr_apply,
11622+ mgr->set_default_color = &omap_dss_mgr_set_def_color,
11623+ mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
11624+ mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
11625+ mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
11626+
11627+ dss_overlay_setup_dispc_manager(mgr);
11628+
11629+ omap_dss_add_overlay_manager(mgr);
11630+
11631+ r = kobject_init_and_add(&mgr->kobj, &manager_ktype,
11632+ &pdev->dev.kobj, "manager%d", i);
11633+
11634+ if (r) {
11635+ DSSERR("failed to create sysfs file\n");
11636+ continue;
11637+ }
11638+ }
11639+
11640+ return 0;
11641+}
11642+
11643+void dss_uninit_overlay_managers(struct platform_device *pdev)
11644+{
11645+ struct omap_overlay_manager *mgr;
11646+
11647+ while (!list_empty(&manager_list)) {
11648+ mgr = list_first_entry(&manager_list,
11649+ struct omap_overlay_manager, list);
11650+ list_del(&mgr->list);
11651+ kobject_del(&mgr->kobj);
11652+ kobject_put(&mgr->kobj);
11653+ kfree(mgr);
11654+ }
11655+
11656+ num_managers = 0;
11657+}
11658+
11659+int omap_dss_get_num_overlay_managers(void)
11660+{
11661+ return num_managers;
11662+}
11663+EXPORT_SYMBOL(omap_dss_get_num_overlay_managers);
11664+
11665+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num)
11666+{
11667+ int i = 0;
11668+ struct omap_overlay_manager *mgr;
11669+
11670+ list_for_each_entry(mgr, &manager_list, list) {
11671+ if (i++ == num)
11672+ return mgr;
11673+ }
11674+
11675+ return NULL;
11676+}
11677+EXPORT_SYMBOL(omap_dss_get_overlay_manager);
11678+
11679+#ifdef L4_EXAMPLE
11680+static int ovl_mgr_apply_l4(struct omap_overlay_manager *mgr)
11681+{
11682+ DSSDBG("omap_dss_mgr_apply_l4(%s)\n", mgr->name);
11683+
11684+ return 0;
11685+}
11686+#endif
11687+
11688diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
11689new file mode 100644
11690index 0000000..968edbe
11691--- /dev/null
11692+++ b/drivers/video/omap2/dss/overlay.c
11693@@ -0,0 +1,587 @@
11694+/*
11695+ * linux/drivers/video/omap2/dss/overlay.c
11696+ *
11697+ * Copyright (C) 2009 Nokia Corporation
11698+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
11699+ *
11700+ * Some code and ideas taken from drivers/video/omap/ driver
11701+ * by Imre Deak.
11702+ *
11703+ * This program is free software; you can redistribute it and/or modify it
11704+ * under the terms of the GNU General Public License version 2 as published by
11705+ * the Free Software Foundation.
11706+ *
11707+ * This program is distributed in the hope that it will be useful, but WITHOUT
11708+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11709+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11710+ * more details.
11711+ *
11712+ * You should have received a copy of the GNU General Public License along with
11713+ * this program. If not, see <http://www.gnu.org/licenses/>.
11714+ */
11715+
11716+#define DSS_SUBSYS_NAME "OVERLAY"
11717+
11718+#include <linux/kernel.h>
11719+#include <linux/module.h>
11720+#include <linux/err.h>
11721+#include <linux/sysfs.h>
11722+#include <linux/kobject.h>
11723+#include <linux/platform_device.h>
11724+
11725+#include <mach/display.h>
11726+
11727+#include "dss.h"
11728+
11729+static int num_overlays;
11730+static struct list_head overlay_list;
11731+
11732+static ssize_t overlay_name_show(struct omap_overlay *ovl, char *buf)
11733+{
11734+ return snprintf(buf, PAGE_SIZE, "%s\n", ovl->name);
11735+}
11736+
11737+static ssize_t overlay_manager_show(struct omap_overlay *ovl, char *buf)
11738+{
11739+ return snprintf(buf, PAGE_SIZE, "%s\n",
11740+ ovl->manager ? ovl->manager->name : "<none>");
11741+}
11742+
11743+static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf, size_t size)
11744+{
11745+ int i, r;
11746+ struct omap_overlay_manager *mgr = NULL;
11747+ int len = size;
11748+
11749+ if (buf[size-1] == '\n')
11750+ --len;
11751+
11752+ if (len > 0) {
11753+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
11754+ mgr = omap_dss_get_overlay_manager(i);
11755+
11756+ if (strncmp(buf, mgr->name, len) == 0)
11757+ break;
11758+
11759+ mgr = NULL;
11760+ }
11761+ }
11762+
11763+ if (len > 0 && mgr == NULL)
11764+ return -EINVAL;
11765+
11766+ if (mgr)
11767+ DSSDBG("manager %s found\n", mgr->name);
11768+
11769+ if (mgr != ovl->manager) {
11770+ /* detach old manager */
11771+ if (ovl->manager) {
11772+ r = ovl->unset_manager(ovl);
11773+ if (r) {
11774+ DSSERR("detach failed\n");
11775+ return r;
11776+ }
11777+ }
11778+
11779+ if (mgr) {
11780+ r = ovl->set_manager(ovl, mgr);
11781+ if (r) {
11782+ DSSERR("Failed to attach overlay\n");
11783+ return r;
11784+ }
11785+ }
11786+ }
11787+
11788+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
11789+ return r;
11790+
11791+ return size;
11792+}
11793+
11794+static ssize_t overlay_input_size_show(struct omap_overlay *ovl, char *buf)
11795+{
11796+ return snprintf(buf, PAGE_SIZE, "%d,%d\n",
11797+ ovl->info.width, ovl->info.height);
11798+}
11799+
11800+static ssize_t overlay_screen_width_show(struct omap_overlay *ovl, char *buf)
11801+{
11802+ return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.screen_width);
11803+}
11804+
11805+static ssize_t overlay_position_show(struct omap_overlay *ovl, char *buf)
11806+{
11807+ return snprintf(buf, PAGE_SIZE, "%d,%d\n",
11808+ ovl->info.pos_x, ovl->info.pos_y);
11809+}
11810+
11811+static ssize_t overlay_position_store(struct omap_overlay *ovl,
11812+ const char *buf, size_t size)
11813+{
11814+ int r;
11815+ char *last;
11816+ struct omap_overlay_info info;
11817+
11818+ ovl->get_overlay_info(ovl, &info);
11819+
11820+ info.pos_x = simple_strtoul(buf, &last, 10);
11821+ ++last;
11822+ if (last - buf >= size)
11823+ return -EINVAL;
11824+
11825+ info.pos_y = simple_strtoul(last, &last, 10);
11826+
11827+ if ((r = ovl->set_overlay_info(ovl, &info)))
11828+ return r;
11829+
11830+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
11831+ return r;
11832+
11833+ return size;
11834+}
11835+
11836+static ssize_t overlay_output_size_show(struct omap_overlay *ovl, char *buf)
11837+{
11838+ return snprintf(buf, PAGE_SIZE, "%d,%d\n",
11839+ ovl->info.out_width, ovl->info.out_height);
11840+}
11841+
11842+static ssize_t overlay_output_size_store(struct omap_overlay *ovl,
11843+ const char *buf, size_t size)
11844+{
11845+ int r;
11846+ char *last;
11847+ struct omap_overlay_info info;
11848+
11849+ ovl->get_overlay_info(ovl, &info);
11850+
11851+ info.out_width = simple_strtoul(buf, &last, 10);
11852+ ++last;
11853+ if (last - buf >= size)
11854+ return -EINVAL;
11855+
11856+ info.out_height = simple_strtoul(last, &last, 10);
11857+
11858+ if ((r = ovl->set_overlay_info(ovl, &info)))
11859+ return r;
11860+
11861+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
11862+ return r;
11863+
11864+ return size;
11865+}
11866+
11867+static ssize_t overlay_enabled_show(struct omap_overlay *ovl, char *buf)
11868+{
11869+ return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.enabled);
11870+}
11871+
11872+static ssize_t overlay_enabled_store(struct omap_overlay *ovl, const char *buf, size_t size)
11873+{
11874+ int r;
11875+ struct omap_overlay_info info;
11876+
11877+ ovl->get_overlay_info(ovl, &info);
11878+
11879+ info.enabled = simple_strtoul(buf, NULL, 10);
11880+
11881+ if ((r = ovl->set_overlay_info(ovl, &info)))
11882+ return r;
11883+
11884+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
11885+ return r;
11886+
11887+ return size;
11888+}
11889+
11890+struct overlay_attribute {
11891+ struct attribute attr;
11892+ ssize_t (*show)(struct omap_overlay *, char *);
11893+ ssize_t (*store)(struct omap_overlay *, const char *, size_t);
11894+};
11895+
11896+#define OVERLAY_ATTR(_name, _mode, _show, _store) \
11897+ struct overlay_attribute overlay_attr_##_name = \
11898+ __ATTR(_name, _mode, _show, _store)
11899+
11900+static OVERLAY_ATTR(name, S_IRUGO, overlay_name_show, NULL);
11901+static OVERLAY_ATTR(manager, S_IRUGO|S_IWUSR,
11902+ overlay_manager_show, overlay_manager_store);
11903+static OVERLAY_ATTR(input_size, S_IRUGO, overlay_input_size_show, NULL);
11904+static OVERLAY_ATTR(screen_width, S_IRUGO, overlay_screen_width_show, NULL);
11905+static OVERLAY_ATTR(position, S_IRUGO|S_IWUSR,
11906+ overlay_position_show, overlay_position_store);
11907+static OVERLAY_ATTR(output_size, S_IRUGO|S_IWUSR,
11908+ overlay_output_size_show, overlay_output_size_store);
11909+static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
11910+ overlay_enabled_show, overlay_enabled_store);
11911+
11912+static struct attribute *overlay_sysfs_attrs[] = {
11913+ &overlay_attr_name.attr,
11914+ &overlay_attr_manager.attr,
11915+ &overlay_attr_input_size.attr,
11916+ &overlay_attr_screen_width.attr,
11917+ &overlay_attr_position.attr,
11918+ &overlay_attr_output_size.attr,
11919+ &overlay_attr_enabled.attr,
11920+ NULL
11921+};
11922+
11923+static ssize_t overlay_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
11924+{
11925+ struct omap_overlay *overlay;
11926+ struct overlay_attribute *overlay_attr;
11927+
11928+ overlay = container_of(kobj, struct omap_overlay, kobj);
11929+ overlay_attr = container_of(attr, struct overlay_attribute, attr);
11930+
11931+ if (!overlay_attr->show)
11932+ return -ENOENT;
11933+
11934+ return overlay_attr->show(overlay, buf);
11935+}
11936+
11937+static ssize_t overlay_attr_store(struct kobject *kobj, struct attribute *attr,
11938+ const char *buf, size_t size)
11939+{
11940+ struct omap_overlay *overlay;
11941+ struct overlay_attribute *overlay_attr;
11942+
11943+ overlay = container_of(kobj, struct omap_overlay, kobj);
11944+ overlay_attr = container_of(attr, struct overlay_attribute, attr);
11945+
11946+ if (!overlay_attr->store)
11947+ return -ENOENT;
11948+
11949+ return overlay_attr->store(overlay, buf, size);
11950+}
11951+
11952+static struct sysfs_ops overlay_sysfs_ops = {
11953+ .show = overlay_attr_show,
11954+ .store = overlay_attr_store,
11955+};
11956+
11957+static struct kobj_type overlay_ktype = {
11958+ .sysfs_ops = &overlay_sysfs_ops,
11959+ .default_attrs = overlay_sysfs_attrs,
11960+};
11961+
11962+/* Check if overlay parameters are compatible with display */
11963+int dss_check_overlay(struct omap_overlay *ovl, struct omap_display *display)
11964+{
11965+ struct omap_overlay_info *info;
11966+ u16 outw, outh;
11967+ u16 dw, dh;
11968+
11969+ if (!display)
11970+ return 0;
11971+
11972+ if (!ovl->info.enabled)
11973+ return 0;
11974+
11975+ info = &ovl->info;
11976+
11977+ display->get_resolution(display, &dw, &dh);
11978+
11979+ DSSDBG("check_overlay %d: (%d,%d %dx%d -> %dx%d) disp (%dx%d)\n",
11980+ ovl->id,
11981+ info->pos_x, info->pos_y,
11982+ info->width, info->height,
11983+ info->out_width, info->out_height,
11984+ dw, dh);
11985+
11986+ if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
11987+ outw = info->width;
11988+ outh = info->height;
11989+ } else {
11990+ if (info->out_width == 0)
11991+ outw = info->width;
11992+ else
11993+ outw = info->out_width;
11994+
11995+ if (info->out_height == 0)
11996+ outh = info->height;
11997+ else
11998+ outh = info->out_height;
11999+ }
12000+
12001+ if (dw < info->pos_x + outw) {
12002+ DSSDBG("check_overlay failed 1: %d < %d + %d\n",
12003+ dw, info->pos_x, outw);
12004+ return -EINVAL;
12005+ }
12006+
12007+ if (dh < info->pos_y + outh) {
12008+ DSSDBG("check_overlay failed 2: %d < %d + %d\n",
12009+ dh, info->pos_y, outh);
12010+ return -EINVAL;
12011+ }
12012+
12013+ if ((ovl->supported_modes & info->color_mode) == 0) {
12014+ DSSERR("overlay doesn't support mode %d\n", info->color_mode);
12015+ return -EINVAL;
12016+ }
12017+
12018+ return 0;
12019+}
12020+
12021+static int dss_ovl_set_overlay_info(struct omap_overlay *ovl,
12022+ struct omap_overlay_info *info)
12023+{
12024+ int r;
12025+ struct omap_overlay_info old_info;
12026+
12027+ old_info = ovl->info;
12028+ ovl->info = *info;
12029+
12030+ if (ovl->manager) {
12031+ r = dss_check_overlay(ovl, ovl->manager->display);
12032+ if (r) {
12033+ ovl->info = old_info;
12034+ return r;
12035+ }
12036+ }
12037+
12038+ return 0;
12039+}
12040+
12041+static void dss_ovl_get_overlay_info(struct omap_overlay *ovl,
12042+ struct omap_overlay_info *info)
12043+{
12044+ *info = ovl->info;
12045+}
12046+
12047+static int omap_dss_set_manager(struct omap_overlay *ovl,
12048+ struct omap_overlay_manager *mgr)
12049+{
12050+ int r;
12051+
12052+ if (ovl->manager) {
12053+ DSSERR("overlay '%s' already has a manager '%s'\n",
12054+ ovl->name, ovl->manager->name);
12055+ }
12056+
12057+ r = dss_check_overlay(ovl, mgr->display);
12058+ if (r)
12059+ return r;
12060+
12061+ ovl->manager = mgr;
12062+
12063+ return 0;
12064+}
12065+
12066+static int omap_dss_unset_manager(struct omap_overlay *ovl)
12067+{
12068+ if (!ovl->manager) {
12069+ DSSERR("failed to detach overlay: manager not set\n");
12070+ return -EINVAL;
12071+ }
12072+
12073+ ovl->manager = NULL;
12074+
12075+ return 0;
12076+}
12077+
12078+int omap_dss_get_num_overlays(void)
12079+{
12080+ return num_overlays;
12081+}
12082+EXPORT_SYMBOL(omap_dss_get_num_overlays);
12083+
12084+struct omap_overlay *omap_dss_get_overlay(int num)
12085+{
12086+ int i = 0;
12087+ struct omap_overlay *ovl;
12088+
12089+ list_for_each_entry(ovl, &overlay_list, list) {
12090+ if (i++ == num)
12091+ return ovl;
12092+ }
12093+
12094+ return NULL;
12095+}
12096+EXPORT_SYMBOL(omap_dss_get_overlay);
12097+
12098+static void omap_dss_add_overlay(struct omap_overlay *overlay)
12099+{
12100+ ++num_overlays;
12101+ list_add_tail(&overlay->list, &overlay_list);
12102+}
12103+
12104+static struct omap_overlay *dispc_overlays[3];
12105+
12106+void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr)
12107+{
12108+ mgr->num_overlays = 3;
12109+ mgr->overlays = dispc_overlays;
12110+}
12111+
12112+void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name)
12113+{
12114+ int i, r;
12115+ struct omap_overlay_manager *lcd_mgr;
12116+ struct omap_overlay_manager *tv_mgr;
12117+ struct omap_overlay_manager *def_mgr = NULL;
12118+
12119+ INIT_LIST_HEAD(&overlay_list);
12120+
12121+ num_overlays = 0;
12122+
12123+ for (i = 0; i < 3; ++i) {
12124+ struct omap_overlay *ovl;
12125+ ovl = kzalloc(sizeof(*ovl), GFP_KERNEL);
12126+
12127+ BUG_ON(ovl == NULL);
12128+
12129+ switch (i) {
12130+ case 0:
12131+ ovl->name = "gfx";
12132+ ovl->id = OMAP_DSS_GFX;
12133+ ovl->supported_modes = OMAP_DSS_COLOR_GFX_OMAP3;
12134+ ovl->caps = OMAP_DSS_OVL_CAP_DISPC;
12135+ break;
12136+ case 1:
12137+ ovl->name = "vid1";
12138+ ovl->id = OMAP_DSS_VIDEO1;
12139+ ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
12140+ ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
12141+ OMAP_DSS_OVL_CAP_DISPC;
12142+ break;
12143+ case 2:
12144+ ovl->name = "vid2";
12145+ ovl->id = OMAP_DSS_VIDEO2;
12146+ ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
12147+ ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
12148+ OMAP_DSS_OVL_CAP_DISPC;
12149+ break;
12150+ }
12151+
12152+ ovl->set_manager = &omap_dss_set_manager;
12153+ ovl->unset_manager = &omap_dss_unset_manager;
12154+ ovl->set_overlay_info = &dss_ovl_set_overlay_info;
12155+ ovl->get_overlay_info = &dss_ovl_get_overlay_info;
12156+
12157+ omap_dss_add_overlay(ovl);
12158+
12159+ r = kobject_init_and_add(&ovl->kobj, &overlay_ktype,
12160+ &pdev->dev.kobj, "overlay%d", i);
12161+
12162+ if (r) {
12163+ DSSERR("failed to create sysfs file\n");
12164+ continue;
12165+ }
12166+
12167+ dispc_overlays[i] = ovl;
12168+ }
12169+
12170+ lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD);
12171+ tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV);
12172+
12173+ if (def_disp_name) {
12174+ for (i = 0; i < omap_dss_get_num_displays() ; i++) {
12175+ struct omap_display *display = dss_get_display(i);
12176+
12177+ if (strcmp(display->name, def_disp_name) == 0) {
12178+ if (display->type != OMAP_DISPLAY_TYPE_VENC) {
12179+ lcd_mgr->set_display(lcd_mgr, display);
12180+ def_mgr = lcd_mgr;
12181+ } else {
12182+ lcd_mgr->set_display(tv_mgr, display);
12183+ def_mgr = tv_mgr;
12184+ }
12185+
12186+ break;
12187+ }
12188+ }
12189+
12190+ if (!def_mgr)
12191+ DSSWARN("default display %s not found\n",
12192+ def_disp_name);
12193+ }
12194+
12195+ if (def_mgr != lcd_mgr) {
12196+ /* connect lcd manager to first non-VENC display found */
12197+ for (i = 0; i < omap_dss_get_num_displays(); i++) {
12198+ struct omap_display *display = dss_get_display(i);
12199+ if (display->type != OMAP_DISPLAY_TYPE_VENC) {
12200+ lcd_mgr->set_display(lcd_mgr, display);
12201+
12202+ if (!def_mgr)
12203+ def_mgr = lcd_mgr;
12204+
12205+ break;
12206+ }
12207+ }
12208+ }
12209+
12210+ if (def_mgr != tv_mgr) {
12211+ /* connect tv manager to first VENC display found */
12212+ for (i = 0; i < omap_dss_get_num_displays(); i++) {
12213+ struct omap_display *display = dss_get_display(i);
12214+ if (display->type == OMAP_DISPLAY_TYPE_VENC) {
12215+ tv_mgr->set_display(tv_mgr, display);
12216+
12217+ if (!def_mgr)
12218+ def_mgr = tv_mgr;
12219+
12220+ break;
12221+ }
12222+ }
12223+ }
12224+
12225+ /* connect all dispc overlays to def_mgr */
12226+ if (def_mgr) {
12227+ for (i = 0; i < 3; i++) {
12228+ struct omap_overlay *ovl;
12229+ ovl = omap_dss_get_overlay(i);
12230+ omap_dss_set_manager(ovl, def_mgr);
12231+ }
12232+ }
12233+
12234+#ifdef L4_EXAMPLE
12235+ /* setup L4 overlay as an example */
12236+ {
12237+ static struct omap_overlay ovl = {
12238+ .name = "l4-ovl",
12239+ .supported_modes = OMAP_DSS_COLOR_RGB24U,
12240+ .set_manager = &omap_dss_set_manager,
12241+ .unset_manager = &omap_dss_unset_manager,
12242+ .setup_input = &omap_dss_setup_overlay_input,
12243+ .setup_output = &omap_dss_setup_overlay_output,
12244+ .enable = &omap_dss_enable_overlay,
12245+ };
12246+
12247+ static struct omap_overlay_manager mgr = {
12248+ .name = "l4",
12249+ .num_overlays = 1,
12250+ .overlays = &ovl,
12251+ .set_display = &omap_dss_set_display,
12252+ .unset_display = &omap_dss_unset_display,
12253+ .apply = &ovl_mgr_apply_l4,
12254+ .supported_displays =
12255+ OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
12256+ };
12257+
12258+ omap_dss_add_overlay(&ovl);
12259+ omap_dss_add_overlay_manager(&mgr);
12260+ omap_dss_set_manager(&ovl, &mgr);
12261+ }
12262+#endif
12263+}
12264+
12265+void dss_uninit_overlays(struct platform_device *pdev)
12266+{
12267+ struct omap_overlay *ovl;
12268+
12269+ while (!list_empty(&overlay_list)) {
12270+ ovl = list_first_entry(&overlay_list,
12271+ struct omap_overlay, list);
12272+ list_del(&ovl->list);
12273+ kobject_del(&ovl->kobj);
12274+ kobject_put(&ovl->kobj);
12275+ kfree(ovl);
12276+ }
12277+
12278+ num_overlays = 0;
12279+}
12280+
12281diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
12282new file mode 100644
12283index 0000000..3e9ae1e
12284--- /dev/null
12285+++ b/drivers/video/omap2/dss/rfbi.c
12286@@ -0,0 +1,1304 @@
12287+/*
12288+ * linux/drivers/video/omap2/dss/rfbi.c
12289+ *
12290+ * Copyright (C) 2009 Nokia Corporation
12291+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
12292+ *
12293+ * Some code and ideas taken from drivers/video/omap/ driver
12294+ * by Imre Deak.
12295+ *
12296+ * This program is free software; you can redistribute it and/or modify it
12297+ * under the terms of the GNU General Public License version 2 as published by
12298+ * the Free Software Foundation.
12299+ *
12300+ * This program is distributed in the hope that it will be useful, but WITHOUT
12301+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12302+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12303+ * more details.
12304+ *
12305+ * You should have received a copy of the GNU General Public License along with
12306+ * this program. If not, see <http://www.gnu.org/licenses/>.
12307+ */
12308+
12309+#define DSS_SUBSYS_NAME "RFBI"
12310+
12311+#include <linux/kernel.h>
12312+#include <linux/dma-mapping.h>
12313+#include <linux/vmalloc.h>
12314+#include <linux/clk.h>
12315+#include <linux/io.h>
12316+#include <linux/delay.h>
12317+#include <linux/kfifo.h>
12318+#include <linux/ktime.h>
12319+#include <linux/hrtimer.h>
12320+#include <linux/seq_file.h>
12321+
12322+#include <mach/board.h>
12323+#include <mach/display.h>
12324+#include "dss.h"
12325+
12326+/*#define MEASURE_PERF*/
12327+
12328+#define RFBI_BASE 0x48050800
12329+
12330+struct rfbi_reg { u16 idx; };
12331+
12332+#define RFBI_REG(idx) ((const struct rfbi_reg) { idx })
12333+
12334+#define RFBI_REVISION RFBI_REG(0x0000)
12335+#define RFBI_SYSCONFIG RFBI_REG(0x0010)
12336+#define RFBI_SYSSTATUS RFBI_REG(0x0014)
12337+#define RFBI_CONTROL RFBI_REG(0x0040)
12338+#define RFBI_PIXEL_CNT RFBI_REG(0x0044)
12339+#define RFBI_LINE_NUMBER RFBI_REG(0x0048)
12340+#define RFBI_CMD RFBI_REG(0x004c)
12341+#define RFBI_PARAM RFBI_REG(0x0050)
12342+#define RFBI_DATA RFBI_REG(0x0054)
12343+#define RFBI_READ RFBI_REG(0x0058)
12344+#define RFBI_STATUS RFBI_REG(0x005c)
12345+
12346+#define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18)
12347+#define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18)
12348+#define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18)
12349+#define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18)
12350+#define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18)
12351+#define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18)
12352+
12353+#define RFBI_VSYNC_WIDTH RFBI_REG(0x0090)
12354+#define RFBI_HSYNC_WIDTH RFBI_REG(0x0094)
12355+
12356+#define RFBI_CMD_FIFO_LEN_BYTES (16 * sizeof(struct update_param))
12357+
12358+#define REG_FLD_MOD(idx, val, start, end) \
12359+ rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
12360+
12361+/* To work around an RFBI transfer rate limitation */
12362+#define OMAP_RFBI_RATE_LIMIT 1
12363+
12364+enum omap_rfbi_cycleformat {
12365+ OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
12366+ OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
12367+ OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
12368+ OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
12369+};
12370+
12371+enum omap_rfbi_datatype {
12372+ OMAP_DSS_RFBI_DATATYPE_12 = 0,
12373+ OMAP_DSS_RFBI_DATATYPE_16 = 1,
12374+ OMAP_DSS_RFBI_DATATYPE_18 = 2,
12375+ OMAP_DSS_RFBI_DATATYPE_24 = 3,
12376+};
12377+
12378+enum omap_rfbi_parallelmode {
12379+ OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
12380+ OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
12381+ OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
12382+ OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
12383+};
12384+
12385+enum update_cmd {
12386+ RFBI_CMD_UPDATE = 0,
12387+ RFBI_CMD_SYNC = 1,
12388+};
12389+
12390+static int rfbi_convert_timings(struct rfbi_timings *t);
12391+static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
12392+static void process_cmd_fifo(void);
12393+
12394+static struct {
12395+ void __iomem *base;
12396+
12397+ unsigned long l4_khz;
12398+
12399+ enum omap_rfbi_datatype datatype;
12400+ enum omap_rfbi_parallelmode parallelmode;
12401+
12402+ enum omap_rfbi_te_mode te_mode;
12403+ int te_enabled;
12404+
12405+ void (*framedone_callback)(void *data);
12406+ void *framedone_callback_data;
12407+
12408+ struct omap_display *display[2];
12409+
12410+ struct kfifo *cmd_fifo;
12411+ spinlock_t cmd_lock;
12412+ struct completion cmd_done;
12413+ atomic_t cmd_fifo_full;
12414+ atomic_t cmd_pending;
12415+#ifdef MEASURE_PERF
12416+ unsigned perf_bytes;
12417+ ktime_t perf_setup_time;
12418+ ktime_t perf_start_time;
12419+#endif
12420+} rfbi;
12421+
12422+struct update_region {
12423+ u16 x;
12424+ u16 y;
12425+ u16 w;
12426+ u16 h;
12427+};
12428+
12429+struct update_param {
12430+ u8 rfbi_module;
12431+ u8 cmd;
12432+
12433+ union {
12434+ struct update_region r;
12435+ struct completion *sync;
12436+ } par;
12437+};
12438+
12439+static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
12440+{
12441+ __raw_writel(val, rfbi.base + idx.idx);
12442+}
12443+
12444+static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
12445+{
12446+ return __raw_readl(rfbi.base + idx.idx);
12447+}
12448+
12449+static void rfbi_enable_clocks(bool enable)
12450+{
12451+ if (enable)
12452+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
12453+ else
12454+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
12455+}
12456+
12457+void omap_rfbi_write_command(const void *buf, u32 len)
12458+{
12459+ rfbi_enable_clocks(1);
12460+ switch (rfbi.parallelmode) {
12461+ case OMAP_DSS_RFBI_PARALLELMODE_8:
12462+ {
12463+ const u8 *b = buf;
12464+ for (; len; len--)
12465+ rfbi_write_reg(RFBI_CMD, *b++);
12466+ break;
12467+ }
12468+
12469+ case OMAP_DSS_RFBI_PARALLELMODE_16:
12470+ {
12471+ const u16 *w = buf;
12472+ BUG_ON(len & 1);
12473+ for (; len; len -= 2)
12474+ rfbi_write_reg(RFBI_CMD, *w++);
12475+ break;
12476+ }
12477+
12478+ case OMAP_DSS_RFBI_PARALLELMODE_9:
12479+ case OMAP_DSS_RFBI_PARALLELMODE_12:
12480+ default:
12481+ BUG();
12482+ }
12483+ rfbi_enable_clocks(0);
12484+}
12485+EXPORT_SYMBOL(omap_rfbi_write_command);
12486+
12487+void omap_rfbi_read_data(void *buf, u32 len)
12488+{
12489+ rfbi_enable_clocks(1);
12490+ switch (rfbi.parallelmode) {
12491+ case OMAP_DSS_RFBI_PARALLELMODE_8:
12492+ {
12493+ u8 *b = buf;
12494+ for (; len; len--) {
12495+ rfbi_write_reg(RFBI_READ, 0);
12496+ *b++ = rfbi_read_reg(RFBI_READ);
12497+ }
12498+ break;
12499+ }
12500+
12501+ case OMAP_DSS_RFBI_PARALLELMODE_16:
12502+ {
12503+ u16 *w = buf;
12504+ BUG_ON(len & ~1);
12505+ for (; len; len -= 2) {
12506+ rfbi_write_reg(RFBI_READ, 0);
12507+ *w++ = rfbi_read_reg(RFBI_READ);
12508+ }
12509+ break;
12510+ }
12511+
12512+ case OMAP_DSS_RFBI_PARALLELMODE_9:
12513+ case OMAP_DSS_RFBI_PARALLELMODE_12:
12514+ default:
12515+ BUG();
12516+ }
12517+ rfbi_enable_clocks(0);
12518+}
12519+EXPORT_SYMBOL(omap_rfbi_read_data);
12520+
12521+void omap_rfbi_write_data(const void *buf, u32 len)
12522+{
12523+ rfbi_enable_clocks(1);
12524+ switch (rfbi.parallelmode) {
12525+ case OMAP_DSS_RFBI_PARALLELMODE_8:
12526+ {
12527+ const u8 *b = buf;
12528+ for (; len; len--)
12529+ rfbi_write_reg(RFBI_PARAM, *b++);
12530+ break;
12531+ }
12532+
12533+ case OMAP_DSS_RFBI_PARALLELMODE_16:
12534+ {
12535+ const u16 *w = buf;
12536+ BUG_ON(len & 1);
12537+ for (; len; len -= 2)
12538+ rfbi_write_reg(RFBI_PARAM, *w++);
12539+ break;
12540+ }
12541+
12542+ case OMAP_DSS_RFBI_PARALLELMODE_9:
12543+ case OMAP_DSS_RFBI_PARALLELMODE_12:
12544+ default:
12545+ BUG();
12546+
12547+ }
12548+ rfbi_enable_clocks(0);
12549+}
12550+EXPORT_SYMBOL(omap_rfbi_write_data);
12551+
12552+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
12553+ u16 x, u16 y,
12554+ u16 w, u16 h)
12555+{
12556+ int start_offset = scr_width * y + x;
12557+ int horiz_offset = scr_width - w;
12558+ int i;
12559+
12560+ rfbi_enable_clocks(1);
12561+
12562+ if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
12563+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
12564+ const u16 __iomem *pd = buf;
12565+ pd += start_offset;
12566+
12567+ for (; h; --h) {
12568+ for (i = 0; i < w; ++i) {
12569+ const u8 __iomem *b = (const u8 __iomem *)pd;
12570+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
12571+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
12572+ ++pd;
12573+ }
12574+ pd += horiz_offset;
12575+ }
12576+ } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
12577+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
12578+ const u32 __iomem *pd = buf;
12579+ pd += start_offset;
12580+
12581+ for (; h; --h) {
12582+ for (i = 0; i < w; ++i) {
12583+ const u8 __iomem *b = (const u8 __iomem *)pd;
12584+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2));
12585+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
12586+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
12587+ ++pd;
12588+ }
12589+ pd += horiz_offset;
12590+ }
12591+ } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
12592+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
12593+ const u16 __iomem *pd = buf;
12594+ pd += start_offset;
12595+
12596+ for (; h; --h) {
12597+ for (i = 0; i < w; ++i) {
12598+ rfbi_write_reg(RFBI_PARAM, __raw_readw(pd));
12599+ ++pd;
12600+ }
12601+ pd += horiz_offset;
12602+ }
12603+ } else {
12604+ BUG();
12605+ }
12606+
12607+ rfbi_enable_clocks(0);
12608+}
12609+EXPORT_SYMBOL(omap_rfbi_write_pixels);
12610+
12611+#ifdef MEASURE_PERF
12612+static void perf_mark_setup(void)
12613+{
12614+ rfbi.perf_setup_time = ktime_get();
12615+}
12616+
12617+static void perf_mark_start(void)
12618+{
12619+ rfbi.perf_start_time = ktime_get();
12620+}
12621+
12622+static void perf_show(const char *name)
12623+{
12624+ ktime_t t, setup_time, trans_time;
12625+ u32 total_bytes;
12626+ u32 setup_us, trans_us, total_us;
12627+
12628+ t = ktime_get();
12629+
12630+ setup_time = ktime_sub(rfbi.perf_start_time, rfbi.perf_setup_time);
12631+ setup_us = (u32)ktime_to_us(setup_time);
12632+ if (setup_us == 0)
12633+ setup_us = 1;
12634+
12635+ trans_time = ktime_sub(t, rfbi.perf_start_time);
12636+ trans_us = (u32)ktime_to_us(trans_time);
12637+ if (trans_us == 0)
12638+ trans_us = 1;
12639+
12640+ total_us = setup_us + trans_us;
12641+
12642+ total_bytes = rfbi.perf_bytes;
12643+
12644+ DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, "
12645+ "%u kbytes/sec\n",
12646+ name,
12647+ setup_us,
12648+ trans_us,
12649+ total_us,
12650+ 1000*1000 / total_us,
12651+ total_bytes,
12652+ total_bytes * 1000 / total_us);
12653+}
12654+#else
12655+#define perf_mark_setup()
12656+#define perf_mark_start()
12657+#define perf_show(x)
12658+#endif
12659+
12660+void rfbi_transfer_area(u16 width, u16 height,
12661+ void (callback)(void *data), void *data)
12662+{
12663+ u32 l;
12664+
12665+ /*BUG_ON(callback == 0);*/
12666+ BUG_ON(rfbi.framedone_callback != NULL);
12667+
12668+ DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
12669+
12670+ dispc_set_lcd_size(width, height);
12671+
12672+ dispc_enable_lcd_out(1);
12673+
12674+ rfbi.framedone_callback = callback;
12675+ rfbi.framedone_callback_data = data;
12676+
12677+ rfbi_enable_clocks(1);
12678+
12679+ rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
12680+
12681+ l = rfbi_read_reg(RFBI_CONTROL);
12682+ l = FLD_MOD(l, 1, 0, 0); /* enable */
12683+ if (!rfbi.te_enabled)
12684+ l = FLD_MOD(l, 1, 4, 4); /* ITE */
12685+
12686+ perf_mark_start();
12687+
12688+ rfbi_write_reg(RFBI_CONTROL, l);
12689+}
12690+
12691+static void framedone_callback(void *data, u32 mask)
12692+{
12693+ void (*callback)(void *data);
12694+
12695+ DSSDBG("FRAMEDONE\n");
12696+
12697+ perf_show("DISPC");
12698+
12699+ REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
12700+
12701+ rfbi_enable_clocks(0);
12702+
12703+ callback = rfbi.framedone_callback;
12704+ rfbi.framedone_callback = NULL;
12705+
12706+ /*callback(rfbi.framedone_callback_data);*/
12707+
12708+ atomic_set(&rfbi.cmd_pending, 0);
12709+
12710+ process_cmd_fifo();
12711+}
12712+
12713+#if 1 /* VERBOSE */
12714+static void rfbi_print_timings(void)
12715+{
12716+ u32 l;
12717+ u32 time;
12718+
12719+ l = rfbi_read_reg(RFBI_CONFIG(0));
12720+ time = 1000000000 / rfbi.l4_khz;
12721+ if (l & (1 << 4))
12722+ time *= 2;
12723+
12724+ DSSDBG("Tick time %u ps\n", time);
12725+ l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
12726+ DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
12727+ "REONTIME %d, REOFFTIME %d\n",
12728+ l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
12729+ (l >> 20) & 0x0f, (l >> 24) & 0x3f);
12730+
12731+ l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
12732+ DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
12733+ "ACCESSTIME %d\n",
12734+ (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
12735+ (l >> 22) & 0x3f);
12736+}
12737+#else
12738+static void rfbi_print_timings(void) {}
12739+#endif
12740+
12741+
12742+
12743+
12744+static u32 extif_clk_period;
12745+
12746+static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
12747+{
12748+ int bus_tick = extif_clk_period * div;
12749+ return (ps + bus_tick - 1) / bus_tick * bus_tick;
12750+}
12751+
12752+static int calc_reg_timing(struct rfbi_timings *t, int div)
12753+{
12754+ t->clk_div = div;
12755+
12756+ t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
12757+
12758+ t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
12759+ t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
12760+ t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
12761+
12762+ t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
12763+ t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
12764+ t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
12765+
12766+ t->access_time = round_to_extif_ticks(t->access_time, div);
12767+ t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
12768+ t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
12769+
12770+ DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
12771+ t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
12772+ DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
12773+ t->we_on_time, t->we_off_time, t->re_cycle_time,
12774+ t->we_cycle_time);
12775+ DSSDBG("[reg]rdaccess %d cspulse %d\n",
12776+ t->access_time, t->cs_pulse_width);
12777+
12778+ return rfbi_convert_timings(t);
12779+}
12780+
12781+static int calc_extif_timings(struct rfbi_timings *t)
12782+{
12783+ u32 max_clk_div;
12784+ int div;
12785+
12786+ rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
12787+ for (div = 1; div <= max_clk_div; div++) {
12788+ if (calc_reg_timing(t, div) == 0)
12789+ break;
12790+ }
12791+
12792+ if (div <= max_clk_div)
12793+ return 0;
12794+
12795+ DSSERR("can't setup timings\n");
12796+ return -1;
12797+}
12798+
12799+
12800+void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
12801+{
12802+ int r;
12803+
12804+ if (!t->converted) {
12805+ r = calc_extif_timings(t);
12806+ if (r < 0)
12807+ DSSERR("Failed to calc timings\n");
12808+ }
12809+
12810+ BUG_ON(!t->converted);
12811+
12812+ rfbi_enable_clocks(1);
12813+ rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
12814+ rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
12815+
12816+ /* TIMEGRANULARITY */
12817+ REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
12818+ (t->tim[2] ? 1 : 0), 4, 4);
12819+
12820+ rfbi_print_timings();
12821+ rfbi_enable_clocks(0);
12822+}
12823+
12824+static int ps_to_rfbi_ticks(int time, int div)
12825+{
12826+ unsigned long tick_ps;
12827+ int ret;
12828+
12829+ /* Calculate in picosecs to yield more exact results */
12830+ tick_ps = 1000000000 / (rfbi.l4_khz) * div;
12831+
12832+ ret = (time + tick_ps - 1) / tick_ps;
12833+
12834+ return ret;
12835+}
12836+
12837+#ifdef OMAP_RFBI_RATE_LIMIT
12838+unsigned long rfbi_get_max_tx_rate(void)
12839+{
12840+ unsigned long l4_rate, dss1_rate;
12841+ int min_l4_ticks = 0;
12842+ int i;
12843+
12844+ /* According to TI this can't be calculated so make the
12845+ * adjustments for a couple of known frequencies and warn for
12846+ * others.
12847+ */
12848+ static const struct {
12849+ unsigned long l4_clk; /* HZ */
12850+ unsigned long dss1_clk; /* HZ */
12851+ unsigned long min_l4_ticks;
12852+ } ftab[] = {
12853+ { 55, 132, 7, }, /* 7.86 MPix/s */
12854+ { 110, 110, 12, }, /* 9.16 MPix/s */
12855+ { 110, 132, 10, }, /* 11 Mpix/s */
12856+ { 120, 120, 10, }, /* 12 Mpix/s */
12857+ { 133, 133, 10, }, /* 13.3 Mpix/s */
12858+ };
12859+
12860+ l4_rate = rfbi.l4_khz / 1000;
12861+ dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000;
12862+
12863+ for (i = 0; i < ARRAY_SIZE(ftab); i++) {
12864+ /* Use a window instead of an exact match, to account
12865+ * for different DPLL multiplier / divider pairs.
12866+ */
12867+ if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
12868+ abs(ftab[i].dss1_clk - dss1_rate) < 3) {
12869+ min_l4_ticks = ftab[i].min_l4_ticks;
12870+ break;
12871+ }
12872+ }
12873+ if (i == ARRAY_SIZE(ftab)) {
12874+ /* Can't be sure, return anyway the maximum not
12875+ * rate-limited. This might cause a problem only for the
12876+ * tearing synchronisation.
12877+ */
12878+ DSSERR("can't determine maximum RFBI transfer rate\n");
12879+ return rfbi.l4_khz * 1000;
12880+ }
12881+ return rfbi.l4_khz * 1000 / min_l4_ticks;
12882+}
12883+#else
12884+int rfbi_get_max_tx_rate(void)
12885+{
12886+ return rfbi.l4_khz * 1000;
12887+}
12888+#endif
12889+
12890+static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
12891+{
12892+ *clk_period = 1000000000 / rfbi.l4_khz;
12893+ *max_clk_div = 2;
12894+}
12895+
12896+static int rfbi_convert_timings(struct rfbi_timings *t)
12897+{
12898+ u32 l;
12899+ int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
12900+ int actim, recyc, wecyc;
12901+ int div = t->clk_div;
12902+
12903+ if (div <= 0 || div > 2)
12904+ return -1;
12905+
12906+ /* Make sure that after conversion it still holds that:
12907+ * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
12908+ * csoff > cson, csoff >= max(weoff, reoff), actim > reon
12909+ */
12910+ weon = ps_to_rfbi_ticks(t->we_on_time, div);
12911+ weoff = ps_to_rfbi_ticks(t->we_off_time, div);
12912+ if (weoff <= weon)
12913+ weoff = weon + 1;
12914+ if (weon > 0x0f)
12915+ return -1;
12916+ if (weoff > 0x3f)
12917+ return -1;
12918+
12919+ reon = ps_to_rfbi_ticks(t->re_on_time, div);
12920+ reoff = ps_to_rfbi_ticks(t->re_off_time, div);
12921+ if (reoff <= reon)
12922+ reoff = reon + 1;
12923+ if (reon > 0x0f)
12924+ return -1;
12925+ if (reoff > 0x3f)
12926+ return -1;
12927+
12928+ cson = ps_to_rfbi_ticks(t->cs_on_time, div);
12929+ csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
12930+ if (csoff <= cson)
12931+ csoff = cson + 1;
12932+ if (csoff < max(weoff, reoff))
12933+ csoff = max(weoff, reoff);
12934+ if (cson > 0x0f)
12935+ return -1;
12936+ if (csoff > 0x3f)
12937+ return -1;
12938+
12939+ l = cson;
12940+ l |= csoff << 4;
12941+ l |= weon << 10;
12942+ l |= weoff << 14;
12943+ l |= reon << 20;
12944+ l |= reoff << 24;
12945+
12946+ t->tim[0] = l;
12947+
12948+ actim = ps_to_rfbi_ticks(t->access_time, div);
12949+ if (actim <= reon)
12950+ actim = reon + 1;
12951+ if (actim > 0x3f)
12952+ return -1;
12953+
12954+ wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
12955+ if (wecyc < weoff)
12956+ wecyc = weoff;
12957+ if (wecyc > 0x3f)
12958+ return -1;
12959+
12960+ recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
12961+ if (recyc < reoff)
12962+ recyc = reoff;
12963+ if (recyc > 0x3f)
12964+ return -1;
12965+
12966+ cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
12967+ if (cs_pulse > 0x3f)
12968+ return -1;
12969+
12970+ l = wecyc;
12971+ l |= recyc << 6;
12972+ l |= cs_pulse << 12;
12973+ l |= actim << 22;
12974+
12975+ t->tim[1] = l;
12976+
12977+ t->tim[2] = div - 1;
12978+
12979+ t->converted = 1;
12980+
12981+ return 0;
12982+}
12983+
12984+/* xxx FIX module selection missing */
12985+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
12986+ unsigned hs_pulse_time, unsigned vs_pulse_time,
12987+ int hs_pol_inv, int vs_pol_inv, int extif_div)
12988+{
12989+ int hs, vs;
12990+ int min;
12991+ u32 l;
12992+
12993+ hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
12994+ vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
12995+ if (hs < 2)
12996+ return -EDOM;
12997+ if (mode == OMAP_DSS_RFBI_TE_MODE_2)
12998+ min = 2;
12999+ else /* OMAP_DSS_RFBI_TE_MODE_1 */
13000+ min = 4;
13001+ if (vs < min)
13002+ return -EDOM;
13003+ if (vs == hs)
13004+ return -EINVAL;
13005+ rfbi.te_mode = mode;
13006+ DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
13007+ mode, hs, vs, hs_pol_inv, vs_pol_inv);
13008+
13009+ rfbi_enable_clocks(1);
13010+ rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
13011+ rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
13012+
13013+ l = rfbi_read_reg(RFBI_CONFIG(0));
13014+ if (hs_pol_inv)
13015+ l &= ~(1 << 21);
13016+ else
13017+ l |= 1 << 21;
13018+ if (vs_pol_inv)
13019+ l &= ~(1 << 20);
13020+ else
13021+ l |= 1 << 20;
13022+ rfbi_enable_clocks(0);
13023+
13024+ return 0;
13025+}
13026+EXPORT_SYMBOL(omap_rfbi_setup_te);
13027+
13028+/* xxx FIX module selection missing */
13029+int omap_rfbi_enable_te(bool enable, unsigned line)
13030+{
13031+ u32 l;
13032+
13033+ DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
13034+ if (line > (1 << 11) - 1)
13035+ return -EINVAL;
13036+
13037+ rfbi_enable_clocks(1);
13038+ l = rfbi_read_reg(RFBI_CONFIG(0));
13039+ l &= ~(0x3 << 2);
13040+ if (enable) {
13041+ rfbi.te_enabled = 1;
13042+ l |= rfbi.te_mode << 2;
13043+ } else
13044+ rfbi.te_enabled = 0;
13045+ rfbi_write_reg(RFBI_CONFIG(0), l);
13046+ rfbi_write_reg(RFBI_LINE_NUMBER, line);
13047+ rfbi_enable_clocks(0);
13048+
13049+ return 0;
13050+}
13051+EXPORT_SYMBOL(omap_rfbi_enable_te);
13052+
13053+#if 0
13054+static void rfbi_enable_config(int enable1, int enable2)
13055+{
13056+ u32 l;
13057+ int cs = 0;
13058+
13059+ if (enable1)
13060+ cs |= 1<<0;
13061+ if (enable2)
13062+ cs |= 1<<1;
13063+
13064+ rfbi_enable_clocks(1);
13065+
13066+ l = rfbi_read_reg(RFBI_CONTROL);
13067+
13068+ l = FLD_MOD(l, cs, 3, 2);
13069+ l = FLD_MOD(l, 0, 1, 1);
13070+
13071+ rfbi_write_reg(RFBI_CONTROL, l);
13072+
13073+
13074+ l = rfbi_read_reg(RFBI_CONFIG(0));
13075+ l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
13076+ /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
13077+ /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
13078+
13079+ l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
13080+ l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
13081+ l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
13082+
13083+ l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
13084+ rfbi_write_reg(RFBI_CONFIG(0), l);
13085+
13086+ rfbi_enable_clocks(0);
13087+}
13088+#endif
13089+
13090+int rfbi_configure(int rfbi_module, int bpp, int lines)
13091+{
13092+ u32 l;
13093+ int cycle1 = 0, cycle2 = 0, cycle3 = 0;
13094+ enum omap_rfbi_cycleformat cycleformat;
13095+ enum omap_rfbi_datatype datatype;
13096+ enum omap_rfbi_parallelmode parallelmode;
13097+
13098+ switch (bpp) {
13099+ case 12:
13100+ datatype = OMAP_DSS_RFBI_DATATYPE_12;
13101+ break;
13102+ case 16:
13103+ datatype = OMAP_DSS_RFBI_DATATYPE_16;
13104+ break;
13105+ case 18:
13106+ datatype = OMAP_DSS_RFBI_DATATYPE_18;
13107+ break;
13108+ case 24:
13109+ datatype = OMAP_DSS_RFBI_DATATYPE_24;
13110+ break;
13111+ default:
13112+ BUG();
13113+ return 1;
13114+ }
13115+ rfbi.datatype = datatype;
13116+
13117+ switch (lines) {
13118+ case 8:
13119+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
13120+ break;
13121+ case 9:
13122+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
13123+ break;
13124+ case 12:
13125+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
13126+ break;
13127+ case 16:
13128+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
13129+ break;
13130+ default:
13131+ BUG();
13132+ return 1;
13133+ }
13134+ rfbi.parallelmode = parallelmode;
13135+
13136+ if ((bpp % lines) == 0) {
13137+ switch (bpp / lines) {
13138+ case 1:
13139+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
13140+ break;
13141+ case 2:
13142+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
13143+ break;
13144+ case 3:
13145+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
13146+ break;
13147+ default:
13148+ BUG();
13149+ return 1;
13150+ }
13151+ } else if ((2 * bpp % lines) == 0) {
13152+ if ((2 * bpp / lines) == 3)
13153+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
13154+ else {
13155+ BUG();
13156+ return 1;
13157+ }
13158+ } else {
13159+ BUG();
13160+ return 1;
13161+ }
13162+
13163+ switch (cycleformat) {
13164+ case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
13165+ cycle1 = lines;
13166+ break;
13167+
13168+ case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
13169+ cycle1 = lines;
13170+ cycle2 = lines;
13171+ break;
13172+
13173+ case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
13174+ cycle1 = lines;
13175+ cycle2 = lines;
13176+ cycle3 = lines;
13177+ break;
13178+
13179+ case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
13180+ cycle1 = lines;
13181+ cycle2 = (lines / 2) | ((lines / 2) << 16);
13182+ cycle3 = (lines << 16);
13183+ break;
13184+ }
13185+
13186+ rfbi_enable_clocks(1);
13187+
13188+ REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
13189+
13190+ l = 0;
13191+ l |= FLD_VAL(parallelmode, 1, 0);
13192+ l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */
13193+ l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */
13194+ l |= FLD_VAL(datatype, 6, 5);
13195+ /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
13196+ l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */
13197+ l |= FLD_VAL(cycleformat, 10, 9);
13198+ l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */
13199+ l |= FLD_VAL(0, 16, 16); /* A0POLARITY */
13200+ l |= FLD_VAL(0, 17, 17); /* REPOLARITY */
13201+ l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */
13202+ l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */
13203+ l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */
13204+ l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */
13205+ rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
13206+
13207+ rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
13208+ rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
13209+ rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
13210+
13211+
13212+ l = rfbi_read_reg(RFBI_CONTROL);
13213+ l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
13214+ l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
13215+ rfbi_write_reg(RFBI_CONTROL, l);
13216+
13217+
13218+ DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
13219+ bpp, lines, cycle1, cycle2, cycle3);
13220+
13221+ rfbi_enable_clocks(0);
13222+
13223+ return 0;
13224+}
13225+EXPORT_SYMBOL(rfbi_configure);
13226+
13227+static int rfbi_find_display(struct omap_display *disp)
13228+{
13229+ if (disp == rfbi.display[0])
13230+ return 0;
13231+
13232+ if (disp == rfbi.display[1])
13233+ return 1;
13234+
13235+ BUG();
13236+ return -1;
13237+}
13238+
13239+
13240+static void signal_fifo_waiters(void)
13241+{
13242+ if (atomic_read(&rfbi.cmd_fifo_full) > 0) {
13243+ /* DSSDBG("SIGNALING: Fifo not full for waiter!\n"); */
13244+ complete(&rfbi.cmd_done);
13245+ atomic_dec(&rfbi.cmd_fifo_full);
13246+ }
13247+}
13248+
13249+/* returns 1 for async op, and 0 for sync op */
13250+static int do_update(struct omap_display *display, struct update_region *upd)
13251+{
13252+ u16 x = upd->x;
13253+ u16 y = upd->y;
13254+ u16 w = upd->w;
13255+ u16 h = upd->h;
13256+
13257+ perf_mark_setup();
13258+
13259+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
13260+ /*display->ctrl->enable_te(display, 1); */
13261+ dispc_setup_partial_planes(display, &x, &y, &w, &h);
13262+ }
13263+
13264+#ifdef MEASURE_PERF
13265+ rfbi.perf_bytes = w * h * 2; /* XXX always 16bit */
13266+#endif
13267+
13268+ display->ctrl->setup_update(display, x, y, w, h);
13269+
13270+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
13271+ rfbi_transfer_area(w, h, NULL, NULL);
13272+ return 1;
13273+ } else {
13274+ struct omap_overlay *ovl;
13275+ void __iomem *addr;
13276+ int scr_width;
13277+
13278+ ovl = display->manager->overlays[0];
13279+ scr_width = ovl->info.screen_width;
13280+ addr = ovl->info.vaddr;
13281+
13282+ omap_rfbi_write_pixels(addr, scr_width, x, y, w, h);
13283+
13284+ perf_show("L4");
13285+
13286+ return 0;
13287+ }
13288+}
13289+
13290+static void process_cmd_fifo(void)
13291+{
13292+ int len;
13293+ struct update_param p;
13294+ struct omap_display *display;
13295+ unsigned long flags;
13296+
13297+ if (atomic_inc_return(&rfbi.cmd_pending) != 1)
13298+ return;
13299+
13300+ while (true) {
13301+ spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
13302+
13303+ len = __kfifo_get(rfbi.cmd_fifo, (unsigned char *)&p,
13304+ sizeof(struct update_param));
13305+ if (len == 0) {
13306+ DSSDBG("nothing more in fifo\n");
13307+ atomic_set(&rfbi.cmd_pending, 0);
13308+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
13309+ break;
13310+ }
13311+
13312+ /* DSSDBG("fifo full %d\n", rfbi.cmd_fifo_full.counter);*/
13313+
13314+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
13315+
13316+ BUG_ON(len != sizeof(struct update_param));
13317+ BUG_ON(p.rfbi_module > 1);
13318+
13319+ display = rfbi.display[p.rfbi_module];
13320+
13321+ if (p.cmd == RFBI_CMD_UPDATE) {
13322+ if (do_update(display, &p.par.r))
13323+ break; /* async op */
13324+ } else if (p.cmd == RFBI_CMD_SYNC) {
13325+ DSSDBG("Signaling SYNC done!\n");
13326+ complete(p.par.sync);
13327+ } else
13328+ BUG();
13329+ }
13330+
13331+ signal_fifo_waiters();
13332+}
13333+
13334+static void rfbi_push_cmd(struct update_param *p)
13335+{
13336+ int ret;
13337+
13338+ while (1) {
13339+ unsigned long flags;
13340+ int available;
13341+
13342+ spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
13343+ available = RFBI_CMD_FIFO_LEN_BYTES -
13344+ __kfifo_len(rfbi.cmd_fifo);
13345+
13346+/* DSSDBG("%d bytes left in fifo\n", available); */
13347+ if (available < sizeof(struct update_param)) {
13348+ DSSDBG("Going to wait because FIFO FULL..\n");
13349+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
13350+ atomic_inc(&rfbi.cmd_fifo_full);
13351+ wait_for_completion(&rfbi.cmd_done);
13352+ /*DSSDBG("Woke up because fifo not full anymore\n");*/
13353+ continue;
13354+ }
13355+
13356+ ret = __kfifo_put(rfbi.cmd_fifo, (unsigned char *)p,
13357+ sizeof(struct update_param));
13358+/* DSSDBG("pushed %d bytes\n", ret);*/
13359+
13360+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
13361+
13362+ BUG_ON(ret != sizeof(struct update_param));
13363+
13364+ break;
13365+ }
13366+}
13367+
13368+static void rfbi_push_update(int rfbi_module, int x, int y, int w, int h)
13369+{
13370+ struct update_param p;
13371+
13372+ p.rfbi_module = rfbi_module;
13373+ p.cmd = RFBI_CMD_UPDATE;
13374+
13375+ p.par.r.x = x;
13376+ p.par.r.y = y;
13377+ p.par.r.w = w;
13378+ p.par.r.h = h;
13379+
13380+ DSSDBG("RFBI pushed %d,%d %dx%d\n", x, y, w, h);
13381+
13382+ rfbi_push_cmd(&p);
13383+
13384+ process_cmd_fifo();
13385+}
13386+
13387+static void rfbi_push_sync(int rfbi_module, struct completion *sync_comp)
13388+{
13389+ struct update_param p;
13390+
13391+ p.rfbi_module = rfbi_module;
13392+ p.cmd = RFBI_CMD_SYNC;
13393+ p.par.sync = sync_comp;
13394+
13395+ rfbi_push_cmd(&p);
13396+
13397+ DSSDBG("RFBI sync pushed to cmd fifo\n");
13398+
13399+ process_cmd_fifo();
13400+}
13401+
13402+void rfbi_dump_regs(struct seq_file *s)
13403+{
13404+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
13405+
13406+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
13407+
13408+ DUMPREG(RFBI_REVISION);
13409+ DUMPREG(RFBI_SYSCONFIG);
13410+ DUMPREG(RFBI_SYSSTATUS);
13411+ DUMPREG(RFBI_CONTROL);
13412+ DUMPREG(RFBI_PIXEL_CNT);
13413+ DUMPREG(RFBI_LINE_NUMBER);
13414+ DUMPREG(RFBI_CMD);
13415+ DUMPREG(RFBI_PARAM);
13416+ DUMPREG(RFBI_DATA);
13417+ DUMPREG(RFBI_READ);
13418+ DUMPREG(RFBI_STATUS);
13419+
13420+ DUMPREG(RFBI_CONFIG(0));
13421+ DUMPREG(RFBI_ONOFF_TIME(0));
13422+ DUMPREG(RFBI_CYCLE_TIME(0));
13423+ DUMPREG(RFBI_DATA_CYCLE1(0));
13424+ DUMPREG(RFBI_DATA_CYCLE2(0));
13425+ DUMPREG(RFBI_DATA_CYCLE3(0));
13426+
13427+ DUMPREG(RFBI_CONFIG(1));
13428+ DUMPREG(RFBI_ONOFF_TIME(1));
13429+ DUMPREG(RFBI_CYCLE_TIME(1));
13430+ DUMPREG(RFBI_DATA_CYCLE1(1));
13431+ DUMPREG(RFBI_DATA_CYCLE2(1));
13432+ DUMPREG(RFBI_DATA_CYCLE3(1));
13433+
13434+ DUMPREG(RFBI_VSYNC_WIDTH);
13435+ DUMPREG(RFBI_HSYNC_WIDTH);
13436+
13437+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
13438+#undef DUMPREG
13439+}
13440+
13441+int rfbi_init(void)
13442+{
13443+ u32 rev;
13444+ u32 l;
13445+
13446+ spin_lock_init(&rfbi.cmd_lock);
13447+ rfbi.cmd_fifo = kfifo_alloc(RFBI_CMD_FIFO_LEN_BYTES, GFP_KERNEL,
13448+ &rfbi.cmd_lock);
13449+ if (IS_ERR(rfbi.cmd_fifo))
13450+ return -ENOMEM;
13451+
13452+ init_completion(&rfbi.cmd_done);
13453+ atomic_set(&rfbi.cmd_fifo_full, 0);
13454+ atomic_set(&rfbi.cmd_pending, 0);
13455+
13456+ rfbi.base = ioremap(RFBI_BASE, SZ_256);
13457+ if (!rfbi.base) {
13458+ DSSERR("can't ioremap RFBI\n");
13459+ return -ENOMEM;
13460+ }
13461+
13462+ rfbi_enable_clocks(1);
13463+
13464+ msleep(10);
13465+
13466+ rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000;
13467+
13468+ /* Enable autoidle and smart-idle */
13469+ l = rfbi_read_reg(RFBI_SYSCONFIG);
13470+ l |= (1 << 0) | (2 << 3);
13471+ rfbi_write_reg(RFBI_SYSCONFIG, l);
13472+
13473+ rev = rfbi_read_reg(RFBI_REVISION);
13474+ printk(KERN_INFO "OMAP RFBI rev %d.%d\n",
13475+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
13476+
13477+ rfbi_enable_clocks(0);
13478+
13479+ return 0;
13480+}
13481+
13482+void rfbi_exit(void)
13483+{
13484+ DSSDBG("rfbi_exit\n");
13485+
13486+ kfifo_free(rfbi.cmd_fifo);
13487+
13488+ iounmap(rfbi.base);
13489+}
13490+
13491+/* struct omap_display support */
13492+static int rfbi_display_update(struct omap_display *display,
13493+ u16 x, u16 y, u16 w, u16 h)
13494+{
13495+ int rfbi_module;
13496+
13497+ if (w == 0 || h == 0)
13498+ return 0;
13499+
13500+ rfbi_module = rfbi_find_display(display);
13501+
13502+ rfbi_push_update(rfbi_module, x, y, w, h);
13503+
13504+ return 0;
13505+}
13506+
13507+static int rfbi_display_sync(struct omap_display *display)
13508+{
13509+ struct completion sync_comp;
13510+ int rfbi_module;
13511+
13512+ rfbi_module = rfbi_find_display(display);
13513+
13514+ init_completion(&sync_comp);
13515+ rfbi_push_sync(rfbi_module, &sync_comp);
13516+ DSSDBG("Waiting for SYNC to happen...\n");
13517+ wait_for_completion(&sync_comp);
13518+ DSSDBG("Released from SYNC\n");
13519+ return 0;
13520+}
13521+
13522+static int rfbi_display_enable_te(struct omap_display *display, bool enable)
13523+{
13524+ display->ctrl->enable_te(display, enable);
13525+ return 0;
13526+}
13527+
13528+static int rfbi_display_enable(struct omap_display *display)
13529+{
13530+ int r;
13531+
13532+ BUG_ON(display->panel == NULL || display->ctrl == NULL);
13533+
13534+ r = omap_dispc_register_isr(framedone_callback, NULL,
13535+ DISPC_IRQ_FRAMEDONE);
13536+ if (r) {
13537+ DSSERR("can't get FRAMEDONE irq\n");
13538+ return r;
13539+ }
13540+
13541+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
13542+
13543+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI);
13544+
13545+ dispc_set_tft_data_lines(display->ctrl->pixel_size);
13546+
13547+ rfbi_configure(display->hw_config.u.rfbi.channel,
13548+ display->ctrl->pixel_size,
13549+ display->hw_config.u.rfbi.data_lines);
13550+
13551+ rfbi_set_timings(display->hw_config.u.rfbi.channel,
13552+ &display->ctrl->timings);
13553+
13554+
13555+ if (display->ctrl && display->ctrl->enable) {
13556+ r = display->ctrl->enable(display);
13557+ if (r)
13558+ goto err;
13559+ }
13560+
13561+ if (display->panel && display->panel->enable) {
13562+ r = display->panel->enable(display);
13563+ if (r)
13564+ goto err;
13565+ }
13566+
13567+ return 0;
13568+err:
13569+ return -ENODEV;
13570+}
13571+
13572+static void rfbi_display_disable(struct omap_display *display)
13573+{
13574+ display->ctrl->disable(display);
13575+ omap_dispc_unregister_isr(framedone_callback, NULL,
13576+ DISPC_IRQ_FRAMEDONE);
13577+}
13578+
13579+void rfbi_init_display(struct omap_display *display)
13580+{
13581+ display->enable = rfbi_display_enable;
13582+ display->disable = rfbi_display_disable;
13583+ display->update = rfbi_display_update;
13584+ display->sync = rfbi_display_sync;
13585+ display->enable_te = rfbi_display_enable_te;
13586+
13587+ rfbi.display[display->hw_config.u.rfbi.channel] = display;
13588+
13589+ display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
13590+}
13591diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
13592new file mode 100644
13593index 0000000..fbff2b2
13594--- /dev/null
13595+++ b/drivers/video/omap2/dss/sdi.c
13596@@ -0,0 +1,245 @@
13597+/*
13598+ * linux/drivers/video/omap2/dss/sdi.c
13599+ *
13600+ * Copyright (C) 2009 Nokia Corporation
13601+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
13602+ *
13603+ * This program is free software; you can redistribute it and/or modify it
13604+ * under the terms of the GNU General Public License version 2 as published by
13605+ * the Free Software Foundation.
13606+ *
13607+ * This program is distributed in the hope that it will be useful, but WITHOUT
13608+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13609+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13610+ * more details.
13611+ *
13612+ * You should have received a copy of the GNU General Public License along with
13613+ * this program. If not, see <http://www.gnu.org/licenses/>.
13614+ */
13615+
13616+#define DSS_SUBSYS_NAME "SDI"
13617+
13618+#include <linux/kernel.h>
13619+#include <linux/clk.h>
13620+#include <linux/delay.h>
13621+#include <linux/err.h>
13622+
13623+#include <mach/board.h>
13624+#include <mach/display.h>
13625+#include "dss.h"
13626+
13627+
13628+static struct {
13629+ bool skip_init;
13630+ bool update_enabled;
13631+} sdi;
13632+
13633+static void sdi_basic_init(void)
13634+{
13635+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
13636+
13637+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
13638+ dispc_set_tft_data_lines(24);
13639+ dispc_lcd_enable_signal_polarity(1);
13640+}
13641+
13642+static int sdi_display_enable(struct omap_display *display)
13643+{
13644+ struct dispc_clock_info cinfo;
13645+ u16 lck_div, pck_div;
13646+ unsigned long fck;
13647+ struct omap_panel *panel = display->panel;
13648+ unsigned long pck;
13649+ int r;
13650+
13651+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
13652+ DSSERR("display already enabled\n");
13653+ return -EINVAL;
13654+ }
13655+
13656+ /* In case of skip_init sdi_init has already enabled the clocks */
13657+ if (!sdi.skip_init)
13658+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
13659+
13660+ sdi_basic_init();
13661+
13662+ /* 15.5.9.1.2 */
13663+ panel->config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
13664+
13665+ dispc_set_pol_freq(panel);
13666+
13667+ if (!sdi.skip_init)
13668+ r = dispc_calc_clock_div(1, panel->timings.pixel_clock * 1000,
13669+ &cinfo);
13670+ else
13671+ r = dispc_get_clock_div(&cinfo);
13672+
13673+ if (r)
13674+ goto err0;
13675+
13676+ fck = cinfo.fck;
13677+ lck_div = cinfo.lck_div;
13678+ pck_div = cinfo.pck_div;
13679+
13680+ pck = fck / lck_div / pck_div / 1000;
13681+
13682+ if (pck != panel->timings.pixel_clock) {
13683+ DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
13684+ "got %lu kHz\n",
13685+ panel->timings.pixel_clock, pck);
13686+
13687+ panel->timings.pixel_clock = pck;
13688+ }
13689+
13690+
13691+ dispc_set_lcd_timings(&panel->timings);
13692+
13693+ r = dispc_set_clock_div(&cinfo);
13694+ if (r)
13695+ goto err1;
13696+
13697+ if (!sdi.skip_init) {
13698+ dss_sdi_init(display->hw_config.u.sdi.datapairs);
13699+ dss_sdi_enable();
13700+ mdelay(2);
13701+ }
13702+
13703+ dispc_enable_lcd_out(1);
13704+
13705+ r = panel->enable(display);
13706+ if (r)
13707+ goto err2;
13708+
13709+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
13710+
13711+ sdi.skip_init = 0;
13712+
13713+ return 0;
13714+err2:
13715+ dispc_enable_lcd_out(0);
13716+err1:
13717+err0:
13718+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
13719+ return r;
13720+}
13721+
13722+static int sdi_display_resume(struct omap_display *display);
13723+
13724+static void sdi_display_disable(struct omap_display *display)
13725+{
13726+ if (display->state == OMAP_DSS_DISPLAY_DISABLED)
13727+ return;
13728+
13729+ if (display->state == OMAP_DSS_DISPLAY_SUSPENDED)
13730+ sdi_display_resume(display);
13731+
13732+ display->panel->disable(display);
13733+
13734+ dispc_enable_lcd_out(0);
13735+
13736+ dss_sdi_disable();
13737+
13738+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
13739+
13740+ display->state = OMAP_DSS_DISPLAY_DISABLED;
13741+}
13742+
13743+static int sdi_display_suspend(struct omap_display *display)
13744+{
13745+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
13746+ return -EINVAL;
13747+
13748+ if (display->panel->suspend)
13749+ display->panel->suspend(display);
13750+
13751+ dispc_enable_lcd_out(0);
13752+
13753+ dss_sdi_disable();
13754+
13755+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
13756+
13757+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
13758+
13759+ return 0;
13760+}
13761+
13762+static int sdi_display_resume(struct omap_display *display)
13763+{
13764+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
13765+ return -EINVAL;
13766+
13767+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
13768+
13769+ dss_sdi_enable();
13770+ mdelay(2);
13771+
13772+ dispc_enable_lcd_out(1);
13773+
13774+ if (display->panel->resume)
13775+ display->panel->resume(display);
13776+
13777+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
13778+
13779+ return 0;
13780+}
13781+
13782+static int sdi_display_set_update_mode(struct omap_display *display,
13783+ enum omap_dss_update_mode mode)
13784+{
13785+ if (mode == OMAP_DSS_UPDATE_MANUAL)
13786+ return -EINVAL;
13787+
13788+ if (mode == OMAP_DSS_UPDATE_DISABLED) {
13789+ dispc_enable_lcd_out(0);
13790+ sdi.update_enabled = 0;
13791+ } else {
13792+ dispc_enable_lcd_out(1);
13793+ sdi.update_enabled = 1;
13794+ }
13795+
13796+ return 0;
13797+}
13798+
13799+static enum omap_dss_update_mode sdi_display_get_update_mode(
13800+ struct omap_display *display)
13801+{
13802+ return sdi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
13803+ OMAP_DSS_UPDATE_DISABLED;
13804+}
13805+
13806+static void sdi_get_timings(struct omap_display *display,
13807+ struct omap_video_timings *timings)
13808+{
13809+ *timings = display->panel->timings;
13810+}
13811+
13812+void sdi_init_display(struct omap_display *display)
13813+{
13814+ DSSDBG("SDI init\n");
13815+
13816+ display->enable = sdi_display_enable;
13817+ display->disable = sdi_display_disable;
13818+ display->suspend = sdi_display_suspend;
13819+ display->resume = sdi_display_resume;
13820+ display->set_update_mode = sdi_display_set_update_mode;
13821+ display->get_update_mode = sdi_display_get_update_mode;
13822+ display->get_timings = sdi_get_timings;
13823+}
13824+
13825+int sdi_init(bool skip_init)
13826+{
13827+ /* we store this for first display enable, then clear it */
13828+ sdi.skip_init = skip_init;
13829+
13830+ /*
13831+ * Enable clocks already here, otherwise there would be a toggle
13832+ * of them until sdi_display_enable is called.
13833+ */
13834+ if (skip_init)
13835+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
13836+ return 0;
13837+}
13838+
13839+void sdi_exit(void)
13840+{
13841+}
13842diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
13843new file mode 100644
13844index 0000000..aceed9f
13845--- /dev/null
13846+++ b/drivers/video/omap2/dss/venc.c
13847@@ -0,0 +1,600 @@
13848+/*
13849+ * linux/drivers/video/omap2/dss/venc.c
13850+ *
13851+ * Copyright (C) 2009 Nokia Corporation
13852+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
13853+ *
13854+ * VENC settings from TI's DSS driver
13855+ *
13856+ * This program is free software; you can redistribute it and/or modify it
13857+ * under the terms of the GNU General Public License version 2 as published by
13858+ * the Free Software Foundation.
13859+ *
13860+ * This program is distributed in the hope that it will be useful, but WITHOUT
13861+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13862+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13863+ * more details.
13864+ *
13865+ * You should have received a copy of the GNU General Public License along with
13866+ * this program. If not, see <http://www.gnu.org/licenses/>.
13867+ */
13868+
13869+#define DSS_SUBSYS_NAME "VENC"
13870+
13871+#include <linux/kernel.h>
13872+#include <linux/module.h>
13873+#include <linux/clk.h>
13874+#include <linux/err.h>
13875+#include <linux/io.h>
13876+#include <linux/mutex.h>
13877+#include <linux/completion.h>
13878+#include <linux/delay.h>
13879+#include <linux/string.h>
13880+
13881+#include <mach/display.h>
13882+#include <mach/cpu.h>
13883+
13884+#include "dss.h"
13885+
13886+#define VENC_BASE 0x48050C00
13887+
13888+/* Venc registers */
13889+#define VENC_REV_ID 0x00
13890+#define VENC_STATUS 0x04
13891+#define VENC_F_CONTROL 0x08
13892+#define VENC_VIDOUT_CTRL 0x10
13893+#define VENC_SYNC_CTRL 0x14
13894+#define VENC_LLEN 0x1C
13895+#define VENC_FLENS 0x20
13896+#define VENC_HFLTR_CTRL 0x24
13897+#define VENC_CC_CARR_WSS_CARR 0x28
13898+#define VENC_C_PHASE 0x2C
13899+#define VENC_GAIN_U 0x30
13900+#define VENC_GAIN_V 0x34
13901+#define VENC_GAIN_Y 0x38
13902+#define VENC_BLACK_LEVEL 0x3C
13903+#define VENC_BLANK_LEVEL 0x40
13904+#define VENC_X_COLOR 0x44
13905+#define VENC_M_CONTROL 0x48
13906+#define VENC_BSTAMP_WSS_DATA 0x4C
13907+#define VENC_S_CARR 0x50
13908+#define VENC_LINE21 0x54
13909+#define VENC_LN_SEL 0x58
13910+#define VENC_L21__WC_CTL 0x5C
13911+#define VENC_HTRIGGER_VTRIGGER 0x60
13912+#define VENC_SAVID__EAVID 0x64
13913+#define VENC_FLEN__FAL 0x68
13914+#define VENC_LAL__PHASE_RESET 0x6C
13915+#define VENC_HS_INT_START_STOP_X 0x70
13916+#define VENC_HS_EXT_START_STOP_X 0x74
13917+#define VENC_VS_INT_START_X 0x78
13918+#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
13919+#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
13920+#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
13921+#define VENC_VS_EXT_STOP_Y 0x88
13922+#define VENC_AVID_START_STOP_X 0x90
13923+#define VENC_AVID_START_STOP_Y 0x94
13924+#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
13925+#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
13926+#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
13927+#define VENC_TVDETGP_INT_START_STOP_X 0xB0
13928+#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
13929+#define VENC_GEN_CTRL 0xB8
13930+#define VENC_OUTPUT_CONTROL 0xC4
13931+#define VENC_DAC_B__DAC_C 0xC8
13932+
13933+struct venc_config {
13934+ u32 f_control;
13935+ u32 vidout_ctrl;
13936+ u32 sync_ctrl;
13937+ u32 llen;
13938+ u32 flens;
13939+ u32 hfltr_ctrl;
13940+ u32 cc_carr_wss_carr;
13941+ u32 c_phase;
13942+ u32 gain_u;
13943+ u32 gain_v;
13944+ u32 gain_y;
13945+ u32 black_level;
13946+ u32 blank_level;
13947+ u32 x_color;
13948+ u32 m_control;
13949+ u32 bstamp_wss_data;
13950+ u32 s_carr;
13951+ u32 line21;
13952+ u32 ln_sel;
13953+ u32 l21__wc_ctl;
13954+ u32 htrigger_vtrigger;
13955+ u32 savid__eavid;
13956+ u32 flen__fal;
13957+ u32 lal__phase_reset;
13958+ u32 hs_int_start_stop_x;
13959+ u32 hs_ext_start_stop_x;
13960+ u32 vs_int_start_x;
13961+ u32 vs_int_stop_x__vs_int_start_y;
13962+ u32 vs_int_stop_y__vs_ext_start_x;
13963+ u32 vs_ext_stop_x__vs_ext_start_y;
13964+ u32 vs_ext_stop_y;
13965+ u32 avid_start_stop_x;
13966+ u32 avid_start_stop_y;
13967+ u32 fid_int_start_x__fid_int_start_y;
13968+ u32 fid_int_offset_y__fid_ext_start_x;
13969+ u32 fid_ext_start_y__fid_ext_offset_y;
13970+ u32 tvdetgp_int_start_stop_x;
13971+ u32 tvdetgp_int_start_stop_y;
13972+ u32 gen_ctrl;
13973+};
13974+
13975+/* from TRM */
13976+static const struct venc_config venc_config_pal_trm = {
13977+ .f_control = 0,
13978+ .vidout_ctrl = 1,
13979+ .sync_ctrl = 0x40,
13980+ .llen = 0x35F, /* 863 */
13981+ .flens = 0x270, /* 624 */
13982+ .hfltr_ctrl = 0,
13983+ .cc_carr_wss_carr = 0x2F7225ED,
13984+ .c_phase = 0,
13985+ .gain_u = 0x111,
13986+ .gain_v = 0x181,
13987+ .gain_y = 0x140,
13988+ .black_level = 0x3B,
13989+ .blank_level = 0x3B,
13990+ .x_color = 0x7,
13991+ .m_control = 0x2,
13992+ .bstamp_wss_data = 0x3F,
13993+ .s_carr = 0x2A098ACB,
13994+ .line21 = 0,
13995+ .ln_sel = 0x01290015,
13996+ .l21__wc_ctl = 0x0000F603,
13997+ .htrigger_vtrigger = 0,
13998+
13999+ .savid__eavid = 0x06A70108,
14000+ .flen__fal = 0x00180270,
14001+ .lal__phase_reset = 0x00040135,
14002+ .hs_int_start_stop_x = 0x00880358,
14003+ .hs_ext_start_stop_x = 0x000F035F,
14004+ .vs_int_start_x = 0x01A70000,
14005+ .vs_int_stop_x__vs_int_start_y = 0x000001A7,
14006+ .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
14007+ .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
14008+ .vs_ext_stop_y = 0x00000025,
14009+ .avid_start_stop_x = 0x03530083,
14010+ .avid_start_stop_y = 0x026C002E,
14011+ .fid_int_start_x__fid_int_start_y = 0x0001008A,
14012+ .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
14013+ .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
14014+
14015+ .tvdetgp_int_start_stop_x = 0x00140001,
14016+ .tvdetgp_int_start_stop_y = 0x00010001,
14017+ .gen_ctrl = 0x00FF0000,
14018+};
14019+
14020+/* from TRM */
14021+static const struct venc_config venc_config_ntsc_trm = {
14022+ .f_control = 0,
14023+ .vidout_ctrl = 1,
14024+ .sync_ctrl = 0x8040,
14025+ .llen = 0x359,
14026+ .flens = 0x20C,
14027+ .hfltr_ctrl = 0,
14028+ .cc_carr_wss_carr = 0x043F2631,
14029+ .c_phase = 0,
14030+ .gain_u = 0x102,
14031+ .gain_v = 0x16C,
14032+ .gain_y = 0x12F,
14033+ .black_level = 0x43,
14034+ .blank_level = 0x38,
14035+ .x_color = 0x7,
14036+ .m_control = 0x1,
14037+ .bstamp_wss_data = 0x38,
14038+ .s_carr = 0x21F07C1F,
14039+ .line21 = 0,
14040+ .ln_sel = 0x01310011,
14041+ .l21__wc_ctl = 0x0000F003,
14042+ .htrigger_vtrigger = 0,
14043+
14044+ .savid__eavid = 0x069300F4,
14045+ .flen__fal = 0x0016020C,
14046+ .lal__phase_reset = 0x00060107,
14047+ .hs_int_start_stop_x = 0x008E0350,
14048+ .hs_ext_start_stop_x = 0x000F0359,
14049+ .vs_int_start_x = 0x01A00000,
14050+ .vs_int_stop_x__vs_int_start_y = 0x020701A0,
14051+ .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
14052+ .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
14053+ .vs_ext_stop_y = 0x00000006,
14054+ .avid_start_stop_x = 0x03480078,
14055+ .avid_start_stop_y = 0x02060024,
14056+ .fid_int_start_x__fid_int_start_y = 0x0001008A,
14057+ .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
14058+ .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
14059+
14060+ .tvdetgp_int_start_stop_x = 0x00140001,
14061+ .tvdetgp_int_start_stop_y = 0x00010001,
14062+ .gen_ctrl = 0x00F90000,
14063+};
14064+
14065+static const struct venc_config venc_config_pal_bdghi = {
14066+ .f_control = 0,
14067+ .vidout_ctrl = 0,
14068+ .sync_ctrl = 0,
14069+ .hfltr_ctrl = 0,
14070+ .x_color = 0,
14071+ .line21 = 0,
14072+ .ln_sel = 21,
14073+ .htrigger_vtrigger = 0,
14074+ .tvdetgp_int_start_stop_x = 0x00140001,
14075+ .tvdetgp_int_start_stop_y = 0x00010001,
14076+ .gen_ctrl = 0x00FB0000,
14077+
14078+ .llen = 864-1,
14079+ .flens = 625-1,
14080+ .cc_carr_wss_carr = 0x2F7625ED,
14081+ .c_phase = 0xDF,
14082+ .gain_u = 0x111,
14083+ .gain_v = 0x181,
14084+ .gain_y = 0x140,
14085+ .black_level = 0x3e,
14086+ .blank_level = 0x3e,
14087+ .m_control = 0<<2 | 1<<1,
14088+ .bstamp_wss_data = 0x42,
14089+ .s_carr = 0x2a098acb,
14090+ .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
14091+ .savid__eavid = 0x06A70108,
14092+ .flen__fal = 23<<16 | 624<<0,
14093+ .lal__phase_reset = 2<<17 | 310<<0,
14094+ .hs_int_start_stop_x = 0x00920358,
14095+ .hs_ext_start_stop_x = 0x000F035F,
14096+ .vs_int_start_x = 0x1a7<<16,
14097+ .vs_int_stop_x__vs_int_start_y = 0x000601A7,
14098+ .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
14099+ .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
14100+ .vs_ext_stop_y = 0x05,
14101+ .avid_start_stop_x = 0x03530082,
14102+ .avid_start_stop_y = 0x0270002E,
14103+ .fid_int_start_x__fid_int_start_y = 0x0005008A,
14104+ .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
14105+ .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
14106+};
14107+
14108+const struct omap_video_timings omap_dss_pal_timings = {
14109+ .x_res = 720,
14110+ .y_res = 574,
14111+ .pixel_clock = 26181,
14112+ .hsw = 32,
14113+ .hfp = 80,
14114+ .hbp = 48,
14115+ .vsw = 7,
14116+ .vfp = 3,
14117+ .vbp = 6,
14118+};
14119+EXPORT_SYMBOL(omap_dss_pal_timings);
14120+
14121+const struct omap_video_timings omap_dss_ntsc_timings = {
14122+ .x_res = 720,
14123+ .y_res = 482,
14124+ .pixel_clock = 22153,
14125+ .hsw = 32,
14126+ .hfp = 80,
14127+ .hbp = 48,
14128+ .vsw = 10,
14129+ .vfp = 3,
14130+ .vbp = 6,
14131+};
14132+EXPORT_SYMBOL(omap_dss_ntsc_timings);
14133+
14134+static struct {
14135+ void __iomem *base;
14136+ struct mutex venc_lock;
14137+} venc;
14138+
14139+static struct omap_panel venc_panel = {
14140+ .name = "tv-out",
14141+};
14142+
14143+static inline void venc_write_reg(int idx, u32 val)
14144+{
14145+ __raw_writel(val, venc.base + idx);
14146+}
14147+
14148+static inline u32 venc_read_reg(int idx)
14149+{
14150+ u32 l = __raw_readl(venc.base + idx);
14151+ return l;
14152+}
14153+
14154+static void venc_write_config(const struct venc_config *config)
14155+{
14156+ DSSDBG("write venc conf\n");
14157+
14158+ venc_write_reg(VENC_LLEN, config->llen);
14159+ venc_write_reg(VENC_FLENS, config->flens);
14160+ venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
14161+ venc_write_reg(VENC_C_PHASE, config->c_phase);
14162+ venc_write_reg(VENC_GAIN_U, config->gain_u);
14163+ venc_write_reg(VENC_GAIN_V, config->gain_v);
14164+ venc_write_reg(VENC_GAIN_Y, config->gain_y);
14165+ venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
14166+ venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
14167+ venc_write_reg(VENC_M_CONTROL, config->m_control);
14168+ venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data);
14169+ venc_write_reg(VENC_S_CARR, config->s_carr);
14170+ venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
14171+ venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
14172+ venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
14173+ venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
14174+ venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
14175+ venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
14176+ venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
14177+ venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
14178+ config->vs_int_stop_x__vs_int_start_y);
14179+ venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
14180+ config->vs_int_stop_y__vs_ext_start_x);
14181+ venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
14182+ config->vs_ext_stop_x__vs_ext_start_y);
14183+ venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
14184+ venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
14185+ venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
14186+ venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
14187+ config->fid_int_start_x__fid_int_start_y);
14188+ venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
14189+ config->fid_int_offset_y__fid_ext_start_x);
14190+ venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
14191+ config->fid_ext_start_y__fid_ext_offset_y);
14192+
14193+ venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
14194+ venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
14195+ venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
14196+ venc_write_reg(VENC_X_COLOR, config->x_color);
14197+ venc_write_reg(VENC_LINE21, config->line21);
14198+ venc_write_reg(VENC_LN_SEL, config->ln_sel);
14199+ venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
14200+ venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
14201+ config->tvdetgp_int_start_stop_x);
14202+ venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
14203+ config->tvdetgp_int_start_stop_y);
14204+ venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
14205+ venc_write_reg(VENC_F_CONTROL, config->f_control);
14206+ venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
14207+}
14208+
14209+static void venc_reset(void)
14210+{
14211+ int t = 1000;
14212+
14213+ venc_write_reg(VENC_F_CONTROL, 1<<8);
14214+ while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
14215+ if (--t == 0) {
14216+ DSSERR("Failed to reset venc\n");
14217+ return;
14218+ }
14219+ }
14220+
14221+ /* the magical sleep that makes things work */
14222+ msleep(20);
14223+}
14224+
14225+static void venc_enable_clocks(int enable)
14226+{
14227+ if (enable)
14228+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
14229+ DSS_CLK_96M);
14230+ else
14231+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
14232+ DSS_CLK_96M);
14233+}
14234+
14235+static const struct venc_config *venc_timings_to_config(
14236+ struct omap_video_timings *timings)
14237+{
14238+ if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
14239+ return &venc_config_pal_trm;
14240+
14241+ if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
14242+ return &venc_config_ntsc_trm;
14243+
14244+ BUG();
14245+}
14246+
14247+int venc_init(void)
14248+{
14249+ u8 rev_id;
14250+
14251+ mutex_init(&venc.venc_lock);
14252+
14253+ venc_panel.timings = omap_dss_pal_timings;
14254+
14255+ venc.base = ioremap(VENC_BASE, SZ_1K);
14256+ if (!venc.base) {
14257+ DSSERR("can't ioremap VENC\n");
14258+ return -ENOMEM;
14259+ }
14260+
14261+ venc_enable_clocks(1);
14262+
14263+ rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
14264+ printk(KERN_INFO "OMAP VENC rev %d\n", rev_id);
14265+
14266+ venc_enable_clocks(0);
14267+
14268+ return 0;
14269+}
14270+
14271+void venc_exit(void)
14272+{
14273+ iounmap(venc.base);
14274+}
14275+
14276+static void venc_power_on(struct omap_display *display)
14277+{
14278+ venc_enable_clocks(1);
14279+
14280+ venc_reset();
14281+ venc_write_config(venc_timings_to_config(&display->panel->timings));
14282+
14283+ dss_set_venc_output(display->hw_config.u.venc.type);
14284+ dss_set_dac_pwrdn_bgz(1);
14285+
14286+ if (display->hw_config.u.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) {
14287+ if (cpu_is_omap24xx())
14288+ venc_write_reg(VENC_OUTPUT_CONTROL, 0x2);
14289+ else
14290+ venc_write_reg(VENC_OUTPUT_CONTROL, 0xa);
14291+ } else { /* S-Video */
14292+ venc_write_reg(VENC_OUTPUT_CONTROL, 0xd);
14293+ }
14294+
14295+ dispc_set_digit_size(display->panel->timings.x_res,
14296+ display->panel->timings.y_res/2);
14297+
14298+ if (display->hw_config.panel_enable)
14299+ display->hw_config.panel_enable(display);
14300+
14301+ dispc_enable_digit_out(1);
14302+}
14303+
14304+static void venc_power_off(struct omap_display *display)
14305+{
14306+ venc_write_reg(VENC_OUTPUT_CONTROL, 0);
14307+ dss_set_dac_pwrdn_bgz(0);
14308+
14309+ dispc_enable_digit_out(0);
14310+
14311+ if (display->hw_config.panel_disable)
14312+ display->hw_config.panel_disable(display);
14313+
14314+ venc_enable_clocks(0);
14315+}
14316+
14317+static int venc_enable_display(struct omap_display *display)
14318+{
14319+ int r = 0;
14320+
14321+ DSSDBG("venc_enable_display\n");
14322+
14323+ mutex_lock(&venc.venc_lock);
14324+
14325+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
14326+ r = -EINVAL;
14327+ goto err;
14328+ }
14329+
14330+ venc_power_on(display);
14331+
14332+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
14333+err:
14334+ mutex_unlock(&venc.venc_lock);
14335+
14336+ return r;
14337+}
14338+
14339+static void venc_disable_display(struct omap_display *display)
14340+{
14341+ DSSDBG("venc_disable_display\n");
14342+
14343+ mutex_lock(&venc.venc_lock);
14344+
14345+ if (display->state == OMAP_DSS_DISPLAY_DISABLED)
14346+ goto end;
14347+
14348+ if (display->state == OMAP_DSS_DISPLAY_SUSPENDED) {
14349+ /* suspended is the same as disabled with venc */
14350+ display->state = OMAP_DSS_DISPLAY_DISABLED;
14351+ goto end;
14352+ }
14353+
14354+ venc_power_off(display);
14355+
14356+ display->state = OMAP_DSS_DISPLAY_DISABLED;
14357+end:
14358+ mutex_unlock(&venc.venc_lock);
14359+}
14360+
14361+static int venc_display_suspend(struct omap_display *display)
14362+{
14363+ int r = 0;
14364+
14365+ DSSDBG("venc_display_suspend\n");
14366+
14367+ mutex_lock(&venc.venc_lock);
14368+
14369+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE) {
14370+ r = -EINVAL;
14371+ goto err;
14372+ }
14373+
14374+ venc_power_off(display);
14375+
14376+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
14377+err:
14378+ mutex_unlock(&venc.venc_lock);
14379+
14380+ return r;
14381+}
14382+
14383+static int venc_display_resume(struct omap_display *display)
14384+{
14385+ int r = 0;
14386+
14387+ DSSDBG("venc_display_resume\n");
14388+
14389+ mutex_lock(&venc.venc_lock);
14390+
14391+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED) {
14392+ r = -EINVAL;
14393+ goto err;
14394+ }
14395+
14396+ venc_power_on(display);
14397+
14398+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
14399+err:
14400+ mutex_unlock(&venc.venc_lock);
14401+
14402+ return r;
14403+}
14404+
14405+static void venc_get_timings(struct omap_display *display,
14406+ struct omap_video_timings *timings)
14407+{
14408+ *timings = venc_panel.timings;
14409+}
14410+
14411+static void venc_set_timings(struct omap_display *display,
14412+ struct omap_video_timings *timings)
14413+{
14414+ DSSDBG("venc_set_timings\n");
14415+ display->panel->timings = *timings;
14416+ if (display->state == OMAP_DSS_DISPLAY_ACTIVE) {
14417+ /* turn the venc off and on to get new timings to use */
14418+ venc_disable_display(display);
14419+ venc_enable_display(display);
14420+ }
14421+}
14422+
14423+static int venc_check_timings(struct omap_display *display,
14424+ struct omap_video_timings *timings)
14425+{
14426+ DSSDBG("venc_check_timings\n");
14427+
14428+ if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
14429+ return 0;
14430+
14431+ if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
14432+ return 0;
14433+
14434+ return -EINVAL;
14435+}
14436+
14437+void venc_init_display(struct omap_display *display)
14438+{
14439+ display->panel = &venc_panel;
14440+ display->enable = venc_enable_display;
14441+ display->disable = venc_disable_display;
14442+ display->suspend = venc_display_suspend;
14443+ display->resume = venc_display_resume;
14444+ display->get_timings = venc_get_timings;
14445+ display->set_timings = venc_set_timings;
14446+ display->check_timings = venc_check_timings;
14447+}
14448--
144491.5.6.5
14450
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0004-DSS2-OMAP-framebuffer-driver.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0004-DSS2-OMAP-framebuffer-driver.patch
new file mode 100644
index 0000000000..09afa7e5be
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0004-DSS2-OMAP-framebuffer-driver.patch
@@ -0,0 +1,3403 @@
1From db9314f01a207e256d545244d3d00dc4ce535280 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 2 Apr 2009 10:25:48 +0300
4Subject: [PATCH] DSS2: OMAP framebuffer driver
5
6Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7---
8 arch/arm/plat-omap/fb.c | 28 +
9 drivers/video/omap/Kconfig | 5 +-
10 drivers/video/omap2/omapfb/Kconfig | 35 +
11 drivers/video/omap2/omapfb/Makefile | 2 +
12 drivers/video/omap2/omapfb/omapfb-ioctl.c | 656 ++++++++++
13 drivers/video/omap2/omapfb/omapfb-main.c | 2010 +++++++++++++++++++++++++++++
14 drivers/video/omap2/omapfb/omapfb-sysfs.c | 371 ++++++
15 drivers/video/omap2/omapfb/omapfb.h | 153 +++
16 include/linux/omapfb.h | 20 +
17 9 files changed, 3278 insertions(+), 2 deletions(-)
18 create mode 100644 drivers/video/omap2/omapfb/Kconfig
19 create mode 100644 drivers/video/omap2/omapfb/Makefile
20 create mode 100644 drivers/video/omap2/omapfb/omapfb-ioctl.c
21 create mode 100644 drivers/video/omap2/omapfb/omapfb-main.c
22 create mode 100644 drivers/video/omap2/omapfb/omapfb-sysfs.c
23 create mode 100644 drivers/video/omap2/omapfb/omapfb.h
24
25diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
26index 40615a6..1dc3415 100644
27--- a/arch/arm/plat-omap/fb.c
28+++ b/arch/arm/plat-omap/fb.c
29@@ -327,6 +327,34 @@ static inline int omap_init_fb(void)
30
31 arch_initcall(omap_init_fb);
32
33+#elif defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
34+
35+static u64 omap_fb_dma_mask = ~(u32)0;
36+static struct omapfb_platform_data omapfb_config;
37+
38+static struct platform_device omap_fb_device = {
39+ .name = "omapfb",
40+ .id = -1,
41+ .dev = {
42+ .dma_mask = &omap_fb_dma_mask,
43+ .coherent_dma_mask = ~(u32)0,
44+ .platform_data = &omapfb_config,
45+ },
46+ .num_resources = 0,
47+};
48+
49+void omapfb_set_platform_data(struct omapfb_platform_data *data)
50+{
51+ omapfb_config = *data;
52+}
53+
54+static inline int omap_init_fb(void)
55+{
56+ return platform_device_register(&omap_fb_device);
57+}
58+
59+arch_initcall(omap_init_fb);
60+
61 #else
62
63 void omapfb_reserve_sdram(void) {}
64diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig
65index c355b59..a1c10de 100644
66--- a/drivers/video/omap/Kconfig
67+++ b/drivers/video/omap/Kconfig
68@@ -1,6 +1,7 @@
69 config FB_OMAP
70 tristate "OMAP frame buffer support (EXPERIMENTAL)"
71- depends on FB && ARCH_OMAP
72+ depends on FB && ARCH_OMAP && (OMAP2_DSS = "n")
73+
74 select FB_CFB_FILLRECT
75 select FB_CFB_COPYAREA
76 select FB_CFB_IMAGEBLIT
77@@ -72,7 +73,7 @@ config FB_OMAP_LCD_MIPID
78
79 config FB_OMAP_BOOTLOADER_INIT
80 bool "Check bootloader initialization"
81- depends on FB_OMAP
82+ depends on FB_OMAP || FB_OMAP2
83 help
84 Say Y here if you want to enable checking if the bootloader has
85 already initialized the display controller. In this case the
86diff --git a/drivers/video/omap2/omapfb/Kconfig b/drivers/video/omap2/omapfb/Kconfig
87new file mode 100644
88index 0000000..4f66033
89--- /dev/null
90+++ b/drivers/video/omap2/omapfb/Kconfig
91@@ -0,0 +1,35 @@
92+menuconfig FB_OMAP2
93+ tristate "OMAP2/3 frame buffer support (EXPERIMENTAL)"
94+ depends on FB && OMAP2_DSS
95+
96+ select FB_CFB_FILLRECT
97+ select FB_CFB_COPYAREA
98+ select FB_CFB_IMAGEBLIT
99+ help
100+ Frame buffer driver for OMAP2/3 based boards.
101+
102+config FB_OMAP2_DEBUG_SUPPORT
103+ bool "Debug support for OMAP2/3 FB"
104+ default y
105+ depends on FB_OMAP2
106+ help
107+ Support for debug output. You have to enable the actual printing
108+ with debug module parameter.
109+
110+config FB_OMAP2_FORCE_AUTO_UPDATE
111+ bool "Force main display to automatic update mode"
112+ depends on FB_OMAP2
113+ help
114+ Forces main display to automatic update mode (if possible),
115+ and also enables tearsync (if possible). By default
116+ displays that support manual update are started in manual
117+ update mode.
118+
119+config FB_OMAP2_NUM_FBS
120+ int "Number of framebuffers"
121+ range 1 10
122+ default 3
123+ depends on FB_OMAP2
124+ help
125+ Select the number of framebuffers created. OMAP2/3 has 3 overlays
126+ so normally this would be 3.
127diff --git a/drivers/video/omap2/omapfb/Makefile b/drivers/video/omap2/omapfb/Makefile
128new file mode 100644
129index 0000000..51c2e00
130--- /dev/null
131+++ b/drivers/video/omap2/omapfb/Makefile
132@@ -0,0 +1,2 @@
133+obj-$(CONFIG_FB_OMAP2) += omapfb.o
134+omapfb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o
135diff --git a/drivers/video/omap2/omapfb/omapfb-ioctl.c b/drivers/video/omap2/omapfb/omapfb-ioctl.c
136new file mode 100644
137index 0000000..7f18d2a
138--- /dev/null
139+++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c
140@@ -0,0 +1,656 @@
141+/*
142+ * linux/drivers/video/omap2/omapfb-ioctl.c
143+ *
144+ * Copyright (C) 2008 Nokia Corporation
145+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
146+ *
147+ * Some code and ideas taken from drivers/video/omap/ driver
148+ * by Imre Deak.
149+ *
150+ * This program is free software; you can redistribute it and/or modify it
151+ * under the terms of the GNU General Public License version 2 as published by
152+ * the Free Software Foundation.
153+ *
154+ * This program is distributed in the hope that it will be useful, but WITHOUT
155+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
156+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
157+ * more details.
158+ *
159+ * You should have received a copy of the GNU General Public License along with
160+ * this program. If not, see <http://www.gnu.org/licenses/>.
161+ */
162+
163+#include <linux/fb.h>
164+#include <linux/device.h>
165+#include <linux/uaccess.h>
166+#include <linux/platform_device.h>
167+#include <linux/mm.h>
168+#include <linux/omapfb.h>
169+#include <linux/vmalloc.h>
170+
171+#include <mach/display.h>
172+#include <mach/vrfb.h>
173+
174+#include "omapfb.h"
175+
176+static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
177+{
178+ struct omapfb_info *ofbi = FB2OFB(fbi);
179+ struct omapfb2_device *fbdev = ofbi->fbdev;
180+ struct omap_display *display = fb2display(fbi);
181+ struct omap_overlay *ovl;
182+ struct omap_overlay_info info;
183+ int r = 0;
184+
185+ DBG("omapfb_setup_plane\n");
186+
187+ omapfb_lock(fbdev);
188+
189+ if (ofbi->num_overlays != 1) {
190+ r = -EINVAL;
191+ goto out;
192+ }
193+
194+ /* XXX uses only the first overlay */
195+ ovl = ofbi->overlays[0];
196+
197+ if (pi->enabled && !ofbi->region.size) {
198+ /*
199+ * This plane's memory was freed, can't enable it
200+ * until it's reallocated.
201+ */
202+ r = -EINVAL;
203+ goto out;
204+ }
205+
206+ ovl->get_overlay_info(ovl, &info);
207+
208+ info.pos_x = pi->pos_x;
209+ info.pos_y = pi->pos_y;
210+ info.out_width = pi->out_width;
211+ info.out_height = pi->out_height;
212+ info.enabled = pi->enabled;
213+
214+ r = ovl->set_overlay_info(ovl, &info);
215+ if (r)
216+ goto out;
217+
218+ if (ovl->manager) {
219+ r = ovl->manager->apply(ovl->manager);
220+ if (r)
221+ goto out;
222+ }
223+
224+ if (display) {
225+ u16 w, h;
226+
227+ if (display->sync)
228+ display->sync(display);
229+
230+ display->get_resolution(display, &w, &h);
231+
232+ if (display->update)
233+ display->update(display, 0, 0, w, h);
234+ }
235+
236+out:
237+ omapfb_unlock(fbdev);
238+ if (r)
239+ dev_err(fbdev->dev, "setup_plane failed\n");
240+ return r;
241+}
242+
243+static int omapfb_query_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
244+{
245+ struct omapfb_info *ofbi = FB2OFB(fbi);
246+ struct omapfb2_device *fbdev = ofbi->fbdev;
247+
248+ omapfb_lock(fbdev);
249+
250+ if (ofbi->num_overlays != 1) {
251+ memset(pi, 0, sizeof(*pi));
252+ } else {
253+ struct omap_overlay_info *ovli;
254+ struct omap_overlay *ovl;
255+
256+ ovl = ofbi->overlays[0];
257+ ovli = &ovl->info;
258+
259+ pi->pos_x = ovli->pos_x;
260+ pi->pos_y = ovli->pos_y;
261+ pi->enabled = ovli->enabled;
262+ pi->channel_out = 0; /* xxx */
263+ pi->mirror = 0;
264+ pi->out_width = ovli->out_width;
265+ pi->out_height = ovli->out_height;
266+ }
267+
268+ omapfb_unlock(fbdev);
269+
270+ return 0;
271+}
272+
273+static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
274+{
275+ struct omapfb_info *ofbi = FB2OFB(fbi);
276+ struct omapfb2_device *fbdev = ofbi->fbdev;
277+ struct omapfb2_mem_region *rg;
278+ int r, i;
279+ size_t size;
280+
281+ if (mi->type > OMAPFB_MEMTYPE_MAX)
282+ return -EINVAL;
283+
284+ size = PAGE_ALIGN(mi->size);
285+
286+ rg = &ofbi->region;
287+
288+ omapfb_lock(fbdev);
289+
290+ for (i = 0; i < ofbi->num_overlays; i++) {
291+ if (ofbi->overlays[i]->info.enabled) {
292+ r = -EBUSY;
293+ goto out;
294+ }
295+ }
296+
297+ if (rg->size != size || rg->type != mi->type) {
298+ r = omapfb_realloc_fbmem(fbi, size, mi->type);
299+ if (r) {
300+ dev_err(fbdev->dev, "realloc fbmem failed\n");
301+ goto out;
302+ }
303+ }
304+
305+ r = 0;
306+out:
307+ omapfb_unlock(fbdev);
308+
309+ return r;
310+}
311+
312+static int omapfb_query_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
313+{
314+ struct omapfb_info *ofbi = FB2OFB(fbi);
315+ struct omapfb2_device *fbdev = ofbi->fbdev;
316+ struct omapfb2_mem_region *rg;
317+
318+ rg = &ofbi->region;
319+ memset(mi, 0, sizeof(*mi));
320+
321+ omapfb_lock(fbdev);
322+ mi->size = rg->size;
323+ mi->type = rg->type;
324+ omapfb_unlock(fbdev);
325+
326+ return 0;
327+}
328+
329+static int omapfb_update_window(struct fb_info *fbi,
330+ u32 x, u32 y, u32 w, u32 h)
331+{
332+ struct omapfb_info *ofbi = FB2OFB(fbi);
333+ struct omapfb2_device *fbdev = ofbi->fbdev;
334+ struct omap_display *display = fb2display(fbi);
335+ u16 dw, dh;
336+
337+ if (!display)
338+ return 0;
339+
340+ if (w == 0 || h == 0)
341+ return 0;
342+
343+ display->get_resolution(display, &dw, &dh);
344+
345+ if (x + w > dw || y + h > dh)
346+ return -EINVAL;
347+
348+ omapfb_lock(fbdev);
349+ display->update(display, x, y, w, h);
350+ omapfb_unlock(fbdev);
351+
352+ return 0;
353+}
354+
355+static int omapfb_set_update_mode(struct fb_info *fbi,
356+ enum omapfb_update_mode mode)
357+{
358+ struct omapfb_info *ofbi = FB2OFB(fbi);
359+ struct omapfb2_device *fbdev = ofbi->fbdev;
360+ struct omap_display *display = fb2display(fbi);
361+ enum omap_dss_update_mode um;
362+ int r;
363+
364+ if (!display || !display->set_update_mode)
365+ return -EINVAL;
366+
367+ switch (mode) {
368+ case OMAPFB_UPDATE_DISABLED:
369+ um = OMAP_DSS_UPDATE_DISABLED;
370+ break;
371+
372+ case OMAPFB_AUTO_UPDATE:
373+ um = OMAP_DSS_UPDATE_AUTO;
374+ break;
375+
376+ case OMAPFB_MANUAL_UPDATE:
377+ um = OMAP_DSS_UPDATE_MANUAL;
378+ break;
379+
380+ default:
381+ return -EINVAL;
382+ }
383+
384+ omapfb_lock(fbdev);
385+ r = display->set_update_mode(display, um);
386+ omapfb_unlock(fbdev);
387+
388+ return r;
389+}
390+
391+static int omapfb_get_update_mode(struct fb_info *fbi,
392+ enum omapfb_update_mode *mode)
393+{
394+ struct omapfb_info *ofbi = FB2OFB(fbi);
395+ struct omapfb2_device *fbdev = ofbi->fbdev;
396+ struct omap_display *display = fb2display(fbi);
397+ enum omap_dss_update_mode m;
398+
399+ if (!display || !display->get_update_mode)
400+ return -EINVAL;
401+
402+ omapfb_lock(fbdev);
403+ m = display->get_update_mode(display);
404+ omapfb_unlock(fbdev);
405+
406+ switch (m) {
407+ case OMAP_DSS_UPDATE_DISABLED:
408+ *mode = OMAPFB_UPDATE_DISABLED;
409+ break;
410+ case OMAP_DSS_UPDATE_AUTO:
411+ *mode = OMAPFB_AUTO_UPDATE;
412+ break;
413+ case OMAP_DSS_UPDATE_MANUAL:
414+ *mode = OMAPFB_MANUAL_UPDATE;
415+ break;
416+ default:
417+ BUG();
418+ }
419+
420+ return 0;
421+}
422+
423+/* XXX this color key handling is a hack... */
424+static struct omapfb_color_key omapfb_color_keys[2];
425+
426+static int _omapfb_set_color_key(struct omap_overlay_manager *mgr,
427+ struct omapfb_color_key *ck)
428+{
429+ enum omap_dss_color_key_type kt;
430+
431+ if(!mgr->set_default_color || !mgr->set_trans_key ||
432+ !mgr->enable_trans_key)
433+ return 0;
434+
435+ if (ck->key_type == OMAPFB_COLOR_KEY_DISABLED) {
436+ mgr->enable_trans_key(mgr, 0);
437+ omapfb_color_keys[mgr->id] = *ck;
438+ return 0;
439+ }
440+
441+ switch(ck->key_type) {
442+ case OMAPFB_COLOR_KEY_GFX_DST:
443+ kt = OMAP_DSS_COLOR_KEY_GFX_DST;
444+ break;
445+ case OMAPFB_COLOR_KEY_VID_SRC:
446+ kt = OMAP_DSS_COLOR_KEY_VID_SRC;
447+ break;
448+ default:
449+ return -EINVAL;
450+ }
451+
452+ mgr->set_default_color(mgr, ck->background);
453+ mgr->set_trans_key(mgr, kt, ck->trans_key);
454+ mgr->enable_trans_key(mgr, 1);
455+
456+ omapfb_color_keys[mgr->id] = *ck;
457+
458+ return 0;
459+}
460+
461+static int omapfb_set_color_key(struct fb_info *fbi,
462+ struct omapfb_color_key *ck)
463+{
464+ struct omapfb_info *ofbi = FB2OFB(fbi);
465+ struct omapfb2_device *fbdev = ofbi->fbdev;
466+ int r;
467+ int i;
468+ struct omap_overlay_manager *mgr = NULL;
469+
470+ omapfb_lock(fbdev);
471+
472+ for (i = 0; i < ofbi->num_overlays; i++) {
473+ if (ofbi->overlays[i]->manager) {
474+ mgr = ofbi->overlays[i]->manager;
475+ break;
476+ }
477+ }
478+
479+ if (!mgr) {
480+ r = -EINVAL;
481+ goto err;
482+ }
483+
484+ if(!mgr->set_default_color || !mgr->set_trans_key ||
485+ !mgr->enable_trans_key) {
486+ r = -ENODEV;
487+ goto err;
488+ }
489+
490+ r = _omapfb_set_color_key(mgr, ck);
491+err:
492+ omapfb_unlock(fbdev);
493+
494+ return r;
495+}
496+
497+static int omapfb_get_color_key(struct fb_info *fbi,
498+ struct omapfb_color_key *ck)
499+{
500+ struct omapfb_info *ofbi = FB2OFB(fbi);
501+ struct omapfb2_device *fbdev = ofbi->fbdev;
502+ struct omap_overlay_manager *mgr = NULL;
503+ int r = 0;
504+ int i;
505+
506+ omapfb_lock(fbdev);
507+
508+ for (i = 0; i < ofbi->num_overlays; i++) {
509+ if (ofbi->overlays[i]->manager) {
510+ mgr = ofbi->overlays[i]->manager;
511+ break;
512+ }
513+ }
514+
515+ if (!mgr) {
516+ r = -EINVAL;
517+ goto err;
518+ }
519+
520+ if(!mgr->set_default_color || !mgr->set_trans_key ||
521+ !mgr->enable_trans_key) {
522+ r = -ENODEV;
523+ goto err;
524+ }
525+
526+ *ck = omapfb_color_keys[mgr->id];
527+err:
528+ omapfb_unlock(fbdev);
529+
530+ return r;
531+}
532+
533+static int omapfb_memory_read(struct fb_info *fbi,
534+ struct omapfb_memory_read *mr)
535+{
536+ struct omap_display *display = fb2display(fbi);
537+ struct omapfb_info *ofbi = FB2OFB(fbi);
538+ struct omapfb2_device *fbdev = ofbi->fbdev;
539+ void *buf;
540+ int r;
541+
542+ if (!display || !display->memory_read)
543+ return -ENOENT;
544+
545+ if (!access_ok(VERIFY_WRITE, mr->buffer, mr->buffer_size))
546+ return -EFAULT;
547+
548+ if (mr->w * mr->h * 3 > mr->buffer_size)
549+ return -EINVAL;
550+
551+ buf = vmalloc(mr->buffer_size);
552+ if (!buf) {
553+ DBG("vmalloc failed\n");
554+ return -ENOMEM;
555+ }
556+
557+ omapfb_lock(fbdev);
558+
559+ r = display->memory_read(display, buf, mr->buffer_size,
560+ mr->x, mr->y, mr->w, mr->h);
561+
562+ if (r > 0) {
563+ if (copy_to_user(mr->buffer, buf, mr->buffer_size))
564+ r = -EFAULT;
565+ }
566+
567+ vfree(buf);
568+
569+ omapfb_unlock(fbdev);
570+
571+ return r;
572+}
573+
574+int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
575+{
576+ struct omapfb_info *ofbi = FB2OFB(fbi);
577+ struct omapfb2_device *fbdev = ofbi->fbdev;
578+ struct omap_display *display = fb2display(fbi);
579+
580+ union {
581+ struct omapfb_update_window_old uwnd_o;
582+ struct omapfb_update_window uwnd;
583+ struct omapfb_plane_info plane_info;
584+ struct omapfb_caps caps;
585+ struct omapfb_mem_info mem_info;
586+ struct omapfb_color_key color_key;
587+ enum omapfb_update_mode update_mode;
588+ int test_num;
589+ struct omapfb_memory_read memory_read;
590+ } p;
591+
592+ int r = 0;
593+
594+ switch (cmd) {
595+ case OMAPFB_SYNC_GFX:
596+ DBG("ioctl SYNC_GFX\n");
597+ if (!display || !display->sync) {
598+ /* DSS1 never returns an error here, so we neither */
599+ /*r = -EINVAL;*/
600+ break;
601+ }
602+
603+ omapfb_lock(fbdev);
604+ r = display->sync(display);
605+ omapfb_unlock(fbdev);
606+ break;
607+
608+ case OMAPFB_UPDATE_WINDOW_OLD:
609+ DBG("ioctl UPDATE_WINDOW_OLD\n");
610+ if (!display || !display->update) {
611+ r = -EINVAL;
612+ break;
613+ }
614+
615+ if (copy_from_user(&p.uwnd_o,
616+ (void __user *)arg,
617+ sizeof(p.uwnd_o))) {
618+ r = -EFAULT;
619+ break;
620+ }
621+
622+ r = omapfb_update_window(fbi, p.uwnd_o.x, p.uwnd_o.y,
623+ p.uwnd_o.width, p.uwnd_o.height);
624+ break;
625+
626+ case OMAPFB_UPDATE_WINDOW:
627+ DBG("ioctl UPDATE_WINDOW\n");
628+ if (!display || !display->update) {
629+ r = -EINVAL;
630+ break;
631+ }
632+
633+ if (copy_from_user(&p.uwnd, (void __user *)arg,
634+ sizeof(p.uwnd))) {
635+ r = -EFAULT;
636+ break;
637+ }
638+
639+ r = omapfb_update_window(fbi, p.uwnd.x, p.uwnd.y,
640+ p.uwnd.width, p.uwnd.height);
641+ break;
642+
643+ case OMAPFB_SETUP_PLANE:
644+ DBG("ioctl SETUP_PLANE\n");
645+ if (copy_from_user(&p.plane_info, (void __user *)arg,
646+ sizeof(p.plane_info)))
647+ r = -EFAULT;
648+ else
649+ r = omapfb_setup_plane(fbi, &p.plane_info);
650+ break;
651+
652+ case OMAPFB_QUERY_PLANE:
653+ DBG("ioctl QUERY_PLANE\n");
654+ r = omapfb_query_plane(fbi, &p.plane_info);
655+ if (r < 0)
656+ break;
657+ if (copy_to_user((void __user *)arg, &p.plane_info,
658+ sizeof(p.plane_info)))
659+ r = -EFAULT;
660+ break;
661+
662+ case OMAPFB_SETUP_MEM:
663+ DBG("ioctl SETUP_MEM\n");
664+ if (copy_from_user(&p.mem_info, (void __user *)arg,
665+ sizeof(p.mem_info)))
666+ r = -EFAULT;
667+ else
668+ r = omapfb_setup_mem(fbi, &p.mem_info);
669+ break;
670+
671+ case OMAPFB_QUERY_MEM:
672+ DBG("ioctl QUERY_MEM\n");
673+ r = omapfb_query_mem(fbi, &p.mem_info);
674+ if (r < 0)
675+ break;
676+ if (copy_to_user((void __user *)arg, &p.mem_info,
677+ sizeof(p.mem_info)))
678+ r = -EFAULT;
679+ break;
680+
681+ case OMAPFB_GET_CAPS:
682+ DBG("ioctl GET_CAPS\n");
683+ if (!display) {
684+ r = -EINVAL;
685+ break;
686+ }
687+
688+ p.caps.ctrl = display->caps;
689+
690+ if (copy_to_user((void __user *)arg, &p.caps, sizeof(p.caps)))
691+ r = -EFAULT;
692+ break;
693+
694+ case OMAPFB_SET_UPDATE_MODE:
695+ DBG("ioctl SET_UPDATE_MODE\n");
696+ if (get_user(p.update_mode, (int __user *)arg))
697+ r = -EFAULT;
698+ else
699+ r = omapfb_set_update_mode(fbi, p.update_mode);
700+ break;
701+
702+ case OMAPFB_GET_UPDATE_MODE:
703+ DBG("ioctl GET_UPDATE_MODE\n");
704+ r = omapfb_get_update_mode(fbi, &p.update_mode);
705+ if (r)
706+ break;
707+ if (put_user(p.update_mode,
708+ (enum omapfb_update_mode __user *)arg))
709+ r = -EFAULT;
710+ break;
711+
712+ case OMAPFB_SET_COLOR_KEY:
713+ DBG("ioctl SET_COLOR_KEY\n");
714+ if (copy_from_user(&p.color_key, (void __user *)arg,
715+ sizeof(p.color_key)))
716+ r = -EFAULT;
717+ else
718+ r = omapfb_set_color_key(fbi, &p.color_key);
719+ break;
720+
721+ case OMAPFB_GET_COLOR_KEY:
722+ DBG("ioctl GET_COLOR_KEY\n");
723+ if ((r = omapfb_get_color_key(fbi, &p.color_key)) < 0)
724+ break;
725+ if (copy_to_user((void __user *)arg, &p.color_key,
726+ sizeof(p.color_key)))
727+ r = -EFAULT;
728+ break;
729+
730+ case OMAPFB_WAITFORVSYNC:
731+ DBG("ioctl WAITFORVSYNC\n");
732+ if (!display) {
733+ r = -EINVAL;
734+ break;
735+ }
736+
737+ r = display->wait_vsync(display);
738+ break;
739+
740+ /* LCD and CTRL tests do the same thing for backward
741+ * compatibility */
742+ case OMAPFB_LCD_TEST:
743+ DBG("ioctl LCD_TEST\n");
744+ if (get_user(p.test_num, (int __user *)arg)) {
745+ r = -EFAULT;
746+ break;
747+ }
748+ if (!display || !display->run_test) {
749+ r = -EINVAL;
750+ break;
751+ }
752+
753+ r = display->run_test(display, p.test_num);
754+
755+ break;
756+
757+ case OMAPFB_CTRL_TEST:
758+ DBG("ioctl CTRL_TEST\n");
759+ if (get_user(p.test_num, (int __user *)arg)) {
760+ r = -EFAULT;
761+ break;
762+ }
763+ if (!display || !display->run_test) {
764+ r = -EINVAL;
765+ break;
766+ }
767+
768+ r = display->run_test(display, p.test_num);
769+
770+ break;
771+
772+ case OMAPFB_MEMORY_READ:
773+ DBG("ioctl MEMORY_READ\n");
774+
775+ if (copy_from_user(&p.memory_read, (void __user *)arg,
776+ sizeof(p.memory_read))) {
777+ r = -EFAULT;
778+ break;
779+ }
780+
781+ r = omapfb_memory_read(fbi, &p.memory_read);
782+
783+ break;
784+
785+ default:
786+ dev_err(fbdev->dev, "Unknown ioctl 0x%x\n", cmd);
787+ r = -EINVAL;
788+ }
789+
790+ if (r < 0)
791+ DBG("ioctl failed: %d\n", r);
792+
793+ return r;
794+}
795+
796+
797diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
798new file mode 100644
799index 0000000..852abe5
800--- /dev/null
801+++ b/drivers/video/omap2/omapfb/omapfb-main.c
802@@ -0,0 +1,2010 @@
803+/*
804+ * linux/drivers/video/omap2/omapfb-main.c
805+ *
806+ * Copyright (C) 2008 Nokia Corporation
807+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
808+ *
809+ * Some code and ideas taken from drivers/video/omap/ driver
810+ * by Imre Deak.
811+ *
812+ * This program is free software; you can redistribute it and/or modify it
813+ * under the terms of the GNU General Public License version 2 as published by
814+ * the Free Software Foundation.
815+ *
816+ * This program is distributed in the hope that it will be useful, but WITHOUT
817+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
818+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
819+ * more details.
820+ *
821+ * You should have received a copy of the GNU General Public License along with
822+ * this program. If not, see <http://www.gnu.org/licenses/>.
823+ */
824+
825+#include <linux/module.h>
826+#include <linux/delay.h>
827+#include <linux/fb.h>
828+#include <linux/dma-mapping.h>
829+#include <linux/vmalloc.h>
830+#include <linux/device.h>
831+#include <linux/platform_device.h>
832+#include <linux/omapfb.h>
833+
834+#include <mach/display.h>
835+#include <mach/vram.h>
836+#include <mach/vrfb.h>
837+
838+#include "omapfb.h"
839+
840+#define MODULE_NAME "omapfb"
841+
842+static char *def_mode;
843+static char *def_vram;
844+static int def_vrfb;
845+static int def_rotate;
846+static int def_mirror;
847+
848+#ifdef DEBUG
849+unsigned int omapfb_debug;
850+module_param_named(debug, omapfb_debug, bool, 0644);
851+static unsigned int omapfb_test_pattern;
852+module_param_named(test, omapfb_test_pattern, bool, 0644);
853+#endif
854+
855+#ifdef DEBUG
856+static void draw_pixel(struct fb_info *fbi, int x, int y, unsigned color)
857+{
858+ struct fb_var_screeninfo *var = &fbi->var;
859+ struct fb_fix_screeninfo *fix = &fbi->fix;
860+ void __iomem *addr = fbi->screen_base;
861+ const unsigned bytespp = var->bits_per_pixel >> 3;
862+ const unsigned line_len = fix->line_length / bytespp;
863+
864+ int r = (color >> 16) & 0xff;
865+ int g = (color >> 8) & 0xff;
866+ int b = (color >> 0) & 0xff;
867+
868+ if (var->bits_per_pixel == 16) {
869+ u16 __iomem *p = (u16 __iomem *)addr;
870+ p += y * line_len + x;
871+
872+ r = r * 32 / 256;
873+ g = g * 64 / 256;
874+ b = b * 32 / 256;
875+
876+ __raw_writew((r << 11) | (g << 5) | (b << 0), p);
877+ } else if (var->bits_per_pixel == 24) {
878+ u8 __iomem *p = (u8 __iomem *)addr;
879+ p += (y * line_len + x) * 3;
880+
881+ __raw_writeb(b, p + 0);
882+ __raw_writeb(g, p + 1);
883+ __raw_writeb(r, p + 2);
884+ } else if (var->bits_per_pixel == 32) {
885+ u32 __iomem *p = (u32 __iomem *)addr;
886+ p += y * line_len + x;
887+ __raw_writel(color, p);
888+ }
889+}
890+
891+static void fill_fb(struct fb_info *fbi)
892+{
893+ struct fb_var_screeninfo *var = &fbi->var;
894+ const short w = var->xres_virtual;
895+ const short h = var->yres_virtual;
896+ void __iomem *addr = fbi->screen_base;
897+ int y, x;
898+
899+ if (!addr)
900+ return;
901+
902+ DBG("fill_fb %dx%d, line_len %d bytes\n", w, h, fbi->fix.line_length);
903+
904+ for (y = 0; y < h; y++) {
905+ for (x = 0; x < w; x++) {
906+ if (x < 20 && y < 20)
907+ draw_pixel(fbi, x, y, 0xffffff);
908+ else if (x < 20 && (y > 20 && y < h - 20))
909+ draw_pixel(fbi, x, y, 0xff);
910+ else if (y < 20 && (x > 20 && x < w - 20))
911+ draw_pixel(fbi, x, y, 0xff00);
912+ else if (x > w - 20 && (y > 20 && y < h - 20))
913+ draw_pixel(fbi, x, y, 0xff0000);
914+ else if (y > h - 20 && (x > 20 && x < w - 20))
915+ draw_pixel(fbi, x, y, 0xffff00);
916+ else if (x == 20 || x == w - 20 ||
917+ y == 20 || y == h - 20)
918+ draw_pixel(fbi, x, y, 0xffffff);
919+ else if (x == y || w - x == h - y)
920+ draw_pixel(fbi, x, y, 0xff00ff);
921+ else if (w - x == y || x == h - y)
922+ draw_pixel(fbi, x, y, 0x00ffff);
923+ else if (x > 20 && y > 20 && x < w - 20 && y < h - 20) {
924+ int t = x * 3 / w;
925+ unsigned r = 0, g = 0, b = 0;
926+ unsigned c;
927+ if (var->bits_per_pixel == 16) {
928+ if (t == 0)
929+ b = (y % 32) * 256 / 32;
930+ else if (t == 1)
931+ g = (y % 64) * 256 / 64;
932+ else if (t == 2)
933+ r = (y % 32) * 256 / 32;
934+ } else {
935+ if (t == 0)
936+ b = (y % 256);
937+ else if (t == 1)
938+ g = (y % 256);
939+ else if (t == 2)
940+ r = (y % 256);
941+ }
942+ c = (r << 16) | (g << 8) | (b << 0);
943+ draw_pixel(fbi, x, y, c);
944+ } else {
945+ draw_pixel(fbi, x, y, 0);
946+ }
947+ }
948+ }
949+}
950+#endif
951+
952+static unsigned omapfb_get_vrfb_offset(struct omapfb_info *ofbi, int rot)
953+{
954+ struct vrfb *vrfb = &ofbi->region.vrfb;
955+ unsigned offset;
956+
957+ switch (rot) {
958+ case FB_ROTATE_UR:
959+ offset = 0;
960+ break;
961+ case FB_ROTATE_CW:
962+ offset = vrfb->yoffset;
963+ break;
964+ case FB_ROTATE_UD:
965+ offset = vrfb->yoffset * OMAP_VRFB_LINE_LEN + vrfb->xoffset;
966+ break;
967+ case FB_ROTATE_CCW:
968+ offset = vrfb->xoffset * OMAP_VRFB_LINE_LEN;
969+ break;
970+ default:
971+ BUG();
972+ }
973+
974+ offset *= vrfb->bytespp;
975+
976+ return offset;
977+}
978+
979+static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi)
980+{
981+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
982+ unsigned offset;
983+ int rot;
984+
985+ rot = ofbi->rotation;
986+
987+ offset = omapfb_get_vrfb_offset(ofbi, rot);
988+
989+ return ofbi->region.vrfb.paddr[rot] + offset;
990+ } else {
991+ return ofbi->region.paddr;
992+ }
993+}
994+
995+u32 omapfb_get_region_paddr(struct omapfb_info *ofbi)
996+{
997+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
998+ return ofbi->region.vrfb.paddr[0];
999+ else
1000+ return ofbi->region.paddr;
1001+}
1002+
1003+void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi)
1004+{
1005+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
1006+ return ofbi->region.vrfb.vaddr[0];
1007+ else
1008+ return ofbi->region.vaddr;
1009+}
1010+
1011+static struct omapfb_colormode omapfb_colormodes[] = {
1012+ {
1013+ .dssmode = OMAP_DSS_COLOR_UYVY,
1014+ .bits_per_pixel = 16,
1015+ .nonstd = OMAPFB_COLOR_YUV422,
1016+ }, {
1017+ .dssmode = OMAP_DSS_COLOR_YUV2,
1018+ .bits_per_pixel = 16,
1019+ .nonstd = OMAPFB_COLOR_YUY422,
1020+ }, {
1021+ .dssmode = OMAP_DSS_COLOR_ARGB16,
1022+ .bits_per_pixel = 16,
1023+ .red = { .length = 4, .offset = 8, .msb_right = 0 },
1024+ .green = { .length = 4, .offset = 4, .msb_right = 0 },
1025+ .blue = { .length = 4, .offset = 0, .msb_right = 0 },
1026+ .transp = { .length = 4, .offset = 12, .msb_right = 0 },
1027+ }, {
1028+ .dssmode = OMAP_DSS_COLOR_RGB16,
1029+ .bits_per_pixel = 16,
1030+ .red = { .length = 5, .offset = 11, .msb_right = 0 },
1031+ .green = { .length = 6, .offset = 5, .msb_right = 0 },
1032+ .blue = { .length = 5, .offset = 0, .msb_right = 0 },
1033+ .transp = { .length = 0, .offset = 0, .msb_right = 0 },
1034+ }, {
1035+ .dssmode = OMAP_DSS_COLOR_RGB24P,
1036+ .bits_per_pixel = 24,
1037+ .red = { .length = 8, .offset = 16, .msb_right = 0 },
1038+ .green = { .length = 8, .offset = 8, .msb_right = 0 },
1039+ .blue = { .length = 8, .offset = 0, .msb_right = 0 },
1040+ .transp = { .length = 0, .offset = 0, .msb_right = 0 },
1041+ }, {
1042+ .dssmode = OMAP_DSS_COLOR_RGB24U,
1043+ .bits_per_pixel = 32,
1044+ .red = { .length = 8, .offset = 16, .msb_right = 0 },
1045+ .green = { .length = 8, .offset = 8, .msb_right = 0 },
1046+ .blue = { .length = 8, .offset = 0, .msb_right = 0 },
1047+ .transp = { .length = 0, .offset = 0, .msb_right = 0 },
1048+ }, {
1049+ .dssmode = OMAP_DSS_COLOR_ARGB32,
1050+ .bits_per_pixel = 32,
1051+ .red = { .length = 8, .offset = 16, .msb_right = 0 },
1052+ .green = { .length = 8, .offset = 8, .msb_right = 0 },
1053+ .blue = { .length = 8, .offset = 0, .msb_right = 0 },
1054+ .transp = { .length = 8, .offset = 24, .msb_right = 0 },
1055+ }, {
1056+ .dssmode = OMAP_DSS_COLOR_RGBA32,
1057+ .bits_per_pixel = 32,
1058+ .red = { .length = 8, .offset = 24, .msb_right = 0 },
1059+ .green = { .length = 8, .offset = 16, .msb_right = 0 },
1060+ .blue = { .length = 8, .offset = 8, .msb_right = 0 },
1061+ .transp = { .length = 8, .offset = 0, .msb_right = 0 },
1062+ }, {
1063+ .dssmode = OMAP_DSS_COLOR_RGBX32,
1064+ .bits_per_pixel = 32,
1065+ .red = { .length = 8, .offset = 24, .msb_right = 0 },
1066+ .green = { .length = 8, .offset = 16, .msb_right = 0 },
1067+ .blue = { .length = 8, .offset = 8, .msb_right = 0 },
1068+ .transp = { .length = 0, .offset = 0, .msb_right = 0 },
1069+ },
1070+};
1071+
1072+static bool cmp_var_to_colormode(struct fb_var_screeninfo *var,
1073+ struct omapfb_colormode *color)
1074+{
1075+ bool cmp_component(struct fb_bitfield *f1, struct fb_bitfield *f2)
1076+ {
1077+ return f1->length == f2->length &&
1078+ f1->offset == f2->offset &&
1079+ f1->msb_right == f2->msb_right;
1080+ }
1081+
1082+ if (var->bits_per_pixel == 0 ||
1083+ var->red.length == 0 ||
1084+ var->blue.length == 0 ||
1085+ var->green.length == 0)
1086+ return 0;
1087+
1088+ return var->bits_per_pixel == color->bits_per_pixel &&
1089+ cmp_component(&var->red, &color->red) &&
1090+ cmp_component(&var->green, &color->green) &&
1091+ cmp_component(&var->blue, &color->blue) &&
1092+ cmp_component(&var->transp, &color->transp);
1093+}
1094+
1095+static void assign_colormode_to_var(struct fb_var_screeninfo *var,
1096+ struct omapfb_colormode *color)
1097+{
1098+ var->bits_per_pixel = color->bits_per_pixel;
1099+ var->nonstd = color->nonstd;
1100+ var->red = color->red;
1101+ var->green = color->green;
1102+ var->blue = color->blue;
1103+ var->transp = color->transp;
1104+}
1105+
1106+static enum omap_color_mode fb_mode_to_dss_mode(struct fb_var_screeninfo *var)
1107+{
1108+ enum omap_color_mode dssmode;
1109+ int i;
1110+
1111+ /* first match with nonstd field */
1112+ if (var->nonstd) {
1113+ for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
1114+ struct omapfb_colormode *mode = &omapfb_colormodes[i];
1115+ if (var->nonstd == mode->nonstd) {
1116+ assign_colormode_to_var(var, mode);
1117+ return mode->dssmode;
1118+ }
1119+ }
1120+
1121+ return -EINVAL;
1122+ }
1123+
1124+ /* then try exact match of bpp and colors */
1125+ for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
1126+ struct omapfb_colormode *mode = &omapfb_colormodes[i];
1127+ if (cmp_var_to_colormode(var, mode)) {
1128+ assign_colormode_to_var(var, mode);
1129+ return mode->dssmode;
1130+ }
1131+ }
1132+
1133+ /* match with bpp if user has not filled color fields
1134+ * properly */
1135+ switch (var->bits_per_pixel) {
1136+ case 1:
1137+ dssmode = OMAP_DSS_COLOR_CLUT1;
1138+ break;
1139+ case 2:
1140+ dssmode = OMAP_DSS_COLOR_CLUT2;
1141+ break;
1142+ case 4:
1143+ dssmode = OMAP_DSS_COLOR_CLUT4;
1144+ break;
1145+ case 8:
1146+ dssmode = OMAP_DSS_COLOR_CLUT8;
1147+ break;
1148+ case 12:
1149+ dssmode = OMAP_DSS_COLOR_RGB12U;
1150+ break;
1151+ case 16:
1152+ dssmode = OMAP_DSS_COLOR_RGB16;
1153+ break;
1154+ case 24:
1155+ dssmode = OMAP_DSS_COLOR_RGB24P;
1156+ break;
1157+ case 32:
1158+ dssmode = OMAP_DSS_COLOR_RGB24U;
1159+ break;
1160+ default:
1161+ return -EINVAL;
1162+ }
1163+
1164+ for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
1165+ struct omapfb_colormode *mode = &omapfb_colormodes[i];
1166+ if (dssmode == mode->dssmode) {
1167+ assign_colormode_to_var(var, mode);
1168+ return mode->dssmode;
1169+ }
1170+ }
1171+
1172+ return -EINVAL;
1173+}
1174+
1175+void set_fb_fix(struct fb_info *fbi)
1176+{
1177+ struct fb_fix_screeninfo *fix = &fbi->fix;
1178+ struct fb_var_screeninfo *var = &fbi->var;
1179+ struct omapfb_info *ofbi = FB2OFB(fbi);
1180+ struct omapfb2_mem_region *rg = &ofbi->region;
1181+
1182+ DBG("set_fb_fix\n");
1183+
1184+ /* used by open/write in fbmem.c */
1185+ fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi);
1186+
1187+ /* used by mmap in fbmem.c */
1188+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
1189+ fix->line_length =
1190+ (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
1191+ else
1192+ fix->line_length =
1193+ (var->xres_virtual * var->bits_per_pixel) >> 3;
1194+ fix->smem_start = omapfb_get_region_paddr(ofbi);
1195+ fix->smem_len = rg->size;
1196+
1197+ fix->type = FB_TYPE_PACKED_PIXELS;
1198+
1199+ if (var->nonstd)
1200+ fix->visual = FB_VISUAL_PSEUDOCOLOR;
1201+ else {
1202+ switch (var->bits_per_pixel) {
1203+ case 32:
1204+ case 24:
1205+ case 16:
1206+ case 12:
1207+ fix->visual = FB_VISUAL_TRUECOLOR;
1208+ /* 12bpp is stored in 16 bits */
1209+ break;
1210+ case 1:
1211+ case 2:
1212+ case 4:
1213+ case 8:
1214+ fix->visual = FB_VISUAL_PSEUDOCOLOR;
1215+ break;
1216+ }
1217+ }
1218+
1219+ fix->accel = FB_ACCEL_NONE;
1220+
1221+ fix->xpanstep = 1;
1222+ fix->ypanstep = 1;
1223+
1224+ if (rg->size) {
1225+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
1226+ omap_vrfb_setup(&rg->vrfb, rg->paddr,
1227+ var->xres_virtual, var->yres_virtual,
1228+ var->bits_per_pixel >> 3);
1229+ }
1230+}
1231+
1232+/* check new var and possibly modify it to be ok */
1233+int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
1234+{
1235+ struct omapfb_info *ofbi = FB2OFB(fbi);
1236+ struct omap_display *display = fb2display(fbi);
1237+ unsigned long max_frame_size;
1238+ unsigned long line_size;
1239+ int xres_min, yres_min;
1240+ int xres_max, yres_max;
1241+ enum omap_color_mode mode = 0;
1242+ int i;
1243+ int bytespp;
1244+
1245+ DBG("check_fb_var %d\n", ofbi->id);
1246+
1247+ if (ofbi->region.size == 0)
1248+ return 0;
1249+
1250+ mode = fb_mode_to_dss_mode(var);
1251+ if (mode < 0) {
1252+ DBG("cannot convert var to omap dss mode\n");
1253+ return -EINVAL;
1254+ }
1255+
1256+ for (i = 0; i < ofbi->num_overlays; ++i) {
1257+ if ((ofbi->overlays[i]->supported_modes & mode) == 0) {
1258+ DBG("invalid mode\n");
1259+ return -EINVAL;
1260+ }
1261+ }
1262+
1263+ if (var->rotate < 0 || var->rotate > 3)
1264+ return -EINVAL;
1265+
1266+ if (var->rotate != fbi->var.rotate) {
1267+ DBG("rotation changing\n");
1268+
1269+ ofbi->rotation = var->rotate;
1270+
1271+ if (abs(var->rotate - fbi->var.rotate) != 2) {
1272+ int tmp;
1273+ DBG("rotate changing 90/270 degrees. "
1274+ "swapping x/y res\n");
1275+
1276+ tmp = var->yres;
1277+ var->yres = var->xres;
1278+ var->xres = tmp;
1279+
1280+ tmp = var->yres_virtual;
1281+ var->yres_virtual = var->xres_virtual;
1282+ var->xres_virtual = tmp;
1283+ }
1284+ }
1285+
1286+ xres_min = OMAPFB_PLANE_XRES_MIN;
1287+ xres_max = 2048;
1288+ yres_min = OMAPFB_PLANE_YRES_MIN;
1289+ yres_max = 2048;
1290+
1291+ bytespp = var->bits_per_pixel >> 3;
1292+
1293+ /* XXX: some applications seem to set virtual res to 0. */
1294+ if (var->xres_virtual == 0)
1295+ var->xres_virtual = var->xres;
1296+
1297+ if (var->yres_virtual == 0)
1298+ var->yres_virtual = var->yres;
1299+
1300+ if (var->xres_virtual < xres_min || var->yres_virtual < yres_min)
1301+ return -EINVAL;
1302+
1303+ if (var->xres < xres_min)
1304+ var->xres = xres_min;
1305+ if (var->yres < yres_min)
1306+ var->yres = yres_min;
1307+ if (var->xres > xres_max)
1308+ var->xres = xres_max;
1309+ if (var->yres > yres_max)
1310+ var->yres = yres_max;
1311+
1312+ if (var->xres > var->xres_virtual)
1313+ var->xres = var->xres_virtual;
1314+ if (var->yres > var->yres_virtual)
1315+ var->yres = var->yres_virtual;
1316+
1317+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
1318+ line_size = OMAP_VRFB_LINE_LEN * bytespp;
1319+ else
1320+ line_size = var->xres_virtual * bytespp;
1321+
1322+ max_frame_size = ofbi->region.size;
1323+
1324+ DBG("max frame size %lu, line size %lu\n", max_frame_size, line_size);
1325+
1326+ if (line_size * var->yres_virtual > max_frame_size) {
1327+ DBG("can't fit FB into memory, reducing y\n");
1328+ var->yres_virtual = max_frame_size / line_size;
1329+
1330+ if (var->yres_virtual < yres_min)
1331+ var->yres_virtual = yres_min;
1332+
1333+ if (var->yres > var->yres_virtual)
1334+ var->yres = var->yres_virtual;
1335+ }
1336+
1337+ if (line_size * var->yres_virtual > max_frame_size) {
1338+ DBG("can't fit FB into memory, reducing x\n");
1339+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
1340+ return -EINVAL;
1341+
1342+ var->xres_virtual = max_frame_size / var->yres_virtual /
1343+ bytespp;
1344+
1345+ if (var->xres_virtual < xres_min)
1346+ var->xres_virtual = xres_min;
1347+
1348+ if (var->xres > var->xres_virtual)
1349+ var->xres = var->xres_virtual;
1350+
1351+ line_size = var->xres_virtual * bytespp;
1352+ }
1353+
1354+ if (line_size * var->yres_virtual > max_frame_size) {
1355+ DBG("cannot fit FB to memory\n");
1356+ return -EINVAL;
1357+ }
1358+
1359+ if (var->xres + var->xoffset > var->xres_virtual)
1360+ var->xoffset = var->xres_virtual - var->xres;
1361+ if (var->yres + var->yoffset > var->yres_virtual)
1362+ var->yoffset = var->yres_virtual - var->yres;
1363+
1364+ DBG("xres = %d, yres = %d, vxres = %d, vyres = %d\n",
1365+ var->xres, var->yres,
1366+ var->xres_virtual, var->yres_virtual);
1367+
1368+ var->height = -1;
1369+ var->width = -1;
1370+ var->grayscale = 0;
1371+
1372+ if (display && display->get_timings) {
1373+ struct omap_video_timings timings;
1374+ display->get_timings(display, &timings);
1375+
1376+ /* pixclock in ps, the rest in pixclock */
1377+ var->pixclock = timings.pixel_clock != 0 ?
1378+ KHZ2PICOS(timings.pixel_clock) :
1379+ 0;
1380+ var->left_margin = timings.hfp;
1381+ var->right_margin = timings.hbp;
1382+ var->upper_margin = timings.vfp;
1383+ var->lower_margin = timings.vbp;
1384+ var->hsync_len = timings.hsw;
1385+ var->vsync_len = timings.vsw;
1386+ } else {
1387+ var->pixclock = 0;
1388+ var->left_margin = 0;
1389+ var->right_margin = 0;
1390+ var->upper_margin = 0;
1391+ var->lower_margin = 0;
1392+ var->hsync_len = 0;
1393+ var->vsync_len = 0;
1394+ }
1395+
1396+ /* TODO: get these from panel->config */
1397+ var->vmode = FB_VMODE_NONINTERLACED;
1398+ var->sync = 0;
1399+
1400+ return 0;
1401+}
1402+
1403+/*
1404+ * ---------------------------------------------------------------------------
1405+ * fbdev framework callbacks
1406+ * ---------------------------------------------------------------------------
1407+ */
1408+static int omapfb_open(struct fb_info *fbi, int user)
1409+{
1410+ return 0;
1411+}
1412+
1413+static int omapfb_release(struct fb_info *fbi, int user)
1414+{
1415+ struct omapfb_info *ofbi = FB2OFB(fbi);
1416+ struct omapfb2_device *fbdev = ofbi->fbdev;
1417+ struct omap_display *display = fb2display(fbi);
1418+
1419+ DBG("Closing fb with plane index %d\n", ofbi->id);
1420+
1421+ omapfb_lock(fbdev);
1422+#if 1
1423+ if (display && display->get_update_mode && display->update) {
1424+ /* XXX this update should be removed, I think. But it's
1425+ * good for debugging */
1426+ if (display->get_update_mode(display) ==
1427+ OMAP_DSS_UPDATE_MANUAL) {
1428+ u16 w, h;
1429+
1430+ if (display->sync)
1431+ display->sync(display);
1432+
1433+ display->get_resolution(display, &w, &h);
1434+ display->update(display, 0, 0, w, h);
1435+ }
1436+ }
1437+#endif
1438+
1439+ if (display && display->sync)
1440+ display->sync(display);
1441+
1442+ omapfb_unlock(fbdev);
1443+
1444+ return 0;
1445+}
1446+
1447+/* setup overlay according to the fb */
1448+static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
1449+ u16 posx, u16 posy, u16 outw, u16 outh)
1450+{
1451+ int r = 0;
1452+ struct omapfb_info *ofbi = FB2OFB(fbi);
1453+ struct fb_var_screeninfo *var = &fbi->var;
1454+ struct fb_fix_screeninfo *fix = &fbi->fix;
1455+ enum omap_color_mode mode = 0;
1456+ int offset;
1457+ u32 data_start_p;
1458+ void __iomem *data_start_v;
1459+ struct omap_overlay_info info;
1460+ int xres, yres;
1461+ int screen_width;
1462+ int rot, mirror;
1463+
1464+ DBG("setup_overlay %d, posx %d, posy %d, outw %d, outh %d\n", ofbi->id,
1465+ posx, posy, outw, outh);
1466+
1467+ if (ofbi->rotation == FB_ROTATE_CW || ofbi->rotation == FB_ROTATE_CCW) {
1468+ xres = var->yres;
1469+ yres = var->xres;
1470+ } else {
1471+ xres = var->xres;
1472+ yres = var->yres;
1473+ }
1474+
1475+ offset = ((var->yoffset * var->xres_virtual +
1476+ var->xoffset) * var->bits_per_pixel) >> 3;
1477+
1478+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
1479+ data_start_p = omapfb_get_region_rot_paddr(ofbi);
1480+ data_start_v = NULL;
1481+ } else {
1482+ data_start_p = omapfb_get_region_paddr(ofbi);
1483+ data_start_v = omapfb_get_region_vaddr(ofbi);
1484+ }
1485+
1486+ data_start_p += offset;
1487+ data_start_v += offset;
1488+
1489+ mode = fb_mode_to_dss_mode(var);
1490+
1491+ if (mode == -EINVAL) {
1492+ DBG("fb_mode_to_dss_mode failed");
1493+ r = -EINVAL;
1494+ goto err;
1495+ }
1496+
1497+ screen_width = fix->line_length / (var->bits_per_pixel >> 3);
1498+
1499+ ovl->get_overlay_info(ovl, &info);
1500+
1501+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
1502+ rot = 0;
1503+ mirror = 0;
1504+ } else {
1505+ rot = ofbi->rotation;
1506+ mirror = ofbi->mirror;
1507+ }
1508+
1509+ info.paddr = data_start_p;
1510+ info.vaddr = data_start_v;
1511+ info.screen_width = screen_width;
1512+ info.width = xres;
1513+ info.height = yres;
1514+ info.color_mode = mode;
1515+ info.rotation = rot;
1516+ info.mirror = mirror;
1517+
1518+ info.pos_x = posx;
1519+ info.pos_y = posy;
1520+ info.out_width = outw;
1521+ info.out_height = outh;
1522+
1523+ r = ovl->set_overlay_info(ovl, &info);
1524+ if (r) {
1525+ DBG("ovl->setup_overlay_info failed\n");
1526+ goto err;
1527+ }
1528+
1529+ return 0;
1530+
1531+err:
1532+ DBG("setup_overlay failed\n");
1533+ return r;
1534+}
1535+
1536+/* apply var to the overlay */
1537+int omapfb_apply_changes(struct fb_info *fbi, int init)
1538+{
1539+ int r = 0;
1540+ struct omapfb_info *ofbi = FB2OFB(fbi);
1541+ struct fb_var_screeninfo *var = &fbi->var;
1542+ struct omap_overlay *ovl;
1543+ u16 posx, posy;
1544+ u16 outw, outh;
1545+ int i;
1546+
1547+#ifdef DEBUG
1548+ if (omapfb_test_pattern)
1549+ fill_fb(fbi);
1550+#endif
1551+
1552+ for (i = 0; i < ofbi->num_overlays; i++) {
1553+ ovl = ofbi->overlays[i];
1554+
1555+ DBG("apply_changes, fb %d, ovl %d\n", ofbi->id, ovl->id);
1556+
1557+ if (ofbi->region.size == 0) {
1558+ /* the fb is not available. disable the overlay */
1559+ omapfb_overlay_enable(ovl, 0);
1560+ if (!init && ovl->manager)
1561+ ovl->manager->apply(ovl->manager);
1562+ continue;
1563+ }
1564+
1565+ if (init || (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
1566+ if (ofbi->rotation == FB_ROTATE_CW ||
1567+ ofbi->rotation == FB_ROTATE_CCW) {
1568+ outw = var->yres;
1569+ outh = var->xres;
1570+ } else {
1571+ outw = var->xres;
1572+ outh = var->yres;
1573+ }
1574+ } else {
1575+ outw = ovl->info.out_width;
1576+ outh = ovl->info.out_height;
1577+ }
1578+
1579+ if (init) {
1580+ posx = 0;
1581+ posy = 0;
1582+ } else {
1583+ posx = ovl->info.pos_x;
1584+ posy = ovl->info.pos_y;
1585+ }
1586+
1587+ r = omapfb_setup_overlay(fbi, ovl, posx, posy, outw, outh);
1588+ if (r)
1589+ goto err;
1590+
1591+ if (!init && ovl->manager)
1592+ ovl->manager->apply(ovl->manager);
1593+ }
1594+ return 0;
1595+err:
1596+ DBG("apply_changes failed\n");
1597+ return r;
1598+}
1599+
1600+/* checks var and eventually tweaks it to something supported,
1601+ * DO NOT MODIFY PAR */
1602+static int omapfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
1603+{
1604+ int r;
1605+
1606+ DBG("check_var(%d)\n", FB2OFB(fbi)->id);
1607+
1608+ r = check_fb_var(fbi, var);
1609+
1610+ return r;
1611+}
1612+
1613+/* set the video mode according to info->var */
1614+static int omapfb_set_par(struct fb_info *fbi)
1615+{
1616+ int r;
1617+
1618+ DBG("set_par(%d)\n", FB2OFB(fbi)->id);
1619+
1620+ set_fb_fix(fbi);
1621+ r = omapfb_apply_changes(fbi, 0);
1622+
1623+ return r;
1624+}
1625+
1626+static int omapfb_pan_display(struct fb_var_screeninfo *var,
1627+ struct fb_info *fbi)
1628+{
1629+ struct omapfb_info *ofbi = FB2OFB(fbi);
1630+ struct omapfb2_device *fbdev = ofbi->fbdev;
1631+ int r = 0;
1632+
1633+ DBG("pan_display(%d)\n", ofbi->id);
1634+
1635+ omapfb_lock(fbdev);
1636+
1637+ if (var->xoffset != fbi->var.xoffset ||
1638+ var->yoffset != fbi->var.yoffset) {
1639+ struct fb_var_screeninfo new_var;
1640+
1641+ new_var = fbi->var;
1642+ new_var.xoffset = var->xoffset;
1643+ new_var.yoffset = var->yoffset;
1644+
1645+ r = check_fb_var(fbi, &new_var);
1646+
1647+ if (r == 0) {
1648+ fbi->var = new_var;
1649+ set_fb_fix(fbi);
1650+ r = omapfb_apply_changes(fbi, 0);
1651+ }
1652+ }
1653+
1654+ omapfb_unlock(fbdev);
1655+
1656+ return r;
1657+}
1658+
1659+static void mmap_user_open(struct vm_area_struct *vma)
1660+{
1661+ struct omapfb_info *ofbi = (struct omapfb_info *)vma->vm_private_data;
1662+
1663+ atomic_inc(&ofbi->map_count);
1664+}
1665+
1666+static void mmap_user_close(struct vm_area_struct *vma)
1667+{
1668+ struct omapfb_info *ofbi = (struct omapfb_info *)vma->vm_private_data;
1669+
1670+ atomic_dec(&ofbi->map_count);
1671+}
1672+
1673+static struct vm_operations_struct mmap_user_ops = {
1674+ .open = mmap_user_open,
1675+ .close = mmap_user_close,
1676+};
1677+
1678+static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
1679+{
1680+ struct omapfb_info *ofbi = FB2OFB(fbi);
1681+ struct fb_fix_screeninfo *fix = &fbi->fix;
1682+ unsigned long off;
1683+ unsigned long start;
1684+ u32 len;
1685+
1686+ if (vma->vm_end - vma->vm_start == 0)
1687+ return 0;
1688+ if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1689+ return -EINVAL;
1690+ off = vma->vm_pgoff << PAGE_SHIFT;
1691+
1692+ start = omapfb_get_region_paddr(ofbi);
1693+ len = fix->smem_len;
1694+ if (off >= len)
1695+ return -EINVAL;
1696+ if ((vma->vm_end - vma->vm_start + off) > len)
1697+ return -EINVAL;
1698+
1699+ off += start;
1700+
1701+ DBG("user mmap region start %lx, len %d, off %lx\n", start, len, off);
1702+
1703+ vma->vm_pgoff = off >> PAGE_SHIFT;
1704+ vma->vm_flags |= VM_IO | VM_RESERVED;
1705+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1706+ vma->vm_ops = &mmap_user_ops;
1707+ vma->vm_private_data = ofbi;
1708+ if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
1709+ vma->vm_end - vma->vm_start, vma->vm_page_prot))
1710+ return -EAGAIN;
1711+ /* vm_ops.open won't be called for mmap itself. */
1712+ atomic_inc(&ofbi->map_count);
1713+ return 0;
1714+}
1715+
1716+/* Store a single color palette entry into a pseudo palette or the hardware
1717+ * palette if one is available. For now we support only 16bpp and thus store
1718+ * the entry only to the pseudo palette.
1719+ */
1720+static int _setcolreg(struct fb_info *fbi, u_int regno, u_int red, u_int green,
1721+ u_int blue, u_int transp, int update_hw_pal)
1722+{
1723+ /*struct omapfb_info *ofbi = FB2OFB(fbi);*/
1724+ /*struct omapfb2_device *fbdev = ofbi->fbdev;*/
1725+ struct fb_var_screeninfo *var = &fbi->var;
1726+ int r = 0;
1727+
1728+ enum omapfb_color_format mode = OMAPFB_COLOR_RGB24U; /* XXX */
1729+
1730+ /*switch (plane->color_mode) {*/
1731+ switch (mode) {
1732+ case OMAPFB_COLOR_YUV422:
1733+ case OMAPFB_COLOR_YUV420:
1734+ case OMAPFB_COLOR_YUY422:
1735+ r = -EINVAL;
1736+ break;
1737+ case OMAPFB_COLOR_CLUT_8BPP:
1738+ case OMAPFB_COLOR_CLUT_4BPP:
1739+ case OMAPFB_COLOR_CLUT_2BPP:
1740+ case OMAPFB_COLOR_CLUT_1BPP:
1741+ /*
1742+ if (fbdev->ctrl->setcolreg)
1743+ r = fbdev->ctrl->setcolreg(regno, red, green, blue,
1744+ transp, update_hw_pal);
1745+ */
1746+ /* Fallthrough */
1747+ r = -EINVAL;
1748+ break;
1749+ case OMAPFB_COLOR_RGB565:
1750+ case OMAPFB_COLOR_RGB444:
1751+ case OMAPFB_COLOR_RGB24P:
1752+ case OMAPFB_COLOR_RGB24U:
1753+ if (r != 0)
1754+ break;
1755+
1756+ if (regno < 0) {
1757+ r = -EINVAL;
1758+ break;
1759+ }
1760+
1761+ if (regno < 16) {
1762+ u16 pal;
1763+ pal = ((red >> (16 - var->red.length)) <<
1764+ var->red.offset) |
1765+ ((green >> (16 - var->green.length)) <<
1766+ var->green.offset) |
1767+ (blue >> (16 - var->blue.length));
1768+ ((u32 *)(fbi->pseudo_palette))[regno] = pal;
1769+ }
1770+ break;
1771+ default:
1772+ BUG();
1773+ }
1774+ return r;
1775+}
1776+
1777+static int omapfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1778+ u_int transp, struct fb_info *info)
1779+{
1780+ DBG("setcolreg\n");
1781+
1782+ return _setcolreg(info, regno, red, green, blue, transp, 1);
1783+}
1784+
1785+static int omapfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1786+{
1787+ int count, index, r;
1788+ u16 *red, *green, *blue, *transp;
1789+ u16 trans = 0xffff;
1790+
1791+ DBG("setcmap\n");
1792+
1793+ red = cmap->red;
1794+ green = cmap->green;
1795+ blue = cmap->blue;
1796+ transp = cmap->transp;
1797+ index = cmap->start;
1798+
1799+ for (count = 0; count < cmap->len; count++) {
1800+ if (transp)
1801+ trans = *transp++;
1802+ r = _setcolreg(info, index++, *red++, *green++, *blue++, trans,
1803+ count == cmap->len - 1);
1804+ if (r != 0)
1805+ return r;
1806+ }
1807+
1808+ return 0;
1809+}
1810+
1811+static int omapfb_blank(int blank, struct fb_info *fbi)
1812+{
1813+ struct omapfb_info *ofbi = FB2OFB(fbi);
1814+ struct omapfb2_device *fbdev = ofbi->fbdev;
1815+ struct omap_display *display = fb2display(fbi);
1816+ int do_update = 0;
1817+ int r = 0;
1818+
1819+ omapfb_lock(fbdev);
1820+
1821+ switch (blank) {
1822+ case FB_BLANK_UNBLANK:
1823+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
1824+ goto exit;
1825+
1826+ if (display->resume)
1827+ r = display->resume(display);
1828+
1829+ if (r == 0 && display->get_update_mode &&
1830+ display->get_update_mode(display) ==
1831+ OMAP_DSS_UPDATE_MANUAL)
1832+ do_update = 1;
1833+
1834+ break;
1835+
1836+ case FB_BLANK_NORMAL:
1837+ /* FB_BLANK_NORMAL could be implemented.
1838+ * Needs DSS additions. */
1839+ case FB_BLANK_VSYNC_SUSPEND:
1840+ case FB_BLANK_HSYNC_SUSPEND:
1841+ case FB_BLANK_POWERDOWN:
1842+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
1843+ goto exit;
1844+
1845+ if (display->suspend)
1846+ r = display->suspend(display);
1847+
1848+ break;
1849+
1850+ default:
1851+ r = -EINVAL;
1852+ }
1853+
1854+exit:
1855+ omapfb_unlock(fbdev);
1856+
1857+ if (r == 0 && do_update && display->update) {
1858+ u16 w, h;
1859+ display->get_resolution(display, &w, &h);
1860+
1861+ r = display->update(display, 0, 0, w, h);
1862+ }
1863+
1864+ return r;
1865+}
1866+
1867+#if 0
1868+/* XXX fb_read and fb_write are needed for VRFB */
1869+ssize_t omapfb_write(struct fb_info *info, const char __user *buf,
1870+ size_t count, loff_t *ppos)
1871+{
1872+ DBG("omapfb_write %d, %lu\n", count, (unsigned long)*ppos);
1873+ // XXX needed for VRFB
1874+ return count;
1875+}
1876+#endif
1877+
1878+static struct fb_ops omapfb_ops = {
1879+ .owner = THIS_MODULE,
1880+ .fb_open = omapfb_open,
1881+ .fb_release = omapfb_release,
1882+ .fb_fillrect = cfb_fillrect,
1883+ .fb_copyarea = cfb_copyarea,
1884+ .fb_imageblit = cfb_imageblit,
1885+ .fb_blank = omapfb_blank,
1886+ .fb_ioctl = omapfb_ioctl,
1887+ .fb_check_var = omapfb_check_var,
1888+ .fb_set_par = omapfb_set_par,
1889+ .fb_pan_display = omapfb_pan_display,
1890+ .fb_mmap = omapfb_mmap,
1891+ .fb_setcolreg = omapfb_setcolreg,
1892+ .fb_setcmap = omapfb_setcmap,
1893+ //.fb_write = omapfb_write,
1894+};
1895+
1896+static void omapfb_free_fbmem(struct fb_info *fbi)
1897+{
1898+ struct omapfb_info *ofbi = FB2OFB(fbi);
1899+ struct omapfb2_device *fbdev = ofbi->fbdev;
1900+ struct omapfb2_mem_region *rg;
1901+
1902+ rg = &ofbi->region;
1903+
1904+ if (rg->paddr)
1905+ if (omap_vram_free(rg->paddr, rg->size))
1906+ dev_err(fbdev->dev, "VRAM FREE failed\n");
1907+
1908+ if (rg->vaddr)
1909+ iounmap(rg->vaddr);
1910+
1911+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
1912+ /* unmap the 0 angle rotation */
1913+ if (rg->vrfb.vaddr[0]) {
1914+ iounmap(rg->vrfb.vaddr[0]);
1915+ omap_vrfb_release_ctx(&rg->vrfb);
1916+ }
1917+ }
1918+
1919+ rg->vaddr = NULL;
1920+ rg->paddr = 0;
1921+ rg->alloc = 0;
1922+ rg->size = 0;
1923+}
1924+
1925+static int omapfb_free_all_fbmem(struct omapfb2_device *fbdev)
1926+{
1927+ int i;
1928+
1929+ DBG("free all fbmem\n");
1930+
1931+ for (i = 0; i < fbdev->num_fbs; i++) {
1932+ struct fb_info *fbi = fbdev->fbs[i];
1933+ omapfb_free_fbmem(fbi);
1934+ memset(&fbi->fix, 0, sizeof(fbi->fix));
1935+ memset(&fbi->var, 0, sizeof(fbi->var));
1936+ }
1937+
1938+ return 0;
1939+}
1940+
1941+static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
1942+ unsigned long paddr)
1943+{
1944+ struct omapfb_info *ofbi = FB2OFB(fbi);
1945+ struct omapfb2_device *fbdev = ofbi->fbdev;
1946+ struct omapfb2_mem_region *rg;
1947+ void __iomem *vaddr;
1948+ int r;
1949+ int clear = 0;
1950+
1951+ rg = &ofbi->region;
1952+ memset(rg, 0, sizeof(*rg));
1953+
1954+ size = PAGE_ALIGN(size);
1955+
1956+ if (!paddr) {
1957+ DBG("allocating %lu bytes for fb %d\n", size, ofbi->id);
1958+ r = omap_vram_alloc(OMAPFB_MEMTYPE_SDRAM, size, &paddr);
1959+ clear = 1;
1960+ } else {
1961+ DBG("reserving %lu bytes at %lx for fb %d\n", size, paddr,
1962+ ofbi->id);
1963+ r = omap_vram_reserve(paddr, size);
1964+ }
1965+
1966+ if (r) {
1967+ dev_err(fbdev->dev, "failed to allocate framebuffer\n");
1968+ return -ENOMEM;
1969+ }
1970+
1971+ if (ofbi->rotation_type != OMAPFB_ROT_VRFB) {
1972+ vaddr = ioremap_wc(paddr, size);
1973+
1974+ if (!vaddr) {
1975+ dev_err(fbdev->dev, "failed to ioremap framebuffer\n");
1976+ omap_vram_free(paddr, size);
1977+ return -ENOMEM;
1978+ }
1979+
1980+ DBG("allocated VRAM paddr %lx, vaddr %p\n", paddr, vaddr);
1981+
1982+ if (clear)
1983+ memset_io(vaddr, 0, size);
1984+ } else {
1985+ void __iomem *va;
1986+
1987+ r = omap_vrfb_request_ctx(&rg->vrfb);
1988+ if (r) {
1989+ dev_err(fbdev->dev, "vrfb create ctx failed\n");
1990+ return r;
1991+ }
1992+
1993+ /* only ioremap the 0 angle view */
1994+ va = ioremap_wc(rg->vrfb.paddr[0], size);
1995+
1996+ if(!va) {
1997+ printk(KERN_ERR "vrfb: ioremap failed\n");
1998+ return -ENOMEM;
1999+ }
2000+
2001+ DBG("ioremapped vrfb area 0 to %p\n", va);
2002+
2003+ rg->vrfb.vaddr[0] = va;
2004+
2005+ vaddr = NULL;
2006+
2007+ if (clear)
2008+ memset_io(va, 0, size);
2009+ }
2010+
2011+ rg->paddr = paddr;
2012+ rg->vaddr = vaddr;
2013+ rg->size = size;
2014+ rg->alloc = 1;
2015+
2016+ return 0;
2017+}
2018+
2019+/* allocate fbmem using display resolution as reference */
2020+static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
2021+ unsigned long paddr)
2022+{
2023+ struct omapfb_info *ofbi = FB2OFB(fbi);
2024+ struct omap_display *display;
2025+ int bytespp;
2026+
2027+ display = fb2display(fbi);
2028+
2029+ if (!display)
2030+ return 0;
2031+
2032+ switch (display->get_recommended_bpp(display)) {
2033+ case 16:
2034+ bytespp = 2;
2035+ break;
2036+ case 24:
2037+ bytespp = 4;
2038+ break;
2039+ default:
2040+ bytespp = 4;
2041+ break;
2042+ }
2043+
2044+ if (!size) {
2045+ u16 w, h;
2046+
2047+ display->get_resolution(display, &w, &h);
2048+
2049+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
2050+ int oldw = w, oldh = h;
2051+
2052+ omap_vrfb_adjust_size(&w, &h, bytespp);
2053+
2054+ /* Because we change the resolution of the 0 degree view,
2055+ * we need to alloc max(w, h) for height */
2056+ h = max(w, h);
2057+ w = OMAP_VRFB_LINE_LEN;
2058+
2059+ DBG("adjusting fb mem size for VRFB, %dx%d -> %dx%d\n",
2060+ oldw, oldh, w, h);
2061+ }
2062+
2063+ size = w * h * bytespp;
2064+ }
2065+
2066+ return omapfb_alloc_fbmem(fbi, size, paddr);
2067+}
2068+
2069+static int omapfb_parse_vram_param(const char *param, int max_entries,
2070+ unsigned long *sizes, unsigned long *paddrs)
2071+{
2072+ int fbnum;
2073+ unsigned long size;
2074+ unsigned long paddr = 0;
2075+ char *p, *start;
2076+
2077+ start = (char *)param;
2078+
2079+ while (1) {
2080+ p = start;
2081+
2082+ fbnum = simple_strtoul(p, &p, 10);
2083+
2084+ if (p == param)
2085+ return -EINVAL;
2086+
2087+ if (*p != ':')
2088+ return -EINVAL;
2089+
2090+ if (fbnum >= max_entries)
2091+ return -EINVAL;
2092+
2093+ size = memparse(p + 1, &p);
2094+
2095+ if (!size)
2096+ return -EINVAL;
2097+
2098+ paddr = 0;
2099+
2100+ if (*p == '@') {
2101+ paddr = simple_strtoul(p + 1, &p, 16);
2102+
2103+ if (!paddr)
2104+ return -EINVAL;
2105+
2106+ }
2107+
2108+ paddrs[fbnum] = paddr;
2109+ sizes[fbnum] = size;
2110+
2111+ if (*p == 0)
2112+ break;
2113+
2114+ if (*p != ',')
2115+ return -EINVAL;
2116+
2117+ ++p;
2118+
2119+ start = p;
2120+ }
2121+
2122+ return 0;
2123+}
2124+
2125+static int omapfb_allocate_all_fbs(struct omapfb2_device *fbdev)
2126+{
2127+ int i, r;
2128+ unsigned long vram_sizes[10];
2129+ unsigned long vram_paddrs[10];
2130+
2131+ memset(&vram_sizes, 0, sizeof(vram_sizes));
2132+ memset(&vram_paddrs, 0, sizeof(vram_paddrs));
2133+
2134+ if (def_vram && omapfb_parse_vram_param(def_vram, 10,
2135+ vram_sizes, vram_paddrs)) {
2136+ dev_err(fbdev->dev, "failed to parse vram parameter\n");
2137+
2138+ memset(&vram_sizes, 0, sizeof(vram_sizes));
2139+ memset(&vram_paddrs, 0, sizeof(vram_paddrs));
2140+ }
2141+
2142+ if (fbdev->dev->platform_data) {
2143+ struct omapfb_platform_data *opd;
2144+ opd = fbdev->dev->platform_data;
2145+ for (i = 0; i < opd->mem_desc.region_cnt; ++i) {
2146+ if (!vram_sizes[i]) {
2147+ unsigned long size;
2148+ unsigned long paddr;
2149+
2150+ size = opd->mem_desc.region[i].size;
2151+ paddr = opd->mem_desc.region[i].paddr;
2152+
2153+ vram_sizes[i] = size;
2154+ vram_paddrs[i] = paddr;
2155+ }
2156+ }
2157+ }
2158+
2159+ for (i = 0; i < fbdev->num_fbs; i++) {
2160+ /* allocate memory automatically only for fb0, or if
2161+ * excplicitly defined with vram or plat data option */
2162+ if (i == 0 || vram_sizes[i] != 0) {
2163+ r = omapfb_alloc_fbmem_display(fbdev->fbs[i],
2164+ vram_sizes[i], vram_paddrs[i]);
2165+
2166+ if (r)
2167+ return r;
2168+ }
2169+ }
2170+
2171+ for (i = 0; i < fbdev->num_fbs; i++) {
2172+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
2173+ struct omapfb2_mem_region *rg;
2174+ rg = &ofbi->region;
2175+
2176+ DBG("region%d phys %08x virt %p size=%lu\n",
2177+ i,
2178+ rg->paddr,
2179+ rg->vaddr,
2180+ rg->size);
2181+ }
2182+
2183+ return 0;
2184+}
2185+
2186+int omapfb_realloc_fbmem(struct fb_info *fbi, unsigned long size, int type)
2187+{
2188+ struct omapfb_info *ofbi = FB2OFB(fbi);
2189+ struct omapfb2_device *fbdev = ofbi->fbdev;
2190+ struct omap_display *display = fb2display(fbi);
2191+ struct omapfb2_mem_region *rg = &ofbi->region;
2192+ unsigned long old_size = rg->size;
2193+ unsigned long old_paddr = rg->paddr;
2194+ int old_type = rg->type;
2195+ int r;
2196+
2197+ if (type > OMAPFB_MEMTYPE_MAX)
2198+ return -EINVAL;
2199+
2200+ size = PAGE_ALIGN(size);
2201+
2202+ if (old_size == size && old_type == type)
2203+ return 0;
2204+
2205+ if (display && display->sync)
2206+ display->sync(display);
2207+
2208+ omapfb_free_fbmem(fbi);
2209+
2210+ if (size == 0) {
2211+ memset(&fbi->fix, 0, sizeof(fbi->fix));
2212+ memset(&fbi->var, 0, sizeof(fbi->var));
2213+ return 0;
2214+ }
2215+
2216+ r = omapfb_alloc_fbmem(fbi, size, 0);
2217+
2218+ if (r) {
2219+ if (old_size)
2220+ omapfb_alloc_fbmem(fbi, old_size, old_paddr);
2221+
2222+ if (rg->size == 0) {
2223+ memset(&fbi->fix, 0, sizeof(fbi->fix));
2224+ memset(&fbi->var, 0, sizeof(fbi->var));
2225+ }
2226+
2227+ return r;
2228+ }
2229+
2230+ if (old_size == size)
2231+ return 0;
2232+
2233+ if (old_size == 0) {
2234+ DBG("initializing fb %d\n", ofbi->id);
2235+ r = omapfb_fb_init(fbdev, fbi);
2236+ if (r) {
2237+ DBG("omapfb_fb_init failed\n");
2238+ goto err;
2239+ }
2240+ r = omapfb_apply_changes(fbi, 1);
2241+ if (r) {
2242+ DBG("omapfb_apply_changes failed\n");
2243+ goto err;
2244+ }
2245+ } else {
2246+ struct fb_var_screeninfo new_var;
2247+ memcpy(&new_var, &fbi->var, sizeof(new_var));
2248+ r = check_fb_var(fbi, &new_var);
2249+ if (r)
2250+ goto err;
2251+ memcpy(&fbi->var, &new_var, sizeof(fbi->var));
2252+ set_fb_fix(fbi);
2253+ }
2254+
2255+ return 0;
2256+err:
2257+ omapfb_free_fbmem(fbi);
2258+ memset(&fbi->fix, 0, sizeof(fbi->fix));
2259+ memset(&fbi->var, 0, sizeof(fbi->var));
2260+ return r;
2261+}
2262+
2263+/* initialize fb_info, var, fix to something sane based on the display */
2264+int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
2265+{
2266+ struct fb_var_screeninfo *var = &fbi->var;
2267+ struct fb_fix_screeninfo *fix = &fbi->fix;
2268+ struct omap_display *display = fb2display(fbi);
2269+ struct omapfb_info *ofbi = FB2OFB(fbi);
2270+ int r = 0;
2271+
2272+ fbi->fbops = &omapfb_ops;
2273+ fbi->flags = FBINFO_FLAG_DEFAULT;
2274+ fbi->pseudo_palette = fbdev->pseudo_palette;
2275+
2276+ strncpy(fix->id, MODULE_NAME, sizeof(fix->id));
2277+
2278+ if (ofbi->region.size == 0) {
2279+ memset(&fbi->fix, 0, sizeof(fbi->fix));
2280+ memset(&fbi->var, 0, sizeof(fbi->var));
2281+ return 0;
2282+ }
2283+
2284+ var->nonstd = 0;
2285+
2286+ var->rotate = ofbi->rotation;
2287+
2288+ if (display) {
2289+ u16 w, h;
2290+ display->get_resolution(display, &w, &h);
2291+
2292+ if (ofbi->rotation == FB_ROTATE_CW ||
2293+ ofbi->rotation == FB_ROTATE_CCW) {
2294+ var->xres = h;
2295+ var->yres = w;
2296+ } else {
2297+ var->xres = w;
2298+ var->yres = h;
2299+ }
2300+
2301+ var->xres_virtual = var->xres;
2302+ var->yres_virtual = var->yres;
2303+
2304+ switch (display->get_recommended_bpp(display)) {
2305+ case 16:
2306+ var->bits_per_pixel = 16;
2307+ break;
2308+ case 24:
2309+ var->bits_per_pixel = 32;
2310+ break;
2311+ default:
2312+ dev_err(fbdev->dev, "illegal display bpp\n");
2313+ return -EINVAL;
2314+ }
2315+ } else {
2316+ /* if there's no display, let's just guess some basic values */
2317+ var->xres = 320;
2318+ var->yres = 240;
2319+ var->xres_virtual = var->xres;
2320+ var->yres_virtual = var->yres;
2321+ var->bits_per_pixel = 16;
2322+ }
2323+
2324+ r = check_fb_var(fbi, var);
2325+ if (r)
2326+ goto err;
2327+
2328+ set_fb_fix(fbi);
2329+err:
2330+ return r;
2331+}
2332+
2333+static void fbinfo_cleanup(struct omapfb2_device *fbdev, struct fb_info *fbi)
2334+{
2335+ fb_dealloc_cmap(&fbi->cmap);
2336+}
2337+
2338+
2339+static void omapfb_free_resources(struct omapfb2_device *fbdev)
2340+{
2341+ int i;
2342+
2343+ DBG("free_resources\n");
2344+
2345+ if (fbdev == NULL)
2346+ return;
2347+
2348+ for (i = 0; i < fbdev->num_fbs; i++)
2349+ unregister_framebuffer(fbdev->fbs[i]);
2350+
2351+ /* free the reserved fbmem */
2352+ omapfb_free_all_fbmem(fbdev);
2353+
2354+ for (i = 0; i < fbdev->num_fbs; i++) {
2355+ fbinfo_cleanup(fbdev, fbdev->fbs[i]);
2356+ framebuffer_release(fbdev->fbs[i]);
2357+ }
2358+
2359+ for (i = 0; i < fbdev->num_displays; i++) {
2360+ if (fbdev->displays[i]->state != OMAP_DSS_DISPLAY_DISABLED)
2361+ fbdev->displays[i]->disable(fbdev->displays[i]);
2362+
2363+ omap_dss_put_display(fbdev->displays[i]);
2364+ }
2365+
2366+ dev_set_drvdata(fbdev->dev, NULL);
2367+ kfree(fbdev);
2368+}
2369+
2370+static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
2371+{
2372+ int r, i;
2373+
2374+ fbdev->num_fbs = 0;
2375+
2376+ DBG("create %d framebuffers\n", CONFIG_FB_OMAP2_NUM_FBS);
2377+
2378+ /* allocate fb_infos */
2379+ for (i = 0; i < CONFIG_FB_OMAP2_NUM_FBS; i++) {
2380+ struct fb_info *fbi;
2381+ struct omapfb_info *ofbi;
2382+
2383+ fbi = framebuffer_alloc(sizeof(struct omapfb_info),
2384+ fbdev->dev);
2385+
2386+ if (fbi == NULL) {
2387+ dev_err(fbdev->dev,
2388+ "unable to allocate memory for plane info\n");
2389+ return -ENOMEM;
2390+ }
2391+
2392+ fbdev->fbs[i] = fbi;
2393+
2394+ ofbi = FB2OFB(fbi);
2395+ ofbi->fbdev = fbdev;
2396+ ofbi->id = i;
2397+
2398+ /* assign these early, so that fb alloc can use them */
2399+ ofbi->rotation_type = def_vrfb ? OMAPFB_ROT_VRFB :
2400+ OMAPFB_ROT_DMA;
2401+ ofbi->rotation = def_rotate;
2402+ ofbi->mirror = def_mirror;
2403+
2404+ fbdev->num_fbs++;
2405+ }
2406+
2407+ DBG("fb_infos allocated\n");
2408+
2409+ /* assign overlays for the fbs */
2410+ for (i = 0; i < min(fbdev->num_fbs, fbdev->num_overlays); i++) {
2411+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
2412+
2413+ ofbi->overlays[0] = fbdev->overlays[i];
2414+ ofbi->num_overlays = 1;
2415+ }
2416+
2417+ /* allocate fb memories */
2418+ r = omapfb_allocate_all_fbs(fbdev);
2419+ if (r) {
2420+ dev_err(fbdev->dev, "failed to allocate fbmem\n");
2421+ return r;
2422+ }
2423+
2424+ DBG("fbmems allocated\n");
2425+
2426+ /* setup fb_infos */
2427+ for (i = 0; i < fbdev->num_fbs; i++) {
2428+ r = omapfb_fb_init(fbdev, fbdev->fbs[i]);
2429+ if (r) {
2430+ dev_err(fbdev->dev, "failed to setup fb_info\n");
2431+ return r;
2432+ }
2433+ }
2434+
2435+ DBG("fb_infos initialized\n");
2436+
2437+ for (i = 0; i < fbdev->num_fbs; i++) {
2438+ r = register_framebuffer(fbdev->fbs[i]);
2439+ if (r != 0) {
2440+ dev_err(fbdev->dev,
2441+ "registering framebuffer %d failed\n", i);
2442+ return r;
2443+ }
2444+ }
2445+
2446+ DBG("framebuffers registered\n");
2447+
2448+ for (i = 0; i < fbdev->num_fbs; i++) {
2449+ r = omapfb_apply_changes(fbdev->fbs[i], 1);
2450+ if (r) {
2451+ dev_err(fbdev->dev, "failed to change mode\n");
2452+ return r;
2453+ }
2454+ }
2455+
2456+ DBG("create sysfs for fbs\n");
2457+ r = omapfb_create_sysfs(fbdev);
2458+ if (r) {
2459+ dev_err(fbdev->dev, "failed to create sysfs entries\n");
2460+ return r;
2461+ }
2462+
2463+ /* Enable fb0 */
2464+ if (fbdev->num_fbs > 0) {
2465+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[0]);
2466+
2467+ if (ofbi->num_overlays > 0 ) {
2468+ struct omap_overlay *ovl = ofbi->overlays[0];
2469+
2470+ r = omapfb_overlay_enable(ovl, 1);
2471+
2472+ if (r) {
2473+ dev_err(fbdev->dev,
2474+ "failed to enable overlay\n");
2475+ return r;
2476+ }
2477+ }
2478+ }
2479+
2480+ DBG("create_framebuffers done\n");
2481+
2482+ return 0;
2483+}
2484+
2485+int omapfb_mode_to_timings(const char *mode_str,
2486+ struct omap_video_timings *timings, u8 *bpp)
2487+{
2488+ struct fb_info fbi;
2489+ struct fb_var_screeninfo var;
2490+ struct fb_ops fbops;
2491+ int r;
2492+
2493+#ifdef CONFIG_OMAP2_DSS_VENC
2494+ if (strcmp(mode_str, "pal") == 0) {
2495+ *timings = omap_dss_pal_timings;
2496+ *bpp = 0;
2497+ return 0;
2498+ } else if (strcmp(mode_str, "ntsc") == 0) {
2499+ *timings = omap_dss_ntsc_timings;
2500+ *bpp = 0;
2501+ return 0;
2502+ }
2503+#endif
2504+
2505+ /* this is quite a hack, but I wanted to use the modedb and for
2506+ * that we need fb_info and var, so we create dummy ones */
2507+
2508+ memset(&fbi, 0, sizeof(fbi));
2509+ memset(&var, 0, sizeof(var));
2510+ memset(&fbops, 0, sizeof(fbops));
2511+ fbi.fbops = &fbops;
2512+
2513+ r = fb_find_mode(&var, &fbi, mode_str, NULL, 0, NULL, 24);
2514+
2515+ if (r != 0) {
2516+ timings->pixel_clock = PICOS2KHZ(var.pixclock);
2517+ timings->hfp = var.left_margin;
2518+ timings->hbp = var.right_margin;
2519+ timings->vfp = var.upper_margin;
2520+ timings->vbp = var.lower_margin;
2521+ timings->hsw = var.hsync_len;
2522+ timings->vsw = var.vsync_len;
2523+ timings->x_res = var.xres;
2524+ timings->y_res = var.yres;
2525+
2526+ switch (var.bits_per_pixel) {
2527+ case 16:
2528+ *bpp = 16;
2529+ break;
2530+ case 24:
2531+ case 32:
2532+ default:
2533+ *bpp = 24;
2534+ break;
2535+ }
2536+
2537+ return 0;
2538+ } else {
2539+ return -EINVAL;
2540+ }
2541+}
2542+
2543+static int omapfb_set_def_mode(struct omap_display *display, char *mode_str)
2544+{
2545+ int r;
2546+ u8 bpp;
2547+ struct omap_video_timings timings;
2548+
2549+ r = omapfb_mode_to_timings(mode_str, &timings, &bpp);
2550+ if (r)
2551+ return r;
2552+
2553+ display->panel->recommended_bpp = bpp;
2554+
2555+ if (!display->check_timings || !display->set_timings)
2556+ return -EINVAL;
2557+
2558+ r = display->check_timings(display, &timings);
2559+ if (r)
2560+ return r;
2561+
2562+ display->set_timings(display, &timings);
2563+
2564+ return 0;
2565+}
2566+
2567+static int omapfb_parse_def_modes(struct omapfb2_device *fbdev)
2568+{
2569+ char *str, *options, *this_opt;
2570+ int r = 0;
2571+
2572+ str = kmalloc(strlen(def_mode) + 1, GFP_KERNEL);
2573+ strcpy(str, def_mode);
2574+ options = str;
2575+
2576+ while (!r && (this_opt = strsep(&options, ",")) != NULL) {
2577+ char *p, *display_str, *mode_str;
2578+ struct omap_display *display;
2579+ int i;
2580+
2581+ p = strchr(this_opt, ':');
2582+ if (!p) {
2583+ r = -EINVAL;
2584+ break;
2585+ }
2586+
2587+ *p = 0;
2588+ display_str = this_opt;
2589+ mode_str = p + 1;
2590+
2591+ display = NULL;
2592+ for (i = 0; i < fbdev->num_displays; ++i) {
2593+ if (strcmp(fbdev->displays[i]->name,
2594+ display_str) == 0) {
2595+ display = fbdev->displays[i];
2596+ break;
2597+ }
2598+ }
2599+
2600+ if (!display) {
2601+ r = -EINVAL;
2602+ break;
2603+ }
2604+
2605+ r = omapfb_set_def_mode(display, mode_str);
2606+ if (r)
2607+ break;
2608+ }
2609+
2610+ kfree(str);
2611+
2612+ return r;
2613+}
2614+
2615+static int omapfb_probe(struct platform_device *pdev)
2616+{
2617+ struct omapfb2_device *fbdev = NULL;
2618+ int r = 0;
2619+ int i, t;
2620+ struct omap_overlay *ovl;
2621+ struct omap_display *def_display;
2622+
2623+ DBG("omapfb_probe\n");
2624+
2625+ if (pdev->num_resources != 0) {
2626+ dev_err(&pdev->dev, "probed for an unknown device\n");
2627+ r = -ENODEV;
2628+ goto err0;
2629+ }
2630+
2631+ fbdev = kzalloc(sizeof(struct omapfb2_device), GFP_KERNEL);
2632+ if (fbdev == NULL) {
2633+ r = -ENOMEM;
2634+ goto err0;
2635+ }
2636+
2637+ mutex_init(&fbdev->mtx);
2638+
2639+ fbdev->dev = &pdev->dev;
2640+ platform_set_drvdata(pdev, fbdev);
2641+
2642+ fbdev->num_displays = 0;
2643+ t = omap_dss_get_num_displays();
2644+ for (i = 0; i < t; i++) {
2645+ struct omap_display *display;
2646+ display = omap_dss_get_display(i);
2647+ if (!display) {
2648+ dev_err(&pdev->dev, "can't get display %d\n", i);
2649+ r = -EINVAL;
2650+ goto cleanup;
2651+ }
2652+
2653+ fbdev->displays[fbdev->num_displays++] = display;
2654+ }
2655+
2656+ if (fbdev->num_displays == 0) {
2657+ dev_err(&pdev->dev, "no displays\n");
2658+ r = -EINVAL;
2659+ goto cleanup;
2660+ }
2661+
2662+ fbdev->num_overlays = omap_dss_get_num_overlays();
2663+ for (i = 0; i < fbdev->num_overlays; i++)
2664+ fbdev->overlays[i] = omap_dss_get_overlay(i);
2665+
2666+ fbdev->num_managers = omap_dss_get_num_overlay_managers();
2667+ for (i = 0; i < fbdev->num_managers; i++)
2668+ fbdev->managers[i] = omap_dss_get_overlay_manager(i);
2669+
2670+
2671+ /* gfx overlay should be the default one. find a display
2672+ * connected to that, and use it as default display */
2673+ ovl = omap_dss_get_overlay(0);
2674+ if (ovl->manager && ovl->manager->display) {
2675+ def_display = ovl->manager->display;
2676+ } else {
2677+ dev_err(&pdev->dev, "cannot find default display\n");
2678+ r = -EINVAL;
2679+ goto cleanup;
2680+ }
2681+
2682+ if (def_mode && strlen(def_mode) > 0) {
2683+ if (omapfb_parse_def_modes(fbdev))
2684+ dev_err(&pdev->dev, "cannot parse default modes\n");
2685+ }
2686+
2687+ r = omapfb_create_framebuffers(fbdev);
2688+ if (r)
2689+ goto cleanup;
2690+
2691+ for (i = 0; i < fbdev->num_managers; i++) {
2692+ struct omap_overlay_manager *mgr;
2693+ mgr = fbdev->managers[i];
2694+ r = mgr->apply(mgr);
2695+ if (r) {
2696+ dev_err(fbdev->dev, "failed to apply dispc config\n");
2697+ goto cleanup;
2698+ }
2699+ }
2700+
2701+ DBG("mgr->apply'ed\n");
2702+
2703+ r = def_display->enable(def_display);
2704+ if (r) {
2705+ dev_err(fbdev->dev, "Failed to enable display '%s'\n",
2706+ def_display->name);
2707+ goto cleanup;
2708+ }
2709+
2710+ /* set the update mode */
2711+ if (def_display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
2712+#ifdef CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE
2713+ if (def_display->set_update_mode)
2714+ def_display->set_update_mode(def_display,
2715+ OMAP_DSS_UPDATE_AUTO);
2716+ if (def_display->enable_te)
2717+ def_display->enable_te(def_display, 1);
2718+#else
2719+ if (def_display->set_update_mode)
2720+ def_display->set_update_mode(def_display,
2721+ OMAP_DSS_UPDATE_MANUAL);
2722+ if (def_display->enable_te)
2723+ def_display->enable_te(def_display, 0);
2724+#endif
2725+ } else {
2726+ if (def_display->set_update_mode)
2727+ def_display->set_update_mode(def_display,
2728+ OMAP_DSS_UPDATE_AUTO);
2729+ }
2730+
2731+ for (i = 0; i < fbdev->num_displays; i++) {
2732+ struct omap_display *display = fbdev->displays[i];
2733+ u16 w, h;
2734+
2735+ if (!display->get_update_mode || !display->update)
2736+ continue;
2737+
2738+ if (display->get_update_mode(display) ==
2739+ OMAP_DSS_UPDATE_MANUAL) {
2740+
2741+ display->get_resolution(display, &w, &h);
2742+ display->update(display, 0, 0, w, h);
2743+ }
2744+ }
2745+
2746+ DBG("display->updated\n");
2747+
2748+ return 0;
2749+
2750+cleanup:
2751+ omapfb_free_resources(fbdev);
2752+err0:
2753+ dev_err(&pdev->dev, "failed to setup omapfb\n");
2754+ return r;
2755+}
2756+
2757+static int omapfb_remove(struct platform_device *pdev)
2758+{
2759+ struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
2760+
2761+ /* FIXME: wait till completion of pending events */
2762+
2763+ omapfb_remove_sysfs(fbdev);
2764+
2765+ omapfb_free_resources(fbdev);
2766+
2767+ return 0;
2768+}
2769+
2770+static struct platform_driver omapfb_driver = {
2771+ .probe = omapfb_probe,
2772+ .remove = omapfb_remove,
2773+ .driver = {
2774+ .name = "omapfb",
2775+ .owner = THIS_MODULE,
2776+ },
2777+};
2778+
2779+static int __init omapfb_init(void)
2780+{
2781+ DBG("omapfb_init\n");
2782+
2783+ if (platform_driver_register(&omapfb_driver)) {
2784+ printk(KERN_ERR "failed to register omapfb driver\n");
2785+ return -ENODEV;
2786+ }
2787+
2788+ return 0;
2789+}
2790+
2791+static void __exit omapfb_exit(void)
2792+{
2793+ DBG("omapfb_exit\n");
2794+ platform_driver_unregister(&omapfb_driver);
2795+}
2796+
2797+module_param_named(mode, def_mode, charp, 0);
2798+module_param_named(vram, def_vram, charp, 0);
2799+module_param_named(rotate, def_rotate, int, 0);
2800+module_param_named(vrfb, def_vrfb, bool, 0);
2801+module_param_named(mirror, def_mirror, bool, 0);
2802+
2803+/* late_initcall to let panel/ctrl drivers loaded first.
2804+ * I guess better option would be a more dynamic approach,
2805+ * so that omapfb reacts to new panels when they are loaded */
2806+late_initcall(omapfb_init);
2807+/*module_init(omapfb_init);*/
2808+module_exit(omapfb_exit);
2809+
2810+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
2811+MODULE_DESCRIPTION("OMAP2/3 Framebuffer");
2812+MODULE_LICENSE("GPL v2");
2813diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
2814new file mode 100644
2815index 0000000..2c88718
2816--- /dev/null
2817+++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
2818@@ -0,0 +1,371 @@
2819+/*
2820+ * linux/drivers/video/omap2/omapfb-sysfs.c
2821+ *
2822+ * Copyright (C) 2008 Nokia Corporation
2823+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2824+ *
2825+ * Some code and ideas taken from drivers/video/omap/ driver
2826+ * by Imre Deak.
2827+ *
2828+ * This program is free software; you can redistribute it and/or modify it
2829+ * under the terms of the GNU General Public License version 2 as published by
2830+ * the Free Software Foundation.
2831+ *
2832+ * This program is distributed in the hope that it will be useful, but WITHOUT
2833+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2834+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
2835+ * more details.
2836+ *
2837+ * You should have received a copy of the GNU General Public License along with
2838+ * this program. If not, see <http://www.gnu.org/licenses/>.
2839+ */
2840+
2841+#include <linux/fb.h>
2842+#include <linux/sysfs.h>
2843+#include <linux/device.h>
2844+#include <linux/uaccess.h>
2845+#include <linux/platform_device.h>
2846+#include <linux/kernel.h>
2847+#include <linux/mm.h>
2848+#include <linux/omapfb.h>
2849+
2850+#include <mach/display.h>
2851+#include <mach/vrfb.h>
2852+
2853+#include "omapfb.h"
2854+
2855+static ssize_t show_rotate_type(struct device *dev,
2856+ struct device_attribute *attr, char *buf)
2857+{
2858+ struct fb_info *fbi = dev_get_drvdata(dev);
2859+ struct omapfb_info *ofbi = FB2OFB(fbi);
2860+
2861+ return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->rotation_type);
2862+}
2863+
2864+static ssize_t show_mirror(struct device *dev,
2865+ struct device_attribute *attr, char *buf)
2866+{
2867+ struct fb_info *fbi = dev_get_drvdata(dev);
2868+ struct omapfb_info *ofbi = FB2OFB(fbi);
2869+
2870+ return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->mirror);
2871+}
2872+
2873+static ssize_t store_mirror(struct device *dev,
2874+ struct device_attribute *attr,
2875+ const char *buf, size_t count)
2876+{
2877+ struct fb_info *fbi = dev_get_drvdata(dev);
2878+ struct omapfb_info *ofbi = FB2OFB(fbi);
2879+ struct omapfb2_device *fbdev = ofbi->fbdev;
2880+ bool mirror;
2881+ int r;
2882+ struct fb_var_screeninfo new_var;
2883+
2884+ mirror = simple_strtoul(buf, NULL, 0);
2885+
2886+ if (mirror != 0 && mirror != 1)
2887+ return -EINVAL;
2888+
2889+ omapfb_lock(fbdev);
2890+
2891+ ofbi->mirror = mirror;
2892+
2893+ memcpy(&new_var, &fbi->var, sizeof(new_var));
2894+ r = check_fb_var(fbi, &new_var);
2895+ if (r)
2896+ goto out;
2897+ memcpy(&fbi->var, &new_var, sizeof(fbi->var));
2898+
2899+ set_fb_fix(fbi);
2900+
2901+ r = omapfb_apply_changes(fbi, 0);
2902+ if (r)
2903+ goto out;
2904+
2905+ r = count;
2906+out:
2907+ omapfb_unlock(fbdev);
2908+
2909+ return r;
2910+}
2911+
2912+static ssize_t show_overlays(struct device *dev,
2913+ struct device_attribute *attr, char *buf)
2914+{
2915+ struct fb_info *fbi = dev_get_drvdata(dev);
2916+ struct omapfb_info *ofbi = FB2OFB(fbi);
2917+ struct omapfb2_device *fbdev = ofbi->fbdev;
2918+ ssize_t l = 0;
2919+ int t;
2920+
2921+ for (t = 0; t < ofbi->num_overlays; t++) {
2922+ struct omap_overlay *ovl = ofbi->overlays[t];
2923+ int ovlnum;
2924+
2925+ for (ovlnum = 0; ovlnum < fbdev->num_overlays; ++ovlnum)
2926+ if (ovl == fbdev->overlays[ovlnum])
2927+ break;
2928+
2929+ l += snprintf(buf + l, PAGE_SIZE - l, "%s%d",
2930+ t == 0 ? "" : ",", ovlnum);
2931+ }
2932+
2933+ l += snprintf(buf + l, PAGE_SIZE - l, "\n");
2934+
2935+ return l;
2936+}
2937+
2938+static struct omapfb_info *get_overlay_fb(struct omapfb2_device *fbdev,
2939+ struct omap_overlay *ovl)
2940+{
2941+ int i, t;
2942+
2943+ for (i = 0; i < fbdev->num_fbs; i++) {
2944+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
2945+
2946+ for (t = 0; t < ofbi->num_overlays; t++) {
2947+ if (ofbi->overlays[t] == ovl)
2948+ return ofbi;
2949+ }
2950+ }
2951+
2952+ return NULL;
2953+}
2954+
2955+static ssize_t store_overlays(struct device *dev, struct device_attribute *attr,
2956+ const char *buf, size_t count)
2957+{
2958+ struct fb_info *fbi = dev_get_drvdata(dev);
2959+ struct omapfb_info *ofbi = FB2OFB(fbi);
2960+ struct omapfb2_device *fbdev = ofbi->fbdev;
2961+ struct omap_overlay *ovls[OMAPFB_MAX_OVL_PER_FB];
2962+ struct omap_overlay *ovl;
2963+ int num_ovls, r, i;
2964+ int len;
2965+
2966+ num_ovls = 0;
2967+
2968+ len = strlen(buf);
2969+ if (buf[len - 1] == '\n')
2970+ len = len - 1;
2971+
2972+ omapfb_lock(fbdev);
2973+
2974+ if (len > 0) {
2975+ char *p = (char *)buf;
2976+ int ovlnum;
2977+
2978+ while (p < buf + len) {
2979+ int found;
2980+ if (num_ovls == OMAPFB_MAX_OVL_PER_FB) {
2981+ r = -EINVAL;
2982+ goto out;
2983+ }
2984+
2985+ ovlnum = simple_strtoul(p, &p, 0);
2986+ if (ovlnum > fbdev->num_overlays) {
2987+ r = -EINVAL;
2988+ goto out;
2989+ }
2990+
2991+ found = 0;
2992+ for (i = 0; i < num_ovls; ++i) {
2993+ if (ovls[i] == fbdev->overlays[ovlnum]) {
2994+ found = 1;
2995+ break;
2996+ }
2997+ }
2998+
2999+ if (!found)
3000+ ovls[num_ovls++] = fbdev->overlays[ovlnum];
3001+
3002+ p++;
3003+ }
3004+ }
3005+
3006+ for (i = 0; i < num_ovls; ++i) {
3007+ struct omapfb_info *ofbi2 = get_overlay_fb(fbdev, ovls[i]);
3008+ if (ofbi2 && ofbi2 != ofbi) {
3009+ dev_err(fbdev->dev, "overlay already in use\n");
3010+ r = -EINVAL;
3011+ goto out;
3012+ }
3013+ }
3014+
3015+ /* detach unused overlays */
3016+ for (i = 0; i < ofbi->num_overlays; ++i) {
3017+ int t, found;
3018+
3019+ ovl = ofbi->overlays[i];
3020+
3021+ found = 0;
3022+
3023+ for (t = 0; t < num_ovls; ++t) {
3024+ if (ovl == ovls[t]) {
3025+ found = 1;
3026+ break;
3027+ }
3028+ }
3029+
3030+ if (found)
3031+ continue;
3032+
3033+ DBG("detaching %d\n", ofbi->overlays[i]->id);
3034+
3035+ omapfb_overlay_enable(ovl, 0);
3036+
3037+ if (ovl->manager)
3038+ ovl->manager->apply(ovl->manager);
3039+
3040+ for (t = i + 1; t < ofbi->num_overlays; t++)
3041+ ofbi->overlays[t-1] = ofbi->overlays[t];
3042+
3043+ ofbi->num_overlays--;
3044+ i--;
3045+ }
3046+
3047+ for (i = 0; i < num_ovls; ++i) {
3048+ int t, found;
3049+
3050+ ovl = ovls[i];
3051+
3052+ found = 0;
3053+
3054+ for (t = 0; t < ofbi->num_overlays; ++t) {
3055+ if (ovl == ofbi->overlays[t]) {
3056+ found = 1;
3057+ break;
3058+ }
3059+ }
3060+
3061+ if (found)
3062+ continue;
3063+
3064+ ofbi->overlays[ofbi->num_overlays++] = ovl;
3065+
3066+ r = omapfb_apply_changes(fbi, 1);
3067+ if (r)
3068+ goto out;
3069+
3070+ if (ovl->manager) {
3071+ r = ovl->manager->apply(ovl->manager);
3072+ if (r)
3073+ goto out;
3074+ }
3075+ }
3076+
3077+ r = count;
3078+out:
3079+ omapfb_unlock(fbdev);
3080+
3081+ return r;
3082+}
3083+
3084+static ssize_t show_size(struct device *dev,
3085+ struct device_attribute *attr, char *buf)
3086+{
3087+ struct fb_info *fbi = dev_get_drvdata(dev);
3088+ struct omapfb_info *ofbi = FB2OFB(fbi);
3089+
3090+ return snprintf(buf, PAGE_SIZE, "%lu\n", ofbi->region.size);
3091+}
3092+
3093+static ssize_t store_size(struct device *dev, struct device_attribute *attr,
3094+ const char *buf, size_t count)
3095+{
3096+ struct fb_info *fbi = dev_get_drvdata(dev);
3097+ struct omapfb_info *ofbi = FB2OFB(fbi);
3098+ struct omapfb2_device *fbdev = ofbi->fbdev;
3099+ unsigned long size;
3100+ int r;
3101+ int i;
3102+
3103+ size = PAGE_ALIGN(simple_strtoul(buf, NULL, 0));
3104+
3105+ omapfb_lock(fbdev);
3106+
3107+ for (i = 0; i < ofbi->num_overlays; i++) {
3108+ if (ofbi->overlays[i]->info.enabled) {
3109+ r = -EBUSY;
3110+ goto out;
3111+ }
3112+ }
3113+
3114+ if (size != ofbi->region.size) {
3115+ r = omapfb_realloc_fbmem(fbi, size, ofbi->region.type);
3116+ if (r) {
3117+ dev_err(dev, "realloc fbmem failed\n");
3118+ goto out;
3119+ }
3120+ }
3121+
3122+ r = count;
3123+out:
3124+ omapfb_unlock(fbdev);
3125+
3126+ return r;
3127+}
3128+
3129+static ssize_t show_phys(struct device *dev,
3130+ struct device_attribute *attr, char *buf)
3131+{
3132+ struct fb_info *fbi = dev_get_drvdata(dev);
3133+ struct omapfb_info *ofbi = FB2OFB(fbi);
3134+
3135+ return snprintf(buf, PAGE_SIZE, "%0x\n", ofbi->region.paddr);
3136+}
3137+
3138+static ssize_t show_virt(struct device *dev,
3139+ struct device_attribute *attr, char *buf)
3140+{
3141+ struct fb_info *fbi = dev_get_drvdata(dev);
3142+ struct omapfb_info *ofbi = FB2OFB(fbi);
3143+
3144+ return snprintf(buf, PAGE_SIZE, "%p\n", ofbi->region.vaddr);
3145+}
3146+
3147+static struct device_attribute omapfb_attrs[] = {
3148+ __ATTR(rotate_type, S_IRUGO, show_rotate_type, NULL),
3149+ __ATTR(mirror, S_IRUGO | S_IWUSR, show_mirror, store_mirror),
3150+ __ATTR(size, S_IRUGO | S_IWUSR, show_size, store_size),
3151+ __ATTR(overlays, S_IRUGO | S_IWUSR, show_overlays, store_overlays),
3152+ __ATTR(phys_addr, S_IRUGO, show_phys, NULL),
3153+ __ATTR(virt_addr, S_IRUGO, show_virt, NULL),
3154+};
3155+
3156+int omapfb_create_sysfs(struct omapfb2_device *fbdev)
3157+{
3158+ int i;
3159+ int r;
3160+
3161+ DBG("create sysfs for fbs\n");
3162+ for (i = 0; i < fbdev->num_fbs; i++) {
3163+ int t;
3164+ for (t = 0; t < ARRAY_SIZE(omapfb_attrs); t++) {
3165+ r = device_create_file(fbdev->fbs[i]->dev,
3166+ &omapfb_attrs[t]);
3167+
3168+ if (r) {
3169+ dev_err(fbdev->dev, "failed to create sysfs file\n");
3170+ return r;
3171+ }
3172+ }
3173+ }
3174+
3175+ return 0;
3176+}
3177+
3178+void omapfb_remove_sysfs(struct omapfb2_device *fbdev)
3179+{
3180+ int i, t;
3181+
3182+ DBG("remove sysfs for fbs\n");
3183+ for (i = 0; i < fbdev->num_fbs; i++) {
3184+ for (t = 0; t < ARRAY_SIZE(omapfb_attrs); t++)
3185+ device_remove_file(fbdev->fbs[i]->dev,
3186+ &omapfb_attrs[t]);
3187+ }
3188+}
3189+
3190diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h
3191new file mode 100644
3192index 0000000..65e9e6e
3193--- /dev/null
3194+++ b/drivers/video/omap2/omapfb/omapfb.h
3195@@ -0,0 +1,153 @@
3196+/*
3197+ * linux/drivers/video/omap2/omapfb.h
3198+ *
3199+ * Copyright (C) 2008 Nokia Corporation
3200+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3201+ *
3202+ * Some code and ideas taken from drivers/video/omap/ driver
3203+ * by Imre Deak.
3204+ *
3205+ * This program is free software; you can redistribute it and/or modify it
3206+ * under the terms of the GNU General Public License version 2 as published by
3207+ * the Free Software Foundation.
3208+ *
3209+ * This program is distributed in the hope that it will be useful, but WITHOUT
3210+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3211+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3212+ * more details.
3213+ *
3214+ * You should have received a copy of the GNU General Public License along with
3215+ * this program. If not, see <http://www.gnu.org/licenses/>.
3216+ */
3217+
3218+#ifndef __DRIVERS_VIDEO_OMAP2_OMAPFB_H__
3219+#define __DRIVERS_VIDEO_OMAP2_OMAPFB_H__
3220+
3221+#ifdef CONFIG_FB_OMAP2_DEBUG_SUPPORT
3222+#define DEBUG
3223+#endif
3224+
3225+#ifdef DEBUG
3226+extern unsigned int omapfb_debug;
3227+#define DBG(format, ...) \
3228+ if (omapfb_debug) \
3229+ printk(KERN_DEBUG "OMAPFB: " format, ## __VA_ARGS__)
3230+#else
3231+#define DBG(format, ...)
3232+#endif
3233+
3234+#define FB2OFB(fb_info) ((struct omapfb_info *)(fb_info->par))
3235+
3236+/* max number of overlays to which a framebuffer data can be direct */
3237+#define OMAPFB_MAX_OVL_PER_FB 3
3238+
3239+struct omapfb2_mem_region {
3240+ u32 paddr;
3241+ void __iomem *vaddr;
3242+ struct vrfb vrfb;
3243+ unsigned long size;
3244+ u8 type; /* OMAPFB_PLANE_MEM_* */
3245+ bool alloc; /* allocated by the driver */
3246+ bool map; /* kernel mapped by the driver */
3247+};
3248+
3249+enum omapfb_rotation_type {
3250+ OMAPFB_ROT_DMA = 0,
3251+ OMAPFB_ROT_VRFB = 1,
3252+};
3253+
3254+/* appended to fb_info */
3255+struct omapfb_info {
3256+ int id;
3257+ struct omapfb2_mem_region region;
3258+ atomic_t map_count;
3259+ int num_overlays;
3260+ struct omap_overlay *overlays[OMAPFB_MAX_OVL_PER_FB];
3261+ struct omapfb2_device *fbdev;
3262+ enum omapfb_rotation_type rotation_type;
3263+ u8 rotation;
3264+ bool mirror;
3265+};
3266+
3267+struct omapfb2_device {
3268+ struct device *dev;
3269+ struct mutex mtx;
3270+
3271+ u32 pseudo_palette[17];
3272+
3273+ int state;
3274+
3275+ unsigned num_fbs;
3276+ struct fb_info *fbs[10];
3277+
3278+ unsigned num_displays;
3279+ struct omap_display *displays[10];
3280+ unsigned num_overlays;
3281+ struct omap_overlay *overlays[10];
3282+ unsigned num_managers;
3283+ struct omap_overlay_manager *managers[10];
3284+};
3285+
3286+struct omapfb_colormode {
3287+ enum omap_color_mode dssmode;
3288+ u32 bits_per_pixel;
3289+ u32 nonstd;
3290+ struct fb_bitfield red;
3291+ struct fb_bitfield green;
3292+ struct fb_bitfield blue;
3293+ struct fb_bitfield transp;
3294+};
3295+
3296+u32 omapfb_get_region_paddr(struct omapfb_info *ofbi);
3297+void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi);
3298+
3299+void set_fb_fix(struct fb_info *fbi);
3300+int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var);
3301+int omapfb_realloc_fbmem(struct fb_info *fbi, unsigned long size, int type);
3302+int omapfb_apply_changes(struct fb_info *fbi, int init);
3303+int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi);
3304+
3305+int omapfb_create_sysfs(struct omapfb2_device *fbdev);
3306+void omapfb_remove_sysfs(struct omapfb2_device *fbdev);
3307+
3308+int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg);
3309+
3310+int omapfb_mode_to_timings(const char *mode_str,
3311+ struct omap_video_timings *timings, u8 *bpp);
3312+
3313+/* find the display connected to this fb, if any */
3314+static inline struct omap_display *fb2display(struct fb_info *fbi)
3315+{
3316+ struct omapfb_info *ofbi = FB2OFB(fbi);
3317+ int i;
3318+
3319+ /* XXX: returns the display connected to first attached overlay */
3320+ for (i = 0; i < ofbi->num_overlays; i++) {
3321+ if (ofbi->overlays[i]->manager)
3322+ return ofbi->overlays[i]->manager->display;
3323+ }
3324+
3325+ return NULL;
3326+}
3327+
3328+static inline void omapfb_lock(struct omapfb2_device *fbdev)
3329+{
3330+ mutex_lock(&fbdev->mtx);
3331+}
3332+
3333+static inline void omapfb_unlock(struct omapfb2_device *fbdev)
3334+{
3335+ mutex_unlock(&fbdev->mtx);
3336+}
3337+
3338+static inline int omapfb_overlay_enable(struct omap_overlay *ovl,
3339+ int enable)
3340+{
3341+ struct omap_overlay_info info;
3342+
3343+ ovl->get_overlay_info(ovl, &info);
3344+ info.enabled = enable;
3345+ return ovl->set_overlay_info(ovl, &info);
3346+}
3347+
3348+#endif
3349diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
3350index b226bdf..96190b2 100644
3351--- a/include/linux/omapfb.h
3352+++ b/include/linux/omapfb.h
3353@@ -50,6 +50,8 @@
3354 #define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window)
3355 #define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info)
3356 #define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info)
3357+#define OMAPFB_WAITFORVSYNC OMAP_IO(57)
3358+#define OMAPFB_MEMORY_READ OMAP_IOR(58, struct omapfb_memory_read)
3359
3360 #define OMAPFB_CAPS_GENERIC_MASK 0x00000fff
3361 #define OMAPFB_CAPS_LCDC_MASK 0x00fff000
3362@@ -90,6 +92,13 @@ enum omapfb_color_format {
3363 OMAPFB_COLOR_CLUT_1BPP,
3364 OMAPFB_COLOR_RGB444,
3365 OMAPFB_COLOR_YUY422,
3366+
3367+ OMAPFB_COLOR_ARGB16,
3368+ OMAPFB_COLOR_RGB24U, /* RGB24, 32-bit container */
3369+ OMAPFB_COLOR_RGB24P, /* RGB24, 24-bit container */
3370+ OMAPFB_COLOR_ARGB32,
3371+ OMAPFB_COLOR_RGBA32,
3372+ OMAPFB_COLOR_RGBX32,
3373 };
3374
3375 struct omapfb_update_window {
3376@@ -161,6 +170,15 @@ enum omapfb_update_mode {
3377 OMAPFB_MANUAL_UPDATE
3378 };
3379
3380+struct omapfb_memory_read {
3381+ __u16 x;
3382+ __u16 y;
3383+ __u16 w;
3384+ __u16 h;
3385+ size_t buffer_size;
3386+ void __user *buffer;
3387+};
3388+
3389 #ifdef __KERNEL__
3390
3391 #include <linux/completion.h>
3392@@ -376,6 +394,8 @@ extern struct lcd_ctrl omap1_lcd_ctrl;
3393 extern struct lcd_ctrl omap2_disp_ctrl;
3394 #endif
3395
3396+extern void omapfb_set_platform_data(struct omapfb_platform_data *data);
3397+
3398 extern void omapfb_reserve_sdram(void);
3399 extern void omapfb_register_panel(struct lcd_panel *panel);
3400 extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
3401--
34021.5.6.5
3403
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0005-DSS2-Add-panel-drivers.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0005-DSS2-Add-panel-drivers.patch
new file mode 100644
index 0000000000..d12586ca2f
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0005-DSS2-Add-panel-drivers.patch
@@ -0,0 +1,396 @@
1From 4cc0368574f587f448231ccd121266bed4bf9729 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 2 Apr 2009 10:29:56 +0300
4Subject: [PATCH] DSS2: Add panel drivers
5
6- Generic panel
7- Samsung LTE430WQ-F0C LCD Panel
8- Sharp LS037V7DW01 LCD Panel
9
10Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
11---
12 drivers/video/omap2/displays/Kconfig | 21 ++++
13 drivers/video/omap2/displays/Makefile | 3 +
14 drivers/video/omap2/displays/panel-generic.c | 96 +++++++++++++++++
15 .../omap2/displays/panel-samsung-lte430wq-f0c.c | 108 +++++++++++++++++++
16 .../video/omap2/displays/panel-sharp-ls037v7dw01.c | 112 ++++++++++++++++++++
17 5 files changed, 340 insertions(+), 0 deletions(-)
18 create mode 100644 drivers/video/omap2/displays/Kconfig
19 create mode 100644 drivers/video/omap2/displays/Makefile
20 create mode 100644 drivers/video/omap2/displays/panel-generic.c
21 create mode 100644 drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
22 create mode 100644 drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
23
24diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
25new file mode 100644
26index 0000000..0419ec8
27--- /dev/null
28+++ b/drivers/video/omap2/displays/Kconfig
29@@ -0,0 +1,21 @@
30+menu "OMAP2/3 Display Device Drivers"
31+ depends on OMAP2_DSS
32+
33+config PANEL_GENERIC
34+ tristate "Generic Panel"
35+ help
36+ Generic panel driver.
37+ Used for DVI output for Beagle and OMAP3 SDP.
38+
39+config PANEL_SAMSUNG_LTE430WQ_F0C
40+ tristate "Samsung LTE430WQ-F0C LCD Panel"
41+ depends on OMAP2_DSS
42+ help
43+ LCD Panel used on Overo Palo43
44+
45+config PANEL_SHARP_LS037V7DW01
46+ tristate "Sharp LS037V7DW01 LCD Panel"
47+ depends on OMAP2_DSS
48+ help
49+ LCD Panel used in TI's SDP3430 and EVM boards
50+endmenu
51diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
52new file mode 100644
53index 0000000..a26bbd2
54--- /dev/null
55+++ b/drivers/video/omap2/displays/Makefile
56@@ -0,0 +1,3 @@
57+obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o
58+obj-$(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) += panel-samsung-lte430wq-f0c.o
59+obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
60diff --git a/drivers/video/omap2/displays/panel-generic.c b/drivers/video/omap2/displays/panel-generic.c
61new file mode 100644
62index 0000000..8382acb
63--- /dev/null
64+++ b/drivers/video/omap2/displays/panel-generic.c
65@@ -0,0 +1,96 @@
66+/*
67+ * Generic panel support
68+ *
69+ * Copyright (C) 2008 Nokia Corporation
70+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
71+ *
72+ * This program is free software; you can redistribute it and/or modify it
73+ * under the terms of the GNU General Public License version 2 as published by
74+ * the Free Software Foundation.
75+ *
76+ * This program is distributed in the hope that it will be useful, but WITHOUT
77+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
78+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
79+ * more details.
80+ *
81+ * You should have received a copy of the GNU General Public License along with
82+ * this program. If not, see <http://www.gnu.org/licenses/>.
83+ */
84+
85+#include <linux/module.h>
86+#include <linux/delay.h>
87+
88+#include <mach/display.h>
89+
90+static int generic_panel_init(struct omap_display *display)
91+{
92+ return 0;
93+}
94+
95+static int generic_panel_enable(struct omap_display *display)
96+{
97+ int r = 0;
98+
99+ if (display->hw_config.panel_enable)
100+ r = display->hw_config.panel_enable(display);
101+
102+ return r;
103+}
104+
105+static void generic_panel_disable(struct omap_display *display)
106+{
107+ if (display->hw_config.panel_disable)
108+ display->hw_config.panel_disable(display);
109+}
110+
111+static int generic_panel_suspend(struct omap_display *display)
112+{
113+ generic_panel_disable(display);
114+ return 0;
115+}
116+
117+static int generic_panel_resume(struct omap_display *display)
118+{
119+ return generic_panel_enable(display);
120+}
121+
122+static struct omap_panel generic_panel = {
123+ .owner = THIS_MODULE,
124+ .name = "panel-generic",
125+ .init = generic_panel_init,
126+ .enable = generic_panel_enable,
127+ .disable = generic_panel_disable,
128+ .suspend = generic_panel_suspend,
129+ .resume = generic_panel_resume,
130+
131+ .timings = {
132+ /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */
133+ .x_res = 640,
134+ .y_res = 480,
135+ .pixel_clock = 23500,
136+ .hfp = 48,
137+ .hsw = 32,
138+ .hbp = 80,
139+ .vfp = 3,
140+ .vsw = 4,
141+ .vbp = 7,
142+ },
143+
144+ .config = OMAP_DSS_LCD_TFT,
145+};
146+
147+
148+static int __init generic_panel_drv_init(void)
149+{
150+ omap_dss_register_panel(&generic_panel);
151+ return 0;
152+}
153+
154+static void __exit generic_panel_drv_exit(void)
155+{
156+ omap_dss_unregister_panel(&generic_panel);
157+}
158+
159+module_init(generic_panel_drv_init);
160+module_exit(generic_panel_drv_exit);
161+MODULE_LICENSE("GPL");
162diff --git a/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
163new file mode 100644
164index 0000000..e4bb781
165--- /dev/null
166+++ b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
167@@ -0,0 +1,108 @@
168+/*
169+ * LCD panel driver for Samsung LTE430WQ-F0C
170+ *
171+ * Author: Steve Sakoman <steve@sakoman.com>
172+ *
173+ * This program is free software; you can redistribute it and/or modify it
174+ * under the terms of the GNU General Public License version 2 as published by
175+ * the Free Software Foundation.
176+ *
177+ * This program is distributed in the hope that it will be useful, but WITHOUT
178+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
179+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
180+ * more details.
181+ *
182+ * You should have received a copy of the GNU General Public License along with
183+ * this program. If not, see <http://www.gnu.org/licenses/>.
184+ */
185+
186+#include <linux/module.h>
187+#include <linux/delay.h>
188+
189+#include <mach/display.h>
190+
191+static int samsung_lte_panel_init(struct omap_display *display)
192+{
193+ return 0;
194+}
195+
196+static void samsung_lte_panel_cleanup(struct omap_display *display)
197+{
198+}
199+
200+static int samsung_lte_panel_enable(struct omap_display *display)
201+{
202+ int r = 0;
203+
204+ /* wait couple of vsyncs until enabling the LCD */
205+ msleep(50);
206+
207+ if (display->hw_config.panel_enable)
208+ r = display->hw_config.panel_enable(display);
209+
210+ return r;
211+}
212+
213+static void samsung_lte_panel_disable(struct omap_display *display)
214+{
215+ if (display->hw_config.panel_disable)
216+ display->hw_config.panel_disable(display);
217+
218+ /* wait at least 5 vsyncs after disabling the LCD */
219+ msleep(100);
220+}
221+
222+static int samsung_lte_panel_suspend(struct omap_display *display)
223+{
224+ samsung_lte_panel_disable(display);
225+ return 0;
226+}
227+
228+static int samsung_lte_panel_resume(struct omap_display *display)
229+{
230+ return samsung_lte_panel_enable(display);
231+}
232+
233+static struct omap_panel samsung_lte_panel = {
234+ .owner = THIS_MODULE,
235+ .name = "samsung-lte430wq-f0c",
236+ .init = samsung_lte_panel_init,
237+ .cleanup = samsung_lte_panel_cleanup,
238+ .enable = samsung_lte_panel_enable,
239+ .disable = samsung_lte_panel_disable,
240+ .suspend = samsung_lte_panel_suspend,
241+ .resume = samsung_lte_panel_resume,
242+
243+ .timings = {
244+ .x_res = 480,
245+ .y_res = 272,
246+
247+ .pixel_clock = 9200,
248+
249+ .hsw = 41,
250+ .hfp = 8,
251+ .hbp = 45-41,
252+
253+ .vsw = 10,
254+ .vfp = 4,
255+ .vbp = 12-10,
256+ },
257+ .recommended_bpp = 16,
258+ .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IVS,
259+};
260+
261+
262+static int __init samsung_lte_panel_drv_init(void)
263+{
264+ omap_dss_register_panel(&samsung_lte_panel);
265+ return 0;
266+}
267+
268+static void __exit samsung_lte_panel_drv_exit(void)
269+{
270+ omap_dss_unregister_panel(&samsung_lte_panel);
271+}
272+
273+module_init(samsung_lte_panel_drv_init);
274+module_exit(samsung_lte_panel_drv_exit);
275+MODULE_LICENSE("GPL");
276diff --git a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
277new file mode 100644
278index 0000000..1f99150
279--- /dev/null
280+++ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
281@@ -0,0 +1,112 @@
282+/*
283+ * LCD panel driver for Sharp LS037V7DW01
284+ *
285+ * Copyright (C) 2008 Nokia Corporation
286+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
287+ *
288+ * This program is free software; you can redistribute it and/or modify it
289+ * under the terms of the GNU General Public License version 2 as published by
290+ * the Free Software Foundation.
291+ *
292+ * This program is distributed in the hope that it will be useful, but WITHOUT
293+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
294+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
295+ * more details.
296+ *
297+ * You should have received a copy of the GNU General Public License along with
298+ * this program. If not, see <http://www.gnu.org/licenses/>.
299+ */
300+
301+#include <linux/module.h>
302+#include <linux/delay.h>
303+
304+#include <mach/display.h>
305+
306+static int sharp_ls_panel_init(struct omap_display *display)
307+{
308+ return 0;
309+}
310+
311+static void sharp_ls_panel_cleanup(struct omap_display *display)
312+{
313+}
314+
315+static int sharp_ls_panel_enable(struct omap_display *display)
316+{
317+ int r = 0;
318+
319+ /* wait couple of vsyncs until enabling the LCD */
320+ msleep(50);
321+
322+ if (display->hw_config.panel_enable)
323+ r = display->hw_config.panel_enable(display);
324+
325+ return r;
326+}
327+
328+static void sharp_ls_panel_disable(struct omap_display *display)
329+{
330+ if (display->hw_config.panel_disable)
331+ display->hw_config.panel_disable(display);
332+
333+ /* wait at least 5 vsyncs after disabling the LCD */
334+
335+ msleep(100);
336+}
337+
338+static int sharp_ls_panel_suspend(struct omap_display *display)
339+{
340+ sharp_ls_panel_disable(display);
341+ return 0;
342+}
343+
344+static int sharp_ls_panel_resume(struct omap_display *display)
345+{
346+ return sharp_ls_panel_enable(display);
347+}
348+
349+static struct omap_panel sharp_ls_panel = {
350+ .owner = THIS_MODULE,
351+ .name = "sharp-ls037v7dw01",
352+ .init = sharp_ls_panel_init,
353+ .cleanup = sharp_ls_panel_cleanup,
354+ .enable = sharp_ls_panel_enable,
355+ .disable = sharp_ls_panel_disable,
356+ .suspend = sharp_ls_panel_suspend,
357+ .resume = sharp_ls_panel_resume,
358+
359+ .timings = {
360+ .x_res = 480,
361+ .y_res = 640,
362+
363+ .pixel_clock = 19200,
364+
365+ .hsw = 2,
366+ .hfp = 1,
367+ .hbp = 28,
368+
369+ .vsw = 1,
370+ .vfp = 1,
371+ .vbp = 1,
372+ },
373+
374+ .acb = 0x28,
375+
376+ .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS,
377+};
378+
379+
380+static int __init sharp_ls_panel_drv_init(void)
381+{
382+ omap_dss_register_panel(&sharp_ls_panel);
383+ return 0;
384+}
385+
386+static void __exit sharp_ls_panel_drv_exit(void)
387+{
388+ omap_dss_unregister_panel(&sharp_ls_panel);
389+}
390+
391+module_init(sharp_ls_panel_drv_init);
392+module_exit(sharp_ls_panel_drv_exit);
393+MODULE_LICENSE("GPL");
394--
3951.5.6.5
396
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0006-DSS2-HACK-Add-DSS2-support-for-N800.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0006-DSS2-HACK-Add-DSS2-support-for-N800.patch
new file mode 100644
index 0000000000..0025f1aa8b
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0006-DSS2-HACK-Add-DSS2-support-for-N800.patch
@@ -0,0 +1,1079 @@
1From 18a25382e81c03230e022ca2eb7e0fce24479d6a Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 2 Apr 2009 10:31:57 +0300
4Subject: [PATCH] DSS2: HACK: Add DSS2 support for N800
5
6Works, but it an ugly quick hack.
7
8Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
9---
10 arch/arm/mach-omap2/board-n800.c | 216 +++++++++++---
11 drivers/video/omap2/displays/Kconfig | 10 +
12 drivers/video/omap2/displays/Makefile | 3 +
13 drivers/video/omap2/displays/ctrl-blizzard.c | 279 +++++++++++++++++
14 drivers/video/omap2/displays/panel-n800.c | 435 ++++++++++++++++++++++++++
15 5 files changed, 905 insertions(+), 38 deletions(-)
16 create mode 100644 drivers/video/omap2/displays/ctrl-blizzard.c
17 create mode 100644 drivers/video/omap2/displays/panel-n800.c
18
19diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c
20index f6f6571..6de60ae 100644
21--- a/arch/arm/mach-omap2/board-n800.c
22+++ b/arch/arm/mach-omap2/board-n800.c
23@@ -41,6 +41,8 @@
24 #include <mach/clock.h>
25 #include <mach/gpio-switch.h>
26 #include <mach/blizzard.h>
27+#include <mach/display.h>
28+#include <mach/vram.h>
29
30 #include <../drivers/cbus/tahvo.h>
31 #include <../drivers/media/video/tcm825x.h>
32@@ -161,23 +163,176 @@ static struct omap_uart_config n800_uart_config __initdata = {
33
34 #include "../../../drivers/cbus/retu.h"
35
36-static struct omap_fbmem_config n800_fbmem0_config __initdata = {
37- .size = 752 * 1024,
38+static struct omap_tmp105_config n800_tmp105_config __initdata = {
39+ .tmp105_irq_pin = 125,
40+ .set_power = n800_tmp105_set_power,
41 };
42
43-static struct omap_fbmem_config n800_fbmem1_config __initdata = {
44- .size = 752 * 1024,
45-};
46
47-static struct omap_fbmem_config n800_fbmem2_config __initdata = {
48- .size = 752 * 1024,
49+
50+
51+/* DISPLAY */
52+static struct {
53+ struct clk *sys_ck;
54+} blizzard;
55+
56+static int blizzard_get_clocks(void)
57+{
58+ blizzard.sys_ck = clk_get(0, "osc_ck");
59+ if (IS_ERR(blizzard.sys_ck)) {
60+ printk(KERN_ERR "can't get Blizzard clock\n");
61+ return PTR_ERR(blizzard.sys_ck);
62+ }
63+ return 0;
64+}
65+
66+static unsigned long blizzard_get_clock_rate(void)
67+{
68+ return clk_get_rate(blizzard.sys_ck);
69+}
70+
71+static int n800_pn800_enable(struct omap_display *display)
72+{
73+ if (display->hw_config.panel_reset_gpio != -1) {
74+ printk("enabling panel gpio\n");
75+ gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
76+ }
77+
78+ return 0;
79+}
80+
81+static void n800_pn800_disable(struct omap_display *display)
82+{
83+ if (display->hw_config.panel_reset_gpio != -1) {
84+ printk("disabling panel gpio\n");
85+ gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
86+ msleep(120);
87+ }
88+}
89+
90+static int n800_blizzard_enable(struct omap_display *display)
91+{
92+ printk("enabling bliz powers\n");
93+
94+ /* Vcore to 1.475V */
95+ tahvo_set_clear_reg_bits(0x07, 0, 0xf);
96+ msleep(10);
97+
98+ clk_enable(blizzard.sys_ck);
99+
100+ if (display->hw_config.ctrl_reset_gpio != -1)
101+ gpio_direction_output(display->hw_config.ctrl_reset_gpio, 1);
102+
103+ printk("osc_ck %lu\n", blizzard_get_clock_rate());
104+
105+ return 0;
106+}
107+
108+static void n800_blizzard_disable(struct omap_display *display)
109+{
110+ printk("disabling bliz powers\n");
111+
112+ if (display->hw_config.ctrl_reset_gpio != -1)
113+ gpio_direction_output(display->hw_config.ctrl_reset_gpio, 0);
114+
115+ clk_disable(blizzard.sys_ck);
116+
117+ /* Vcore to 1.005V */
118+ tahvo_set_clear_reg_bits(0x07, 0xf, 0);
119+}
120+
121+static int n800_set_backlight_level(struct omap_display *display, int level)
122+{
123+ return 0;
124+}
125+
126+static struct omap_dss_display_config n800_dsi_display_data = {
127+ .type = OMAP_DISPLAY_TYPE_DBI,
128+ .name = "lcd",
129+ .ctrl_name = "ctrl-blizzard",
130+ .panel_name = "panel-pn800",
131+ .panel_reset_gpio = -1,
132+ .ctrl_reset_gpio = N800_BLIZZARD_POWERDOWN_GPIO,
133+ .panel_enable = n800_pn800_enable,
134+ .panel_disable = n800_pn800_disable,
135+ .ctrl_enable = n800_blizzard_enable,
136+ .ctrl_disable = n800_blizzard_disable,
137+ .set_backlight = n800_set_backlight_level,
138+ .u.rfbi = {
139+ .channel = 0,
140+ /* 8 for cmd mode, 16 for pixel data. ctrl-blizzard handles switching */
141+ .data_lines = 8,
142+ },
143+ .panel_data = 0, // XXX used for panel datalines
144+};
145+static struct omap_dss_board_info n800_dss_data = {
146+ .num_displays = 1,
147+ .displays = {
148+ &n800_dsi_display_data,
149+ },
150 };
151
152-static struct omap_tmp105_config n800_tmp105_config __initdata = {
153- .tmp105_irq_pin = 125,
154- .set_power = n800_tmp105_set_power,
155+static struct platform_device n800_dss_device = {
156+ .name = "omapdss",
157+ .id = -1,
158+ .dev = {
159+ .platform_data = &n800_dss_data,
160+ },
161 };
162
163+static void __init n800_display_init(void)
164+{
165+ int r;
166+ const struct omap_lcd_config *conf;
167+
168+ conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
169+ if (conf != NULL) {
170+ n800_dsi_display_data.panel_reset_gpio = conf->nreset_gpio;
171+ n800_dsi_display_data.panel_data =
172+ (void*)(u32)conf->data_lines; // XXX
173+ //printk("\n\nTULI %d\n\n", conf->data_lines);
174+ } else {
175+ printk("\n\nEI TULLU MIOTÄÄÄ\n\n");
176+ }
177+
178+ blizzard_get_clocks();
179+ clk_enable(blizzard.sys_ck); // XXX always enable
180+
181+ //omapfb_set_ctrl_platform_data(&n800_blizzard_data);
182+ //
183+ if (n800_dsi_display_data.ctrl_reset_gpio != -1) {
184+ r = gpio_request(n800_dsi_display_data.ctrl_reset_gpio,
185+ "Blizzard pd");
186+ if (r < 0) {
187+ n800_dsi_display_data.ctrl_reset_gpio = -1;
188+ printk(KERN_ERR "Unable to get Blizzard GPIO\n");
189+ } else {
190+ gpio_direction_output(n800_dsi_display_data.ctrl_reset_gpio,
191+ 1);
192+ // XXX always enable
193+ }
194+ }
195+
196+ if (n800_dsi_display_data.panel_reset_gpio != -1) {
197+ r = gpio_request(n800_dsi_display_data.panel_reset_gpio,
198+ "panel reset");
199+ if (r < 0) {
200+ n800_dsi_display_data.panel_reset_gpio = -1;
201+ printk(KERN_ERR "Unable to get pn800 GPIO\n");
202+ } else {
203+ gpio_direction_output(n800_dsi_display_data.panel_reset_gpio,
204+ 1);
205+ // XXX always enable
206+ }
207+ }
208+}
209+
210+/* DISPLAY END */
211+
212+
213+
214+
215+
216 static void mipid_shutdown(struct mipid_platform_data *pdata)
217 {
218 if (pdata->nreset_gpio != -1) {
219@@ -191,6 +346,7 @@ static struct mipid_platform_data n800_mipid_platform_data = {
220 .shutdown = mipid_shutdown,
221 };
222
223+#if 0
224 static void __init mipid_dev_init(void)
225 {
226 const struct omap_lcd_config *conf;
227@@ -201,26 +357,9 @@ static void __init mipid_dev_init(void)
228 n800_mipid_platform_data.data_lines = conf->data_lines;
229 }
230 }
231+#endif
232
233-static struct {
234- struct clk *sys_ck;
235-} blizzard;
236-
237-static int blizzard_get_clocks(void)
238-{
239- blizzard.sys_ck = clk_get(0, "osc_ck");
240- if (IS_ERR(blizzard.sys_ck)) {
241- printk(KERN_ERR "can't get Blizzard clock\n");
242- return PTR_ERR(blizzard.sys_ck);
243- }
244- return 0;
245-}
246-
247-static unsigned long blizzard_get_clock_rate(struct device *dev)
248-{
249- return clk_get_rate(blizzard.sys_ck);
250-}
251-
252+#if 0
253 static void blizzard_enable_clocks(int enable)
254 {
255 if (enable)
256@@ -265,14 +404,12 @@ static void __init blizzard_dev_init(void)
257 gpio_direction_output(N800_BLIZZARD_POWERDOWN_GPIO, 1);
258
259 blizzard_get_clocks();
260- omapfb_set_ctrl_platform_data(&n800_blizzard_data);
261+ //omapfb_set_ctrl_platform_data(&n800_blizzard_data);
262 }
263+#endif
264
265 static struct omap_board_config_kernel n800_config[] __initdata = {
266 { OMAP_TAG_UART, &n800_uart_config },
267- { OMAP_TAG_FBMEM, &n800_fbmem0_config },
268- { OMAP_TAG_FBMEM, &n800_fbmem1_config },
269- { OMAP_TAG_FBMEM, &n800_fbmem2_config },
270 { OMAP_TAG_TMP105, &n800_tmp105_config },
271 };
272
273@@ -379,7 +516,7 @@ static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
274
275 static struct spi_board_info n800_spi_board_info[] __initdata = {
276 {
277- .modalias = "lcd_mipid",
278+ .modalias = "panel-n800",
279 .bus_num = 1,
280 .chip_select = 1,
281 .max_speed_hz = 4000000,
282@@ -404,7 +541,7 @@ static struct spi_board_info n800_spi_board_info[] __initdata = {
283
284 static struct spi_board_info n810_spi_board_info[] __initdata = {
285 {
286- .modalias = "lcd_mipid",
287+ .modalias = "panel-n800",
288 .bus_num = 1,
289 .chip_select = 1,
290 .max_speed_hz = 4000000,
291@@ -582,6 +719,7 @@ static struct platform_device *n800_devices[] __initdata = {
292 #if defined(CONFIG_CBUS_RETU_HEADSET)
293 &retu_headset_device,
294 #endif
295+ &n800_dss_device,
296 };
297
298 #ifdef CONFIG_MENELAUS
299@@ -713,9 +851,10 @@ void __init nokia_n800_common_init(void)
300 if (machine_is_nokia_n810())
301 i2c_register_board_info(2, n810_i2c_board_info_2,
302 ARRAY_SIZE(n810_i2c_board_info_2));
303-
304- mipid_dev_init();
305- blizzard_dev_init();
306+
307+ //mipid_dev_init();
308+ //blizzard_dev_init();
309+ n800_display_init();
310 }
311
312 static void __init nokia_n800_init(void)
313@@ -735,6 +874,7 @@ void __init nokia_n800_map_io(void)
314 omap_board_config_size = ARRAY_SIZE(n800_config);
315
316 omap2_set_globals_242x();
317+ omap2_set_sdram_vram(800 * 480 * 2 * 3, 0);
318 omap2_map_common_io();
319 }
320
321diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
322index 0419ec8..356ceb1 100644
323--- a/drivers/video/omap2/displays/Kconfig
324+++ b/drivers/video/omap2/displays/Kconfig
325@@ -18,4 +18,14 @@ config PANEL_SHARP_LS037V7DW01
326 depends on OMAP2_DSS
327 help
328 LCD Panel used in TI's SDP3430 and EVM boards
329+
330+config PANEL_N800
331+ tristate "Panel N8x0"
332+ help
333+ N8x0 LCD (hack)
334+
335+config CTRL_BLIZZARD
336+ tristate "Blizzard Controller"
337+ help
338+ Blizzard Controller (hack)
339 endmenu
340diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
341index a26bbd2..1b74b7e 100644
342--- a/drivers/video/omap2/displays/Makefile
343+++ b/drivers/video/omap2/displays/Makefile
344@@ -1,3 +1,6 @@
345 obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o
346 obj-$(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) += panel-samsung-lte430wq-f0c.o
347 obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
348+
349+obj-$(CONFIG_CTRL_BLIZZARD) += ctrl-blizzard.o
350+obj-$(CONFIG_PANEL_N800) += panel-n800.o
351diff --git a/drivers/video/omap2/displays/ctrl-blizzard.c b/drivers/video/omap2/displays/ctrl-blizzard.c
352new file mode 100644
353index 0000000..6698e4d
354--- /dev/null
355+++ b/drivers/video/omap2/displays/ctrl-blizzard.c
356@@ -0,0 +1,279 @@
357+
358+//#define DEBUG
359+
360+#include <linux/kernel.h>
361+#include <linux/module.h>
362+#include <linux/clk.h>
363+#include <linux/delay.h>
364+#include <linux/err.h>
365+
366+#include <mach/display.h>
367+#include <mach/dma.h>
368+
369+#ifdef DEBUG
370+#define DBG(format, ...) printk(KERN_DEBUG "Blizzard: " format, ## __VA_ARGS__)
371+#else
372+#define DBG(format, ...)
373+#endif
374+
375+#define BLIZZARD_REV_CODE 0x00
376+#define BLIZZARD_CONFIG 0x02
377+#define BLIZZARD_PLL_DIV 0x04
378+#define BLIZZARD_PLL_LOCK_RANGE 0x06
379+#define BLIZZARD_PLL_CLOCK_SYNTH_0 0x08
380+#define BLIZZARD_PLL_CLOCK_SYNTH_1 0x0a
381+#define BLIZZARD_PLL_MODE 0x0c
382+#define BLIZZARD_CLK_SRC 0x0e
383+#define BLIZZARD_MEM_BANK0_ACTIVATE 0x10
384+#define BLIZZARD_MEM_BANK0_STATUS 0x14
385+#define BLIZZARD_PANEL_CONFIGURATION 0x28
386+#define BLIZZARD_HDISP 0x2a
387+#define BLIZZARD_HNDP 0x2c
388+#define BLIZZARD_VDISP0 0x2e
389+#define BLIZZARD_VDISP1 0x30
390+#define BLIZZARD_VNDP 0x32
391+#define BLIZZARD_HSW 0x34
392+#define BLIZZARD_VSW 0x38
393+#define BLIZZARD_DISPLAY_MODE 0x68
394+#define BLIZZARD_INPUT_WIN_X_START_0 0x6c
395+#define BLIZZARD_DATA_SOURCE_SELECT 0x8e
396+#define BLIZZARD_DISP_MEM_DATA_PORT 0x90
397+#define BLIZZARD_DISP_MEM_READ_ADDR0 0x92
398+#define BLIZZARD_POWER_SAVE 0xE6
399+#define BLIZZARD_NDISP_CTRL_STATUS 0xE8
400+
401+/* Data source select */
402+/* For S1D13745 */
403+#define BLIZZARD_SRC_WRITE_LCD_BACKGROUND 0x00
404+#define BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE 0x01
405+#define BLIZZARD_SRC_WRITE_OVERLAY_ENABLE 0x04
406+#define BLIZZARD_SRC_DISABLE_OVERLAY 0x05
407+/* For S1D13744 */
408+#define BLIZZARD_SRC_WRITE_LCD 0x00
409+#define BLIZZARD_SRC_BLT_LCD 0x06
410+
411+#define BLIZZARD_COLOR_RGB565 0x01
412+#define BLIZZARD_COLOR_YUV420 0x09
413+
414+#define BLIZZARD_VERSION_S1D13745 0x01 /* Hailstorm */
415+#define BLIZZARD_VERSION_S1D13744 0x02 /* Blizzard */
416+
417+#define BLIZZARD_AUTO_UPDATE_TIME (HZ / 20)
418+
419+
420+
421+static struct {
422+ int version;
423+} blizzard;
424+
425+
426+static inline void blizzard_cmd(u8 cmd)
427+{
428+ omap_rfbi_write_command(&cmd, 1);
429+}
430+
431+static inline void blizzard_write(u8 cmd, const u8 *buf, int len)
432+{
433+ omap_rfbi_write_command(&cmd, 1);
434+ omap_rfbi_write_data(buf, len);
435+}
436+
437+static inline void blizzard_read(u8 cmd, u8 *buf, int len)
438+{
439+ omap_rfbi_write_command(&cmd, 1);
440+ omap_rfbi_read_data(buf, len);
441+}
442+
443+static u8 blizzard_read_reg(u8 cmd)
444+{
445+ u8 data;
446+ blizzard_read(cmd, &data, 1);
447+ return data;
448+}
449+
450+static int blizzard_ctrl_init(struct omap_display *display)
451+{
452+ DBG("blizzard_ctrl_init\n");
453+
454+ return 0;
455+}
456+
457+
458+static int blizzard_ctrl_enable(struct omap_display *display)
459+{
460+ int r = 0;
461+ u8 rev, conf;
462+
463+ DBG("blizzard_ctrl_enable\n");
464+
465+ if (display->hw_config.ctrl_enable) {
466+ r = display->hw_config.ctrl_enable(display);
467+ if (r)
468+ return r;
469+ }
470+
471+ msleep(100);
472+
473+ rev = blizzard_read_reg(BLIZZARD_CLK_SRC);
474+ printk("CLK_SRC %x\n", rev);
475+
476+ rev = blizzard_read_reg(BLIZZARD_PLL_DIV);
477+ printk("PLLDIV %x\n", rev);
478+
479+ rev = blizzard_read_reg(BLIZZARD_REV_CODE);
480+ conf = blizzard_read_reg(BLIZZARD_CONFIG);
481+
482+ printk("rev %x, conf %x\n", rev, conf);
483+
484+ switch (rev & 0xfc) {
485+ case 0x9c:
486+ blizzard.version = BLIZZARD_VERSION_S1D13744;
487+ pr_info("omapfb: s1d13744 LCD controller rev %d "
488+ "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
489+ break;
490+ case 0xa4:
491+ blizzard.version = BLIZZARD_VERSION_S1D13745;
492+ pr_info("omapfb: s1d13745 LCD controller rev %d "
493+ "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
494+ break;
495+ default:
496+ printk("invalid s1d1374x revision %02x\n",
497+ rev);
498+ r = -ENODEV;
499+ }
500+
501+ return r;
502+}
503+
504+static void blizzard_ctrl_disable(struct omap_display *display)
505+{
506+ DBG("blizzard_ctrl_disable\n");
507+
508+ if (display->hw_config.ctrl_disable)
509+ display->hw_config.ctrl_disable(display);
510+}
511+
512+int rfbi_configure(int rfbi_module, int bpp, int lines);
513+
514+static void blizzard_ctrl_setup_update(struct omap_display *display,
515+ u16 x, u16 y, u16 w, u16 h)
516+{
517+ u8 tmp[18];
518+ int x_end, y_end;
519+
520+ DBG("blizzard_ctrl_setup_update\n");
521+
522+ x_end = x + w - 1;
523+ y_end = y + h - 1;
524+
525+ tmp[0] = x;
526+ tmp[1] = x >> 8;
527+ tmp[2] = y;
528+ tmp[3] = y >> 8;
529+ tmp[4] = x_end;
530+ tmp[5] = x_end >> 8;
531+ tmp[6] = y_end;
532+ tmp[7] = y_end >> 8;
533+
534+ /* scaling? */
535+ tmp[8] = x;
536+ tmp[9] = x >> 8;
537+ tmp[10] = y;
538+ tmp[11] = y >> 8;
539+ tmp[12] = x_end;
540+ tmp[13] = x_end >> 8;
541+ tmp[14] = y_end;
542+ tmp[15] = y_end >> 8;
543+
544+ tmp[16] = BLIZZARD_COLOR_RGB565; //color_mode;
545+
546+ if (blizzard.version == BLIZZARD_VERSION_S1D13745)
547+ tmp[17] = BLIZZARD_SRC_WRITE_LCD_BACKGROUND;
548+ else
549+ tmp[17] = blizzard.version == BLIZZARD_VERSION_S1D13744 ?
550+ BLIZZARD_SRC_WRITE_LCD :
551+ BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE;
552+
553+ rfbi_configure(display->hw_config.u.rfbi.channel,
554+ 16,
555+ 8);
556+
557+ blizzard_write(BLIZZARD_INPUT_WIN_X_START_0, tmp, 18);
558+
559+ rfbi_configure(display->hw_config.u.rfbi.channel,
560+ 16,
561+ 16);
562+}
563+
564+static int blizzard_ctrl_enable_te(struct omap_display *display, bool enable)
565+{
566+ return 0;
567+}
568+
569+static int blizzard_ctrl_rotate(struct omap_display *display, u8 rotate)
570+{
571+ return 0;
572+}
573+
574+static int blizzard_ctrl_mirror(struct omap_display *display, bool enable)
575+{
576+ return 0;
577+}
578+
579+static int blizzard_run_test(struct omap_display *display, int test_num)
580+{
581+ return 0;
582+}
583+
584+static struct omap_ctrl blizzard_ctrl = {
585+ .owner = THIS_MODULE,
586+ .name = "ctrl-blizzard",
587+ .init = blizzard_ctrl_init,
588+ .enable = blizzard_ctrl_enable,
589+ .disable = blizzard_ctrl_disable,
590+ .setup_update = blizzard_ctrl_setup_update,
591+ .enable_te = blizzard_ctrl_enable_te,
592+ .set_rotate = blizzard_ctrl_rotate,
593+ .set_mirror = blizzard_ctrl_mirror,
594+ .run_test = blizzard_run_test,
595+ .pixel_size = 16,
596+
597+ .timings = {
598+ .cs_on_time = 0,
599+
600+ .we_on_time = 9000,
601+ .we_off_time = 18000,
602+ .we_cycle_time = 36000,
603+
604+ .re_on_time = 9000,
605+ .re_off_time = 27000,
606+ .re_cycle_time = 36000,
607+
608+ .access_time = 27000,
609+ .cs_off_time = 36000,
610+
611+ .cs_pulse_width = 0,
612+ },
613+};
614+
615+
616+static int __init blizzard_init(void)
617+{
618+ DBG("blizzard_init\n");
619+ omap_dss_register_ctrl(&blizzard_ctrl);
620+ return 0;
621+}
622+
623+static void __exit blizzard_exit(void)
624+{
625+ DBG("blizzard_exit\n");
626+
627+ omap_dss_unregister_ctrl(&blizzard_ctrl);
628+}
629+
630+module_init(blizzard_init);
631+module_exit(blizzard_exit);
632+
633+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
634+MODULE_DESCRIPTION("Blizzard Driver");
635+MODULE_LICENSE("GPL");
636diff --git a/drivers/video/omap2/displays/panel-n800.c b/drivers/video/omap2/displays/panel-n800.c
637new file mode 100644
638index 0000000..91d3e37
639--- /dev/null
640+++ b/drivers/video/omap2/displays/panel-n800.c
641@@ -0,0 +1,435 @@
642+
643+/*#define DEBUG*/
644+
645+#include <linux/kernel.h>
646+#include <linux/module.h>
647+#include <linux/clk.h>
648+#include <linux/platform_device.h>
649+#include <linux/delay.h>
650+#include <linux/spi/spi.h>
651+#include <linux/jiffies.h>
652+#include <linux/sched.h>
653+#include <linux/backlight.h>
654+#include <linux/fb.h>
655+
656+#include <mach/display.h>
657+#include <mach/dma.h>
658+
659+#define MIPID_CMD_READ_DISP_ID 0x04
660+#define MIPID_CMD_READ_RED 0x06
661+#define MIPID_CMD_READ_GREEN 0x07
662+#define MIPID_CMD_READ_BLUE 0x08
663+#define MIPID_CMD_READ_DISP_STATUS 0x09
664+#define MIPID_CMD_RDDSDR 0x0F
665+#define MIPID_CMD_SLEEP_IN 0x10
666+#define MIPID_CMD_SLEEP_OUT 0x11
667+#define MIPID_CMD_DISP_OFF 0x28
668+#define MIPID_CMD_DISP_ON 0x29
669+
670+#define MIPID_VER_LPH8923 3
671+#define MIPID_VER_LS041Y3 4
672+
673+#define MIPID_ESD_CHECK_PERIOD msecs_to_jiffies(5000)
674+
675+#ifdef DEBUG
676+#define DBG(format, ...) printk(KERN_DEBUG "PN800: " format, ## __VA_ARGS__)
677+#else
678+#define DBG(format, ...)
679+#endif
680+
681+struct pn800_device {
682+ struct backlight_device *bl_dev;
683+ int enabled;
684+ int model;
685+ int revision;
686+ u8 display_id[3];
687+ unsigned int saved_bklight_level;
688+ unsigned long hw_guard_end; /* next value of jiffies
689+ when we can issue the
690+ next sleep in/out command */
691+ unsigned long hw_guard_wait; /* max guard time in jiffies */
692+
693+ struct spi_device *spi;
694+ struct mutex mutex;
695+ struct omap_panel panel;
696+ struct omap_display *display;
697+};
698+
699+
700+static void pn800_transfer(struct pn800_device *md, int cmd,
701+ const u8 *wbuf, int wlen, u8 *rbuf, int rlen)
702+{
703+ struct spi_message m;
704+ struct spi_transfer *x, xfer[4];
705+ u16 w;
706+ int r;
707+
708+ BUG_ON(md->spi == NULL);
709+
710+ spi_message_init(&m);
711+
712+ memset(xfer, 0, sizeof(xfer));
713+ x = &xfer[0];
714+
715+ cmd &= 0xff;
716+ x->tx_buf = &cmd;
717+ x->bits_per_word = 9;
718+ x->len = 2;
719+ spi_message_add_tail(x, &m);
720+
721+ if (wlen) {
722+ x++;
723+ x->tx_buf = wbuf;
724+ x->len = wlen;
725+ x->bits_per_word = 9;
726+ spi_message_add_tail(x, &m);
727+ }
728+
729+ if (rlen) {
730+ x++;
731+ x->rx_buf = &w;
732+ x->len = 1;
733+ spi_message_add_tail(x, &m);
734+
735+ if (rlen > 1) {
736+ /* Arrange for the extra clock before the first
737+ * data bit.
738+ */
739+ x->bits_per_word = 9;
740+ x->len = 2;
741+
742+ x++;
743+ x->rx_buf = &rbuf[1];
744+ x->len = rlen - 1;
745+ spi_message_add_tail(x, &m);
746+ }
747+ }
748+
749+ r = spi_sync(md->spi, &m);
750+ if (r < 0)
751+ dev_dbg(&md->spi->dev, "spi_sync %d\n", r);
752+
753+ if (rlen)
754+ rbuf[0] = w & 0xff;
755+}
756+
757+static inline void pn800_cmd(struct pn800_device *md, int cmd)
758+{
759+ pn800_transfer(md, cmd, NULL, 0, NULL, 0);
760+}
761+
762+static inline void pn800_write(struct pn800_device *md,
763+ int reg, const u8 *buf, int len)
764+{
765+ pn800_transfer(md, reg, buf, len, NULL, 0);
766+}
767+
768+static inline void pn800_read(struct pn800_device *md,
769+ int reg, u8 *buf, int len)
770+{
771+ pn800_transfer(md, reg, NULL, 0, buf, len);
772+}
773+
774+static void set_data_lines(struct pn800_device *md, int data_lines)
775+{
776+ u16 par;
777+
778+ switch (data_lines) {
779+ case 16:
780+ par = 0x150;
781+ break;
782+ case 18:
783+ par = 0x160;
784+ break;
785+ case 24:
786+ par = 0x170;
787+ break;
788+ }
789+ pn800_write(md, 0x3a, (u8 *)&par, 2);
790+}
791+
792+static void send_init_string(struct pn800_device *md)
793+{
794+ u16 initpar[] = { 0x0102, 0x0100, 0x0100 };
795+ int data_lines;
796+
797+ pn800_write(md, 0xc2, (u8 *)initpar, sizeof(initpar));
798+
799+ data_lines = (int)md->display->hw_config.panel_data; // XXX
800+
801+ set_data_lines(md, data_lines);
802+}
803+
804+static void hw_guard_start(struct pn800_device *md, int guard_msec)
805+{
806+ md->hw_guard_wait = msecs_to_jiffies(guard_msec);
807+ md->hw_guard_end = jiffies + md->hw_guard_wait;
808+}
809+
810+static void hw_guard_wait(struct pn800_device *md)
811+{
812+ unsigned long wait = md->hw_guard_end - jiffies;
813+
814+ if ((long)wait > 0 && wait <= md->hw_guard_wait) {
815+ set_current_state(TASK_UNINTERRUPTIBLE);
816+ schedule_timeout(wait);
817+ }
818+}
819+
820+static void set_sleep_mode(struct pn800_device *md, int on)
821+{
822+ int cmd, sleep_time = 50;
823+
824+ if (on)
825+ cmd = MIPID_CMD_SLEEP_IN;
826+ else
827+ cmd = MIPID_CMD_SLEEP_OUT;
828+ hw_guard_wait(md);
829+ pn800_cmd(md, cmd);
830+ hw_guard_start(md, 120);
831+ /*
832+ * When we enable the panel, it seems we _have_ to sleep
833+ * 120 ms before sending the init string. When disabling the
834+ * panel we'll sleep for the duration of 2 frames, so that the
835+ * controller can still provide the PCLK,HS,VS signals. */
836+ if (!on)
837+ sleep_time = 120;
838+ msleep(sleep_time);
839+}
840+
841+static void set_display_state(struct pn800_device *md, int enabled)
842+{
843+ int cmd = enabled ? MIPID_CMD_DISP_ON : MIPID_CMD_DISP_OFF;
844+
845+ pn800_cmd(md, cmd);
846+}
847+
848+static int panel_enabled(struct pn800_device *md)
849+{
850+ u32 disp_status;
851+ int enabled;
852+
853+ pn800_read(md, MIPID_CMD_READ_DISP_STATUS, (u8 *)&disp_status, 4);
854+ disp_status = __be32_to_cpu(disp_status);
855+ enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
856+ dev_dbg(&md->spi->dev,
857+ "LCD panel %s enabled by bootloader (status 0x%04x)\n",
858+ enabled ? "" : "not ", disp_status);
859+ DBG("status %#08x\n", disp_status);
860+ return enabled;
861+}
862+
863+static int panel_detect(struct pn800_device *md)
864+{
865+ pn800_read(md, MIPID_CMD_READ_DISP_ID, md->display_id, 3);
866+ dev_dbg(&md->spi->dev, "MIPI display ID: %02x%02x%02x\n",
867+ md->display_id[0], md->display_id[1], md->display_id[2]);
868+
869+ switch (md->display_id[0]) {
870+ case 0x45:
871+ md->model = MIPID_VER_LPH8923;
872+ md->panel.name = "lph8923";
873+ break;
874+ case 0x83:
875+ md->model = MIPID_VER_LS041Y3;
876+ md->panel.name = "ls041y3";
877+ //md->esd_check = ls041y3_esd_check;
878+ break;
879+ default:
880+ md->panel.name = "unknown";
881+ dev_err(&md->spi->dev, "invalid display ID\n");
882+ return -ENODEV;
883+ }
884+
885+ md->revision = md->display_id[1];
886+ pr_info("omapfb: %s rev %02x LCD detected\n",
887+ md->panel.name, md->revision);
888+
889+ return 0;
890+}
891+
892+
893+
894+static int pn800_panel_enable(struct omap_display *display)
895+{
896+ int r;
897+ struct pn800_device *md =
898+ (struct pn800_device *)display->panel->priv;
899+
900+ DBG("pn800_panel_enable\n");
901+
902+ mutex_lock(&md->mutex);
903+
904+ if (display->hw_config.panel_enable)
905+ display->hw_config.panel_enable(display);
906+
907+ msleep(50); // wait for power up
908+
909+ r = panel_detect(md);
910+ if (r) {
911+ mutex_unlock(&md->mutex);
912+ return r;
913+ }
914+
915+ md->enabled = panel_enabled(md);
916+
917+ if (md->enabled) {
918+ DBG("panel already enabled\n");
919+ ; /*pn800_esd_start_check(md);*/
920+ } else {
921+ ; /*md->saved_bklight_level = pn800_get_bklight_level(panel);*/
922+ }
923+
924+
925+ if (md->enabled) {
926+ mutex_unlock(&md->mutex);
927+ return 0;
928+ }
929+
930+ set_sleep_mode(md, 0);
931+ md->enabled = 1;
932+ send_init_string(md);
933+ set_display_state(md, 1);
934+ //mipid_set_bklight_level(panel, md->saved_bklight_level);
935+ //mipid_esd_start_check(md);
936+
937+ mutex_unlock(&md->mutex);
938+ return 0;
939+}
940+
941+static void pn800_panel_disable(struct omap_display *display)
942+{
943+ struct pn800_device *md =
944+ (struct pn800_device *)display->panel->priv;
945+
946+ DBG("pn800_panel_disable\n");
947+
948+ mutex_lock(&md->mutex);
949+
950+ if (!md->enabled) {
951+ mutex_unlock(&md->mutex);
952+ return;
953+ }
954+ /*md->saved_bklight_level = pn800_get_bklight_level(panel);*/
955+ /*pn800_set_bklight_level(panel, 0);*/
956+
957+ set_display_state(md, 0);
958+ set_sleep_mode(md, 1);
959+ md->enabled = 0;
960+
961+
962+ if (display->hw_config.panel_disable)
963+ display->hw_config.panel_disable(display);
964+
965+ mutex_unlock(&md->mutex);
966+}
967+
968+static int pn800_panel_init(struct omap_display *display)
969+{
970+ struct pn800_device *md =
971+ (struct pn800_device *)display->panel->priv;
972+
973+ DBG("pn800_panel_init\n");
974+
975+ mutex_init(&md->mutex);
976+ md->display = display;
977+
978+ return 0;
979+}
980+
981+static int pn800_run_test(struct omap_display *display, int test_num)
982+{
983+ return 0;
984+}
985+
986+static struct omap_panel pn800_panel = {
987+ .owner = THIS_MODULE,
988+ .name = "panel-pn800",
989+ .init = pn800_panel_init,
990+ /*.remove = pn800_cleanup,*/
991+ .enable = pn800_panel_enable,
992+ .disable = pn800_panel_disable,
993+ //.set_mode = pn800_set_mode,
994+ .run_test = pn800_run_test,
995+
996+ .timings = {
997+ .x_res = 800,
998+ .y_res = 480,
999+
1000+ .pixel_clock = 21940,
1001+ .hsw = 50,
1002+ .hfp = 20,
1003+ .hbp = 15,
1004+
1005+ .vsw = 2,
1006+ .vfp = 1,
1007+ .vbp = 3,
1008+ },
1009+ .config = OMAP_DSS_LCD_TFT,
1010+};
1011+
1012+static int pn800_spi_probe(struct spi_device *spi)
1013+{
1014+ struct pn800_device *md;
1015+
1016+ DBG("pn800_spi_probe\n");
1017+
1018+ md = kzalloc(sizeof(*md), GFP_KERNEL);
1019+ if (md == NULL) {
1020+ dev_err(&spi->dev, "out of memory\n");
1021+ return -ENOMEM;
1022+ }
1023+
1024+ spi->mode = SPI_MODE_0;
1025+ md->spi = spi;
1026+ dev_set_drvdata(&spi->dev, md);
1027+ md->panel = pn800_panel;
1028+ pn800_panel.priv = md;
1029+
1030+ omap_dss_register_panel(&pn800_panel);
1031+
1032+ return 0;
1033+}
1034+
1035+static int pn800_spi_remove(struct spi_device *spi)
1036+{
1037+ struct pn800_device *md = dev_get_drvdata(&spi->dev);
1038+
1039+ DBG("pn800_spi_remove\n");
1040+
1041+ omap_dss_unregister_panel(&pn800_panel);
1042+
1043+ /*pn800_disable(&md->panel);*/
1044+ kfree(md);
1045+
1046+ return 0;
1047+}
1048+
1049+static struct spi_driver pn800_spi_driver = {
1050+ .driver = {
1051+ .name = "panel-n800",
1052+ .bus = &spi_bus_type,
1053+ .owner = THIS_MODULE,
1054+ },
1055+ .probe = pn800_spi_probe,
1056+ .remove = __devexit_p(pn800_spi_remove),
1057+};
1058+
1059+static int __init pn800_init(void)
1060+{
1061+ DBG("pn800_init\n");
1062+ return spi_register_driver(&pn800_spi_driver);
1063+}
1064+
1065+static void __exit pn800_exit(void)
1066+{
1067+ DBG("pn800_exit\n");
1068+ spi_unregister_driver(&pn800_spi_driver);
1069+}
1070+
1071+module_init(pn800_init);
1072+module_exit(pn800_exit);
1073+
1074+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
1075+MODULE_DESCRIPTION("N800 LCD Driver");
1076+MODULE_LICENSE("GPL");
1077--
10781.5.6.5
1079
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0007-DSS2-Add-DSS2-support-for-SDP-Beagle-Overo-EVM.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0007-DSS2-Add-DSS2-support-for-SDP-Beagle-Overo-EVM.patch
new file mode 100644
index 0000000000..26d21d8744
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0007-DSS2-Add-DSS2-support-for-SDP-Beagle-Overo-EVM.patch
@@ -0,0 +1,5715 @@
1From 9292aae93419867b9d0fce5cf3b2697e9250f5b5 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 2 Apr 2009 10:36:05 +0300
4Subject: [PATCH] DSS2: Add DSS2 support for SDP, Beagle, Overo, EVM
5
6Also custom dss_*_defconfigs as an example.
7
8Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
9---
10 arch/arm/configs/dss_omap3_beagle_defconfig | 1371 ++++++++++++++++++++
11 arch/arm/configs/dss_omap_3430sdp_defconfig | 1634 +++++++++++++++++++++++
12 arch/arm/configs/dss_overo_defconfig | 1862 +++++++++++++++++++++++++++
13 arch/arm/mach-omap2/board-3430sdp.c | 227 ++++-
14 arch/arm/mach-omap2/board-omap3beagle.c | 95 ++-
15 arch/arm/mach-omap2/board-omap3evm.c | 217 +++-
16 arch/arm/mach-omap2/board-overo.c | 98 ++-
17 7 files changed, 5475 insertions(+), 29 deletions(-)
18 create mode 100644 arch/arm/configs/dss_omap3_beagle_defconfig
19 create mode 100644 arch/arm/configs/dss_omap_3430sdp_defconfig
20 create mode 100644 arch/arm/configs/dss_overo_defconfig
21
22diff --git a/arch/arm/configs/dss_omap3_beagle_defconfig b/arch/arm/configs/dss_omap3_beagle_defconfig
23new file mode 100644
24index 0000000..7143168
25--- /dev/null
26+++ b/arch/arm/configs/dss_omap3_beagle_defconfig
27@@ -0,0 +1,1371 @@
28+#
29+# Automatically generated make config: don't edit
30+# Linux kernel version: 2.6.29-omap1
31+# Thu Apr 2 11:24:09 2009
32+#
33+CONFIG_ARM=y
34+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
35+CONFIG_GENERIC_GPIO=y
36+CONFIG_GENERIC_TIME=y
37+CONFIG_GENERIC_CLOCKEVENTS=y
38+CONFIG_MMU=y
39+# CONFIG_NO_IOPORT is not set
40+CONFIG_GENERIC_HARDIRQS=y
41+CONFIG_STACKTRACE_SUPPORT=y
42+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
43+CONFIG_LOCKDEP_SUPPORT=y
44+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
45+CONFIG_HARDIRQS_SW_RESEND=y
46+CONFIG_GENERIC_IRQ_PROBE=y
47+CONFIG_RWSEM_GENERIC_SPINLOCK=y
48+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
49+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
50+CONFIG_GENERIC_HWEIGHT=y
51+CONFIG_GENERIC_CALIBRATE_DELAY=y
52+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
53+CONFIG_VECTORS_BASE=0xffff0000
54+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
55+
56+#
57+# General setup
58+#
59+CONFIG_EXPERIMENTAL=y
60+CONFIG_BROKEN_ON_SMP=y
61+CONFIG_INIT_ENV_ARG_LIMIT=32
62+CONFIG_LOCALVERSION=""
63+CONFIG_LOCALVERSION_AUTO=y
64+CONFIG_SWAP=y
65+CONFIG_SYSVIPC=y
66+CONFIG_SYSVIPC_SYSCTL=y
67+# CONFIG_POSIX_MQUEUE is not set
68+CONFIG_BSD_PROCESS_ACCT=y
69+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
70+# CONFIG_TASKSTATS is not set
71+# CONFIG_AUDIT is not set
72+
73+#
74+# RCU Subsystem
75+#
76+CONFIG_CLASSIC_RCU=y
77+# CONFIG_TREE_RCU is not set
78+# CONFIG_PREEMPT_RCU is not set
79+# CONFIG_TREE_RCU_TRACE is not set
80+# CONFIG_PREEMPT_RCU_TRACE is not set
81+# CONFIG_IKCONFIG is not set
82+CONFIG_LOG_BUF_SHIFT=14
83+CONFIG_GROUP_SCHED=y
84+CONFIG_FAIR_GROUP_SCHED=y
85+# CONFIG_RT_GROUP_SCHED is not set
86+CONFIG_USER_SCHED=y
87+# CONFIG_CGROUP_SCHED is not set
88+# CONFIG_CGROUPS is not set
89+CONFIG_SYSFS_DEPRECATED=y
90+CONFIG_SYSFS_DEPRECATED_V2=y
91+# CONFIG_RELAY is not set
92+# CONFIG_NAMESPACES is not set
93+CONFIG_BLK_DEV_INITRD=y
94+CONFIG_INITRAMFS_SOURCE=""
95+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
96+CONFIG_SYSCTL=y
97+CONFIG_ANON_INODES=y
98+CONFIG_EMBEDDED=y
99+CONFIG_UID16=y
100+# CONFIG_SYSCTL_SYSCALL is not set
101+CONFIG_KALLSYMS=y
102+# CONFIG_KALLSYMS_ALL is not set
103+CONFIG_KALLSYMS_EXTRA_PASS=y
104+CONFIG_HOTPLUG=y
105+CONFIG_PRINTK=y
106+CONFIG_BUG=y
107+CONFIG_ELF_CORE=y
108+CONFIG_BASE_FULL=y
109+CONFIG_FUTEX=y
110+CONFIG_EPOLL=y
111+CONFIG_SIGNALFD=y
112+CONFIG_TIMERFD=y
113+CONFIG_EVENTFD=y
114+CONFIG_SHMEM=y
115+CONFIG_AIO=y
116+CONFIG_VM_EVENT_COUNTERS=y
117+CONFIG_COMPAT_BRK=y
118+CONFIG_SLAB=y
119+# CONFIG_SLUB is not set
120+# CONFIG_SLOB is not set
121+# CONFIG_PROFILING is not set
122+CONFIG_HAVE_OPROFILE=y
123+# CONFIG_KPROBES is not set
124+CONFIG_HAVE_KPROBES=y
125+CONFIG_HAVE_KRETPROBES=y
126+CONFIG_HAVE_CLK=y
127+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
128+CONFIG_SLABINFO=y
129+CONFIG_RT_MUTEXES=y
130+CONFIG_BASE_SMALL=0
131+CONFIG_MODULES=y
132+# CONFIG_MODULE_FORCE_LOAD is not set
133+CONFIG_MODULE_UNLOAD=y
134+# CONFIG_MODULE_FORCE_UNLOAD is not set
135+CONFIG_MODVERSIONS=y
136+CONFIG_MODULE_SRCVERSION_ALL=y
137+CONFIG_BLOCK=y
138+# CONFIG_LBD is not set
139+# CONFIG_BLK_DEV_IO_TRACE is not set
140+# CONFIG_BLK_DEV_BSG is not set
141+# CONFIG_BLK_DEV_INTEGRITY is not set
142+
143+#
144+# IO Schedulers
145+#
146+CONFIG_IOSCHED_NOOP=y
147+CONFIG_IOSCHED_AS=y
148+CONFIG_IOSCHED_DEADLINE=y
149+CONFIG_IOSCHED_CFQ=y
150+CONFIG_DEFAULT_AS=y
151+# CONFIG_DEFAULT_DEADLINE is not set
152+# CONFIG_DEFAULT_CFQ is not set
153+# CONFIG_DEFAULT_NOOP is not set
154+CONFIG_DEFAULT_IOSCHED="anticipatory"
155+# CONFIG_FREEZER is not set
156+
157+#
158+# System Type
159+#
160+# CONFIG_ARCH_AAEC2000 is not set
161+# CONFIG_ARCH_INTEGRATOR is not set
162+# CONFIG_ARCH_REALVIEW is not set
163+# CONFIG_ARCH_VERSATILE is not set
164+# CONFIG_ARCH_AT91 is not set
165+# CONFIG_ARCH_CLPS711X is not set
166+# CONFIG_ARCH_EBSA110 is not set
167+# CONFIG_ARCH_EP93XX is not set
168+# CONFIG_ARCH_FOOTBRIDGE is not set
169+# CONFIG_ARCH_NETX is not set
170+# CONFIG_ARCH_H720X is not set
171+# CONFIG_ARCH_IMX is not set
172+# CONFIG_ARCH_IOP13XX is not set
173+# CONFIG_ARCH_IOP32X is not set
174+# CONFIG_ARCH_IOP33X is not set
175+# CONFIG_ARCH_IXP23XX is not set
176+# CONFIG_ARCH_IXP2000 is not set
177+# CONFIG_ARCH_IXP4XX is not set
178+# CONFIG_ARCH_L7200 is not set
179+# CONFIG_ARCH_KIRKWOOD is not set
180+# CONFIG_ARCH_KS8695 is not set
181+# CONFIG_ARCH_NS9XXX is not set
182+# CONFIG_ARCH_LOKI is not set
183+# CONFIG_ARCH_MV78XX0 is not set
184+# CONFIG_ARCH_MXC is not set
185+# CONFIG_ARCH_ORION5X is not set
186+# CONFIG_ARCH_PNX4008 is not set
187+# CONFIG_ARCH_PXA is not set
188+# CONFIG_ARCH_RPC is not set
189+# CONFIG_ARCH_SA1100 is not set
190+# CONFIG_ARCH_S3C2410 is not set
191+# CONFIG_ARCH_S3C64XX is not set
192+# CONFIG_ARCH_SHARK is not set
193+# CONFIG_ARCH_LH7A40X is not set
194+# CONFIG_ARCH_DAVINCI is not set
195+CONFIG_ARCH_OMAP=y
196+# CONFIG_ARCH_MSM is not set
197+# CONFIG_ARCH_W90X900 is not set
198+
199+#
200+# TI OMAP Implementations
201+#
202+CONFIG_ARCH_OMAP_OTG=y
203+# CONFIG_ARCH_OMAP1 is not set
204+# CONFIG_ARCH_OMAP2 is not set
205+CONFIG_ARCH_OMAP3=y
206+
207+#
208+# OMAP Feature Selections
209+#
210+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
211+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
212+# CONFIG_OMAP_SMARTREFLEX is not set
213+# CONFIG_OMAP_RESET_CLOCKS is not set
214+CONFIG_OMAP_BOOT_TAG=y
215+CONFIG_OMAP_BOOT_REASON=y
216+# CONFIG_OMAP_COMPONENT_VERSION is not set
217+# CONFIG_OMAP_GPIO_SWITCH is not set
218+# CONFIG_OMAP_MUX is not set
219+# CONFIG_OMAP_MCBSP is not set
220+# CONFIG_OMAP_MBOX_FWK is not set
221+# CONFIG_OMAP_MPU_TIMER is not set
222+CONFIG_OMAP_32K_TIMER=y
223+CONFIG_OMAP_32K_TIMER_HZ=128
224+CONFIG_OMAP_TICK_GPTIMER=12
225+CONFIG_OMAP_DM_TIMER=y
226+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
227+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
228+CONFIG_OMAP_LL_DEBUG_UART3=y
229+CONFIG_ARCH_OMAP34XX=y
230+CONFIG_ARCH_OMAP3430=y
231+
232+#
233+# OMAP Board Type
234+#
235+# CONFIG_MACH_NOKIA_RX51 is not set
236+# CONFIG_MACH_OMAP_LDP is not set
237+# CONFIG_MACH_OMAP_3430SDP is not set
238+# CONFIG_MACH_OMAP3EVM is not set
239+CONFIG_MACH_OMAP3_BEAGLE=y
240+# CONFIG_MACH_OVERO is not set
241+# CONFIG_MACH_OMAP3_PANDORA is not set
242+
243+#
244+# Processor Type
245+#
246+CONFIG_CPU_32=y
247+CONFIG_CPU_32v6K=y
248+CONFIG_CPU_V7=y
249+CONFIG_CPU_32v7=y
250+CONFIG_CPU_ABRT_EV7=y
251+CONFIG_CPU_PABRT_IFAR=y
252+CONFIG_CPU_CACHE_V7=y
253+CONFIG_CPU_CACHE_VIPT=y
254+CONFIG_CPU_COPY_V6=y
255+CONFIG_CPU_TLB_V7=y
256+CONFIG_CPU_HAS_ASID=y
257+CONFIG_CPU_CP15=y
258+CONFIG_CPU_CP15_MMU=y
259+
260+#
261+# Processor Features
262+#
263+CONFIG_ARM_THUMB=y
264+# CONFIG_ARM_THUMBEE is not set
265+# CONFIG_CPU_ICACHE_DISABLE is not set
266+# CONFIG_CPU_DCACHE_DISABLE is not set
267+# CONFIG_CPU_BPREDICT_DISABLE is not set
268+CONFIG_HAS_TLS_REG=y
269+# CONFIG_OUTER_CACHE is not set
270+
271+#
272+# Bus support
273+#
274+# CONFIG_PCI_SYSCALL is not set
275+# CONFIG_ARCH_SUPPORTS_MSI is not set
276+# CONFIG_PCCARD is not set
277+
278+#
279+# Kernel Features
280+#
281+CONFIG_TICK_ONESHOT=y
282+CONFIG_NO_HZ=y
283+CONFIG_HIGH_RES_TIMERS=y
284+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
285+CONFIG_VMSPLIT_3G=y
286+# CONFIG_VMSPLIT_2G is not set
287+# CONFIG_VMSPLIT_1G is not set
288+CONFIG_PAGE_OFFSET=0xC0000000
289+# CONFIG_PREEMPT is not set
290+CONFIG_HZ=128
291+CONFIG_AEABI=y
292+CONFIG_OABI_COMPAT=y
293+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
294+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
295+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
296+CONFIG_SELECT_MEMORY_MODEL=y
297+CONFIG_FLATMEM_MANUAL=y
298+# CONFIG_DISCONTIGMEM_MANUAL is not set
299+# CONFIG_SPARSEMEM_MANUAL is not set
300+CONFIG_FLATMEM=y
301+CONFIG_FLAT_NODE_MEM_MAP=y
302+CONFIG_PAGEFLAGS_EXTENDED=y
303+CONFIG_SPLIT_PTLOCK_CPUS=4
304+# CONFIG_PHYS_ADDR_T_64BIT is not set
305+CONFIG_ZONE_DMA_FLAG=0
306+CONFIG_VIRT_TO_BUS=y
307+CONFIG_UNEVICTABLE_LRU=y
308+# CONFIG_LEDS is not set
309+CONFIG_ALIGNMENT_TRAP=y
310+
311+#
312+# Boot options
313+#
314+CONFIG_ZBOOT_ROM_TEXT=0x0
315+CONFIG_ZBOOT_ROM_BSS=0x0
316+CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.2.14:/tftpboot/rootfs ip=192.168.2.15 nolock,rsize=1024,wsize=1024 rw"
317+# CONFIG_XIP_KERNEL is not set
318+# CONFIG_KEXEC is not set
319+
320+#
321+# CPU Power Management
322+#
323+# CONFIG_CPU_FREQ is not set
324+# CONFIG_CPU_IDLE is not set
325+
326+#
327+# Floating point emulation
328+#
329+
330+#
331+# At least one emulation must be selected
332+#
333+CONFIG_FPE_NWFPE=y
334+# CONFIG_FPE_NWFPE_XP is not set
335+# CONFIG_FPE_FASTFPE is not set
336+CONFIG_VFP=y
337+CONFIG_VFPv3=y
338+# CONFIG_NEON is not set
339+
340+#
341+# Userspace binary formats
342+#
343+CONFIG_BINFMT_ELF=y
344+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
345+CONFIG_HAVE_AOUT=y
346+# CONFIG_BINFMT_AOUT is not set
347+CONFIG_BINFMT_MISC=y
348+
349+#
350+# Power management options
351+#
352+CONFIG_PM=y
353+# CONFIG_PM_DEBUG is not set
354+# CONFIG_SUSPEND is not set
355+# CONFIG_APM_EMULATION is not set
356+CONFIG_ARCH_SUSPEND_POSSIBLE=y
357+CONFIG_NET=y
358+
359+#
360+# Networking options
361+#
362+CONFIG_COMPAT_NET_DEV_OPS=y
363+CONFIG_PACKET=y
364+# CONFIG_PACKET_MMAP is not set
365+CONFIG_UNIX=y
366+CONFIG_XFRM=y
367+# CONFIG_XFRM_USER is not set
368+# CONFIG_XFRM_SUB_POLICY is not set
369+# CONFIG_XFRM_MIGRATE is not set
370+# CONFIG_XFRM_STATISTICS is not set
371+CONFIG_NET_KEY=y
372+# CONFIG_NET_KEY_MIGRATE is not set
373+CONFIG_INET=y
374+# CONFIG_IP_MULTICAST is not set
375+# CONFIG_IP_ADVANCED_ROUTER is not set
376+CONFIG_IP_FIB_HASH=y
377+CONFIG_IP_PNP=y
378+CONFIG_IP_PNP_DHCP=y
379+CONFIG_IP_PNP_BOOTP=y
380+CONFIG_IP_PNP_RARP=y
381+# CONFIG_NET_IPIP is not set
382+# CONFIG_NET_IPGRE is not set
383+# CONFIG_ARPD is not set
384+# CONFIG_SYN_COOKIES is not set
385+# CONFIG_INET_AH is not set
386+# CONFIG_INET_ESP is not set
387+# CONFIG_INET_IPCOMP is not set
388+# CONFIG_INET_XFRM_TUNNEL is not set
389+# CONFIG_INET_TUNNEL is not set
390+CONFIG_INET_XFRM_MODE_TRANSPORT=y
391+CONFIG_INET_XFRM_MODE_TUNNEL=y
392+CONFIG_INET_XFRM_MODE_BEET=y
393+# CONFIG_INET_LRO is not set
394+CONFIG_INET_DIAG=y
395+CONFIG_INET_TCP_DIAG=y
396+# CONFIG_TCP_CONG_ADVANCED is not set
397+CONFIG_TCP_CONG_CUBIC=y
398+CONFIG_DEFAULT_TCP_CONG="cubic"
399+# CONFIG_TCP_MD5SIG is not set
400+# CONFIG_IPV6 is not set
401+# CONFIG_NETWORK_SECMARK is not set
402+# CONFIG_NETFILTER is not set
403+# CONFIG_IP_DCCP is not set
404+# CONFIG_IP_SCTP is not set
405+# CONFIG_TIPC is not set
406+# CONFIG_ATM is not set
407+# CONFIG_BRIDGE is not set
408+# CONFIG_NET_DSA is not set
409+# CONFIG_VLAN_8021Q is not set
410+# CONFIG_DECNET is not set
411+# CONFIG_LLC2 is not set
412+# CONFIG_IPX is not set
413+# CONFIG_ATALK is not set
414+# CONFIG_X25 is not set
415+# CONFIG_LAPB is not set
416+# CONFIG_ECONET is not set
417+# CONFIG_WAN_ROUTER is not set
418+# CONFIG_NET_SCHED is not set
419+# CONFIG_DCB is not set
420+
421+#
422+# Network testing
423+#
424+# CONFIG_NET_PKTGEN is not set
425+# CONFIG_HAMRADIO is not set
426+# CONFIG_CAN is not set
427+# CONFIG_IRDA is not set
428+# CONFIG_BT is not set
429+# CONFIG_AF_RXRPC is not set
430+# CONFIG_PHONET is not set
431+CONFIG_WIRELESS=y
432+# CONFIG_CFG80211 is not set
433+CONFIG_WIRELESS_OLD_REGULATORY=y
434+# CONFIG_WIRELESS_EXT is not set
435+# CONFIG_LIB80211 is not set
436+# CONFIG_MAC80211 is not set
437+# CONFIG_WIMAX is not set
438+# CONFIG_RFKILL is not set
439+# CONFIG_NET_9P is not set
440+
441+#
442+# Device Drivers
443+#
444+
445+#
446+# Generic Driver Options
447+#
448+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
449+CONFIG_STANDALONE=y
450+CONFIG_PREVENT_FIRMWARE_BUILD=y
451+# CONFIG_FW_LOADER is not set
452+# CONFIG_DEBUG_DRIVER is not set
453+# CONFIG_DEBUG_DEVRES is not set
454+# CONFIG_SYS_HYPERVISOR is not set
455+# CONFIG_CONNECTOR is not set
456+CONFIG_MTD=y
457+# CONFIG_MTD_DEBUG is not set
458+# CONFIG_MTD_CONCAT is not set
459+CONFIG_MTD_PARTITIONS=y
460+# CONFIG_MTD_TESTS is not set
461+# CONFIG_MTD_REDBOOT_PARTS is not set
462+# CONFIG_MTD_CMDLINE_PARTS is not set
463+# CONFIG_MTD_AFS_PARTS is not set
464+# CONFIG_MTD_AR7_PARTS is not set
465+
466+#
467+# User Modules And Translation Layers
468+#
469+CONFIG_MTD_CHAR=y
470+CONFIG_MTD_BLKDEVS=y
471+CONFIG_MTD_BLOCK=y
472+# CONFIG_FTL is not set
473+# CONFIG_NFTL is not set
474+# CONFIG_INFTL is not set
475+# CONFIG_RFD_FTL is not set
476+# CONFIG_SSFDC is not set
477+# CONFIG_MTD_OOPS is not set
478+
479+#
480+# RAM/ROM/Flash chip drivers
481+#
482+# CONFIG_MTD_CFI is not set
483+# CONFIG_MTD_JEDECPROBE is not set
484+CONFIG_MTD_MAP_BANK_WIDTH_1=y
485+CONFIG_MTD_MAP_BANK_WIDTH_2=y
486+CONFIG_MTD_MAP_BANK_WIDTH_4=y
487+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
488+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
489+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
490+CONFIG_MTD_CFI_I1=y
491+CONFIG_MTD_CFI_I2=y
492+# CONFIG_MTD_CFI_I4 is not set
493+# CONFIG_MTD_CFI_I8 is not set
494+# CONFIG_MTD_RAM is not set
495+# CONFIG_MTD_ROM is not set
496+# CONFIG_MTD_ABSENT is not set
497+
498+#
499+# Mapping drivers for chip access
500+#
501+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
502+# CONFIG_MTD_PLATRAM is not set
503+
504+#
505+# Self-contained MTD device drivers
506+#
507+# CONFIG_MTD_SLRAM is not set
508+# CONFIG_MTD_PHRAM is not set
509+# CONFIG_MTD_MTDRAM is not set
510+# CONFIG_MTD_BLOCK2MTD is not set
511+
512+#
513+# Disk-On-Chip Device Drivers
514+#
515+# CONFIG_MTD_DOC2000 is not set
516+# CONFIG_MTD_DOC2001 is not set
517+# CONFIG_MTD_DOC2001PLUS is not set
518+CONFIG_MTD_NAND=y
519+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
520+# CONFIG_MTD_NAND_ECC_SMC is not set
521+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
522+# CONFIG_MTD_NAND_GPIO is not set
523+CONFIG_MTD_NAND_OMAP2=y
524+CONFIG_MTD_NAND_IDS=y
525+# CONFIG_MTD_NAND_DISKONCHIP is not set
526+# CONFIG_MTD_NAND_NANDSIM is not set
527+# CONFIG_MTD_NAND_PLATFORM is not set
528+# CONFIG_MTD_ONENAND is not set
529+
530+#
531+# LPDDR flash memory drivers
532+#
533+# CONFIG_MTD_LPDDR is not set
534+
535+#
536+# UBI - Unsorted block images
537+#
538+# CONFIG_MTD_UBI is not set
539+# CONFIG_PARPORT is not set
540+CONFIG_BLK_DEV=y
541+# CONFIG_BLK_DEV_COW_COMMON is not set
542+CONFIG_BLK_DEV_LOOP=y
543+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
544+# CONFIG_BLK_DEV_NBD is not set
545+CONFIG_BLK_DEV_RAM=y
546+CONFIG_BLK_DEV_RAM_COUNT=16
547+CONFIG_BLK_DEV_RAM_SIZE=16384
548+# CONFIG_BLK_DEV_XIP is not set
549+# CONFIG_CDROM_PKTCDVD is not set
550+# CONFIG_ATA_OVER_ETH is not set
551+# CONFIG_MISC_DEVICES is not set
552+CONFIG_HAVE_IDE=y
553+# CONFIG_IDE is not set
554+
555+#
556+# SCSI device support
557+#
558+# CONFIG_RAID_ATTRS is not set
559+CONFIG_SCSI=y
560+CONFIG_SCSI_DMA=y
561+# CONFIG_SCSI_TGT is not set
562+# CONFIG_SCSI_NETLINK is not set
563+CONFIG_SCSI_PROC_FS=y
564+
565+#
566+# SCSI support type (disk, tape, CD-ROM)
567+#
568+CONFIG_BLK_DEV_SD=y
569+# CONFIG_CHR_DEV_ST is not set
570+# CONFIG_CHR_DEV_OSST is not set
571+# CONFIG_BLK_DEV_SR is not set
572+# CONFIG_CHR_DEV_SG is not set
573+# CONFIG_CHR_DEV_SCH is not set
574+
575+#
576+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
577+#
578+# CONFIG_SCSI_MULTI_LUN is not set
579+# CONFIG_SCSI_CONSTANTS is not set
580+# CONFIG_SCSI_LOGGING is not set
581+# CONFIG_SCSI_SCAN_ASYNC is not set
582+CONFIG_SCSI_WAIT_SCAN=m
583+
584+#
585+# SCSI Transports
586+#
587+# CONFIG_SCSI_SPI_ATTRS is not set
588+# CONFIG_SCSI_FC_ATTRS is not set
589+# CONFIG_SCSI_ISCSI_ATTRS is not set
590+# CONFIG_SCSI_SAS_LIBSAS is not set
591+# CONFIG_SCSI_SRP_ATTRS is not set
592+CONFIG_SCSI_LOWLEVEL=y
593+# CONFIG_ISCSI_TCP is not set
594+# CONFIG_LIBFC is not set
595+# CONFIG_SCSI_DEBUG is not set
596+# CONFIG_SCSI_DH is not set
597+# CONFIG_ATA is not set
598+# CONFIG_MD is not set
599+CONFIG_NETDEVICES=y
600+# CONFIG_DUMMY is not set
601+# CONFIG_BONDING is not set
602+# CONFIG_MACVLAN is not set
603+# CONFIG_EQUALIZER is not set
604+# CONFIG_TUN is not set
605+# CONFIG_VETH is not set
606+# CONFIG_NET_ETHERNET is not set
607+# CONFIG_NETDEV_1000 is not set
608+# CONFIG_NETDEV_10000 is not set
609+
610+#
611+# Wireless LAN
612+#
613+# CONFIG_WLAN_PRE80211 is not set
614+# CONFIG_WLAN_80211 is not set
615+# CONFIG_IWLWIFI_LEDS is not set
616+
617+#
618+# Enable WiMAX (Networking options) to see the WiMAX drivers
619+#
620+# CONFIG_WAN is not set
621+# CONFIG_PPP is not set
622+# CONFIG_SLIP is not set
623+# CONFIG_NETCONSOLE is not set
624+# CONFIG_NETPOLL is not set
625+# CONFIG_NET_POLL_CONTROLLER is not set
626+# CONFIG_ISDN is not set
627+
628+#
629+# Input device support
630+#
631+CONFIG_INPUT=y
632+# CONFIG_INPUT_FF_MEMLESS is not set
633+# CONFIG_INPUT_POLLDEV is not set
634+
635+#
636+# Userland interfaces
637+#
638+# CONFIG_INPUT_MOUSEDEV is not set
639+# CONFIG_INPUT_JOYDEV is not set
640+# CONFIG_INPUT_EVDEV is not set
641+# CONFIG_INPUT_EVBUG is not set
642+
643+#
644+# Input Device Drivers
645+#
646+# CONFIG_INPUT_KEYBOARD is not set
647+# CONFIG_INPUT_MOUSE is not set
648+# CONFIG_INPUT_JOYSTICK is not set
649+# CONFIG_INPUT_TABLET is not set
650+# CONFIG_INPUT_TOUCHSCREEN is not set
651+# CONFIG_INPUT_MISC is not set
652+
653+#
654+# Hardware I/O ports
655+#
656+# CONFIG_SERIO is not set
657+# CONFIG_GAMEPORT is not set
658+
659+#
660+# Character devices
661+#
662+CONFIG_VT=y
663+CONFIG_CONSOLE_TRANSLATIONS=y
664+CONFIG_VT_CONSOLE=y
665+CONFIG_HW_CONSOLE=y
666+# CONFIG_VT_HW_CONSOLE_BINDING is not set
667+CONFIG_DEVKMEM=y
668+# CONFIG_SERIAL_NONSTANDARD is not set
669+
670+#
671+# Serial drivers
672+#
673+CONFIG_SERIAL_8250=y
674+CONFIG_SERIAL_8250_CONSOLE=y
675+CONFIG_SERIAL_8250_NR_UARTS=32
676+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
677+CONFIG_SERIAL_8250_EXTENDED=y
678+CONFIG_SERIAL_8250_MANY_PORTS=y
679+CONFIG_SERIAL_8250_SHARE_IRQ=y
680+CONFIG_SERIAL_8250_DETECT_IRQ=y
681+CONFIG_SERIAL_8250_RSA=y
682+
683+#
684+# Non-8250 serial port support
685+#
686+CONFIG_SERIAL_CORE=y
687+CONFIG_SERIAL_CORE_CONSOLE=y
688+CONFIG_UNIX98_PTYS=y
689+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
690+# CONFIG_LEGACY_PTYS is not set
691+# CONFIG_IPMI_HANDLER is not set
692+CONFIG_HW_RANDOM=y
693+# CONFIG_R3964 is not set
694+# CONFIG_RAW_DRIVER is not set
695+# CONFIG_TCG_TPM is not set
696+CONFIG_I2C=y
697+CONFIG_I2C_BOARDINFO=y
698+CONFIG_I2C_CHARDEV=y
699+CONFIG_I2C_HELPER_AUTO=y
700+
701+#
702+# I2C Hardware Bus support
703+#
704+
705+#
706+# I2C system bus drivers (mostly embedded / system-on-chip)
707+#
708+# CONFIG_I2C_GPIO is not set
709+# CONFIG_I2C_OCORES is not set
710+CONFIG_I2C_OMAP=y
711+# CONFIG_I2C_SIMTEC is not set
712+
713+#
714+# External I2C/SMBus adapter drivers
715+#
716+# CONFIG_I2C_PARPORT_LIGHT is not set
717+# CONFIG_I2C_TAOS_EVM is not set
718+
719+#
720+# Other I2C/SMBus bus drivers
721+#
722+# CONFIG_I2C_PCA_PLATFORM is not set
723+# CONFIG_I2C_STUB is not set
724+
725+#
726+# Miscellaneous I2C Chip support
727+#
728+# CONFIG_DS1682 is not set
729+# CONFIG_SENSORS_PCF8574 is not set
730+# CONFIG_PCF8575 is not set
731+# CONFIG_SENSORS_PCA9539 is not set
732+# CONFIG_SENSORS_PCF8591 is not set
733+# CONFIG_TWL4030_MADC is not set
734+# CONFIG_TWL4030_POWEROFF is not set
735+# CONFIG_SENSORS_MAX6875 is not set
736+# CONFIG_SENSORS_TSL2550 is not set
737+# CONFIG_I2C_DEBUG_CORE is not set
738+# CONFIG_I2C_DEBUG_ALGO is not set
739+# CONFIG_I2C_DEBUG_BUS is not set
740+# CONFIG_I2C_DEBUG_CHIP is not set
741+# CONFIG_SPI is not set
742+CONFIG_ARCH_REQUIRE_GPIOLIB=y
743+CONFIG_GPIOLIB=y
744+# CONFIG_DEBUG_GPIO is not set
745+# CONFIG_GPIO_SYSFS is not set
746+
747+#
748+# Memory mapped GPIO expanders:
749+#
750+
751+#
752+# I2C GPIO expanders:
753+#
754+# CONFIG_GPIO_MAX732X is not set
755+# CONFIG_GPIO_PCA953X is not set
756+# CONFIG_GPIO_PCF857X is not set
757+CONFIG_GPIO_TWL4030=y
758+
759+#
760+# PCI GPIO expanders:
761+#
762+
763+#
764+# SPI GPIO expanders:
765+#
766+# CONFIG_W1 is not set
767+# CONFIG_POWER_SUPPLY is not set
768+# CONFIG_HWMON is not set
769+# CONFIG_THERMAL is not set
770+# CONFIG_THERMAL_HWMON is not set
771+# CONFIG_WATCHDOG is not set
772+CONFIG_SSB_POSSIBLE=y
773+
774+#
775+# Sonics Silicon Backplane
776+#
777+# CONFIG_SSB is not set
778+
779+#
780+# Multifunction device drivers
781+#
782+# CONFIG_MFD_CORE is not set
783+# CONFIG_MFD_SM501 is not set
784+# CONFIG_MFD_ASIC3 is not set
785+# CONFIG_HTC_EGPIO is not set
786+# CONFIG_HTC_PASIC3 is not set
787+# CONFIG_TPS65010 is not set
788+CONFIG_TWL4030_CORE=y
789+# CONFIG_TWL4030_POWER is not set
790+# CONFIG_MFD_TMIO is not set
791+# CONFIG_MFD_T7L66XB is not set
792+# CONFIG_MFD_TC6387XB is not set
793+# CONFIG_MFD_TC6393XB is not set
794+# CONFIG_PMIC_DA903X is not set
795+# CONFIG_MFD_WM8400 is not set
796+# CONFIG_MFD_WM8350_I2C is not set
797+# CONFIG_MFD_PCF50633 is not set
798+
799+#
800+# Multimedia devices
801+#
802+
803+#
804+# Multimedia core support
805+#
806+# CONFIG_VIDEO_DEV is not set
807+# CONFIG_DVB_CORE is not set
808+# CONFIG_VIDEO_MEDIA is not set
809+
810+#
811+# Multimedia drivers
812+#
813+CONFIG_DAB=y
814+
815+#
816+# Graphics support
817+#
818+# CONFIG_VGASTATE is not set
819+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
820+CONFIG_FB=y
821+# CONFIG_FIRMWARE_EDID is not set
822+# CONFIG_FB_DDC is not set
823+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
824+CONFIG_FB_CFB_FILLRECT=m
825+CONFIG_FB_CFB_COPYAREA=m
826+CONFIG_FB_CFB_IMAGEBLIT=m
827+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
828+# CONFIG_FB_SYS_FILLRECT is not set
829+# CONFIG_FB_SYS_COPYAREA is not set
830+# CONFIG_FB_SYS_IMAGEBLIT is not set
831+# CONFIG_FB_FOREIGN_ENDIAN is not set
832+# CONFIG_FB_SYS_FOPS is not set
833+# CONFIG_FB_SVGALIB is not set
834+# CONFIG_FB_MACMODES is not set
835+# CONFIG_FB_BACKLIGHT is not set
836+# CONFIG_FB_MODE_HELPERS is not set
837+# CONFIG_FB_TILEBLITTING is not set
838+
839+#
840+# Frame buffer hardware drivers
841+#
842+# CONFIG_FB_S1D13XXX is not set
843+# CONFIG_FB_VIRTUAL is not set
844+# CONFIG_FB_METRONOME is not set
845+# CONFIG_FB_MB862XX is not set
846+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
847+CONFIG_OMAP2_DSS=m
848+CONFIG_OMAP2_DSS_VRAM_SIZE=12
849+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
850+# CONFIG_OMAP2_DSS_RFBI is not set
851+CONFIG_OMAP2_DSS_VENC=y
852+# CONFIG_OMAP2_DSS_SDI is not set
853+# CONFIG_OMAP2_DSS_DSI is not set
854+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
855+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
856+
857+#
858+# OMAP2/3 Display Device Drivers
859+#
860+CONFIG_PANEL_GENERIC=m
861+# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set
862+# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
863+# CONFIG_PANEL_N800 is not set
864+# CONFIG_CTRL_BLIZZARD is not set
865+CONFIG_FB_OMAP2=m
866+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
867+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
868+CONFIG_FB_OMAP2_NUM_FBS=3
869+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
870+
871+#
872+# Display device support
873+#
874+# CONFIG_DISPLAY_SUPPORT is not set
875+
876+#
877+# Console display driver support
878+#
879+# CONFIG_VGA_CONSOLE is not set
880+CONFIG_DUMMY_CONSOLE=y
881+# CONFIG_FRAMEBUFFER_CONSOLE is not set
882+# CONFIG_LOGO is not set
883+# CONFIG_SOUND is not set
884+# CONFIG_HID_SUPPORT is not set
885+CONFIG_USB_SUPPORT=y
886+CONFIG_USB_ARCH_HAS_HCD=y
887+CONFIG_USB_ARCH_HAS_OHCI=y
888+CONFIG_USB_ARCH_HAS_EHCI=y
889+# CONFIG_USB is not set
890+# CONFIG_USB_OTG_WHITELIST is not set
891+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
892+CONFIG_USB_MUSB_HDRC=y
893+CONFIG_USB_MUSB_SOC=y
894+
895+#
896+# OMAP 343x high speed USB support
897+#
898+# CONFIG_USB_MUSB_HOST is not set
899+CONFIG_USB_MUSB_PERIPHERAL=y
900+# CONFIG_USB_MUSB_OTG is not set
901+CONFIG_USB_GADGET_MUSB_HDRC=y
902+# CONFIG_MUSB_PIO_ONLY is not set
903+CONFIG_USB_INVENTRA_DMA=y
904+# CONFIG_USB_TI_CPPI_DMA is not set
905+# CONFIG_USB_MUSB_DEBUG is not set
906+
907+#
908+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
909+#
910+CONFIG_USB_GADGET=y
911+# CONFIG_USB_GADGET_DEBUG is not set
912+# CONFIG_USB_GADGET_DEBUG_FILES is not set
913+# CONFIG_USB_GADGET_DEBUG_FS is not set
914+CONFIG_USB_GADGET_VBUS_DRAW=2
915+CONFIG_USB_GADGET_SELECTED=y
916+# CONFIG_USB_GADGET_AT91 is not set
917+# CONFIG_USB_GADGET_ATMEL_USBA is not set
918+# CONFIG_USB_GADGET_FSL_USB2 is not set
919+# CONFIG_USB_GADGET_LH7A40X is not set
920+# CONFIG_USB_GADGET_OMAP is not set
921+# CONFIG_USB_GADGET_PXA25X is not set
922+# CONFIG_USB_GADGET_PXA27X is not set
923+# CONFIG_USB_GADGET_S3C2410 is not set
924+# CONFIG_USB_GADGET_IMX is not set
925+# CONFIG_USB_GADGET_M66592 is not set
926+# CONFIG_USB_GADGET_AMD5536UDC is not set
927+# CONFIG_USB_GADGET_FSL_QE is not set
928+# CONFIG_USB_GADGET_CI13XXX is not set
929+# CONFIG_USB_GADGET_NET2280 is not set
930+# CONFIG_USB_GADGET_GOKU is not set
931+# CONFIG_USB_GADGET_DUMMY_HCD is not set
932+CONFIG_USB_GADGET_DUALSPEED=y
933+# CONFIG_USB_ZERO is not set
934+CONFIG_USB_ETH=y
935+CONFIG_USB_ETH_RNDIS=y
936+# CONFIG_USB_GADGETFS is not set
937+# CONFIG_USB_FILE_STORAGE is not set
938+# CONFIG_USB_G_SERIAL is not set
939+# CONFIG_USB_MIDI_GADGET is not set
940+# CONFIG_USB_G_PRINTER is not set
941+# CONFIG_USB_CDC_COMPOSITE is not set
942+
943+#
944+# OTG and related infrastructure
945+#
946+CONFIG_USB_OTG_UTILS=y
947+# CONFIG_USB_GPIO_VBUS is not set
948+# CONFIG_ISP1301_OMAP is not set
949+CONFIG_TWL4030_USB=y
950+CONFIG_MMC=y
951+# CONFIG_MMC_DEBUG is not set
952+# CONFIG_MMC_UNSAFE_RESUME is not set
953+
954+#
955+# MMC/SD/SDIO Card Drivers
956+#
957+CONFIG_MMC_BLOCK=y
958+CONFIG_MMC_BLOCK_BOUNCE=y
959+# CONFIG_SDIO_UART is not set
960+# CONFIG_MMC_TEST is not set
961+
962+#
963+# MMC/SD/SDIO Host Controller Drivers
964+#
965+# CONFIG_MMC_SDHCI is not set
966+CONFIG_MMC_OMAP_HS=y
967+# CONFIG_MEMSTICK is not set
968+# CONFIG_ACCESSIBILITY is not set
969+# CONFIG_NEW_LEDS is not set
970+CONFIG_RTC_LIB=y
971+CONFIG_RTC_CLASS=y
972+CONFIG_RTC_HCTOSYS=y
973+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
974+# CONFIG_RTC_DEBUG is not set
975+
976+#
977+# RTC interfaces
978+#
979+CONFIG_RTC_INTF_SYSFS=y
980+CONFIG_RTC_INTF_PROC=y
981+CONFIG_RTC_INTF_DEV=y
982+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
983+# CONFIG_RTC_DRV_TEST is not set
984+
985+#
986+# I2C RTC drivers
987+#
988+# CONFIG_RTC_DRV_DS1307 is not set
989+# CONFIG_RTC_DRV_DS1374 is not set
990+# CONFIG_RTC_DRV_DS1672 is not set
991+# CONFIG_RTC_DRV_MAX6900 is not set
992+# CONFIG_RTC_DRV_RS5C372 is not set
993+# CONFIG_RTC_DRV_ISL1208 is not set
994+# CONFIG_RTC_DRV_X1205 is not set
995+# CONFIG_RTC_DRV_PCF8563 is not set
996+# CONFIG_RTC_DRV_PCF8583 is not set
997+# CONFIG_RTC_DRV_M41T80 is not set
998+CONFIG_RTC_DRV_TWL4030=y
999+# CONFIG_RTC_DRV_S35390A is not set
1000+# CONFIG_RTC_DRV_FM3130 is not set
1001+# CONFIG_RTC_DRV_RX8581 is not set
1002+
1003+#
1004+# SPI RTC drivers
1005+#
1006+
1007+#
1008+# Platform RTC drivers
1009+#
1010+# CONFIG_RTC_DRV_CMOS is not set
1011+# CONFIG_RTC_DRV_DS1286 is not set
1012+# CONFIG_RTC_DRV_DS1511 is not set
1013+# CONFIG_RTC_DRV_DS1553 is not set
1014+# CONFIG_RTC_DRV_DS1742 is not set
1015+# CONFIG_RTC_DRV_STK17TA8 is not set
1016+# CONFIG_RTC_DRV_M48T86 is not set
1017+# CONFIG_RTC_DRV_M48T35 is not set
1018+# CONFIG_RTC_DRV_M48T59 is not set
1019+# CONFIG_RTC_DRV_BQ4802 is not set
1020+# CONFIG_RTC_DRV_V3020 is not set
1021+
1022+#
1023+# on-CPU RTC drivers
1024+#
1025+# CONFIG_DMADEVICES is not set
1026+CONFIG_REGULATOR=y
1027+# CONFIG_REGULATOR_DEBUG is not set
1028+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
1029+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
1030+# CONFIG_REGULATOR_BQ24022 is not set
1031+CONFIG_REGULATOR_TWL4030=y
1032+# CONFIG_UIO is not set
1033+# CONFIG_STAGING is not set
1034+
1035+#
1036+# CBUS support
1037+#
1038+# CONFIG_CBUS is not set
1039+
1040+#
1041+# File systems
1042+#
1043+CONFIG_EXT2_FS=y
1044+# CONFIG_EXT2_FS_XATTR is not set
1045+# CONFIG_EXT2_FS_XIP is not set
1046+CONFIG_EXT3_FS=y
1047+# CONFIG_EXT3_FS_XATTR is not set
1048+# CONFIG_EXT4_FS is not set
1049+CONFIG_JBD=y
1050+# CONFIG_JBD_DEBUG is not set
1051+# CONFIG_REISERFS_FS is not set
1052+# CONFIG_JFS_FS is not set
1053+# CONFIG_FS_POSIX_ACL is not set
1054+CONFIG_FILE_LOCKING=y
1055+# CONFIG_XFS_FS is not set
1056+# CONFIG_OCFS2_FS is not set
1057+# CONFIG_BTRFS_FS is not set
1058+CONFIG_DNOTIFY=y
1059+CONFIG_INOTIFY=y
1060+CONFIG_INOTIFY_USER=y
1061+CONFIG_QUOTA=y
1062+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
1063+CONFIG_PRINT_QUOTA_WARNING=y
1064+CONFIG_QUOTA_TREE=y
1065+# CONFIG_QFMT_V1 is not set
1066+CONFIG_QFMT_V2=y
1067+CONFIG_QUOTACTL=y
1068+# CONFIG_AUTOFS_FS is not set
1069+# CONFIG_AUTOFS4_FS is not set
1070+# CONFIG_FUSE_FS is not set
1071+
1072+#
1073+# CD-ROM/DVD Filesystems
1074+#
1075+# CONFIG_ISO9660_FS is not set
1076+# CONFIG_UDF_FS is not set
1077+
1078+#
1079+# DOS/FAT/NT Filesystems
1080+#
1081+CONFIG_FAT_FS=y
1082+CONFIG_MSDOS_FS=y
1083+CONFIG_VFAT_FS=y
1084+CONFIG_FAT_DEFAULT_CODEPAGE=437
1085+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1086+# CONFIG_NTFS_FS is not set
1087+
1088+#
1089+# Pseudo filesystems
1090+#
1091+CONFIG_PROC_FS=y
1092+CONFIG_PROC_SYSCTL=y
1093+CONFIG_PROC_PAGE_MONITOR=y
1094+CONFIG_SYSFS=y
1095+CONFIG_TMPFS=y
1096+# CONFIG_TMPFS_POSIX_ACL is not set
1097+# CONFIG_HUGETLB_PAGE is not set
1098+# CONFIG_CONFIGFS_FS is not set
1099+CONFIG_MISC_FILESYSTEMS=y
1100+# CONFIG_ADFS_FS is not set
1101+# CONFIG_AFFS_FS is not set
1102+# CONFIG_HFS_FS is not set
1103+# CONFIG_HFSPLUS_FS is not set
1104+# CONFIG_BEFS_FS is not set
1105+# CONFIG_BFS_FS is not set
1106+# CONFIG_EFS_FS is not set
1107+CONFIG_JFFS2_FS=y
1108+CONFIG_JFFS2_FS_DEBUG=0
1109+CONFIG_JFFS2_FS_WRITEBUFFER=y
1110+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1111+# CONFIG_JFFS2_SUMMARY is not set
1112+# CONFIG_JFFS2_FS_XATTR is not set
1113+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1114+CONFIG_JFFS2_ZLIB=y
1115+# CONFIG_JFFS2_LZO is not set
1116+CONFIG_JFFS2_RTIME=y
1117+# CONFIG_JFFS2_RUBIN is not set
1118+# CONFIG_CRAMFS is not set
1119+# CONFIG_SQUASHFS is not set
1120+# CONFIG_VXFS_FS is not set
1121+# CONFIG_MINIX_FS is not set
1122+# CONFIG_OMFS_FS is not set
1123+# CONFIG_HPFS_FS is not set
1124+# CONFIG_QNX4FS_FS is not set
1125+# CONFIG_ROMFS_FS is not set
1126+# CONFIG_SYSV_FS is not set
1127+# CONFIG_UFS_FS is not set
1128+CONFIG_NETWORK_FILESYSTEMS=y
1129+CONFIG_NFS_FS=y
1130+CONFIG_NFS_V3=y
1131+# CONFIG_NFS_V3_ACL is not set
1132+CONFIG_NFS_V4=y
1133+CONFIG_ROOT_NFS=y
1134+# CONFIG_NFSD is not set
1135+CONFIG_LOCKD=y
1136+CONFIG_LOCKD_V4=y
1137+CONFIG_NFS_COMMON=y
1138+CONFIG_SUNRPC=y
1139+CONFIG_SUNRPC_GSS=y
1140+# CONFIG_SUNRPC_REGISTER_V4 is not set
1141+CONFIG_RPCSEC_GSS_KRB5=y
1142+# CONFIG_RPCSEC_GSS_SPKM3 is not set
1143+# CONFIG_SMB_FS is not set
1144+# CONFIG_CIFS is not set
1145+# CONFIG_NCP_FS is not set
1146+# CONFIG_CODA_FS is not set
1147+# CONFIG_AFS_FS is not set
1148+
1149+#
1150+# Partition Types
1151+#
1152+CONFIG_PARTITION_ADVANCED=y
1153+# CONFIG_ACORN_PARTITION is not set
1154+# CONFIG_OSF_PARTITION is not set
1155+# CONFIG_AMIGA_PARTITION is not set
1156+# CONFIG_ATARI_PARTITION is not set
1157+# CONFIG_MAC_PARTITION is not set
1158+CONFIG_MSDOS_PARTITION=y
1159+# CONFIG_BSD_DISKLABEL is not set
1160+# CONFIG_MINIX_SUBPARTITION is not set
1161+# CONFIG_SOLARIS_X86_PARTITION is not set
1162+# CONFIG_UNIXWARE_DISKLABEL is not set
1163+# CONFIG_LDM_PARTITION is not set
1164+# CONFIG_SGI_PARTITION is not set
1165+# CONFIG_ULTRIX_PARTITION is not set
1166+# CONFIG_SUN_PARTITION is not set
1167+# CONFIG_KARMA_PARTITION is not set
1168+# CONFIG_EFI_PARTITION is not set
1169+# CONFIG_SYSV68_PARTITION is not set
1170+CONFIG_NLS=y
1171+CONFIG_NLS_DEFAULT="iso8859-1"
1172+CONFIG_NLS_CODEPAGE_437=y
1173+# CONFIG_NLS_CODEPAGE_737 is not set
1174+# CONFIG_NLS_CODEPAGE_775 is not set
1175+# CONFIG_NLS_CODEPAGE_850 is not set
1176+# CONFIG_NLS_CODEPAGE_852 is not set
1177+# CONFIG_NLS_CODEPAGE_855 is not set
1178+# CONFIG_NLS_CODEPAGE_857 is not set
1179+# CONFIG_NLS_CODEPAGE_860 is not set
1180+# CONFIG_NLS_CODEPAGE_861 is not set
1181+# CONFIG_NLS_CODEPAGE_862 is not set
1182+# CONFIG_NLS_CODEPAGE_863 is not set
1183+# CONFIG_NLS_CODEPAGE_864 is not set
1184+# CONFIG_NLS_CODEPAGE_865 is not set
1185+# CONFIG_NLS_CODEPAGE_866 is not set
1186+# CONFIG_NLS_CODEPAGE_869 is not set
1187+# CONFIG_NLS_CODEPAGE_936 is not set
1188+# CONFIG_NLS_CODEPAGE_950 is not set
1189+# CONFIG_NLS_CODEPAGE_932 is not set
1190+# CONFIG_NLS_CODEPAGE_949 is not set
1191+# CONFIG_NLS_CODEPAGE_874 is not set
1192+# CONFIG_NLS_ISO8859_8 is not set
1193+# CONFIG_NLS_CODEPAGE_1250 is not set
1194+# CONFIG_NLS_CODEPAGE_1251 is not set
1195+# CONFIG_NLS_ASCII is not set
1196+CONFIG_NLS_ISO8859_1=y
1197+# CONFIG_NLS_ISO8859_2 is not set
1198+# CONFIG_NLS_ISO8859_3 is not set
1199+# CONFIG_NLS_ISO8859_4 is not set
1200+# CONFIG_NLS_ISO8859_5 is not set
1201+# CONFIG_NLS_ISO8859_6 is not set
1202+# CONFIG_NLS_ISO8859_7 is not set
1203+# CONFIG_NLS_ISO8859_9 is not set
1204+# CONFIG_NLS_ISO8859_13 is not set
1205+# CONFIG_NLS_ISO8859_14 is not set
1206+# CONFIG_NLS_ISO8859_15 is not set
1207+# CONFIG_NLS_KOI8_R is not set
1208+# CONFIG_NLS_KOI8_U is not set
1209+# CONFIG_NLS_UTF8 is not set
1210+# CONFIG_DLM is not set
1211+
1212+#
1213+# Kernel hacking
1214+#
1215+# CONFIG_PRINTK_TIME is not set
1216+CONFIG_ENABLE_WARN_DEPRECATED=y
1217+CONFIG_ENABLE_MUST_CHECK=y
1218+CONFIG_FRAME_WARN=1024
1219+CONFIG_MAGIC_SYSRQ=y
1220+# CONFIG_UNUSED_SYMBOLS is not set
1221+CONFIG_DEBUG_FS=y
1222+# CONFIG_HEADERS_CHECK is not set
1223+CONFIG_DEBUG_KERNEL=y
1224+# CONFIG_DEBUG_SHIRQ is not set
1225+CONFIG_DETECT_SOFTLOCKUP=y
1226+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1227+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1228+CONFIG_SCHED_DEBUG=y
1229+# CONFIG_SCHEDSTATS is not set
1230+# CONFIG_TIMER_STATS is not set
1231+# CONFIG_DEBUG_OBJECTS is not set
1232+# CONFIG_DEBUG_SLAB is not set
1233+# CONFIG_DEBUG_RT_MUTEXES is not set
1234+# CONFIG_RT_MUTEX_TESTER is not set
1235+# CONFIG_DEBUG_SPINLOCK is not set
1236+CONFIG_DEBUG_MUTEXES=y
1237+# CONFIG_DEBUG_LOCK_ALLOC is not set
1238+# CONFIG_PROVE_LOCKING is not set
1239+# CONFIG_LOCK_STAT is not set
1240+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1241+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1242+# CONFIG_DEBUG_KOBJECT is not set
1243+CONFIG_DEBUG_BUGVERBOSE=y
1244+CONFIG_DEBUG_INFO=y
1245+# CONFIG_DEBUG_VM is not set
1246+# CONFIG_DEBUG_WRITECOUNT is not set
1247+# CONFIG_DEBUG_MEMORY_INIT is not set
1248+# CONFIG_DEBUG_LIST is not set
1249+# CONFIG_DEBUG_SG is not set
1250+# CONFIG_DEBUG_NOTIFIERS is not set
1251+CONFIG_FRAME_POINTER=y
1252+# CONFIG_BOOT_PRINTK_DELAY is not set
1253+# CONFIG_RCU_TORTURE_TEST is not set
1254+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1255+# CONFIG_BACKTRACE_SELF_TEST is not set
1256+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1257+# CONFIG_FAULT_INJECTION is not set
1258+# CONFIG_LATENCYTOP is not set
1259+CONFIG_HAVE_FUNCTION_TRACER=y
1260+
1261+#
1262+# Tracers
1263+#
1264+# CONFIG_FUNCTION_TRACER is not set
1265+# CONFIG_IRQSOFF_TRACER is not set
1266+# CONFIG_SCHED_TRACER is not set
1267+# CONFIG_CONTEXT_SWITCH_TRACER is not set
1268+# CONFIG_BOOT_TRACER is not set
1269+# CONFIG_TRACE_BRANCH_PROFILING is not set
1270+# CONFIG_STACK_TRACER is not set
1271+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1272+# CONFIG_SAMPLES is not set
1273+CONFIG_HAVE_ARCH_KGDB=y
1274+# CONFIG_KGDB is not set
1275+CONFIG_DEBUG_USER=y
1276+CONFIG_DEBUG_ERRORS=y
1277+# CONFIG_DEBUG_STACK_USAGE is not set
1278+# CONFIG_DEBUG_LL is not set
1279+
1280+#
1281+# Security options
1282+#
1283+# CONFIG_KEYS is not set
1284+# CONFIG_SECURITY is not set
1285+# CONFIG_SECURITYFS is not set
1286+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1287+CONFIG_CRYPTO=y
1288+
1289+#
1290+# Crypto core or helper
1291+#
1292+# CONFIG_CRYPTO_FIPS is not set
1293+CONFIG_CRYPTO_ALGAPI=y
1294+CONFIG_CRYPTO_ALGAPI2=y
1295+CONFIG_CRYPTO_AEAD2=y
1296+CONFIG_CRYPTO_BLKCIPHER=y
1297+CONFIG_CRYPTO_BLKCIPHER2=y
1298+CONFIG_CRYPTO_HASH=y
1299+CONFIG_CRYPTO_HASH2=y
1300+CONFIG_CRYPTO_RNG2=y
1301+CONFIG_CRYPTO_MANAGER=y
1302+CONFIG_CRYPTO_MANAGER2=y
1303+# CONFIG_CRYPTO_GF128MUL is not set
1304+# CONFIG_CRYPTO_NULL is not set
1305+# CONFIG_CRYPTO_CRYPTD is not set
1306+# CONFIG_CRYPTO_AUTHENC is not set
1307+# CONFIG_CRYPTO_TEST is not set
1308+
1309+#
1310+# Authenticated Encryption with Associated Data
1311+#
1312+# CONFIG_CRYPTO_CCM is not set
1313+# CONFIG_CRYPTO_GCM is not set
1314+# CONFIG_CRYPTO_SEQIV is not set
1315+
1316+#
1317+# Block modes
1318+#
1319+CONFIG_CRYPTO_CBC=y
1320+# CONFIG_CRYPTO_CTR is not set
1321+# CONFIG_CRYPTO_CTS is not set
1322+CONFIG_CRYPTO_ECB=m
1323+# CONFIG_CRYPTO_LRW is not set
1324+CONFIG_CRYPTO_PCBC=m
1325+# CONFIG_CRYPTO_XTS is not set
1326+
1327+#
1328+# Hash modes
1329+#
1330+# CONFIG_CRYPTO_HMAC is not set
1331+# CONFIG_CRYPTO_XCBC is not set
1332+
1333+#
1334+# Digest
1335+#
1336+CONFIG_CRYPTO_CRC32C=y
1337+# CONFIG_CRYPTO_MD4 is not set
1338+CONFIG_CRYPTO_MD5=y
1339+# CONFIG_CRYPTO_MICHAEL_MIC is not set
1340+# CONFIG_CRYPTO_RMD128 is not set
1341+# CONFIG_CRYPTO_RMD160 is not set
1342+# CONFIG_CRYPTO_RMD256 is not set
1343+# CONFIG_CRYPTO_RMD320 is not set
1344+# CONFIG_CRYPTO_SHA1 is not set
1345+# CONFIG_CRYPTO_SHA256 is not set
1346+# CONFIG_CRYPTO_SHA512 is not set
1347+# CONFIG_CRYPTO_TGR192 is not set
1348+# CONFIG_CRYPTO_WP512 is not set
1349+
1350+#
1351+# Ciphers
1352+#
1353+# CONFIG_CRYPTO_AES is not set
1354+# CONFIG_CRYPTO_ANUBIS is not set
1355+# CONFIG_CRYPTO_ARC4 is not set
1356+# CONFIG_CRYPTO_BLOWFISH is not set
1357+# CONFIG_CRYPTO_CAMELLIA is not set
1358+# CONFIG_CRYPTO_CAST5 is not set
1359+# CONFIG_CRYPTO_CAST6 is not set
1360+CONFIG_CRYPTO_DES=y
1361+# CONFIG_CRYPTO_FCRYPT is not set
1362+# CONFIG_CRYPTO_KHAZAD is not set
1363+# CONFIG_CRYPTO_SALSA20 is not set
1364+# CONFIG_CRYPTO_SEED is not set
1365+# CONFIG_CRYPTO_SERPENT is not set
1366+# CONFIG_CRYPTO_TEA is not set
1367+# CONFIG_CRYPTO_TWOFISH is not set
1368+
1369+#
1370+# Compression
1371+#
1372+# CONFIG_CRYPTO_DEFLATE is not set
1373+# CONFIG_CRYPTO_LZO is not set
1374+
1375+#
1376+# Random Number Generation
1377+#
1378+# CONFIG_CRYPTO_ANSI_CPRNG is not set
1379+CONFIG_CRYPTO_HW=y
1380+
1381+#
1382+# Library routines
1383+#
1384+CONFIG_BITREVERSE=y
1385+CONFIG_GENERIC_FIND_LAST_BIT=y
1386+CONFIG_CRC_CCITT=y
1387+# CONFIG_CRC16 is not set
1388+# CONFIG_CRC_T10DIF is not set
1389+# CONFIG_CRC_ITU_T is not set
1390+CONFIG_CRC32=y
1391+# CONFIG_CRC7 is not set
1392+CONFIG_LIBCRC32C=y
1393+CONFIG_ZLIB_INFLATE=y
1394+CONFIG_ZLIB_DEFLATE=y
1395+CONFIG_PLIST=y
1396+CONFIG_HAS_IOMEM=y
1397+CONFIG_HAS_IOPORT=y
1398+CONFIG_HAS_DMA=y
1399diff --git a/arch/arm/configs/dss_omap_3430sdp_defconfig b/arch/arm/configs/dss_omap_3430sdp_defconfig
1400new file mode 100644
1401index 0000000..dc30dce
1402--- /dev/null
1403+++ b/arch/arm/configs/dss_omap_3430sdp_defconfig
1404@@ -0,0 +1,1634 @@
1405+#
1406+# Automatically generated make config: don't edit
1407+# Linux kernel version: 2.6.29-omap1
1408+# Thu Apr 2 11:11:24 2009
1409+#
1410+CONFIG_ARM=y
1411+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
1412+CONFIG_GENERIC_GPIO=y
1413+CONFIG_GENERIC_TIME=y
1414+CONFIG_GENERIC_CLOCKEVENTS=y
1415+CONFIG_MMU=y
1416+# CONFIG_NO_IOPORT is not set
1417+CONFIG_GENERIC_HARDIRQS=y
1418+CONFIG_STACKTRACE_SUPPORT=y
1419+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
1420+CONFIG_LOCKDEP_SUPPORT=y
1421+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1422+CONFIG_HARDIRQS_SW_RESEND=y
1423+CONFIG_GENERIC_IRQ_PROBE=y
1424+CONFIG_RWSEM_GENERIC_SPINLOCK=y
1425+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
1426+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
1427+CONFIG_GENERIC_HWEIGHT=y
1428+CONFIG_GENERIC_CALIBRATE_DELAY=y
1429+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
1430+CONFIG_VECTORS_BASE=0xffff0000
1431+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
1432+
1433+#
1434+# General setup
1435+#
1436+CONFIG_EXPERIMENTAL=y
1437+CONFIG_BROKEN_ON_SMP=y
1438+CONFIG_INIT_ENV_ARG_LIMIT=32
1439+CONFIG_LOCALVERSION=""
1440+CONFIG_LOCALVERSION_AUTO=y
1441+CONFIG_SWAP=y
1442+CONFIG_SYSVIPC=y
1443+CONFIG_SYSVIPC_SYSCTL=y
1444+# CONFIG_POSIX_MQUEUE is not set
1445+CONFIG_BSD_PROCESS_ACCT=y
1446+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
1447+# CONFIG_TASKSTATS is not set
1448+# CONFIG_AUDIT is not set
1449+
1450+#
1451+# RCU Subsystem
1452+#
1453+CONFIG_CLASSIC_RCU=y
1454+# CONFIG_TREE_RCU is not set
1455+# CONFIG_PREEMPT_RCU is not set
1456+# CONFIG_TREE_RCU_TRACE is not set
1457+# CONFIG_PREEMPT_RCU_TRACE is not set
1458+# CONFIG_IKCONFIG is not set
1459+CONFIG_LOG_BUF_SHIFT=14
1460+CONFIG_GROUP_SCHED=y
1461+CONFIG_FAIR_GROUP_SCHED=y
1462+# CONFIG_RT_GROUP_SCHED is not set
1463+CONFIG_USER_SCHED=y
1464+# CONFIG_CGROUP_SCHED is not set
1465+# CONFIG_CGROUPS is not set
1466+CONFIG_SYSFS_DEPRECATED=y
1467+CONFIG_SYSFS_DEPRECATED_V2=y
1468+# CONFIG_RELAY is not set
1469+# CONFIG_NAMESPACES is not set
1470+CONFIG_BLK_DEV_INITRD=y
1471+CONFIG_INITRAMFS_SOURCE=""
1472+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
1473+CONFIG_SYSCTL=y
1474+CONFIG_ANON_INODES=y
1475+CONFIG_EMBEDDED=y
1476+CONFIG_UID16=y
1477+# CONFIG_SYSCTL_SYSCALL is not set
1478+CONFIG_KALLSYMS=y
1479+# CONFIG_KALLSYMS_ALL is not set
1480+CONFIG_KALLSYMS_EXTRA_PASS=y
1481+CONFIG_HOTPLUG=y
1482+CONFIG_PRINTK=y
1483+CONFIG_BUG=y
1484+CONFIG_ELF_CORE=y
1485+CONFIG_BASE_FULL=y
1486+CONFIG_FUTEX=y
1487+CONFIG_EPOLL=y
1488+CONFIG_SIGNALFD=y
1489+CONFIG_TIMERFD=y
1490+CONFIG_EVENTFD=y
1491+CONFIG_SHMEM=y
1492+CONFIG_AIO=y
1493+CONFIG_VM_EVENT_COUNTERS=y
1494+CONFIG_COMPAT_BRK=y
1495+CONFIG_SLAB=y
1496+# CONFIG_SLUB is not set
1497+# CONFIG_SLOB is not set
1498+# CONFIG_PROFILING is not set
1499+CONFIG_HAVE_OPROFILE=y
1500+# CONFIG_KPROBES is not set
1501+CONFIG_HAVE_KPROBES=y
1502+CONFIG_HAVE_KRETPROBES=y
1503+CONFIG_HAVE_CLK=y
1504+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
1505+CONFIG_SLABINFO=y
1506+CONFIG_RT_MUTEXES=y
1507+CONFIG_BASE_SMALL=0
1508+CONFIG_MODULES=y
1509+# CONFIG_MODULE_FORCE_LOAD is not set
1510+CONFIG_MODULE_UNLOAD=y
1511+# CONFIG_MODULE_FORCE_UNLOAD is not set
1512+CONFIG_MODVERSIONS=y
1513+CONFIG_MODULE_SRCVERSION_ALL=y
1514+CONFIG_BLOCK=y
1515+# CONFIG_LBD is not set
1516+# CONFIG_BLK_DEV_IO_TRACE is not set
1517+# CONFIG_BLK_DEV_BSG is not set
1518+# CONFIG_BLK_DEV_INTEGRITY is not set
1519+
1520+#
1521+# IO Schedulers
1522+#
1523+CONFIG_IOSCHED_NOOP=y
1524+CONFIG_IOSCHED_AS=y
1525+CONFIG_IOSCHED_DEADLINE=y
1526+CONFIG_IOSCHED_CFQ=y
1527+CONFIG_DEFAULT_AS=y
1528+# CONFIG_DEFAULT_DEADLINE is not set
1529+# CONFIG_DEFAULT_CFQ is not set
1530+# CONFIG_DEFAULT_NOOP is not set
1531+CONFIG_DEFAULT_IOSCHED="anticipatory"
1532+CONFIG_FREEZER=y
1533+
1534+#
1535+# System Type
1536+#
1537+# CONFIG_ARCH_AAEC2000 is not set
1538+# CONFIG_ARCH_INTEGRATOR is not set
1539+# CONFIG_ARCH_REALVIEW is not set
1540+# CONFIG_ARCH_VERSATILE is not set
1541+# CONFIG_ARCH_AT91 is not set
1542+# CONFIG_ARCH_CLPS711X is not set
1543+# CONFIG_ARCH_EBSA110 is not set
1544+# CONFIG_ARCH_EP93XX is not set
1545+# CONFIG_ARCH_FOOTBRIDGE is not set
1546+# CONFIG_ARCH_NETX is not set
1547+# CONFIG_ARCH_H720X is not set
1548+# CONFIG_ARCH_IMX is not set
1549+# CONFIG_ARCH_IOP13XX is not set
1550+# CONFIG_ARCH_IOP32X is not set
1551+# CONFIG_ARCH_IOP33X is not set
1552+# CONFIG_ARCH_IXP23XX is not set
1553+# CONFIG_ARCH_IXP2000 is not set
1554+# CONFIG_ARCH_IXP4XX is not set
1555+# CONFIG_ARCH_L7200 is not set
1556+# CONFIG_ARCH_KIRKWOOD is not set
1557+# CONFIG_ARCH_KS8695 is not set
1558+# CONFIG_ARCH_NS9XXX is not set
1559+# CONFIG_ARCH_LOKI is not set
1560+# CONFIG_ARCH_MV78XX0 is not set
1561+# CONFIG_ARCH_MXC is not set
1562+# CONFIG_ARCH_ORION5X is not set
1563+# CONFIG_ARCH_PNX4008 is not set
1564+# CONFIG_ARCH_PXA is not set
1565+# CONFIG_ARCH_RPC is not set
1566+# CONFIG_ARCH_SA1100 is not set
1567+# CONFIG_ARCH_S3C2410 is not set
1568+# CONFIG_ARCH_S3C64XX is not set
1569+# CONFIG_ARCH_SHARK is not set
1570+# CONFIG_ARCH_LH7A40X is not set
1571+# CONFIG_ARCH_DAVINCI is not set
1572+CONFIG_ARCH_OMAP=y
1573+# CONFIG_ARCH_MSM is not set
1574+# CONFIG_ARCH_W90X900 is not set
1575+
1576+#
1577+# TI OMAP Implementations
1578+#
1579+CONFIG_ARCH_OMAP_OTG=y
1580+# CONFIG_ARCH_OMAP1 is not set
1581+# CONFIG_ARCH_OMAP2 is not set
1582+CONFIG_ARCH_OMAP3=y
1583+
1584+#
1585+# OMAP Feature Selections
1586+#
1587+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
1588+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
1589+CONFIG_OMAP_SMARTREFLEX=y
1590+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
1591+CONFIG_OMAP_RESET_CLOCKS=y
1592+CONFIG_OMAP_BOOT_TAG=y
1593+CONFIG_OMAP_BOOT_REASON=y
1594+# CONFIG_OMAP_COMPONENT_VERSION is not set
1595+# CONFIG_OMAP_GPIO_SWITCH is not set
1596+CONFIG_OMAP_MUX=y
1597+CONFIG_OMAP_MUX_DEBUG=y
1598+CONFIG_OMAP_MUX_WARNINGS=y
1599+# CONFIG_OMAP_MCBSP is not set
1600+# CONFIG_OMAP_MBOX_FWK is not set
1601+# CONFIG_OMAP_MPU_TIMER is not set
1602+CONFIG_OMAP_32K_TIMER=y
1603+CONFIG_OMAP_32K_TIMER_HZ=128
1604+CONFIG_OMAP_TICK_GPTIMER=1
1605+CONFIG_OMAP_DM_TIMER=y
1606+CONFIG_OMAP_LL_DEBUG_UART1=y
1607+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
1608+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
1609+CONFIG_OMAP_SERIAL_WAKE=y
1610+CONFIG_ARCH_OMAP34XX=y
1611+CONFIG_ARCH_OMAP3430=y
1612+
1613+#
1614+# OMAP Board Type
1615+#
1616+# CONFIG_MACH_NOKIA_RX51 is not set
1617+# CONFIG_MACH_OMAP_LDP is not set
1618+CONFIG_MACH_OMAP_3430SDP=y
1619+# CONFIG_MACH_OMAP3EVM is not set
1620+# CONFIG_MACH_OMAP3_BEAGLE is not set
1621+# CONFIG_MACH_OVERO is not set
1622+# CONFIG_MACH_OMAP3_PANDORA is not set
1623+
1624+#
1625+# Processor Type
1626+#
1627+CONFIG_CPU_32=y
1628+CONFIG_CPU_32v6K=y
1629+CONFIG_CPU_V7=y
1630+CONFIG_CPU_32v7=y
1631+CONFIG_CPU_ABRT_EV7=y
1632+CONFIG_CPU_PABRT_IFAR=y
1633+CONFIG_CPU_CACHE_V7=y
1634+CONFIG_CPU_CACHE_VIPT=y
1635+CONFIG_CPU_COPY_V6=y
1636+CONFIG_CPU_TLB_V7=y
1637+CONFIG_CPU_HAS_ASID=y
1638+CONFIG_CPU_CP15=y
1639+CONFIG_CPU_CP15_MMU=y
1640+
1641+#
1642+# Processor Features
1643+#
1644+CONFIG_ARM_THUMB=y
1645+# CONFIG_ARM_THUMBEE is not set
1646+# CONFIG_CPU_ICACHE_DISABLE is not set
1647+# CONFIG_CPU_DCACHE_DISABLE is not set
1648+# CONFIG_CPU_BPREDICT_DISABLE is not set
1649+CONFIG_HAS_TLS_REG=y
1650+# CONFIG_OUTER_CACHE is not set
1651+
1652+#
1653+# Bus support
1654+#
1655+# CONFIG_PCI_SYSCALL is not set
1656+# CONFIG_ARCH_SUPPORTS_MSI is not set
1657+# CONFIG_PCCARD is not set
1658+
1659+#
1660+# Kernel Features
1661+#
1662+CONFIG_TICK_ONESHOT=y
1663+CONFIG_NO_HZ=y
1664+CONFIG_HIGH_RES_TIMERS=y
1665+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
1666+CONFIG_VMSPLIT_3G=y
1667+# CONFIG_VMSPLIT_2G is not set
1668+# CONFIG_VMSPLIT_1G is not set
1669+CONFIG_PAGE_OFFSET=0xC0000000
1670+# CONFIG_PREEMPT is not set
1671+CONFIG_HZ=128
1672+CONFIG_AEABI=y
1673+CONFIG_OABI_COMPAT=y
1674+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
1675+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
1676+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
1677+CONFIG_SELECT_MEMORY_MODEL=y
1678+CONFIG_FLATMEM_MANUAL=y
1679+# CONFIG_DISCONTIGMEM_MANUAL is not set
1680+# CONFIG_SPARSEMEM_MANUAL is not set
1681+CONFIG_FLATMEM=y
1682+CONFIG_FLAT_NODE_MEM_MAP=y
1683+CONFIG_PAGEFLAGS_EXTENDED=y
1684+CONFIG_SPLIT_PTLOCK_CPUS=4
1685+# CONFIG_PHYS_ADDR_T_64BIT is not set
1686+CONFIG_ZONE_DMA_FLAG=0
1687+CONFIG_VIRT_TO_BUS=y
1688+CONFIG_UNEVICTABLE_LRU=y
1689+# CONFIG_LEDS is not set
1690+CONFIG_ALIGNMENT_TRAP=y
1691+
1692+#
1693+# Boot options
1694+#
1695+CONFIG_ZBOOT_ROM_TEXT=0x0
1696+CONFIG_ZBOOT_ROM_BSS=0x0
1697+CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
1698+# CONFIG_XIP_KERNEL is not set
1699+# CONFIG_KEXEC is not set
1700+
1701+#
1702+# CPU Power Management
1703+#
1704+# CONFIG_CPU_FREQ is not set
1705+# CONFIG_CPU_IDLE is not set
1706+
1707+#
1708+# Floating point emulation
1709+#
1710+
1711+#
1712+# At least one emulation must be selected
1713+#
1714+CONFIG_FPE_NWFPE=y
1715+# CONFIG_FPE_NWFPE_XP is not set
1716+# CONFIG_FPE_FASTFPE is not set
1717+CONFIG_VFP=y
1718+CONFIG_VFPv3=y
1719+# CONFIG_NEON is not set
1720+
1721+#
1722+# Userspace binary formats
1723+#
1724+CONFIG_BINFMT_ELF=y
1725+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
1726+CONFIG_HAVE_AOUT=y
1727+# CONFIG_BINFMT_AOUT is not set
1728+CONFIG_BINFMT_MISC=y
1729+
1730+#
1731+# Power management options
1732+#
1733+CONFIG_PM=y
1734+# CONFIG_PM_DEBUG is not set
1735+CONFIG_PM_SLEEP=y
1736+CONFIG_SUSPEND=y
1737+CONFIG_SUSPEND_FREEZER=y
1738+# CONFIG_APM_EMULATION is not set
1739+CONFIG_ARCH_SUSPEND_POSSIBLE=y
1740+CONFIG_NET=y
1741+
1742+#
1743+# Networking options
1744+#
1745+CONFIG_COMPAT_NET_DEV_OPS=y
1746+CONFIG_PACKET=y
1747+# CONFIG_PACKET_MMAP is not set
1748+CONFIG_UNIX=y
1749+CONFIG_XFRM=y
1750+# CONFIG_XFRM_USER is not set
1751+# CONFIG_XFRM_SUB_POLICY is not set
1752+# CONFIG_XFRM_MIGRATE is not set
1753+# CONFIG_XFRM_STATISTICS is not set
1754+CONFIG_NET_KEY=y
1755+# CONFIG_NET_KEY_MIGRATE is not set
1756+CONFIG_INET=y
1757+# CONFIG_IP_MULTICAST is not set
1758+# CONFIG_IP_ADVANCED_ROUTER is not set
1759+CONFIG_IP_FIB_HASH=y
1760+CONFIG_IP_PNP=y
1761+CONFIG_IP_PNP_DHCP=y
1762+CONFIG_IP_PNP_BOOTP=y
1763+CONFIG_IP_PNP_RARP=y
1764+# CONFIG_NET_IPIP is not set
1765+# CONFIG_NET_IPGRE is not set
1766+# CONFIG_ARPD is not set
1767+# CONFIG_SYN_COOKIES is not set
1768+# CONFIG_INET_AH is not set
1769+# CONFIG_INET_ESP is not set
1770+# CONFIG_INET_IPCOMP is not set
1771+# CONFIG_INET_XFRM_TUNNEL is not set
1772+# CONFIG_INET_TUNNEL is not set
1773+CONFIG_INET_XFRM_MODE_TRANSPORT=y
1774+CONFIG_INET_XFRM_MODE_TUNNEL=y
1775+CONFIG_INET_XFRM_MODE_BEET=y
1776+# CONFIG_INET_LRO is not set
1777+CONFIG_INET_DIAG=y
1778+CONFIG_INET_TCP_DIAG=y
1779+# CONFIG_TCP_CONG_ADVANCED is not set
1780+CONFIG_TCP_CONG_CUBIC=y
1781+CONFIG_DEFAULT_TCP_CONG="cubic"
1782+# CONFIG_TCP_MD5SIG is not set
1783+# CONFIG_IPV6 is not set
1784+# CONFIG_NETWORK_SECMARK is not set
1785+# CONFIG_NETFILTER is not set
1786+# CONFIG_IP_DCCP is not set
1787+# CONFIG_IP_SCTP is not set
1788+# CONFIG_TIPC is not set
1789+# CONFIG_ATM is not set
1790+# CONFIG_BRIDGE is not set
1791+# CONFIG_NET_DSA is not set
1792+# CONFIG_VLAN_8021Q is not set
1793+# CONFIG_DECNET is not set
1794+# CONFIG_LLC2 is not set
1795+# CONFIG_IPX is not set
1796+# CONFIG_ATALK is not set
1797+# CONFIG_X25 is not set
1798+# CONFIG_LAPB is not set
1799+# CONFIG_ECONET is not set
1800+# CONFIG_WAN_ROUTER is not set
1801+# CONFIG_NET_SCHED is not set
1802+# CONFIG_DCB is not set
1803+
1804+#
1805+# Network testing
1806+#
1807+# CONFIG_NET_PKTGEN is not set
1808+# CONFIG_HAMRADIO is not set
1809+# CONFIG_CAN is not set
1810+# CONFIG_IRDA is not set
1811+# CONFIG_BT is not set
1812+# CONFIG_AF_RXRPC is not set
1813+# CONFIG_PHONET is not set
1814+CONFIG_WIRELESS=y
1815+# CONFIG_CFG80211 is not set
1816+CONFIG_WIRELESS_OLD_REGULATORY=y
1817+# CONFIG_WIRELESS_EXT is not set
1818+# CONFIG_LIB80211 is not set
1819+# CONFIG_MAC80211 is not set
1820+# CONFIG_WIMAX is not set
1821+# CONFIG_RFKILL is not set
1822+# CONFIG_NET_9P is not set
1823+
1824+#
1825+# Device Drivers
1826+#
1827+
1828+#
1829+# Generic Driver Options
1830+#
1831+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1832+CONFIG_STANDALONE=y
1833+CONFIG_PREVENT_FIRMWARE_BUILD=y
1834+# CONFIG_FW_LOADER is not set
1835+# CONFIG_DEBUG_DRIVER is not set
1836+# CONFIG_DEBUG_DEVRES is not set
1837+# CONFIG_SYS_HYPERVISOR is not set
1838+# CONFIG_CONNECTOR is not set
1839+CONFIG_MTD=y
1840+# CONFIG_MTD_DEBUG is not set
1841+CONFIG_MTD_CONCAT=y
1842+CONFIG_MTD_PARTITIONS=y
1843+# CONFIG_MTD_TESTS is not set
1844+# CONFIG_MTD_REDBOOT_PARTS is not set
1845+CONFIG_MTD_CMDLINE_PARTS=y
1846+# CONFIG_MTD_AFS_PARTS is not set
1847+# CONFIG_MTD_AR7_PARTS is not set
1848+
1849+#
1850+# User Modules And Translation Layers
1851+#
1852+CONFIG_MTD_CHAR=y
1853+CONFIG_MTD_BLKDEVS=y
1854+CONFIG_MTD_BLOCK=y
1855+# CONFIG_FTL is not set
1856+# CONFIG_NFTL is not set
1857+# CONFIG_INFTL is not set
1858+# CONFIG_RFD_FTL is not set
1859+# CONFIG_SSFDC is not set
1860+# CONFIG_MTD_OOPS is not set
1861+
1862+#
1863+# RAM/ROM/Flash chip drivers
1864+#
1865+CONFIG_MTD_CFI=y
1866+# CONFIG_MTD_JEDECPROBE is not set
1867+CONFIG_MTD_GEN_PROBE=y
1868+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
1869+CONFIG_MTD_MAP_BANK_WIDTH_1=y
1870+CONFIG_MTD_MAP_BANK_WIDTH_2=y
1871+CONFIG_MTD_MAP_BANK_WIDTH_4=y
1872+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
1873+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
1874+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
1875+CONFIG_MTD_CFI_I1=y
1876+CONFIG_MTD_CFI_I2=y
1877+# CONFIG_MTD_CFI_I4 is not set
1878+# CONFIG_MTD_CFI_I8 is not set
1879+CONFIG_MTD_CFI_INTELEXT=y
1880+# CONFIG_MTD_CFI_AMDSTD is not set
1881+# CONFIG_MTD_CFI_STAA is not set
1882+CONFIG_MTD_CFI_UTIL=y
1883+# CONFIG_MTD_RAM is not set
1884+# CONFIG_MTD_ROM is not set
1885+# CONFIG_MTD_ABSENT is not set
1886+
1887+#
1888+# Mapping drivers for chip access
1889+#
1890+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
1891+# CONFIG_MTD_PHYSMAP is not set
1892+# CONFIG_MTD_ARM_INTEGRATOR is not set
1893+CONFIG_MTD_OMAP_NOR=y
1894+# CONFIG_MTD_PLATRAM is not set
1895+
1896+#
1897+# Self-contained MTD device drivers
1898+#
1899+# CONFIG_MTD_DATAFLASH is not set
1900+# CONFIG_MTD_M25P80 is not set
1901+# CONFIG_MTD_SLRAM is not set
1902+# CONFIG_MTD_PHRAM is not set
1903+# CONFIG_MTD_MTDRAM is not set
1904+# CONFIG_MTD_BLOCK2MTD is not set
1905+
1906+#
1907+# Disk-On-Chip Device Drivers
1908+#
1909+# CONFIG_MTD_DOC2000 is not set
1910+# CONFIG_MTD_DOC2001 is not set
1911+# CONFIG_MTD_DOC2001PLUS is not set
1912+CONFIG_MTD_NAND=y
1913+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
1914+CONFIG_MTD_NAND_ECC_SMC=y
1915+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
1916+# CONFIG_MTD_NAND_GPIO is not set
1917+CONFIG_MTD_NAND_OMAP2=y
1918+CONFIG_MTD_NAND_IDS=y
1919+# CONFIG_MTD_NAND_DISKONCHIP is not set
1920+# CONFIG_MTD_NAND_NANDSIM is not set
1921+# CONFIG_MTD_NAND_PLATFORM is not set
1922+# CONFIG_MTD_ALAUDA is not set
1923+CONFIG_MTD_ONENAND=y
1924+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
1925+# CONFIG_MTD_ONENAND_GENERIC is not set
1926+CONFIG_MTD_ONENAND_OMAP2=y
1927+# CONFIG_MTD_ONENAND_OTP is not set
1928+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
1929+# CONFIG_MTD_ONENAND_SIM is not set
1930+
1931+#
1932+# LPDDR flash memory drivers
1933+#
1934+# CONFIG_MTD_LPDDR is not set
1935+
1936+#
1937+# UBI - Unsorted block images
1938+#
1939+# CONFIG_MTD_UBI is not set
1940+# CONFIG_PARPORT is not set
1941+CONFIG_BLK_DEV=y
1942+# CONFIG_BLK_DEV_COW_COMMON is not set
1943+CONFIG_BLK_DEV_LOOP=y
1944+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
1945+# CONFIG_BLK_DEV_NBD is not set
1946+# CONFIG_BLK_DEV_UB is not set
1947+CONFIG_BLK_DEV_RAM=y
1948+CONFIG_BLK_DEV_RAM_COUNT=16
1949+CONFIG_BLK_DEV_RAM_SIZE=16384
1950+# CONFIG_BLK_DEV_XIP is not set
1951+# CONFIG_CDROM_PKTCDVD is not set
1952+# CONFIG_ATA_OVER_ETH is not set
1953+CONFIG_MISC_DEVICES=y
1954+# CONFIG_ICS932S401 is not set
1955+# CONFIG_OMAP_STI is not set
1956+# CONFIG_ENCLOSURE_SERVICES is not set
1957+# CONFIG_C2PORT is not set
1958+
1959+#
1960+# EEPROM support
1961+#
1962+# CONFIG_EEPROM_AT24 is not set
1963+# CONFIG_EEPROM_AT25 is not set
1964+# CONFIG_EEPROM_LEGACY is not set
1965+# CONFIG_EEPROM_93CX6 is not set
1966+CONFIG_HAVE_IDE=y
1967+# CONFIG_IDE is not set
1968+
1969+#
1970+# SCSI device support
1971+#
1972+# CONFIG_RAID_ATTRS is not set
1973+CONFIG_SCSI=y
1974+CONFIG_SCSI_DMA=y
1975+# CONFIG_SCSI_TGT is not set
1976+# CONFIG_SCSI_NETLINK is not set
1977+CONFIG_SCSI_PROC_FS=y
1978+
1979+#
1980+# SCSI support type (disk, tape, CD-ROM)
1981+#
1982+CONFIG_BLK_DEV_SD=y
1983+# CONFIG_CHR_DEV_ST is not set
1984+# CONFIG_CHR_DEV_OSST is not set
1985+# CONFIG_BLK_DEV_SR is not set
1986+# CONFIG_CHR_DEV_SG is not set
1987+# CONFIG_CHR_DEV_SCH is not set
1988+
1989+#
1990+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
1991+#
1992+# CONFIG_SCSI_MULTI_LUN is not set
1993+# CONFIG_SCSI_CONSTANTS is not set
1994+# CONFIG_SCSI_LOGGING is not set
1995+# CONFIG_SCSI_SCAN_ASYNC is not set
1996+CONFIG_SCSI_WAIT_SCAN=m
1997+
1998+#
1999+# SCSI Transports
2000+#
2001+# CONFIG_SCSI_SPI_ATTRS is not set
2002+# CONFIG_SCSI_FC_ATTRS is not set
2003+# CONFIG_SCSI_ISCSI_ATTRS is not set
2004+# CONFIG_SCSI_SAS_LIBSAS is not set
2005+# CONFIG_SCSI_SRP_ATTRS is not set
2006+CONFIG_SCSI_LOWLEVEL=y
2007+# CONFIG_ISCSI_TCP is not set
2008+# CONFIG_LIBFC is not set
2009+# CONFIG_SCSI_DEBUG is not set
2010+# CONFIG_SCSI_DH is not set
2011+# CONFIG_ATA is not set
2012+# CONFIG_MD is not set
2013+CONFIG_NETDEVICES=y
2014+# CONFIG_DUMMY is not set
2015+# CONFIG_BONDING is not set
2016+# CONFIG_MACVLAN is not set
2017+# CONFIG_EQUALIZER is not set
2018+# CONFIG_TUN is not set
2019+# CONFIG_VETH is not set
2020+# CONFIG_PHYLIB is not set
2021+CONFIG_NET_ETHERNET=y
2022+CONFIG_MII=y
2023+# CONFIG_AX88796 is not set
2024+CONFIG_SMC91X=y
2025+# CONFIG_DM9000 is not set
2026+# CONFIG_ENC28J60 is not set
2027+# CONFIG_SMC911X is not set
2028+# CONFIG_SMSC911X is not set
2029+# CONFIG_DNET is not set
2030+# CONFIG_IBM_NEW_EMAC_ZMII is not set
2031+# CONFIG_IBM_NEW_EMAC_RGMII is not set
2032+# CONFIG_IBM_NEW_EMAC_TAH is not set
2033+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
2034+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
2035+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
2036+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
2037+# CONFIG_B44 is not set
2038+CONFIG_NETDEV_1000=y
2039+CONFIG_NETDEV_10000=y
2040+
2041+#
2042+# Wireless LAN
2043+#
2044+# CONFIG_WLAN_PRE80211 is not set
2045+# CONFIG_WLAN_80211 is not set
2046+# CONFIG_IWLWIFI_LEDS is not set
2047+
2048+#
2049+# Enable WiMAX (Networking options) to see the WiMAX drivers
2050+#
2051+
2052+#
2053+# USB Network Adapters
2054+#
2055+# CONFIG_USB_CATC is not set
2056+# CONFIG_USB_KAWETH is not set
2057+# CONFIG_USB_PEGASUS is not set
2058+# CONFIG_USB_RTL8150 is not set
2059+# CONFIG_USB_USBNET is not set
2060+# CONFIG_WAN is not set
2061+# CONFIG_PPP is not set
2062+# CONFIG_SLIP is not set
2063+# CONFIG_NETCONSOLE is not set
2064+# CONFIG_NETPOLL is not set
2065+# CONFIG_NET_POLL_CONTROLLER is not set
2066+# CONFIG_ISDN is not set
2067+
2068+#
2069+# Input device support
2070+#
2071+CONFIG_INPUT=y
2072+# CONFIG_INPUT_FF_MEMLESS is not set
2073+# CONFIG_INPUT_POLLDEV is not set
2074+
2075+#
2076+# Userland interfaces
2077+#
2078+# CONFIG_INPUT_MOUSEDEV is not set
2079+# CONFIG_INPUT_JOYDEV is not set
2080+CONFIG_INPUT_EVDEV=y
2081+# CONFIG_INPUT_EVBUG is not set
2082+
2083+#
2084+# Input Device Drivers
2085+#
2086+CONFIG_INPUT_KEYBOARD=y
2087+# CONFIG_KEYBOARD_ATKBD is not set
2088+# CONFIG_KEYBOARD_SUNKBD is not set
2089+# CONFIG_KEYBOARD_LKKBD is not set
2090+# CONFIG_KEYBOARD_XTKBD is not set
2091+# CONFIG_KEYBOARD_NEWTON is not set
2092+# CONFIG_KEYBOARD_STOWAWAY is not set
2093+CONFIG_KEYBOARD_TWL4030=y
2094+# CONFIG_KEYBOARD_GPIO is not set
2095+# CONFIG_INPUT_MOUSE is not set
2096+# CONFIG_INPUT_JOYSTICK is not set
2097+# CONFIG_INPUT_TABLET is not set
2098+CONFIG_INPUT_TOUCHSCREEN=y
2099+CONFIG_TOUCHSCREEN_ADS7846=y
2100+# CONFIG_TOUCHSCREEN_FUJITSU is not set
2101+# CONFIG_TOUCHSCREEN_GUNZE is not set
2102+# CONFIG_TOUCHSCREEN_ELO is not set
2103+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
2104+# CONFIG_TOUCHSCREEN_MTOUCH is not set
2105+# CONFIG_TOUCHSCREEN_INEXIO is not set
2106+# CONFIG_TOUCHSCREEN_MK712 is not set
2107+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
2108+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
2109+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
2110+# CONFIG_TOUCHSCREEN_TSC2005 is not set
2111+# CONFIG_TOUCHSCREEN_TSC210X is not set
2112+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
2113+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
2114+# CONFIG_TOUCHSCREEN_TSC2007 is not set
2115+# CONFIG_INPUT_MISC is not set
2116+
2117+#
2118+# Hardware I/O ports
2119+#
2120+# CONFIG_SERIO is not set
2121+# CONFIG_GAMEPORT is not set
2122+
2123+#
2124+# Character devices
2125+#
2126+CONFIG_VT=y
2127+CONFIG_CONSOLE_TRANSLATIONS=y
2128+CONFIG_VT_CONSOLE=y
2129+CONFIG_HW_CONSOLE=y
2130+# CONFIG_VT_HW_CONSOLE_BINDING is not set
2131+CONFIG_DEVKMEM=y
2132+# CONFIG_SERIAL_NONSTANDARD is not set
2133+
2134+#
2135+# Serial drivers
2136+#
2137+CONFIG_SERIAL_8250=y
2138+CONFIG_SERIAL_8250_CONSOLE=y
2139+CONFIG_SERIAL_8250_NR_UARTS=32
2140+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
2141+CONFIG_SERIAL_8250_EXTENDED=y
2142+CONFIG_SERIAL_8250_MANY_PORTS=y
2143+CONFIG_SERIAL_8250_SHARE_IRQ=y
2144+CONFIG_SERIAL_8250_DETECT_IRQ=y
2145+CONFIG_SERIAL_8250_RSA=y
2146+
2147+#
2148+# Non-8250 serial port support
2149+#
2150+CONFIG_SERIAL_CORE=y
2151+CONFIG_SERIAL_CORE_CONSOLE=y
2152+CONFIG_UNIX98_PTYS=y
2153+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
2154+# CONFIG_LEGACY_PTYS is not set
2155+# CONFIG_IPMI_HANDLER is not set
2156+CONFIG_HW_RANDOM=y
2157+# CONFIG_R3964 is not set
2158+# CONFIG_RAW_DRIVER is not set
2159+# CONFIG_TCG_TPM is not set
2160+CONFIG_I2C=y
2161+CONFIG_I2C_BOARDINFO=y
2162+CONFIG_I2C_CHARDEV=y
2163+CONFIG_I2C_HELPER_AUTO=y
2164+
2165+#
2166+# I2C Hardware Bus support
2167+#
2168+
2169+#
2170+# I2C system bus drivers (mostly embedded / system-on-chip)
2171+#
2172+# CONFIG_I2C_GPIO is not set
2173+# CONFIG_I2C_OCORES is not set
2174+CONFIG_I2C_OMAP=y
2175+# CONFIG_I2C_SIMTEC is not set
2176+
2177+#
2178+# External I2C/SMBus adapter drivers
2179+#
2180+# CONFIG_I2C_PARPORT_LIGHT is not set
2181+# CONFIG_I2C_TAOS_EVM is not set
2182+# CONFIG_I2C_TINY_USB is not set
2183+
2184+#
2185+# Other I2C/SMBus bus drivers
2186+#
2187+# CONFIG_I2C_PCA_PLATFORM is not set
2188+# CONFIG_I2C_STUB is not set
2189+
2190+#
2191+# Miscellaneous I2C Chip support
2192+#
2193+# CONFIG_DS1682 is not set
2194+# CONFIG_SENSORS_PCF8574 is not set
2195+# CONFIG_PCF8575 is not set
2196+# CONFIG_SENSORS_PCA9539 is not set
2197+# CONFIG_SENSORS_PCF8591 is not set
2198+# CONFIG_TWL4030_MADC is not set
2199+# CONFIG_TWL4030_POWEROFF is not set
2200+# CONFIG_SENSORS_MAX6875 is not set
2201+# CONFIG_SENSORS_TSL2550 is not set
2202+# CONFIG_I2C_DEBUG_CORE is not set
2203+# CONFIG_I2C_DEBUG_ALGO is not set
2204+# CONFIG_I2C_DEBUG_BUS is not set
2205+# CONFIG_I2C_DEBUG_CHIP is not set
2206+CONFIG_SPI=y
2207+# CONFIG_SPI_DEBUG is not set
2208+CONFIG_SPI_MASTER=y
2209+
2210+#
2211+# SPI Master Controller Drivers
2212+#
2213+# CONFIG_SPI_BITBANG is not set
2214+# CONFIG_SPI_GPIO is not set
2215+CONFIG_SPI_OMAP24XX=y
2216+
2217+#
2218+# SPI Protocol Masters
2219+#
2220+# CONFIG_SPI_TSC210X is not set
2221+# CONFIG_SPI_TSC2301 is not set
2222+# CONFIG_SPI_SPIDEV is not set
2223+# CONFIG_SPI_TLE62X0 is not set
2224+CONFIG_ARCH_REQUIRE_GPIOLIB=y
2225+CONFIG_GPIOLIB=y
2226+# CONFIG_DEBUG_GPIO is not set
2227+# CONFIG_GPIO_SYSFS is not set
2228+
2229+#
2230+# Memory mapped GPIO expanders:
2231+#
2232+
2233+#
2234+# I2C GPIO expanders:
2235+#
2236+# CONFIG_GPIO_MAX732X is not set
2237+# CONFIG_GPIO_PCA953X is not set
2238+# CONFIG_GPIO_PCF857X is not set
2239+CONFIG_GPIO_TWL4030=y
2240+
2241+#
2242+# PCI GPIO expanders:
2243+#
2244+
2245+#
2246+# SPI GPIO expanders:
2247+#
2248+# CONFIG_GPIO_MAX7301 is not set
2249+# CONFIG_GPIO_MCP23S08 is not set
2250+# CONFIG_W1 is not set
2251+# CONFIG_POWER_SUPPLY is not set
2252+# CONFIG_HWMON is not set
2253+# CONFIG_THERMAL is not set
2254+# CONFIG_THERMAL_HWMON is not set
2255+CONFIG_WATCHDOG=y
2256+CONFIG_WATCHDOG_NOWAYOUT=y
2257+
2258+#
2259+# Watchdog Device Drivers
2260+#
2261+# CONFIG_SOFT_WATCHDOG is not set
2262+CONFIG_OMAP_WATCHDOG=y
2263+
2264+#
2265+# USB-based Watchdog Cards
2266+#
2267+# CONFIG_USBPCWATCHDOG is not set
2268+CONFIG_SSB_POSSIBLE=y
2269+
2270+#
2271+# Sonics Silicon Backplane
2272+#
2273+# CONFIG_SSB is not set
2274+
2275+#
2276+# Multifunction device drivers
2277+#
2278+# CONFIG_MFD_CORE is not set
2279+# CONFIG_MFD_SM501 is not set
2280+# CONFIG_MFD_ASIC3 is not set
2281+# CONFIG_HTC_EGPIO is not set
2282+# CONFIG_HTC_PASIC3 is not set
2283+# CONFIG_TPS65010 is not set
2284+CONFIG_TWL4030_CORE=y
2285+# CONFIG_TWL4030_POWER is not set
2286+# CONFIG_MFD_TMIO is not set
2287+# CONFIG_MFD_T7L66XB is not set
2288+# CONFIG_MFD_TC6387XB is not set
2289+# CONFIG_MFD_TC6393XB is not set
2290+# CONFIG_PMIC_DA903X is not set
2291+# CONFIG_MFD_WM8400 is not set
2292+# CONFIG_MFD_WM8350_I2C is not set
2293+# CONFIG_MFD_PCF50633 is not set
2294+
2295+#
2296+# Multimedia devices
2297+#
2298+
2299+#
2300+# Multimedia core support
2301+#
2302+# CONFIG_VIDEO_DEV is not set
2303+# CONFIG_DVB_CORE is not set
2304+# CONFIG_VIDEO_MEDIA is not set
2305+
2306+#
2307+# Multimedia drivers
2308+#
2309+CONFIG_DAB=y
2310+# CONFIG_USB_DABUSB is not set
2311+
2312+#
2313+# Graphics support
2314+#
2315+# CONFIG_VGASTATE is not set
2316+CONFIG_VIDEO_OUTPUT_CONTROL=m
2317+CONFIG_FB=y
2318+# CONFIG_FIRMWARE_EDID is not set
2319+# CONFIG_FB_DDC is not set
2320+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
2321+CONFIG_FB_CFB_FILLRECT=m
2322+CONFIG_FB_CFB_COPYAREA=m
2323+CONFIG_FB_CFB_IMAGEBLIT=m
2324+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
2325+# CONFIG_FB_SYS_FILLRECT is not set
2326+# CONFIG_FB_SYS_COPYAREA is not set
2327+# CONFIG_FB_SYS_IMAGEBLIT is not set
2328+# CONFIG_FB_FOREIGN_ENDIAN is not set
2329+# CONFIG_FB_SYS_FOPS is not set
2330+# CONFIG_FB_SVGALIB is not set
2331+# CONFIG_FB_MACMODES is not set
2332+# CONFIG_FB_BACKLIGHT is not set
2333+# CONFIG_FB_MODE_HELPERS is not set
2334+# CONFIG_FB_TILEBLITTING is not set
2335+
2336+#
2337+# Frame buffer hardware drivers
2338+#
2339+# CONFIG_FB_S1D13XXX is not set
2340+# CONFIG_FB_VIRTUAL is not set
2341+# CONFIG_FB_METRONOME is not set
2342+# CONFIG_FB_MB862XX is not set
2343+# CONFIG_FB_OMAP_LCD_VGA is not set
2344+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
2345+CONFIG_OMAP2_DSS=m
2346+CONFIG_OMAP2_DSS_VRAM_SIZE=8
2347+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
2348+# CONFIG_OMAP2_DSS_RFBI is not set
2349+CONFIG_OMAP2_DSS_VENC=y
2350+# CONFIG_OMAP2_DSS_SDI is not set
2351+# CONFIG_OMAP2_DSS_DSI is not set
2352+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
2353+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
2354+
2355+#
2356+# OMAP2/3 Display Device Drivers
2357+#
2358+CONFIG_PANEL_GENERIC=m
2359+# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set
2360+CONFIG_PANEL_SHARP_LS037V7DW01=m
2361+# CONFIG_PANEL_N800 is not set
2362+# CONFIG_CTRL_BLIZZARD is not set
2363+CONFIG_FB_OMAP2=m
2364+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
2365+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
2366+CONFIG_FB_OMAP2_NUM_FBS=3
2367+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
2368+
2369+#
2370+# Display device support
2371+#
2372+# CONFIG_DISPLAY_SUPPORT is not set
2373+
2374+#
2375+# Console display driver support
2376+#
2377+# CONFIG_VGA_CONSOLE is not set
2378+CONFIG_DUMMY_CONSOLE=y
2379+# CONFIG_FRAMEBUFFER_CONSOLE is not set
2380+# CONFIG_LOGO is not set
2381+# CONFIG_SOUND is not set
2382+CONFIG_HID_SUPPORT=y
2383+CONFIG_HID=y
2384+# CONFIG_HID_DEBUG is not set
2385+# CONFIG_HIDRAW is not set
2386+
2387+#
2388+# USB Input Devices
2389+#
2390+CONFIG_USB_HID=y
2391+# CONFIG_HID_PID is not set
2392+# CONFIG_USB_HIDDEV is not set
2393+
2394+#
2395+# Special HID drivers
2396+#
2397+CONFIG_HID_COMPAT=y
2398+# CONFIG_HID_A4TECH is not set
2399+# CONFIG_HID_APPLE is not set
2400+# CONFIG_HID_BELKIN is not set
2401+# CONFIG_HID_CHERRY is not set
2402+# CONFIG_HID_CHICONY is not set
2403+# CONFIG_HID_CYPRESS is not set
2404+# CONFIG_HID_EZKEY is not set
2405+# CONFIG_HID_GYRATION is not set
2406+# CONFIG_HID_LOGITECH is not set
2407+# CONFIG_HID_MICROSOFT is not set
2408+# CONFIG_HID_MONTEREY is not set
2409+# CONFIG_HID_NTRIG is not set
2410+# CONFIG_HID_PANTHERLORD is not set
2411+# CONFIG_HID_PETALYNX is not set
2412+# CONFIG_HID_SAMSUNG is not set
2413+# CONFIG_HID_SONY is not set
2414+# CONFIG_HID_SUNPLUS is not set
2415+# CONFIG_GREENASIA_FF is not set
2416+# CONFIG_HID_TOPSEED is not set
2417+# CONFIG_THRUSTMASTER_FF is not set
2418+# CONFIG_ZEROPLUS_FF is not set
2419+CONFIG_USB_SUPPORT=y
2420+CONFIG_USB_ARCH_HAS_HCD=y
2421+CONFIG_USB_ARCH_HAS_OHCI=y
2422+CONFIG_USB_ARCH_HAS_EHCI=y
2423+CONFIG_USB=y
2424+CONFIG_USB_DEBUG=y
2425+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
2426+
2427+#
2428+# Miscellaneous USB options
2429+#
2430+CONFIG_USB_DEVICEFS=y
2431+# CONFIG_USB_DEVICE_CLASS is not set
2432+# CONFIG_USB_DYNAMIC_MINORS is not set
2433+CONFIG_USB_SUSPEND=y
2434+CONFIG_USB_OTG=y
2435+# CONFIG_USB_OTG_WHITELIST is not set
2436+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
2437+CONFIG_USB_MON=y
2438+# CONFIG_USB_WUSB is not set
2439+# CONFIG_USB_WUSB_CBAF is not set
2440+
2441+#
2442+# USB Host Controller Drivers
2443+#
2444+# CONFIG_USB_C67X00_HCD is not set
2445+CONFIG_USB_EHCI_HCD=m
2446+CONFIG_OMAP_EHCI_PHY_MODE=y
2447+# CONFIG_OMAP_EHCI_TLL_MODE is not set
2448+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
2449+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
2450+# CONFIG_USB_OXU210HP_HCD is not set
2451+# CONFIG_USB_ISP116X_HCD is not set
2452+# CONFIG_USB_OHCI_HCD is not set
2453+# CONFIG_USB_SL811_HCD is not set
2454+# CONFIG_USB_R8A66597_HCD is not set
2455+# CONFIG_USB_HWA_HCD is not set
2456+CONFIG_USB_MUSB_HDRC=y
2457+CONFIG_USB_MUSB_SOC=y
2458+
2459+#
2460+# OMAP 343x high speed USB support
2461+#
2462+# CONFIG_USB_MUSB_HOST is not set
2463+# CONFIG_USB_MUSB_PERIPHERAL is not set
2464+CONFIG_USB_MUSB_OTG=y
2465+CONFIG_USB_GADGET_MUSB_HDRC=y
2466+CONFIG_USB_MUSB_HDRC_HCD=y
2467+# CONFIG_MUSB_PIO_ONLY is not set
2468+CONFIG_USB_INVENTRA_DMA=y
2469+# CONFIG_USB_TI_CPPI_DMA is not set
2470+# CONFIG_USB_MUSB_DEBUG is not set
2471+
2472+#
2473+# USB Device Class drivers
2474+#
2475+# CONFIG_USB_ACM is not set
2476+# CONFIG_USB_PRINTER is not set
2477+# CONFIG_USB_WDM is not set
2478+# CONFIG_USB_TMC is not set
2479+
2480+#
2481+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
2482+#
2483+
2484+#
2485+# see USB_STORAGE Help for more information
2486+#
2487+CONFIG_USB_STORAGE=y
2488+CONFIG_USB_STORAGE_DEBUG=y
2489+# CONFIG_USB_STORAGE_DATAFAB is not set
2490+# CONFIG_USB_STORAGE_FREECOM is not set
2491+# CONFIG_USB_STORAGE_ISD200 is not set
2492+# CONFIG_USB_STORAGE_USBAT is not set
2493+# CONFIG_USB_STORAGE_SDDR09 is not set
2494+# CONFIG_USB_STORAGE_SDDR55 is not set
2495+# CONFIG_USB_STORAGE_JUMPSHOT is not set
2496+# CONFIG_USB_STORAGE_ALAUDA is not set
2497+# CONFIG_USB_STORAGE_ONETOUCH is not set
2498+# CONFIG_USB_STORAGE_KARMA is not set
2499+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
2500+# CONFIG_USB_LIBUSUAL is not set
2501+
2502+#
2503+# USB Imaging devices
2504+#
2505+# CONFIG_USB_MDC800 is not set
2506+# CONFIG_USB_MICROTEK is not set
2507+
2508+#
2509+# USB port drivers
2510+#
2511+# CONFIG_USB_SERIAL is not set
2512+
2513+#
2514+# USB Miscellaneous drivers
2515+#
2516+# CONFIG_USB_EMI62 is not set
2517+# CONFIG_USB_EMI26 is not set
2518+# CONFIG_USB_ADUTUX is not set
2519+# CONFIG_USB_SEVSEG is not set
2520+# CONFIG_USB_RIO500 is not set
2521+# CONFIG_USB_LEGOTOWER is not set
2522+# CONFIG_USB_LCD is not set
2523+# CONFIG_USB_BERRY_CHARGE is not set
2524+# CONFIG_USB_LED is not set
2525+# CONFIG_USB_CYPRESS_CY7C63 is not set
2526+# CONFIG_USB_CYTHERM is not set
2527+# CONFIG_USB_PHIDGET is not set
2528+# CONFIG_USB_IDMOUSE is not set
2529+# CONFIG_USB_FTDI_ELAN is not set
2530+# CONFIG_USB_APPLEDISPLAY is not set
2531+# CONFIG_USB_SISUSBVGA is not set
2532+# CONFIG_USB_LD is not set
2533+# CONFIG_USB_TRANCEVIBRATOR is not set
2534+# CONFIG_USB_IOWARRIOR is not set
2535+CONFIG_USB_TEST=y
2536+# CONFIG_USB_ISIGHTFW is not set
2537+# CONFIG_USB_VST is not set
2538+CONFIG_USB_GADGET=y
2539+CONFIG_USB_GADGET_DEBUG=y
2540+CONFIG_USB_GADGET_DEBUG_FILES=y
2541+# CONFIG_USB_GADGET_DEBUG_FS is not set
2542+CONFIG_USB_GADGET_VBUS_DRAW=2
2543+CONFIG_USB_GADGET_SELECTED=y
2544+# CONFIG_USB_GADGET_AT91 is not set
2545+# CONFIG_USB_GADGET_ATMEL_USBA is not set
2546+# CONFIG_USB_GADGET_FSL_USB2 is not set
2547+# CONFIG_USB_GADGET_LH7A40X is not set
2548+# CONFIG_USB_GADGET_OMAP is not set
2549+# CONFIG_USB_GADGET_PXA25X is not set
2550+# CONFIG_USB_GADGET_PXA27X is not set
2551+# CONFIG_USB_GADGET_S3C2410 is not set
2552+# CONFIG_USB_GADGET_IMX is not set
2553+# CONFIG_USB_GADGET_M66592 is not set
2554+# CONFIG_USB_GADGET_AMD5536UDC is not set
2555+# CONFIG_USB_GADGET_FSL_QE is not set
2556+# CONFIG_USB_GADGET_CI13XXX is not set
2557+# CONFIG_USB_GADGET_NET2280 is not set
2558+# CONFIG_USB_GADGET_GOKU is not set
2559+# CONFIG_USB_GADGET_DUMMY_HCD is not set
2560+CONFIG_USB_GADGET_DUALSPEED=y
2561+CONFIG_USB_ZERO=m
2562+# CONFIG_USB_ZERO_HNPTEST is not set
2563+# CONFIG_USB_ETH is not set
2564+# CONFIG_USB_GADGETFS is not set
2565+# CONFIG_USB_FILE_STORAGE is not set
2566+# CONFIG_USB_G_SERIAL is not set
2567+# CONFIG_USB_MIDI_GADGET is not set
2568+# CONFIG_USB_G_PRINTER is not set
2569+# CONFIG_USB_CDC_COMPOSITE is not set
2570+
2571+#
2572+# OTG and related infrastructure
2573+#
2574+CONFIG_USB_OTG_UTILS=y
2575+# CONFIG_USB_GPIO_VBUS is not set
2576+# CONFIG_ISP1301_OMAP is not set
2577+CONFIG_TWL4030_USB=y
2578+CONFIG_MMC=y
2579+# CONFIG_MMC_DEBUG is not set
2580+# CONFIG_MMC_UNSAFE_RESUME is not set
2581+
2582+#
2583+# MMC/SD/SDIO Card Drivers
2584+#
2585+CONFIG_MMC_BLOCK=y
2586+CONFIG_MMC_BLOCK_BOUNCE=y
2587+# CONFIG_SDIO_UART is not set
2588+# CONFIG_MMC_TEST is not set
2589+
2590+#
2591+# MMC/SD/SDIO Host Controller Drivers
2592+#
2593+# CONFIG_MMC_SDHCI is not set
2594+CONFIG_MMC_OMAP_HS=m
2595+# CONFIG_MMC_SPI is not set
2596+# CONFIG_MEMSTICK is not set
2597+# CONFIG_ACCESSIBILITY is not set
2598+# CONFIG_NEW_LEDS is not set
2599+CONFIG_RTC_LIB=y
2600+CONFIG_RTC_CLASS=y
2601+CONFIG_RTC_HCTOSYS=y
2602+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
2603+# CONFIG_RTC_DEBUG is not set
2604+
2605+#
2606+# RTC interfaces
2607+#
2608+CONFIG_RTC_INTF_SYSFS=y
2609+CONFIG_RTC_INTF_PROC=y
2610+CONFIG_RTC_INTF_DEV=y
2611+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
2612+# CONFIG_RTC_DRV_TEST is not set
2613+
2614+#
2615+# I2C RTC drivers
2616+#
2617+# CONFIG_RTC_DRV_DS1307 is not set
2618+# CONFIG_RTC_DRV_DS1374 is not set
2619+# CONFIG_RTC_DRV_DS1672 is not set
2620+# CONFIG_RTC_DRV_MAX6900 is not set
2621+# CONFIG_RTC_DRV_RS5C372 is not set
2622+# CONFIG_RTC_DRV_ISL1208 is not set
2623+# CONFIG_RTC_DRV_X1205 is not set
2624+# CONFIG_RTC_DRV_PCF8563 is not set
2625+# CONFIG_RTC_DRV_PCF8583 is not set
2626+# CONFIG_RTC_DRV_M41T80 is not set
2627+CONFIG_RTC_DRV_TWL4030=y
2628+# CONFIG_RTC_DRV_S35390A is not set
2629+# CONFIG_RTC_DRV_FM3130 is not set
2630+# CONFIG_RTC_DRV_RX8581 is not set
2631+
2632+#
2633+# SPI RTC drivers
2634+#
2635+# CONFIG_RTC_DRV_M41T94 is not set
2636+# CONFIG_RTC_DRV_DS1305 is not set
2637+# CONFIG_RTC_DRV_DS1390 is not set
2638+# CONFIG_RTC_DRV_MAX6902 is not set
2639+# CONFIG_RTC_DRV_R9701 is not set
2640+# CONFIG_RTC_DRV_RS5C348 is not set
2641+# CONFIG_RTC_DRV_DS3234 is not set
2642+
2643+#
2644+# Platform RTC drivers
2645+#
2646+# CONFIG_RTC_DRV_CMOS is not set
2647+# CONFIG_RTC_DRV_DS1286 is not set
2648+# CONFIG_RTC_DRV_DS1511 is not set
2649+# CONFIG_RTC_DRV_DS1553 is not set
2650+# CONFIG_RTC_DRV_DS1742 is not set
2651+# CONFIG_RTC_DRV_STK17TA8 is not set
2652+# CONFIG_RTC_DRV_M48T86 is not set
2653+# CONFIG_RTC_DRV_M48T35 is not set
2654+# CONFIG_RTC_DRV_M48T59 is not set
2655+# CONFIG_RTC_DRV_BQ4802 is not set
2656+# CONFIG_RTC_DRV_V3020 is not set
2657+
2658+#
2659+# on-CPU RTC drivers
2660+#
2661+# CONFIG_DMADEVICES is not set
2662+CONFIG_REGULATOR=y
2663+# CONFIG_REGULATOR_DEBUG is not set
2664+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
2665+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
2666+# CONFIG_REGULATOR_BQ24022 is not set
2667+CONFIG_REGULATOR_TWL4030=y
2668+# CONFIG_UIO is not set
2669+# CONFIG_STAGING is not set
2670+
2671+#
2672+# CBUS support
2673+#
2674+# CONFIG_CBUS is not set
2675+
2676+#
2677+# File systems
2678+#
2679+CONFIG_EXT2_FS=y
2680+# CONFIG_EXT2_FS_XATTR is not set
2681+# CONFIG_EXT2_FS_XIP is not set
2682+CONFIG_EXT3_FS=y
2683+# CONFIG_EXT3_FS_XATTR is not set
2684+# CONFIG_EXT4_FS is not set
2685+CONFIG_JBD=y
2686+# CONFIG_JBD_DEBUG is not set
2687+# CONFIG_REISERFS_FS is not set
2688+# CONFIG_JFS_FS is not set
2689+# CONFIG_FS_POSIX_ACL is not set
2690+CONFIG_FILE_LOCKING=y
2691+# CONFIG_XFS_FS is not set
2692+# CONFIG_OCFS2_FS is not set
2693+# CONFIG_BTRFS_FS is not set
2694+CONFIG_DNOTIFY=y
2695+CONFIG_INOTIFY=y
2696+CONFIG_INOTIFY_USER=y
2697+CONFIG_QUOTA=y
2698+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
2699+CONFIG_PRINT_QUOTA_WARNING=y
2700+CONFIG_QUOTA_TREE=y
2701+# CONFIG_QFMT_V1 is not set
2702+CONFIG_QFMT_V2=y
2703+CONFIG_QUOTACTL=y
2704+# CONFIG_AUTOFS_FS is not set
2705+# CONFIG_AUTOFS4_FS is not set
2706+# CONFIG_FUSE_FS is not set
2707+
2708+#
2709+# CD-ROM/DVD Filesystems
2710+#
2711+# CONFIG_ISO9660_FS is not set
2712+# CONFIG_UDF_FS is not set
2713+
2714+#
2715+# DOS/FAT/NT Filesystems
2716+#
2717+CONFIG_FAT_FS=y
2718+CONFIG_MSDOS_FS=y
2719+CONFIG_VFAT_FS=y
2720+CONFIG_FAT_DEFAULT_CODEPAGE=437
2721+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
2722+# CONFIG_NTFS_FS is not set
2723+
2724+#
2725+# Pseudo filesystems
2726+#
2727+CONFIG_PROC_FS=y
2728+CONFIG_PROC_SYSCTL=y
2729+CONFIG_PROC_PAGE_MONITOR=y
2730+CONFIG_SYSFS=y
2731+CONFIG_TMPFS=y
2732+# CONFIG_TMPFS_POSIX_ACL is not set
2733+# CONFIG_HUGETLB_PAGE is not set
2734+# CONFIG_CONFIGFS_FS is not set
2735+CONFIG_MISC_FILESYSTEMS=y
2736+# CONFIG_ADFS_FS is not set
2737+# CONFIG_AFFS_FS is not set
2738+# CONFIG_HFS_FS is not set
2739+# CONFIG_HFSPLUS_FS is not set
2740+# CONFIG_BEFS_FS is not set
2741+# CONFIG_BFS_FS is not set
2742+# CONFIG_EFS_FS is not set
2743+CONFIG_JFFS2_FS=y
2744+CONFIG_JFFS2_FS_DEBUG=0
2745+CONFIG_JFFS2_FS_WRITEBUFFER=y
2746+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
2747+# CONFIG_JFFS2_SUMMARY is not set
2748+# CONFIG_JFFS2_FS_XATTR is not set
2749+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
2750+CONFIG_JFFS2_ZLIB=y
2751+# CONFIG_JFFS2_LZO is not set
2752+CONFIG_JFFS2_RTIME=y
2753+# CONFIG_JFFS2_RUBIN is not set
2754+# CONFIG_JFFS2_CMODE_NONE is not set
2755+CONFIG_JFFS2_CMODE_PRIORITY=y
2756+# CONFIG_JFFS2_CMODE_SIZE is not set
2757+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
2758+# CONFIG_CRAMFS is not set
2759+# CONFIG_SQUASHFS is not set
2760+# CONFIG_VXFS_FS is not set
2761+# CONFIG_MINIX_FS is not set
2762+# CONFIG_OMFS_FS is not set
2763+# CONFIG_HPFS_FS is not set
2764+# CONFIG_QNX4FS_FS is not set
2765+# CONFIG_ROMFS_FS is not set
2766+# CONFIG_SYSV_FS is not set
2767+# CONFIG_UFS_FS is not set
2768+CONFIG_NETWORK_FILESYSTEMS=y
2769+CONFIG_NFS_FS=y
2770+CONFIG_NFS_V3=y
2771+# CONFIG_NFS_V3_ACL is not set
2772+CONFIG_NFS_V4=y
2773+CONFIG_ROOT_NFS=y
2774+# CONFIG_NFSD is not set
2775+CONFIG_LOCKD=y
2776+CONFIG_LOCKD_V4=y
2777+CONFIG_NFS_COMMON=y
2778+CONFIG_SUNRPC=y
2779+CONFIG_SUNRPC_GSS=y
2780+# CONFIG_SUNRPC_REGISTER_V4 is not set
2781+CONFIG_RPCSEC_GSS_KRB5=y
2782+# CONFIG_RPCSEC_GSS_SPKM3 is not set
2783+# CONFIG_SMB_FS is not set
2784+# CONFIG_CIFS is not set
2785+# CONFIG_NCP_FS is not set
2786+# CONFIG_CODA_FS is not set
2787+# CONFIG_AFS_FS is not set
2788+
2789+#
2790+# Partition Types
2791+#
2792+CONFIG_PARTITION_ADVANCED=y
2793+# CONFIG_ACORN_PARTITION is not set
2794+# CONFIG_OSF_PARTITION is not set
2795+# CONFIG_AMIGA_PARTITION is not set
2796+# CONFIG_ATARI_PARTITION is not set
2797+# CONFIG_MAC_PARTITION is not set
2798+CONFIG_MSDOS_PARTITION=y
2799+# CONFIG_BSD_DISKLABEL is not set
2800+# CONFIG_MINIX_SUBPARTITION is not set
2801+# CONFIG_SOLARIS_X86_PARTITION is not set
2802+# CONFIG_UNIXWARE_DISKLABEL is not set
2803+# CONFIG_LDM_PARTITION is not set
2804+# CONFIG_SGI_PARTITION is not set
2805+# CONFIG_ULTRIX_PARTITION is not set
2806+# CONFIG_SUN_PARTITION is not set
2807+# CONFIG_KARMA_PARTITION is not set
2808+# CONFIG_EFI_PARTITION is not set
2809+# CONFIG_SYSV68_PARTITION is not set
2810+CONFIG_NLS=y
2811+CONFIG_NLS_DEFAULT="iso8859-1"
2812+CONFIG_NLS_CODEPAGE_437=y
2813+# CONFIG_NLS_CODEPAGE_737 is not set
2814+# CONFIG_NLS_CODEPAGE_775 is not set
2815+# CONFIG_NLS_CODEPAGE_850 is not set
2816+# CONFIG_NLS_CODEPAGE_852 is not set
2817+# CONFIG_NLS_CODEPAGE_855 is not set
2818+# CONFIG_NLS_CODEPAGE_857 is not set
2819+# CONFIG_NLS_CODEPAGE_860 is not set
2820+# CONFIG_NLS_CODEPAGE_861 is not set
2821+# CONFIG_NLS_CODEPAGE_862 is not set
2822+# CONFIG_NLS_CODEPAGE_863 is not set
2823+# CONFIG_NLS_CODEPAGE_864 is not set
2824+# CONFIG_NLS_CODEPAGE_865 is not set
2825+# CONFIG_NLS_CODEPAGE_866 is not set
2826+# CONFIG_NLS_CODEPAGE_869 is not set
2827+# CONFIG_NLS_CODEPAGE_936 is not set
2828+# CONFIG_NLS_CODEPAGE_950 is not set
2829+# CONFIG_NLS_CODEPAGE_932 is not set
2830+# CONFIG_NLS_CODEPAGE_949 is not set
2831+# CONFIG_NLS_CODEPAGE_874 is not set
2832+# CONFIG_NLS_ISO8859_8 is not set
2833+# CONFIG_NLS_CODEPAGE_1250 is not set
2834+# CONFIG_NLS_CODEPAGE_1251 is not set
2835+# CONFIG_NLS_ASCII is not set
2836+CONFIG_NLS_ISO8859_1=y
2837+# CONFIG_NLS_ISO8859_2 is not set
2838+# CONFIG_NLS_ISO8859_3 is not set
2839+# CONFIG_NLS_ISO8859_4 is not set
2840+# CONFIG_NLS_ISO8859_5 is not set
2841+# CONFIG_NLS_ISO8859_6 is not set
2842+# CONFIG_NLS_ISO8859_7 is not set
2843+# CONFIG_NLS_ISO8859_9 is not set
2844+# CONFIG_NLS_ISO8859_13 is not set
2845+# CONFIG_NLS_ISO8859_14 is not set
2846+# CONFIG_NLS_ISO8859_15 is not set
2847+# CONFIG_NLS_KOI8_R is not set
2848+# CONFIG_NLS_KOI8_U is not set
2849+# CONFIG_NLS_UTF8 is not set
2850+# CONFIG_DLM is not set
2851+
2852+#
2853+# Kernel hacking
2854+#
2855+# CONFIG_PRINTK_TIME is not set
2856+CONFIG_ENABLE_WARN_DEPRECATED=y
2857+CONFIG_ENABLE_MUST_CHECK=y
2858+CONFIG_FRAME_WARN=1024
2859+CONFIG_MAGIC_SYSRQ=y
2860+# CONFIG_UNUSED_SYMBOLS is not set
2861+CONFIG_DEBUG_FS=y
2862+# CONFIG_HEADERS_CHECK is not set
2863+CONFIG_DEBUG_KERNEL=y
2864+# CONFIG_DEBUG_SHIRQ is not set
2865+CONFIG_DETECT_SOFTLOCKUP=y
2866+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
2867+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
2868+CONFIG_SCHED_DEBUG=y
2869+# CONFIG_SCHEDSTATS is not set
2870+# CONFIG_TIMER_STATS is not set
2871+# CONFIG_DEBUG_OBJECTS is not set
2872+# CONFIG_DEBUG_SLAB is not set
2873+# CONFIG_DEBUG_RT_MUTEXES is not set
2874+# CONFIG_RT_MUTEX_TESTER is not set
2875+# CONFIG_DEBUG_SPINLOCK is not set
2876+CONFIG_DEBUG_MUTEXES=y
2877+# CONFIG_DEBUG_LOCK_ALLOC is not set
2878+# CONFIG_PROVE_LOCKING is not set
2879+# CONFIG_LOCK_STAT is not set
2880+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
2881+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
2882+# CONFIG_DEBUG_KOBJECT is not set
2883+CONFIG_DEBUG_BUGVERBOSE=y
2884+CONFIG_DEBUG_INFO=y
2885+# CONFIG_DEBUG_VM is not set
2886+# CONFIG_DEBUG_WRITECOUNT is not set
2887+# CONFIG_DEBUG_MEMORY_INIT is not set
2888+# CONFIG_DEBUG_LIST is not set
2889+# CONFIG_DEBUG_SG is not set
2890+# CONFIG_DEBUG_NOTIFIERS is not set
2891+CONFIG_FRAME_POINTER=y
2892+# CONFIG_BOOT_PRINTK_DELAY is not set
2893+# CONFIG_RCU_TORTURE_TEST is not set
2894+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
2895+# CONFIG_BACKTRACE_SELF_TEST is not set
2896+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
2897+# CONFIG_FAULT_INJECTION is not set
2898+# CONFIG_LATENCYTOP is not set
2899+CONFIG_HAVE_FUNCTION_TRACER=y
2900+
2901+#
2902+# Tracers
2903+#
2904+# CONFIG_FUNCTION_TRACER is not set
2905+# CONFIG_IRQSOFF_TRACER is not set
2906+# CONFIG_SCHED_TRACER is not set
2907+# CONFIG_CONTEXT_SWITCH_TRACER is not set
2908+# CONFIG_BOOT_TRACER is not set
2909+# CONFIG_TRACE_BRANCH_PROFILING is not set
2910+# CONFIG_STACK_TRACER is not set
2911+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
2912+# CONFIG_SAMPLES is not set
2913+CONFIG_HAVE_ARCH_KGDB=y
2914+# CONFIG_KGDB is not set
2915+CONFIG_DEBUG_USER=y
2916+CONFIG_DEBUG_ERRORS=y
2917+# CONFIG_DEBUG_STACK_USAGE is not set
2918+# CONFIG_DEBUG_LL is not set
2919+
2920+#
2921+# Security options
2922+#
2923+# CONFIG_KEYS is not set
2924+# CONFIG_SECURITY is not set
2925+# CONFIG_SECURITYFS is not set
2926+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
2927+CONFIG_CRYPTO=y
2928+
2929+#
2930+# Crypto core or helper
2931+#
2932+# CONFIG_CRYPTO_FIPS is not set
2933+CONFIG_CRYPTO_ALGAPI=y
2934+CONFIG_CRYPTO_ALGAPI2=y
2935+CONFIG_CRYPTO_AEAD2=y
2936+CONFIG_CRYPTO_BLKCIPHER=y
2937+CONFIG_CRYPTO_BLKCIPHER2=y
2938+CONFIG_CRYPTO_HASH=y
2939+CONFIG_CRYPTO_HASH2=y
2940+CONFIG_CRYPTO_RNG2=y
2941+CONFIG_CRYPTO_MANAGER=y
2942+CONFIG_CRYPTO_MANAGER2=y
2943+# CONFIG_CRYPTO_GF128MUL is not set
2944+# CONFIG_CRYPTO_NULL is not set
2945+# CONFIG_CRYPTO_CRYPTD is not set
2946+# CONFIG_CRYPTO_AUTHENC is not set
2947+# CONFIG_CRYPTO_TEST is not set
2948+
2949+#
2950+# Authenticated Encryption with Associated Data
2951+#
2952+# CONFIG_CRYPTO_CCM is not set
2953+# CONFIG_CRYPTO_GCM is not set
2954+# CONFIG_CRYPTO_SEQIV is not set
2955+
2956+#
2957+# Block modes
2958+#
2959+CONFIG_CRYPTO_CBC=y
2960+# CONFIG_CRYPTO_CTR is not set
2961+# CONFIG_CRYPTO_CTS is not set
2962+CONFIG_CRYPTO_ECB=m
2963+# CONFIG_CRYPTO_LRW is not set
2964+CONFIG_CRYPTO_PCBC=m
2965+# CONFIG_CRYPTO_XTS is not set
2966+
2967+#
2968+# Hash modes
2969+#
2970+# CONFIG_CRYPTO_HMAC is not set
2971+# CONFIG_CRYPTO_XCBC is not set
2972+
2973+#
2974+# Digest
2975+#
2976+CONFIG_CRYPTO_CRC32C=y
2977+# CONFIG_CRYPTO_MD4 is not set
2978+CONFIG_CRYPTO_MD5=y
2979+# CONFIG_CRYPTO_MICHAEL_MIC is not set
2980+# CONFIG_CRYPTO_RMD128 is not set
2981+# CONFIG_CRYPTO_RMD160 is not set
2982+# CONFIG_CRYPTO_RMD256 is not set
2983+# CONFIG_CRYPTO_RMD320 is not set
2984+# CONFIG_CRYPTO_SHA1 is not set
2985+# CONFIG_CRYPTO_SHA256 is not set
2986+# CONFIG_CRYPTO_SHA512 is not set
2987+# CONFIG_CRYPTO_TGR192 is not set
2988+# CONFIG_CRYPTO_WP512 is not set
2989+
2990+#
2991+# Ciphers
2992+#
2993+# CONFIG_CRYPTO_AES is not set
2994+# CONFIG_CRYPTO_ANUBIS is not set
2995+# CONFIG_CRYPTO_ARC4 is not set
2996+# CONFIG_CRYPTO_BLOWFISH is not set
2997+# CONFIG_CRYPTO_CAMELLIA is not set
2998+# CONFIG_CRYPTO_CAST5 is not set
2999+# CONFIG_CRYPTO_CAST6 is not set
3000+CONFIG_CRYPTO_DES=y
3001+# CONFIG_CRYPTO_FCRYPT is not set
3002+# CONFIG_CRYPTO_KHAZAD is not set
3003+# CONFIG_CRYPTO_SALSA20 is not set
3004+# CONFIG_CRYPTO_SEED is not set
3005+# CONFIG_CRYPTO_SERPENT is not set
3006+# CONFIG_CRYPTO_TEA is not set
3007+# CONFIG_CRYPTO_TWOFISH is not set
3008+
3009+#
3010+# Compression
3011+#
3012+# CONFIG_CRYPTO_DEFLATE is not set
3013+# CONFIG_CRYPTO_LZO is not set
3014+
3015+#
3016+# Random Number Generation
3017+#
3018+# CONFIG_CRYPTO_ANSI_CPRNG is not set
3019+CONFIG_CRYPTO_HW=y
3020+
3021+#
3022+# Library routines
3023+#
3024+CONFIG_BITREVERSE=y
3025+CONFIG_GENERIC_FIND_LAST_BIT=y
3026+CONFIG_CRC_CCITT=y
3027+# CONFIG_CRC16 is not set
3028+# CONFIG_CRC_T10DIF is not set
3029+# CONFIG_CRC_ITU_T is not set
3030+CONFIG_CRC32=y
3031+# CONFIG_CRC7 is not set
3032+CONFIG_LIBCRC32C=y
3033+CONFIG_ZLIB_INFLATE=y
3034+CONFIG_ZLIB_DEFLATE=y
3035+CONFIG_PLIST=y
3036+CONFIG_HAS_IOMEM=y
3037+CONFIG_HAS_IOPORT=y
3038+CONFIG_HAS_DMA=y
3039diff --git a/arch/arm/configs/dss_overo_defconfig b/arch/arm/configs/dss_overo_defconfig
3040new file mode 100644
3041index 0000000..755a1b6
3042--- /dev/null
3043+++ b/arch/arm/configs/dss_overo_defconfig
3044@@ -0,0 +1,1862 @@
3045+#
3046+# Automatically generated make config: don't edit
3047+# Linux kernel version: 2.6.29-omap1
3048+# Thu Apr 2 11:30:57 2009
3049+#
3050+CONFIG_ARM=y
3051+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
3052+CONFIG_GENERIC_GPIO=y
3053+CONFIG_GENERIC_TIME=y
3054+CONFIG_GENERIC_CLOCKEVENTS=y
3055+CONFIG_MMU=y
3056+# CONFIG_NO_IOPORT is not set
3057+CONFIG_GENERIC_HARDIRQS=y
3058+CONFIG_STACKTRACE_SUPPORT=y
3059+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
3060+CONFIG_LOCKDEP_SUPPORT=y
3061+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
3062+CONFIG_HARDIRQS_SW_RESEND=y
3063+CONFIG_GENERIC_IRQ_PROBE=y
3064+CONFIG_RWSEM_GENERIC_SPINLOCK=y
3065+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
3066+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
3067+CONFIG_GENERIC_HWEIGHT=y
3068+CONFIG_GENERIC_CALIBRATE_DELAY=y
3069+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
3070+CONFIG_OPROFILE_ARMV7=y
3071+CONFIG_VECTORS_BASE=0xffff0000
3072+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
3073+
3074+#
3075+# General setup
3076+#
3077+CONFIG_EXPERIMENTAL=y
3078+CONFIG_BROKEN_ON_SMP=y
3079+CONFIG_INIT_ENV_ARG_LIMIT=32
3080+CONFIG_LOCALVERSION=""
3081+CONFIG_LOCALVERSION_AUTO=y
3082+CONFIG_SWAP=y
3083+CONFIG_SYSVIPC=y
3084+CONFIG_SYSVIPC_SYSCTL=y
3085+# CONFIG_POSIX_MQUEUE is not set
3086+CONFIG_BSD_PROCESS_ACCT=y
3087+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
3088+# CONFIG_TASKSTATS is not set
3089+# CONFIG_AUDIT is not set
3090+
3091+#
3092+# RCU Subsystem
3093+#
3094+CONFIG_CLASSIC_RCU=y
3095+# CONFIG_TREE_RCU is not set
3096+# CONFIG_PREEMPT_RCU is not set
3097+# CONFIG_TREE_RCU_TRACE is not set
3098+# CONFIG_PREEMPT_RCU_TRACE is not set
3099+CONFIG_IKCONFIG=y
3100+CONFIG_IKCONFIG_PROC=y
3101+CONFIG_LOG_BUF_SHIFT=14
3102+CONFIG_GROUP_SCHED=y
3103+CONFIG_FAIR_GROUP_SCHED=y
3104+# CONFIG_RT_GROUP_SCHED is not set
3105+CONFIG_USER_SCHED=y
3106+# CONFIG_CGROUP_SCHED is not set
3107+# CONFIG_CGROUPS is not set
3108+CONFIG_SYSFS_DEPRECATED=y
3109+CONFIG_SYSFS_DEPRECATED_V2=y
3110+# CONFIG_RELAY is not set
3111+# CONFIG_NAMESPACES is not set
3112+CONFIG_BLK_DEV_INITRD=y
3113+CONFIG_INITRAMFS_SOURCE=""
3114+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
3115+CONFIG_SYSCTL=y
3116+CONFIG_ANON_INODES=y
3117+CONFIG_EMBEDDED=y
3118+CONFIG_UID16=y
3119+# CONFIG_SYSCTL_SYSCALL is not set
3120+CONFIG_KALLSYMS=y
3121+# CONFIG_KALLSYMS_ALL is not set
3122+# CONFIG_KALLSYMS_EXTRA_PASS is not set
3123+CONFIG_HOTPLUG=y
3124+CONFIG_PRINTK=y
3125+CONFIG_BUG=y
3126+# CONFIG_ELF_CORE is not set
3127+CONFIG_BASE_FULL=y
3128+CONFIG_FUTEX=y
3129+CONFIG_EPOLL=y
3130+CONFIG_SIGNALFD=y
3131+CONFIG_TIMERFD=y
3132+CONFIG_EVENTFD=y
3133+CONFIG_SHMEM=y
3134+CONFIG_AIO=y
3135+CONFIG_VM_EVENT_COUNTERS=y
3136+CONFIG_SLUB_DEBUG=y
3137+# CONFIG_COMPAT_BRK is not set
3138+# CONFIG_SLAB is not set
3139+CONFIG_SLUB=y
3140+# CONFIG_SLOB is not set
3141+CONFIG_PROFILING=y
3142+CONFIG_TRACEPOINTS=y
3143+# CONFIG_MARKERS is not set
3144+CONFIG_OPROFILE=y
3145+CONFIG_HAVE_OPROFILE=y
3146+# CONFIG_KPROBES is not set
3147+CONFIG_HAVE_KPROBES=y
3148+CONFIG_HAVE_KRETPROBES=y
3149+CONFIG_HAVE_CLK=y
3150+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
3151+CONFIG_SLABINFO=y
3152+CONFIG_RT_MUTEXES=y
3153+CONFIG_BASE_SMALL=0
3154+CONFIG_MODULES=y
3155+# CONFIG_MODULE_FORCE_LOAD is not set
3156+CONFIG_MODULE_UNLOAD=y
3157+CONFIG_MODULE_FORCE_UNLOAD=y
3158+CONFIG_MODVERSIONS=y
3159+CONFIG_MODULE_SRCVERSION_ALL=y
3160+CONFIG_BLOCK=y
3161+CONFIG_LBD=y
3162+# CONFIG_BLK_DEV_IO_TRACE is not set
3163+# CONFIG_BLK_DEV_BSG is not set
3164+# CONFIG_BLK_DEV_INTEGRITY is not set
3165+
3166+#
3167+# IO Schedulers
3168+#
3169+CONFIG_IOSCHED_NOOP=y
3170+CONFIG_IOSCHED_AS=y
3171+CONFIG_IOSCHED_DEADLINE=y
3172+CONFIG_IOSCHED_CFQ=y
3173+# CONFIG_DEFAULT_AS is not set
3174+# CONFIG_DEFAULT_DEADLINE is not set
3175+CONFIG_DEFAULT_CFQ=y
3176+# CONFIG_DEFAULT_NOOP is not set
3177+CONFIG_DEFAULT_IOSCHED="cfq"
3178+CONFIG_FREEZER=y
3179+
3180+#
3181+# System Type
3182+#
3183+# CONFIG_ARCH_AAEC2000 is not set
3184+# CONFIG_ARCH_INTEGRATOR is not set
3185+# CONFIG_ARCH_REALVIEW is not set
3186+# CONFIG_ARCH_VERSATILE is not set
3187+# CONFIG_ARCH_AT91 is not set
3188+# CONFIG_ARCH_CLPS711X is not set
3189+# CONFIG_ARCH_EBSA110 is not set
3190+# CONFIG_ARCH_EP93XX is not set
3191+# CONFIG_ARCH_FOOTBRIDGE is not set
3192+# CONFIG_ARCH_NETX is not set
3193+# CONFIG_ARCH_H720X is not set
3194+# CONFIG_ARCH_IMX is not set
3195+# CONFIG_ARCH_IOP13XX is not set
3196+# CONFIG_ARCH_IOP32X is not set
3197+# CONFIG_ARCH_IOP33X is not set
3198+# CONFIG_ARCH_IXP23XX is not set
3199+# CONFIG_ARCH_IXP2000 is not set
3200+# CONFIG_ARCH_IXP4XX is not set
3201+# CONFIG_ARCH_L7200 is not set
3202+# CONFIG_ARCH_KIRKWOOD is not set
3203+# CONFIG_ARCH_KS8695 is not set
3204+# CONFIG_ARCH_NS9XXX is not set
3205+# CONFIG_ARCH_LOKI is not set
3206+# CONFIG_ARCH_MV78XX0 is not set
3207+# CONFIG_ARCH_MXC is not set
3208+# CONFIG_ARCH_ORION5X is not set
3209+# CONFIG_ARCH_PNX4008 is not set
3210+# CONFIG_ARCH_PXA is not set
3211+# CONFIG_ARCH_RPC is not set
3212+# CONFIG_ARCH_SA1100 is not set
3213+# CONFIG_ARCH_S3C2410 is not set
3214+# CONFIG_ARCH_S3C64XX is not set
3215+# CONFIG_ARCH_SHARK is not set
3216+# CONFIG_ARCH_LH7A40X is not set
3217+# CONFIG_ARCH_DAVINCI is not set
3218+CONFIG_ARCH_OMAP=y
3219+# CONFIG_ARCH_MSM is not set
3220+# CONFIG_ARCH_W90X900 is not set
3221+
3222+#
3223+# TI OMAP Implementations
3224+#
3225+CONFIG_ARCH_OMAP_OTG=y
3226+# CONFIG_ARCH_OMAP1 is not set
3227+# CONFIG_ARCH_OMAP2 is not set
3228+CONFIG_ARCH_OMAP3=y
3229+
3230+#
3231+# OMAP Feature Selections
3232+#
3233+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
3234+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
3235+CONFIG_OMAP_SMARTREFLEX=y
3236+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
3237+# CONFIG_OMAP_RESET_CLOCKS is not set
3238+CONFIG_OMAP_BOOT_TAG=y
3239+CONFIG_OMAP_BOOT_REASON=y
3240+# CONFIG_OMAP_COMPONENT_VERSION is not set
3241+# CONFIG_OMAP_GPIO_SWITCH is not set
3242+# CONFIG_OMAP_MUX is not set
3243+CONFIG_OMAP_MCBSP=y
3244+# CONFIG_OMAP_MBOX_FWK is not set
3245+# CONFIG_OMAP_MPU_TIMER is not set
3246+CONFIG_OMAP_32K_TIMER=y
3247+CONFIG_OMAP_32K_TIMER_HZ=128
3248+CONFIG_OMAP_TICK_GPTIMER=1
3249+CONFIG_OMAP_DM_TIMER=y
3250+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
3251+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
3252+CONFIG_OMAP_LL_DEBUG_UART3=y
3253+CONFIG_ARCH_OMAP34XX=y
3254+CONFIG_ARCH_OMAP3430=y
3255+
3256+#
3257+# OMAP Board Type
3258+#
3259+# CONFIG_MACH_NOKIA_RX51 is not set
3260+# CONFIG_MACH_OMAP_LDP is not set
3261+# CONFIG_MACH_OMAP_3430SDP is not set
3262+# CONFIG_MACH_OMAP3EVM is not set
3263+# CONFIG_MACH_OMAP3_BEAGLE is not set
3264+CONFIG_MACH_OVERO=y
3265+# CONFIG_MACH_OMAP3_PANDORA is not set
3266+
3267+#
3268+# Processor Type
3269+#
3270+CONFIG_CPU_32=y
3271+CONFIG_CPU_32v6K=y
3272+CONFIG_CPU_V7=y
3273+CONFIG_CPU_32v7=y
3274+CONFIG_CPU_ABRT_EV7=y
3275+CONFIG_CPU_PABRT_IFAR=y
3276+CONFIG_CPU_CACHE_V7=y
3277+CONFIG_CPU_CACHE_VIPT=y
3278+CONFIG_CPU_COPY_V6=y
3279+CONFIG_CPU_TLB_V7=y
3280+CONFIG_CPU_HAS_ASID=y
3281+CONFIG_CPU_CP15=y
3282+CONFIG_CPU_CP15_MMU=y
3283+
3284+#
3285+# Processor Features
3286+#
3287+CONFIG_ARM_THUMB=y
3288+CONFIG_ARM_THUMBEE=y
3289+# CONFIG_CPU_ICACHE_DISABLE is not set
3290+# CONFIG_CPU_DCACHE_DISABLE is not set
3291+# CONFIG_CPU_BPREDICT_DISABLE is not set
3292+CONFIG_HAS_TLS_REG=y
3293+# CONFIG_OUTER_CACHE is not set
3294+
3295+#
3296+# Bus support
3297+#
3298+# CONFIG_PCI_SYSCALL is not set
3299+# CONFIG_ARCH_SUPPORTS_MSI is not set
3300+# CONFIG_PCCARD is not set
3301+
3302+#
3303+# Kernel Features
3304+#
3305+CONFIG_TICK_ONESHOT=y
3306+CONFIG_NO_HZ=y
3307+CONFIG_HIGH_RES_TIMERS=y
3308+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
3309+CONFIG_VMSPLIT_3G=y
3310+# CONFIG_VMSPLIT_2G is not set
3311+# CONFIG_VMSPLIT_1G is not set
3312+CONFIG_PAGE_OFFSET=0xC0000000
3313+# CONFIG_PREEMPT is not set
3314+CONFIG_HZ=128
3315+CONFIG_AEABI=y
3316+# CONFIG_OABI_COMPAT is not set
3317+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
3318+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
3319+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
3320+CONFIG_SELECT_MEMORY_MODEL=y
3321+CONFIG_FLATMEM_MANUAL=y
3322+# CONFIG_DISCONTIGMEM_MANUAL is not set
3323+# CONFIG_SPARSEMEM_MANUAL is not set
3324+CONFIG_FLATMEM=y
3325+CONFIG_FLAT_NODE_MEM_MAP=y
3326+CONFIG_PAGEFLAGS_EXTENDED=y
3327+CONFIG_SPLIT_PTLOCK_CPUS=4
3328+# CONFIG_PHYS_ADDR_T_64BIT is not set
3329+CONFIG_ZONE_DMA_FLAG=0
3330+CONFIG_VIRT_TO_BUS=y
3331+CONFIG_UNEVICTABLE_LRU=y
3332+CONFIG_LEDS=y
3333+CONFIG_ALIGNMENT_TRAP=y
3334+
3335+#
3336+# Boot options
3337+#
3338+CONFIG_ZBOOT_ROM_TEXT=0x0
3339+CONFIG_ZBOOT_ROM_BSS=0x0
3340+CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.2.14:/tftpboot/rootfs ip=192.168.2.15 nolock,rsize=1024,wsize=1024 rw"
3341+# CONFIG_XIP_KERNEL is not set
3342+CONFIG_KEXEC=y
3343+CONFIG_ATAGS_PROC=y
3344+
3345+#
3346+# CPU Power Management
3347+#
3348+CONFIG_CPU_FREQ=y
3349+CONFIG_CPU_FREQ_TABLE=y
3350+# CONFIG_CPU_FREQ_DEBUG is not set
3351+CONFIG_CPU_FREQ_STAT=y
3352+CONFIG_CPU_FREQ_STAT_DETAILS=y
3353+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
3354+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
3355+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
3356+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
3357+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
3358+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
3359+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
3360+CONFIG_CPU_FREQ_GOV_USERSPACE=y
3361+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
3362+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
3363+# CONFIG_CPU_IDLE is not set
3364+
3365+#
3366+# Floating point emulation
3367+#
3368+
3369+#
3370+# At least one emulation must be selected
3371+#
3372+CONFIG_VFP=y
3373+CONFIG_VFPv3=y
3374+CONFIG_NEON=y
3375+
3376+#
3377+# Userspace binary formats
3378+#
3379+CONFIG_BINFMT_ELF=y
3380+CONFIG_HAVE_AOUT=y
3381+CONFIG_BINFMT_AOUT=m
3382+CONFIG_BINFMT_MISC=y
3383+
3384+#
3385+# Power management options
3386+#
3387+CONFIG_PM=y
3388+# CONFIG_PM_DEBUG is not set
3389+CONFIG_PM_SLEEP=y
3390+CONFIG_SUSPEND=y
3391+CONFIG_SUSPEND_FREEZER=y
3392+# CONFIG_APM_EMULATION is not set
3393+CONFIG_ARCH_SUSPEND_POSSIBLE=y
3394+CONFIG_NET=y
3395+
3396+#
3397+# Networking options
3398+#
3399+CONFIG_COMPAT_NET_DEV_OPS=y
3400+CONFIG_PACKET=y
3401+CONFIG_PACKET_MMAP=y
3402+CONFIG_UNIX=y
3403+CONFIG_XFRM=y
3404+# CONFIG_XFRM_USER is not set
3405+# CONFIG_XFRM_SUB_POLICY is not set
3406+# CONFIG_XFRM_MIGRATE is not set
3407+# CONFIG_XFRM_STATISTICS is not set
3408+CONFIG_NET_KEY=y
3409+# CONFIG_NET_KEY_MIGRATE is not set
3410+CONFIG_INET=y
3411+# CONFIG_IP_MULTICAST is not set
3412+# CONFIG_IP_ADVANCED_ROUTER is not set
3413+CONFIG_IP_FIB_HASH=y
3414+CONFIG_IP_PNP=y
3415+CONFIG_IP_PNP_DHCP=y
3416+CONFIG_IP_PNP_BOOTP=y
3417+CONFIG_IP_PNP_RARP=y
3418+# CONFIG_NET_IPIP is not set
3419+# CONFIG_NET_IPGRE is not set
3420+# CONFIG_ARPD is not set
3421+# CONFIG_SYN_COOKIES is not set
3422+# CONFIG_INET_AH is not set
3423+# CONFIG_INET_ESP is not set
3424+# CONFIG_INET_IPCOMP is not set
3425+# CONFIG_INET_XFRM_TUNNEL is not set
3426+CONFIG_INET_TUNNEL=m
3427+CONFIG_INET_XFRM_MODE_TRANSPORT=y
3428+CONFIG_INET_XFRM_MODE_TUNNEL=y
3429+CONFIG_INET_XFRM_MODE_BEET=y
3430+# CONFIG_INET_LRO is not set
3431+CONFIG_INET_DIAG=y
3432+CONFIG_INET_TCP_DIAG=y
3433+# CONFIG_TCP_CONG_ADVANCED is not set
3434+CONFIG_TCP_CONG_CUBIC=y
3435+CONFIG_DEFAULT_TCP_CONG="cubic"
3436+# CONFIG_TCP_MD5SIG is not set
3437+CONFIG_IPV6=m
3438+# CONFIG_IPV6_PRIVACY is not set
3439+# CONFIG_IPV6_ROUTER_PREF is not set
3440+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
3441+# CONFIG_INET6_AH is not set
3442+# CONFIG_INET6_ESP is not set
3443+# CONFIG_INET6_IPCOMP is not set
3444+# CONFIG_IPV6_MIP6 is not set
3445+# CONFIG_INET6_XFRM_TUNNEL is not set
3446+# CONFIG_INET6_TUNNEL is not set
3447+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
3448+CONFIG_INET6_XFRM_MODE_TUNNEL=m
3449+CONFIG_INET6_XFRM_MODE_BEET=m
3450+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
3451+CONFIG_IPV6_SIT=m
3452+CONFIG_IPV6_NDISC_NODETYPE=y
3453+# CONFIG_IPV6_TUNNEL is not set
3454+# CONFIG_IPV6_MULTIPLE_TABLES is not set
3455+# CONFIG_IPV6_MROUTE is not set
3456+# CONFIG_NETWORK_SECMARK is not set
3457+# CONFIG_NETFILTER is not set
3458+# CONFIG_IP_DCCP is not set
3459+# CONFIG_IP_SCTP is not set
3460+# CONFIG_TIPC is not set
3461+# CONFIG_ATM is not set
3462+# CONFIG_BRIDGE is not set
3463+# CONFIG_NET_DSA is not set
3464+# CONFIG_VLAN_8021Q is not set
3465+# CONFIG_DECNET is not set
3466+# CONFIG_LLC2 is not set
3467+# CONFIG_IPX is not set
3468+# CONFIG_ATALK is not set
3469+# CONFIG_X25 is not set
3470+# CONFIG_LAPB is not set
3471+# CONFIG_ECONET is not set
3472+# CONFIG_WAN_ROUTER is not set
3473+# CONFIG_NET_SCHED is not set
3474+# CONFIG_DCB is not set
3475+
3476+#
3477+# Network testing
3478+#
3479+# CONFIG_NET_PKTGEN is not set
3480+# CONFIG_HAMRADIO is not set
3481+# CONFIG_CAN is not set
3482+# CONFIG_IRDA is not set
3483+CONFIG_BT=y
3484+CONFIG_BT_L2CAP=y
3485+CONFIG_BT_SCO=y
3486+CONFIG_BT_RFCOMM=y
3487+CONFIG_BT_RFCOMM_TTY=y
3488+CONFIG_BT_BNEP=y
3489+CONFIG_BT_BNEP_MC_FILTER=y
3490+CONFIG_BT_BNEP_PROTO_FILTER=y
3491+CONFIG_BT_HIDP=y
3492+
3493+#
3494+# Bluetooth device drivers
3495+#
3496+# CONFIG_BT_HCIBTSDIO is not set
3497+CONFIG_BT_HCIUART=y
3498+CONFIG_BT_HCIUART_H4=y
3499+CONFIG_BT_HCIUART_BCSP=y
3500+# CONFIG_BT_HCIUART_LL is not set
3501+# CONFIG_BT_HCIBRF6150 is not set
3502+# CONFIG_BT_HCIH4P is not set
3503+# CONFIG_BT_HCIVHCI is not set
3504+# CONFIG_AF_RXRPC is not set
3505+# CONFIG_PHONET is not set
3506+CONFIG_WIRELESS=y
3507+CONFIG_CFG80211=y
3508+# CONFIG_CFG80211_REG_DEBUG is not set
3509+CONFIG_NL80211=y
3510+CONFIG_WIRELESS_OLD_REGULATORY=y
3511+CONFIG_WIRELESS_EXT=y
3512+CONFIG_WIRELESS_EXT_SYSFS=y
3513+CONFIG_LIB80211=y
3514+CONFIG_LIB80211_CRYPT_WEP=m
3515+CONFIG_LIB80211_CRYPT_CCMP=m
3516+CONFIG_LIB80211_CRYPT_TKIP=m
3517+# CONFIG_LIB80211_DEBUG is not set
3518+CONFIG_MAC80211=y
3519+
3520+#
3521+# Rate control algorithm selection
3522+#
3523+CONFIG_MAC80211_RC_PID=y
3524+CONFIG_MAC80211_RC_MINSTREL=y
3525+CONFIG_MAC80211_RC_DEFAULT_PID=y
3526+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
3527+CONFIG_MAC80211_RC_DEFAULT="pid"
3528+# CONFIG_MAC80211_MESH is not set
3529+CONFIG_MAC80211_LEDS=y
3530+# CONFIG_MAC80211_DEBUGFS is not set
3531+# CONFIG_MAC80211_DEBUG_MENU is not set
3532+# CONFIG_WIMAX is not set
3533+# CONFIG_RFKILL is not set
3534+# CONFIG_NET_9P is not set
3535+
3536+#
3537+# Device Drivers
3538+#
3539+
3540+#
3541+# Generic Driver Options
3542+#
3543+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
3544+CONFIG_STANDALONE=y
3545+CONFIG_PREVENT_FIRMWARE_BUILD=y
3546+CONFIG_FW_LOADER=y
3547+CONFIG_FIRMWARE_IN_KERNEL=y
3548+CONFIG_EXTRA_FIRMWARE=""
3549+# CONFIG_DEBUG_DRIVER is not set
3550+# CONFIG_DEBUG_DEVRES is not set
3551+# CONFIG_SYS_HYPERVISOR is not set
3552+# CONFIG_CONNECTOR is not set
3553+CONFIG_MTD=y
3554+# CONFIG_MTD_DEBUG is not set
3555+CONFIG_MTD_CONCAT=y
3556+CONFIG_MTD_PARTITIONS=y
3557+# CONFIG_MTD_TESTS is not set
3558+# CONFIG_MTD_REDBOOT_PARTS is not set
3559+# CONFIG_MTD_CMDLINE_PARTS is not set
3560+# CONFIG_MTD_AFS_PARTS is not set
3561+# CONFIG_MTD_AR7_PARTS is not set
3562+
3563+#
3564+# User Modules And Translation Layers
3565+#
3566+CONFIG_MTD_CHAR=y
3567+CONFIG_MTD_BLKDEVS=y
3568+CONFIG_MTD_BLOCK=y
3569+# CONFIG_FTL is not set
3570+# CONFIG_NFTL is not set
3571+# CONFIG_INFTL is not set
3572+# CONFIG_RFD_FTL is not set
3573+# CONFIG_SSFDC is not set
3574+# CONFIG_MTD_OOPS is not set
3575+
3576+#
3577+# RAM/ROM/Flash chip drivers
3578+#
3579+# CONFIG_MTD_CFI is not set
3580+# CONFIG_MTD_JEDECPROBE is not set
3581+CONFIG_MTD_MAP_BANK_WIDTH_1=y
3582+CONFIG_MTD_MAP_BANK_WIDTH_2=y
3583+CONFIG_MTD_MAP_BANK_WIDTH_4=y
3584+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
3585+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
3586+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
3587+CONFIG_MTD_CFI_I1=y
3588+CONFIG_MTD_CFI_I2=y
3589+# CONFIG_MTD_CFI_I4 is not set
3590+# CONFIG_MTD_CFI_I8 is not set
3591+# CONFIG_MTD_RAM is not set
3592+# CONFIG_MTD_ROM is not set
3593+# CONFIG_MTD_ABSENT is not set
3594+
3595+#
3596+# Mapping drivers for chip access
3597+#
3598+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
3599+# CONFIG_MTD_PLATRAM is not set
3600+
3601+#
3602+# Self-contained MTD device drivers
3603+#
3604+# CONFIG_MTD_DATAFLASH is not set
3605+# CONFIG_MTD_M25P80 is not set
3606+# CONFIG_MTD_SLRAM is not set
3607+# CONFIG_MTD_PHRAM is not set
3608+# CONFIG_MTD_MTDRAM is not set
3609+# CONFIG_MTD_BLOCK2MTD is not set
3610+
3611+#
3612+# Disk-On-Chip Device Drivers
3613+#
3614+# CONFIG_MTD_DOC2000 is not set
3615+# CONFIG_MTD_DOC2001 is not set
3616+# CONFIG_MTD_DOC2001PLUS is not set
3617+CONFIG_MTD_NAND=y
3618+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
3619+# CONFIG_MTD_NAND_ECC_SMC is not set
3620+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
3621+# CONFIG_MTD_NAND_GPIO is not set
3622+CONFIG_MTD_NAND_OMAP2=y
3623+CONFIG_MTD_NAND_IDS=y
3624+# CONFIG_MTD_NAND_DISKONCHIP is not set
3625+# CONFIG_MTD_NAND_NANDSIM is not set
3626+# CONFIG_MTD_NAND_PLATFORM is not set
3627+# CONFIG_MTD_ONENAND is not set
3628+
3629+#
3630+# LPDDR flash memory drivers
3631+#
3632+# CONFIG_MTD_LPDDR is not set
3633+
3634+#
3635+# UBI - Unsorted block images
3636+#
3637+# CONFIG_MTD_UBI is not set
3638+# CONFIG_PARPORT is not set
3639+CONFIG_BLK_DEV=y
3640+# CONFIG_BLK_DEV_COW_COMMON is not set
3641+CONFIG_BLK_DEV_LOOP=y
3642+CONFIG_BLK_DEV_CRYPTOLOOP=m
3643+# CONFIG_BLK_DEV_NBD is not set
3644+CONFIG_BLK_DEV_RAM=y
3645+CONFIG_BLK_DEV_RAM_COUNT=16
3646+CONFIG_BLK_DEV_RAM_SIZE=16384
3647+# CONFIG_BLK_DEV_XIP is not set
3648+CONFIG_CDROM_PKTCDVD=m
3649+CONFIG_CDROM_PKTCDVD_BUFFERS=8
3650+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
3651+# CONFIG_ATA_OVER_ETH is not set
3652+CONFIG_MISC_DEVICES=y
3653+# CONFIG_ICS932S401 is not set
3654+# CONFIG_OMAP_STI is not set
3655+# CONFIG_ENCLOSURE_SERVICES is not set
3656+# CONFIG_C2PORT is not set
3657+
3658+#
3659+# EEPROM support
3660+#
3661+# CONFIG_EEPROM_AT24 is not set
3662+# CONFIG_EEPROM_AT25 is not set
3663+# CONFIG_EEPROM_LEGACY is not set
3664+CONFIG_EEPROM_93CX6=m
3665+CONFIG_HAVE_IDE=y
3666+# CONFIG_IDE is not set
3667+
3668+#
3669+# SCSI device support
3670+#
3671+CONFIG_RAID_ATTRS=m
3672+CONFIG_SCSI=y
3673+CONFIG_SCSI_DMA=y
3674+# CONFIG_SCSI_TGT is not set
3675+# CONFIG_SCSI_NETLINK is not set
3676+CONFIG_SCSI_PROC_FS=y
3677+
3678+#
3679+# SCSI support type (disk, tape, CD-ROM)
3680+#
3681+CONFIG_BLK_DEV_SD=y
3682+# CONFIG_CHR_DEV_ST is not set
3683+# CONFIG_CHR_DEV_OSST is not set
3684+# CONFIG_BLK_DEV_SR is not set
3685+CONFIG_CHR_DEV_SG=m
3686+# CONFIG_CHR_DEV_SCH is not set
3687+
3688+#
3689+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
3690+#
3691+CONFIG_SCSI_MULTI_LUN=y
3692+# CONFIG_SCSI_CONSTANTS is not set
3693+# CONFIG_SCSI_LOGGING is not set
3694+# CONFIG_SCSI_SCAN_ASYNC is not set
3695+CONFIG_SCSI_WAIT_SCAN=m
3696+
3697+#
3698+# SCSI Transports
3699+#
3700+# CONFIG_SCSI_SPI_ATTRS is not set
3701+# CONFIG_SCSI_FC_ATTRS is not set
3702+# CONFIG_SCSI_ISCSI_ATTRS is not set
3703+# CONFIG_SCSI_SAS_LIBSAS is not set
3704+# CONFIG_SCSI_SRP_ATTRS is not set
3705+CONFIG_SCSI_LOWLEVEL=y
3706+# CONFIG_ISCSI_TCP is not set
3707+# CONFIG_LIBFC is not set
3708+# CONFIG_SCSI_DEBUG is not set
3709+# CONFIG_SCSI_DH is not set
3710+# CONFIG_ATA is not set
3711+CONFIG_MD=y
3712+CONFIG_BLK_DEV_MD=m
3713+CONFIG_MD_LINEAR=m
3714+CONFIG_MD_RAID0=m
3715+CONFIG_MD_RAID1=m
3716+CONFIG_MD_RAID10=m
3717+CONFIG_MD_RAID456=m
3718+CONFIG_MD_RAID5_RESHAPE=y
3719+CONFIG_MD_MULTIPATH=m
3720+CONFIG_MD_FAULTY=m
3721+CONFIG_BLK_DEV_DM=m
3722+# CONFIG_DM_DEBUG is not set
3723+CONFIG_DM_CRYPT=m
3724+CONFIG_DM_SNAPSHOT=m
3725+CONFIG_DM_MIRROR=m
3726+CONFIG_DM_ZERO=m
3727+CONFIG_DM_MULTIPATH=m
3728+CONFIG_DM_DELAY=m
3729+# CONFIG_DM_UEVENT is not set
3730+CONFIG_NETDEVICES=y
3731+CONFIG_DUMMY=m
3732+# CONFIG_BONDING is not set
3733+# CONFIG_MACVLAN is not set
3734+# CONFIG_EQUALIZER is not set
3735+CONFIG_TUN=m
3736+# CONFIG_VETH is not set
3737+# CONFIG_NET_ETHERNET is not set
3738+# CONFIG_NETDEV_1000 is not set
3739+# CONFIG_NETDEV_10000 is not set
3740+
3741+#
3742+# Wireless LAN
3743+#
3744+# CONFIG_WLAN_PRE80211 is not set
3745+CONFIG_WLAN_80211=y
3746+CONFIG_LIBERTAS=y
3747+CONFIG_LIBERTAS_SDIO=y
3748+CONFIG_LIBERTAS_DEBUG=y
3749+# CONFIG_LIBERTAS_THINFIRM is not set
3750+# CONFIG_MAC80211_HWSIM is not set
3751+CONFIG_P54_COMMON=m
3752+# CONFIG_IWLWIFI_LEDS is not set
3753+CONFIG_HOSTAP=m
3754+CONFIG_HOSTAP_FIRMWARE=y
3755+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
3756+# CONFIG_B43 is not set
3757+# CONFIG_B43LEGACY is not set
3758+# CONFIG_RT2X00 is not set
3759+
3760+#
3761+# Enable WiMAX (Networking options) to see the WiMAX drivers
3762+#
3763+# CONFIG_WAN is not set
3764+CONFIG_PPP=m
3765+# CONFIG_PPP_MULTILINK is not set
3766+# CONFIG_PPP_FILTER is not set
3767+CONFIG_PPP_ASYNC=m
3768+CONFIG_PPP_SYNC_TTY=m
3769+CONFIG_PPP_DEFLATE=m
3770+CONFIG_PPP_BSDCOMP=m
3771+CONFIG_PPP_MPPE=m
3772+CONFIG_PPPOE=m
3773+# CONFIG_PPPOL2TP is not set
3774+# CONFIG_SLIP is not set
3775+CONFIG_SLHC=m
3776+# CONFIG_NETCONSOLE is not set
3777+# CONFIG_NETPOLL is not set
3778+# CONFIG_NET_POLL_CONTROLLER is not set
3779+# CONFIG_ISDN is not set
3780+
3781+#
3782+# Input device support
3783+#
3784+CONFIG_INPUT=y
3785+# CONFIG_INPUT_FF_MEMLESS is not set
3786+# CONFIG_INPUT_POLLDEV is not set
3787+
3788+#
3789+# Userland interfaces
3790+#
3791+CONFIG_INPUT_MOUSEDEV=y
3792+CONFIG_INPUT_MOUSEDEV_PSAUX=y
3793+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
3794+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
3795+# CONFIG_INPUT_JOYDEV is not set
3796+CONFIG_INPUT_EVDEV=y
3797+# CONFIG_INPUT_EVBUG is not set
3798+
3799+#
3800+# Input Device Drivers
3801+#
3802+CONFIG_INPUT_KEYBOARD=y
3803+# CONFIG_KEYBOARD_ATKBD is not set
3804+# CONFIG_KEYBOARD_SUNKBD is not set
3805+# CONFIG_KEYBOARD_LKKBD is not set
3806+# CONFIG_KEYBOARD_XTKBD is not set
3807+# CONFIG_KEYBOARD_NEWTON is not set
3808+# CONFIG_KEYBOARD_STOWAWAY is not set
3809+# CONFIG_KEYBOARD_TWL4030 is not set
3810+# CONFIG_KEYBOARD_LM8323 is not set
3811+# CONFIG_KEYBOARD_GPIO is not set
3812+CONFIG_INPUT_MOUSE=y
3813+CONFIG_MOUSE_PS2=y
3814+CONFIG_MOUSE_PS2_ALPS=y
3815+CONFIG_MOUSE_PS2_LOGIPS2PP=y
3816+CONFIG_MOUSE_PS2_SYNAPTICS=y
3817+CONFIG_MOUSE_PS2_TRACKPOINT=y
3818+# CONFIG_MOUSE_PS2_ELANTECH is not set
3819+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
3820+# CONFIG_MOUSE_SERIAL is not set
3821+# CONFIG_MOUSE_APPLETOUCH is not set
3822+# CONFIG_MOUSE_BCM5974 is not set
3823+# CONFIG_MOUSE_VSXXXAA is not set
3824+# CONFIG_MOUSE_GPIO is not set
3825+# CONFIG_INPUT_JOYSTICK is not set
3826+# CONFIG_INPUT_TABLET is not set
3827+# CONFIG_INPUT_TOUCHSCREEN is not set
3828+# CONFIG_INPUT_MISC is not set
3829+
3830+#
3831+# Hardware I/O ports
3832+#
3833+CONFIG_SERIO=y
3834+CONFIG_SERIO_SERPORT=y
3835+CONFIG_SERIO_LIBPS2=y
3836+# CONFIG_SERIO_RAW is not set
3837+# CONFIG_GAMEPORT is not set
3838+
3839+#
3840+# Character devices
3841+#
3842+CONFIG_VT=y
3843+CONFIG_CONSOLE_TRANSLATIONS=y
3844+CONFIG_VT_CONSOLE=y
3845+CONFIG_HW_CONSOLE=y
3846+CONFIG_VT_HW_CONSOLE_BINDING=y
3847+CONFIG_DEVKMEM=y
3848+# CONFIG_SERIAL_NONSTANDARD is not set
3849+
3850+#
3851+# Serial drivers
3852+#
3853+CONFIG_SERIAL_8250=y
3854+CONFIG_SERIAL_8250_CONSOLE=y
3855+CONFIG_SERIAL_8250_NR_UARTS=32
3856+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
3857+CONFIG_SERIAL_8250_EXTENDED=y
3858+CONFIG_SERIAL_8250_MANY_PORTS=y
3859+CONFIG_SERIAL_8250_SHARE_IRQ=y
3860+CONFIG_SERIAL_8250_DETECT_IRQ=y
3861+CONFIG_SERIAL_8250_RSA=y
3862+
3863+#
3864+# Non-8250 serial port support
3865+#
3866+CONFIG_SERIAL_CORE=y
3867+CONFIG_SERIAL_CORE_CONSOLE=y
3868+CONFIG_UNIX98_PTYS=y
3869+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
3870+# CONFIG_LEGACY_PTYS is not set
3871+# CONFIG_IPMI_HANDLER is not set
3872+CONFIG_HW_RANDOM=y
3873+# CONFIG_R3964 is not set
3874+# CONFIG_RAW_DRIVER is not set
3875+# CONFIG_TCG_TPM is not set
3876+CONFIG_I2C=y
3877+CONFIG_I2C_BOARDINFO=y
3878+CONFIG_I2C_CHARDEV=y
3879+CONFIG_I2C_HELPER_AUTO=y
3880+
3881+#
3882+# I2C Hardware Bus support
3883+#
3884+
3885+#
3886+# I2C system bus drivers (mostly embedded / system-on-chip)
3887+#
3888+# CONFIG_I2C_GPIO is not set
3889+# CONFIG_I2C_OCORES is not set
3890+CONFIG_I2C_OMAP=y
3891+# CONFIG_I2C_SIMTEC is not set
3892+
3893+#
3894+# External I2C/SMBus adapter drivers
3895+#
3896+# CONFIG_I2C_PARPORT_LIGHT is not set
3897+# CONFIG_I2C_TAOS_EVM is not set
3898+
3899+#
3900+# Other I2C/SMBus bus drivers
3901+#
3902+# CONFIG_I2C_PCA_PLATFORM is not set
3903+# CONFIG_I2C_STUB is not set
3904+
3905+#
3906+# Miscellaneous I2C Chip support
3907+#
3908+# CONFIG_DS1682 is not set
3909+# CONFIG_SENSORS_PCF8574 is not set
3910+# CONFIG_PCF8575 is not set
3911+# CONFIG_SENSORS_PCA9539 is not set
3912+# CONFIG_SENSORS_PCF8591 is not set
3913+CONFIG_TWL4030_MADC=m
3914+CONFIG_TWL4030_POWEROFF=y
3915+# CONFIG_SENSORS_MAX6875 is not set
3916+# CONFIG_SENSORS_TSL2550 is not set
3917+# CONFIG_SENSORS_TSL2563 is not set
3918+# CONFIG_I2C_DEBUG_CORE is not set
3919+# CONFIG_I2C_DEBUG_ALGO is not set
3920+# CONFIG_I2C_DEBUG_BUS is not set
3921+# CONFIG_I2C_DEBUG_CHIP is not set
3922+CONFIG_SPI=y
3923+# CONFIG_SPI_DEBUG is not set
3924+CONFIG_SPI_MASTER=y
3925+
3926+#
3927+# SPI Master Controller Drivers
3928+#
3929+# CONFIG_SPI_BITBANG is not set
3930+# CONFIG_SPI_GPIO is not set
3931+CONFIG_SPI_OMAP24XX=y
3932+
3933+#
3934+# SPI Protocol Masters
3935+#
3936+# CONFIG_SPI_TSC210X is not set
3937+# CONFIG_SPI_TSC2301 is not set
3938+# CONFIG_SPI_SPIDEV is not set
3939+# CONFIG_SPI_TLE62X0 is not set
3940+CONFIG_ARCH_REQUIRE_GPIOLIB=y
3941+CONFIG_GPIOLIB=y
3942+CONFIG_DEBUG_GPIO=y
3943+CONFIG_GPIO_SYSFS=y
3944+
3945+#
3946+# Memory mapped GPIO expanders:
3947+#
3948+
3949+#
3950+# I2C GPIO expanders:
3951+#
3952+# CONFIG_GPIO_MAX732X is not set
3953+# CONFIG_GPIO_PCA953X is not set
3954+# CONFIG_GPIO_PCF857X is not set
3955+CONFIG_GPIO_TWL4030=y
3956+
3957+#
3958+# PCI GPIO expanders:
3959+#
3960+
3961+#
3962+# SPI GPIO expanders:
3963+#
3964+# CONFIG_GPIO_MAX7301 is not set
3965+# CONFIG_GPIO_MCP23S08 is not set
3966+# CONFIG_W1 is not set
3967+CONFIG_POWER_SUPPLY=m
3968+# CONFIG_POWER_SUPPLY_DEBUG is not set
3969+# CONFIG_PDA_POWER is not set
3970+# CONFIG_BATTERY_DS2760 is not set
3971+# CONFIG_TWL4030_BCI_BATTERY is not set
3972+# CONFIG_BATTERY_BQ27x00 is not set
3973+CONFIG_HWMON=y
3974+# CONFIG_HWMON_VID is not set
3975+# CONFIG_SENSORS_AD7414 is not set
3976+# CONFIG_SENSORS_AD7418 is not set
3977+# CONFIG_SENSORS_ADCXX is not set
3978+# CONFIG_SENSORS_ADM1021 is not set
3979+# CONFIG_SENSORS_ADM1025 is not set
3980+# CONFIG_SENSORS_ADM1026 is not set
3981+# CONFIG_SENSORS_ADM1029 is not set
3982+# CONFIG_SENSORS_ADM1031 is not set
3983+# CONFIG_SENSORS_ADM9240 is not set
3984+# CONFIG_SENSORS_ADT7462 is not set
3985+# CONFIG_SENSORS_ADT7470 is not set
3986+# CONFIG_SENSORS_ADT7473 is not set
3987+# CONFIG_SENSORS_ADT7475 is not set
3988+# CONFIG_SENSORS_ATXP1 is not set
3989+# CONFIG_SENSORS_DS1621 is not set
3990+# CONFIG_SENSORS_F71805F is not set
3991+# CONFIG_SENSORS_F71882FG is not set
3992+# CONFIG_SENSORS_F75375S is not set
3993+# CONFIG_SENSORS_GL518SM is not set
3994+# CONFIG_SENSORS_GL520SM is not set
3995+# CONFIG_SENSORS_IT87 is not set
3996+# CONFIG_SENSORS_LM63 is not set
3997+# CONFIG_SENSORS_LM70 is not set
3998+# CONFIG_SENSORS_LM75 is not set
3999+# CONFIG_SENSORS_LM77 is not set
4000+# CONFIG_SENSORS_LM78 is not set
4001+# CONFIG_SENSORS_LM80 is not set
4002+# CONFIG_SENSORS_LM83 is not set
4003+# CONFIG_SENSORS_LM85 is not set
4004+# CONFIG_SENSORS_LM87 is not set
4005+# CONFIG_SENSORS_LM90 is not set
4006+# CONFIG_SENSORS_LM92 is not set
4007+# CONFIG_SENSORS_LM93 is not set
4008+# CONFIG_SENSORS_LTC4245 is not set
4009+# CONFIG_SENSORS_MAX1111 is not set
4010+# CONFIG_SENSORS_MAX1619 is not set
4011+# CONFIG_SENSORS_MAX6650 is not set
4012+# CONFIG_SENSORS_PC87360 is not set
4013+# CONFIG_SENSORS_PC87427 is not set
4014+# CONFIG_SENSORS_DME1737 is not set
4015+# CONFIG_SENSORS_SMSC47M1 is not set
4016+# CONFIG_SENSORS_SMSC47M192 is not set
4017+# CONFIG_SENSORS_SMSC47B397 is not set
4018+# CONFIG_SENSORS_ADS7828 is not set
4019+# CONFIG_SENSORS_THMC50 is not set
4020+# CONFIG_SENSORS_VT1211 is not set
4021+# CONFIG_SENSORS_W83781D is not set
4022+# CONFIG_SENSORS_W83791D is not set
4023+# CONFIG_SENSORS_W83792D is not set
4024+# CONFIG_SENSORS_W83793 is not set
4025+# CONFIG_SENSORS_W83L785TS is not set
4026+# CONFIG_SENSORS_W83L786NG is not set
4027+# CONFIG_SENSORS_W83627HF is not set
4028+# CONFIG_SENSORS_W83627EHF is not set
4029+# CONFIG_SENSORS_TSC210X is not set
4030+CONFIG_SENSORS_OMAP34XX=y
4031+# CONFIG_HWMON_DEBUG_CHIP is not set
4032+# CONFIG_THERMAL is not set
4033+# CONFIG_THERMAL_HWMON is not set
4034+CONFIG_WATCHDOG=y
4035+CONFIG_WATCHDOG_NOWAYOUT=y
4036+
4037+#
4038+# Watchdog Device Drivers
4039+#
4040+# CONFIG_SOFT_WATCHDOG is not set
4041+CONFIG_OMAP_WATCHDOG=y
4042+CONFIG_SSB_POSSIBLE=y
4043+
4044+#
4045+# Sonics Silicon Backplane
4046+#
4047+# CONFIG_SSB is not set
4048+
4049+#
4050+# Multifunction device drivers
4051+#
4052+# CONFIG_MFD_CORE is not set
4053+# CONFIG_MFD_SM501 is not set
4054+# CONFIG_MFD_ASIC3 is not set
4055+# CONFIG_HTC_EGPIO is not set
4056+# CONFIG_HTC_PASIC3 is not set
4057+# CONFIG_TPS65010 is not set
4058+CONFIG_TWL4030_CORE=y
4059+# CONFIG_TWL4030_POWER is not set
4060+# CONFIG_MFD_TMIO is not set
4061+# CONFIG_MFD_T7L66XB is not set
4062+# CONFIG_MFD_TC6387XB is not set
4063+# CONFIG_MFD_TC6393XB is not set
4064+# CONFIG_PMIC_DA903X is not set
4065+# CONFIG_MFD_WM8400 is not set
4066+# CONFIG_MFD_WM8350_I2C is not set
4067+# CONFIG_MFD_PCF50633 is not set
4068+
4069+#
4070+# Multimedia devices
4071+#
4072+
4073+#
4074+# Multimedia core support
4075+#
4076+CONFIG_VIDEO_DEV=m
4077+CONFIG_VIDEO_V4L2_COMMON=m
4078+CONFIG_VIDEO_ALLOW_V4L1=y
4079+CONFIG_VIDEO_V4L1_COMPAT=y
4080+CONFIG_DVB_CORE=m
4081+CONFIG_VIDEO_MEDIA=m
4082+
4083+#
4084+# Multimedia drivers
4085+#
4086+CONFIG_MEDIA_ATTACH=y
4087+CONFIG_MEDIA_TUNER=m
4088+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
4089+CONFIG_MEDIA_TUNER_SIMPLE=m
4090+CONFIG_MEDIA_TUNER_TDA8290=m
4091+CONFIG_MEDIA_TUNER_TDA9887=m
4092+CONFIG_MEDIA_TUNER_TEA5761=m
4093+CONFIG_MEDIA_TUNER_TEA5767=m
4094+CONFIG_MEDIA_TUNER_MT20XX=m
4095+CONFIG_MEDIA_TUNER_XC2028=m
4096+CONFIG_MEDIA_TUNER_XC5000=m
4097+CONFIG_VIDEO_V4L2=m
4098+CONFIG_VIDEO_V4L1=m
4099+CONFIG_VIDEO_CAPTURE_DRIVERS=y
4100+# CONFIG_VIDEO_ADV_DEBUG is not set
4101+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
4102+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
4103+# CONFIG_VIDEO_VIVI is not set
4104+# CONFIG_VIDEO_CPIA is not set
4105+# CONFIG_VIDEO_SAA5246A is not set
4106+# CONFIG_VIDEO_SAA5249 is not set
4107+# CONFIG_SOC_CAMERA is not set
4108+CONFIG_RADIO_ADAPTERS=y
4109+# CONFIG_RADIO_TEA5764 is not set
4110+# CONFIG_DVB_DYNAMIC_MINORS is not set
4111+CONFIG_DVB_CAPTURE_DRIVERS=y
4112+# CONFIG_TTPCI_EEPROM is not set
4113+# CONFIG_DVB_B2C2_FLEXCOP is not set
4114+
4115+#
4116+# Supported DVB Frontends
4117+#
4118+
4119+#
4120+# Customise DVB Frontends
4121+#
4122+# CONFIG_DVB_FE_CUSTOMISE is not set
4123+
4124+#
4125+# Multistandard (satellite) frontends
4126+#
4127+# CONFIG_DVB_STB0899 is not set
4128+# CONFIG_DVB_STB6100 is not set
4129+
4130+#
4131+# DVB-S (satellite) frontends
4132+#
4133+CONFIG_DVB_CX24110=m
4134+CONFIG_DVB_CX24123=m
4135+CONFIG_DVB_MT312=m
4136+CONFIG_DVB_S5H1420=m
4137+# CONFIG_DVB_STV0288 is not set
4138+# CONFIG_DVB_STB6000 is not set
4139+CONFIG_DVB_STV0299=m
4140+CONFIG_DVB_TDA8083=m
4141+CONFIG_DVB_TDA10086=m
4142+# CONFIG_DVB_TDA8261 is not set
4143+CONFIG_DVB_VES1X93=m
4144+CONFIG_DVB_TUNER_ITD1000=m
4145+# CONFIG_DVB_TUNER_CX24113 is not set
4146+CONFIG_DVB_TDA826X=m
4147+CONFIG_DVB_TUA6100=m
4148+# CONFIG_DVB_CX24116 is not set
4149+# CONFIG_DVB_SI21XX is not set
4150+
4151+#
4152+# DVB-T (terrestrial) frontends
4153+#
4154+CONFIG_DVB_SP8870=m
4155+CONFIG_DVB_SP887X=m
4156+CONFIG_DVB_CX22700=m
4157+CONFIG_DVB_CX22702=m
4158+# CONFIG_DVB_DRX397XD is not set
4159+CONFIG_DVB_L64781=m
4160+CONFIG_DVB_TDA1004X=m
4161+CONFIG_DVB_NXT6000=m
4162+CONFIG_DVB_MT352=m
4163+CONFIG_DVB_ZL10353=m
4164+CONFIG_DVB_DIB3000MB=m
4165+CONFIG_DVB_DIB3000MC=m
4166+CONFIG_DVB_DIB7000M=m
4167+CONFIG_DVB_DIB7000P=m
4168+CONFIG_DVB_TDA10048=m
4169+
4170+#
4171+# DVB-C (cable) frontends
4172+#
4173+CONFIG_DVB_VES1820=m
4174+CONFIG_DVB_TDA10021=m
4175+CONFIG_DVB_TDA10023=m
4176+CONFIG_DVB_STV0297=m
4177+
4178+#
4179+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
4180+#
4181+CONFIG_DVB_NXT200X=m
4182+# CONFIG_DVB_OR51211 is not set
4183+# CONFIG_DVB_OR51132 is not set
4184+CONFIG_DVB_BCM3510=m
4185+CONFIG_DVB_LGDT330X=m
4186+# CONFIG_DVB_LGDT3304 is not set
4187+CONFIG_DVB_S5H1409=m
4188+CONFIG_DVB_AU8522=m
4189+CONFIG_DVB_S5H1411=m
4190+
4191+#
4192+# ISDB-T (terrestrial) frontends
4193+#
4194+# CONFIG_DVB_S921 is not set
4195+
4196+#
4197+# Digital terrestrial only tuners/PLL
4198+#
4199+CONFIG_DVB_PLL=m
4200+CONFIG_DVB_TUNER_DIB0070=m
4201+
4202+#
4203+# SEC control devices for DVB-S
4204+#
4205+CONFIG_DVB_LNBP21=m
4206+# CONFIG_DVB_ISL6405 is not set
4207+CONFIG_DVB_ISL6421=m
4208+# CONFIG_DVB_LGS8GL5 is not set
4209+
4210+#
4211+# Tools to develop new frontends
4212+#
4213+# CONFIG_DVB_DUMMY_FE is not set
4214+# CONFIG_DVB_AF9013 is not set
4215+# CONFIG_DAB is not set
4216+
4217+#
4218+# Graphics support
4219+#
4220+# CONFIG_VGASTATE is not set
4221+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
4222+CONFIG_FB=y
4223+# CONFIG_FIRMWARE_EDID is not set
4224+# CONFIG_FB_DDC is not set
4225+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
4226+CONFIG_FB_CFB_FILLRECT=m
4227+CONFIG_FB_CFB_COPYAREA=m
4228+CONFIG_FB_CFB_IMAGEBLIT=m
4229+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
4230+# CONFIG_FB_SYS_FILLRECT is not set
4231+# CONFIG_FB_SYS_COPYAREA is not set
4232+# CONFIG_FB_SYS_IMAGEBLIT is not set
4233+# CONFIG_FB_FOREIGN_ENDIAN is not set
4234+# CONFIG_FB_SYS_FOPS is not set
4235+# CONFIG_FB_SVGALIB is not set
4236+# CONFIG_FB_MACMODES is not set
4237+# CONFIG_FB_BACKLIGHT is not set
4238+# CONFIG_FB_MODE_HELPERS is not set
4239+# CONFIG_FB_TILEBLITTING is not set
4240+
4241+#
4242+# Frame buffer hardware drivers
4243+#
4244+# CONFIG_FB_S1D13XXX is not set
4245+# CONFIG_FB_VIRTUAL is not set
4246+# CONFIG_FB_METRONOME is not set
4247+# CONFIG_FB_MB862XX is not set
4248+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
4249+CONFIG_OMAP2_DSS=m
4250+CONFIG_OMAP2_DSS_VRAM_SIZE=12
4251+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
4252+# CONFIG_OMAP2_DSS_RFBI is not set
4253+CONFIG_OMAP2_DSS_VENC=y
4254+# CONFIG_OMAP2_DSS_SDI is not set
4255+# CONFIG_OMAP2_DSS_DSI is not set
4256+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
4257+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
4258+
4259+#
4260+# OMAP2/3 Display Device Drivers
4261+#
4262+CONFIG_PANEL_GENERIC=m
4263+CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C=m
4264+# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
4265+# CONFIG_PANEL_N800 is not set
4266+# CONFIG_CTRL_BLIZZARD is not set
4267+CONFIG_FB_OMAP2=m
4268+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
4269+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
4270+CONFIG_FB_OMAP2_NUM_FBS=3
4271+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
4272+
4273+#
4274+# Display device support
4275+#
4276+CONFIG_DISPLAY_SUPPORT=y
4277+
4278+#
4279+# Display hardware drivers
4280+#
4281+
4282+#
4283+# Console display driver support
4284+#
4285+# CONFIG_VGA_CONSOLE is not set
4286+CONFIG_DUMMY_CONSOLE=y
4287+# CONFIG_FRAMEBUFFER_CONSOLE is not set
4288+# CONFIG_LOGO is not set
4289+CONFIG_SOUND=y
4290+CONFIG_SOUND_OSS_CORE=y
4291+CONFIG_SND=y
4292+CONFIG_SND_TIMER=y
4293+CONFIG_SND_PCM=y
4294+CONFIG_SND_SEQUENCER=m
4295+# CONFIG_SND_SEQ_DUMMY is not set
4296+CONFIG_SND_OSSEMUL=y
4297+CONFIG_SND_MIXER_OSS=y
4298+CONFIG_SND_PCM_OSS=y
4299+CONFIG_SND_PCM_OSS_PLUGINS=y
4300+CONFIG_SND_SEQUENCER_OSS=y
4301+# CONFIG_SND_HRTIMER is not set
4302+# CONFIG_SND_DYNAMIC_MINORS is not set
4303+CONFIG_SND_SUPPORT_OLD_API=y
4304+CONFIG_SND_VERBOSE_PROCFS=y
4305+CONFIG_SND_VERBOSE_PRINTK=y
4306+CONFIG_SND_DEBUG=y
4307+# CONFIG_SND_DEBUG_VERBOSE is not set
4308+# CONFIG_SND_PCM_XRUN_DEBUG is not set
4309+CONFIG_SND_DRIVERS=y
4310+# CONFIG_SND_DUMMY is not set
4311+# CONFIG_SND_VIRMIDI is not set
4312+# CONFIG_SND_MTPAV is not set
4313+# CONFIG_SND_SERIAL_U16550 is not set
4314+# CONFIG_SND_MPU401 is not set
4315+CONFIG_SND_ARM=y
4316+CONFIG_SND_SPI=y
4317+CONFIG_SND_SOC=y
4318+CONFIG_SND_OMAP_SOC=y
4319+CONFIG_SND_OMAP_SOC_MCBSP=y
4320+CONFIG_SND_OMAP_SOC_OVERO=y
4321+CONFIG_SND_SOC_I2C_AND_SPI=y
4322+# CONFIG_SND_SOC_ALL_CODECS is not set
4323+CONFIG_SND_SOC_TWL4030=y
4324+# CONFIG_SOUND_PRIME is not set
4325+CONFIG_HID_SUPPORT=y
4326+CONFIG_HID=y
4327+CONFIG_HID_DEBUG=y
4328+# CONFIG_HIDRAW is not set
4329+# CONFIG_HID_PID is not set
4330+
4331+#
4332+# Special HID drivers
4333+#
4334+CONFIG_HID_COMPAT=y
4335+# CONFIG_HID_APPLE is not set
4336+CONFIG_USB_SUPPORT=y
4337+CONFIG_USB_ARCH_HAS_HCD=y
4338+CONFIG_USB_ARCH_HAS_OHCI=y
4339+CONFIG_USB_ARCH_HAS_EHCI=y
4340+# CONFIG_USB is not set
4341+# CONFIG_USB_OTG_WHITELIST is not set
4342+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
4343+CONFIG_USB_MUSB_HDRC=y
4344+CONFIG_USB_MUSB_SOC=y
4345+
4346+#
4347+# OMAP 343x high speed USB support
4348+#
4349+# CONFIG_USB_MUSB_HOST is not set
4350+CONFIG_USB_MUSB_PERIPHERAL=y
4351+# CONFIG_USB_MUSB_OTG is not set
4352+CONFIG_USB_GADGET_MUSB_HDRC=y
4353+# CONFIG_MUSB_PIO_ONLY is not set
4354+CONFIG_USB_INVENTRA_DMA=y
4355+# CONFIG_USB_TI_CPPI_DMA is not set
4356+# CONFIG_USB_MUSB_DEBUG is not set
4357+
4358+#
4359+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
4360+#
4361+CONFIG_USB_GADGET=y
4362+# CONFIG_USB_GADGET_DEBUG is not set
4363+# CONFIG_USB_GADGET_DEBUG_FILES is not set
4364+# CONFIG_USB_GADGET_DEBUG_FS is not set
4365+CONFIG_USB_GADGET_VBUS_DRAW=2
4366+CONFIG_USB_GADGET_SELECTED=y
4367+# CONFIG_USB_GADGET_AT91 is not set
4368+# CONFIG_USB_GADGET_ATMEL_USBA is not set
4369+# CONFIG_USB_GADGET_FSL_USB2 is not set
4370+# CONFIG_USB_GADGET_LH7A40X is not set
4371+# CONFIG_USB_GADGET_OMAP is not set
4372+# CONFIG_USB_GADGET_PXA25X is not set
4373+# CONFIG_USB_GADGET_PXA27X is not set
4374+# CONFIG_USB_GADGET_S3C2410 is not set
4375+# CONFIG_USB_GADGET_IMX is not set
4376+# CONFIG_USB_GADGET_M66592 is not set
4377+# CONFIG_USB_GADGET_AMD5536UDC is not set
4378+# CONFIG_USB_GADGET_FSL_QE is not set
4379+# CONFIG_USB_GADGET_CI13XXX is not set
4380+# CONFIG_USB_GADGET_NET2280 is not set
4381+# CONFIG_USB_GADGET_GOKU is not set
4382+# CONFIG_USB_GADGET_DUMMY_HCD is not set
4383+CONFIG_USB_GADGET_DUALSPEED=y
4384+# CONFIG_USB_ZERO is not set
4385+CONFIG_USB_ETH=y
4386+CONFIG_USB_ETH_RNDIS=y
4387+# CONFIG_USB_GADGETFS is not set
4388+# CONFIG_USB_FILE_STORAGE is not set
4389+# CONFIG_USB_G_SERIAL is not set
4390+# CONFIG_USB_MIDI_GADGET is not set
4391+# CONFIG_USB_G_PRINTER is not set
4392+# CONFIG_USB_CDC_COMPOSITE is not set
4393+
4394+#
4395+# OTG and related infrastructure
4396+#
4397+CONFIG_USB_OTG_UTILS=y
4398+# CONFIG_USB_GPIO_VBUS is not set
4399+# CONFIG_ISP1301_OMAP is not set
4400+CONFIG_TWL4030_USB=y
4401+CONFIG_MMC=y
4402+# CONFIG_MMC_DEBUG is not set
4403+CONFIG_MMC_UNSAFE_RESUME=y
4404+
4405+#
4406+# MMC/SD/SDIO Card Drivers
4407+#
4408+CONFIG_MMC_BLOCK=y
4409+CONFIG_MMC_BLOCK_BOUNCE=y
4410+CONFIG_SDIO_UART=y
4411+# CONFIG_MMC_TEST is not set
4412+
4413+#
4414+# MMC/SD/SDIO Host Controller Drivers
4415+#
4416+# CONFIG_MMC_SDHCI is not set
4417+CONFIG_MMC_OMAP_HS=y
4418+# CONFIG_MMC_SPI is not set
4419+# CONFIG_MEMSTICK is not set
4420+# CONFIG_ACCESSIBILITY is not set
4421+CONFIG_NEW_LEDS=y
4422+CONFIG_LEDS_CLASS=y
4423+
4424+#
4425+# LED drivers
4426+#
4427+# CONFIG_LEDS_OMAP_DEBUG is not set
4428+# CONFIG_LEDS_OMAP is not set
4429+# CONFIG_LEDS_OMAP_PWM is not set
4430+# CONFIG_LEDS_PCA9532 is not set
4431+CONFIG_LEDS_GPIO=y
4432+# CONFIG_LEDS_LP5521 is not set
4433+# CONFIG_LEDS_PCA955X is not set
4434+
4435+#
4436+# LED Triggers
4437+#
4438+CONFIG_LEDS_TRIGGERS=y
4439+CONFIG_LEDS_TRIGGER_TIMER=y
4440+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
4441+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
4442+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
4443+CONFIG_RTC_LIB=y
4444+CONFIG_RTC_CLASS=y
4445+CONFIG_RTC_HCTOSYS=y
4446+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
4447+# CONFIG_RTC_DEBUG is not set
4448+
4449+#
4450+# RTC interfaces
4451+#
4452+CONFIG_RTC_INTF_SYSFS=y
4453+CONFIG_RTC_INTF_PROC=y
4454+CONFIG_RTC_INTF_DEV=y
4455+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
4456+# CONFIG_RTC_DRV_TEST is not set
4457+
4458+#
4459+# I2C RTC drivers
4460+#
4461+# CONFIG_RTC_DRV_DS1307 is not set
4462+# CONFIG_RTC_DRV_DS1374 is not set
4463+# CONFIG_RTC_DRV_DS1672 is not set
4464+# CONFIG_RTC_DRV_MAX6900 is not set
4465+# CONFIG_RTC_DRV_RS5C372 is not set
4466+# CONFIG_RTC_DRV_ISL1208 is not set
4467+# CONFIG_RTC_DRV_X1205 is not set
4468+# CONFIG_RTC_DRV_PCF8563 is not set
4469+# CONFIG_RTC_DRV_PCF8583 is not set
4470+# CONFIG_RTC_DRV_M41T80 is not set
4471+CONFIG_RTC_DRV_TWL4030=y
4472+# CONFIG_RTC_DRV_S35390A is not set
4473+# CONFIG_RTC_DRV_FM3130 is not set
4474+# CONFIG_RTC_DRV_RX8581 is not set
4475+
4476+#
4477+# SPI RTC drivers
4478+#
4479+# CONFIG_RTC_DRV_M41T94 is not set
4480+# CONFIG_RTC_DRV_DS1305 is not set
4481+# CONFIG_RTC_DRV_DS1390 is not set
4482+# CONFIG_RTC_DRV_MAX6902 is not set
4483+# CONFIG_RTC_DRV_R9701 is not set
4484+# CONFIG_RTC_DRV_RS5C348 is not set
4485+# CONFIG_RTC_DRV_DS3234 is not set
4486+
4487+#
4488+# Platform RTC drivers
4489+#
4490+# CONFIG_RTC_DRV_CMOS is not set
4491+# CONFIG_RTC_DRV_DS1286 is not set
4492+# CONFIG_RTC_DRV_DS1511 is not set
4493+# CONFIG_RTC_DRV_DS1553 is not set
4494+# CONFIG_RTC_DRV_DS1742 is not set
4495+# CONFIG_RTC_DRV_STK17TA8 is not set
4496+# CONFIG_RTC_DRV_M48T86 is not set
4497+# CONFIG_RTC_DRV_M48T35 is not set
4498+# CONFIG_RTC_DRV_M48T59 is not set
4499+# CONFIG_RTC_DRV_BQ4802 is not set
4500+# CONFIG_RTC_DRV_V3020 is not set
4501+
4502+#
4503+# on-CPU RTC drivers
4504+#
4505+# CONFIG_DMADEVICES is not set
4506+CONFIG_REGULATOR=y
4507+# CONFIG_REGULATOR_DEBUG is not set
4508+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
4509+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
4510+# CONFIG_REGULATOR_BQ24022 is not set
4511+CONFIG_REGULATOR_TWL4030=y
4512+# CONFIG_UIO is not set
4513+# CONFIG_STAGING is not set
4514+
4515+#
4516+# CBUS support
4517+#
4518+# CONFIG_CBUS is not set
4519+
4520+#
4521+# File systems
4522+#
4523+CONFIG_EXT2_FS=y
4524+# CONFIG_EXT2_FS_XATTR is not set
4525+# CONFIG_EXT2_FS_XIP is not set
4526+CONFIG_EXT3_FS=y
4527+# CONFIG_EXT3_FS_XATTR is not set
4528+# CONFIG_EXT4_FS is not set
4529+CONFIG_JBD=y
4530+# CONFIG_JBD_DEBUG is not set
4531+# CONFIG_REISERFS_FS is not set
4532+# CONFIG_JFS_FS is not set
4533+CONFIG_FS_POSIX_ACL=y
4534+CONFIG_FILE_LOCKING=y
4535+CONFIG_XFS_FS=m
4536+# CONFIG_XFS_QUOTA is not set
4537+# CONFIG_XFS_POSIX_ACL is not set
4538+# CONFIG_XFS_RT is not set
4539+# CONFIG_XFS_DEBUG is not set
4540+# CONFIG_GFS2_FS is not set
4541+# CONFIG_OCFS2_FS is not set
4542+# CONFIG_BTRFS_FS is not set
4543+CONFIG_DNOTIFY=y
4544+CONFIG_INOTIFY=y
4545+CONFIG_INOTIFY_USER=y
4546+CONFIG_QUOTA=y
4547+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
4548+CONFIG_PRINT_QUOTA_WARNING=y
4549+CONFIG_QUOTA_TREE=y
4550+# CONFIG_QFMT_V1 is not set
4551+CONFIG_QFMT_V2=y
4552+CONFIG_QUOTACTL=y
4553+# CONFIG_AUTOFS_FS is not set
4554+# CONFIG_AUTOFS4_FS is not set
4555+CONFIG_FUSE_FS=m
4556+
4557+#
4558+# CD-ROM/DVD Filesystems
4559+#
4560+CONFIG_ISO9660_FS=m
4561+CONFIG_JOLIET=y
4562+CONFIG_ZISOFS=y
4563+CONFIG_UDF_FS=m
4564+CONFIG_UDF_NLS=y
4565+
4566+#
4567+# DOS/FAT/NT Filesystems
4568+#
4569+CONFIG_FAT_FS=y
4570+CONFIG_MSDOS_FS=y
4571+CONFIG_VFAT_FS=y
4572+CONFIG_FAT_DEFAULT_CODEPAGE=437
4573+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
4574+# CONFIG_NTFS_FS is not set
4575+
4576+#
4577+# Pseudo filesystems
4578+#
4579+CONFIG_PROC_FS=y
4580+CONFIG_PROC_SYSCTL=y
4581+CONFIG_PROC_PAGE_MONITOR=y
4582+CONFIG_SYSFS=y
4583+CONFIG_TMPFS=y
4584+# CONFIG_TMPFS_POSIX_ACL is not set
4585+# CONFIG_HUGETLB_PAGE is not set
4586+# CONFIG_CONFIGFS_FS is not set
4587+CONFIG_MISC_FILESYSTEMS=y
4588+# CONFIG_ADFS_FS is not set
4589+# CONFIG_AFFS_FS is not set
4590+# CONFIG_HFS_FS is not set
4591+# CONFIG_HFSPLUS_FS is not set
4592+# CONFIG_BEFS_FS is not set
4593+# CONFIG_BFS_FS is not set
4594+# CONFIG_EFS_FS is not set
4595+CONFIG_JFFS2_FS=y
4596+CONFIG_JFFS2_FS_DEBUG=0
4597+CONFIG_JFFS2_FS_WRITEBUFFER=y
4598+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
4599+CONFIG_JFFS2_SUMMARY=y
4600+CONFIG_JFFS2_FS_XATTR=y
4601+CONFIG_JFFS2_FS_POSIX_ACL=y
4602+CONFIG_JFFS2_FS_SECURITY=y
4603+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
4604+CONFIG_JFFS2_ZLIB=y
4605+CONFIG_JFFS2_LZO=y
4606+CONFIG_JFFS2_RTIME=y
4607+CONFIG_JFFS2_RUBIN=y
4608+# CONFIG_JFFS2_CMODE_NONE is not set
4609+CONFIG_JFFS2_CMODE_PRIORITY=y
4610+# CONFIG_JFFS2_CMODE_SIZE is not set
4611+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
4612+# CONFIG_CRAMFS is not set
4613+# CONFIG_SQUASHFS is not set
4614+# CONFIG_VXFS_FS is not set
4615+# CONFIG_MINIX_FS is not set
4616+# CONFIG_OMFS_FS is not set
4617+# CONFIG_HPFS_FS is not set
4618+# CONFIG_QNX4FS_FS is not set
4619+# CONFIG_ROMFS_FS is not set
4620+# CONFIG_SYSV_FS is not set
4621+# CONFIG_UFS_FS is not set
4622+CONFIG_NETWORK_FILESYSTEMS=y
4623+CONFIG_NFS_FS=y
4624+CONFIG_NFS_V3=y
4625+# CONFIG_NFS_V3_ACL is not set
4626+CONFIG_NFS_V4=y
4627+CONFIG_ROOT_NFS=y
4628+# CONFIG_NFSD is not set
4629+CONFIG_LOCKD=y
4630+CONFIG_LOCKD_V4=y
4631+CONFIG_EXPORTFS=m
4632+CONFIG_NFS_COMMON=y
4633+CONFIG_SUNRPC=y
4634+CONFIG_SUNRPC_GSS=y
4635+# CONFIG_SUNRPC_REGISTER_V4 is not set
4636+CONFIG_RPCSEC_GSS_KRB5=y
4637+# CONFIG_RPCSEC_GSS_SPKM3 is not set
4638+# CONFIG_SMB_FS is not set
4639+# CONFIG_CIFS is not set
4640+# CONFIG_NCP_FS is not set
4641+# CONFIG_CODA_FS is not set
4642+# CONFIG_AFS_FS is not set
4643+
4644+#
4645+# Partition Types
4646+#
4647+CONFIG_PARTITION_ADVANCED=y
4648+# CONFIG_ACORN_PARTITION is not set
4649+# CONFIG_OSF_PARTITION is not set
4650+# CONFIG_AMIGA_PARTITION is not set
4651+# CONFIG_ATARI_PARTITION is not set
4652+# CONFIG_MAC_PARTITION is not set
4653+CONFIG_MSDOS_PARTITION=y
4654+# CONFIG_BSD_DISKLABEL is not set
4655+# CONFIG_MINIX_SUBPARTITION is not set
4656+# CONFIG_SOLARIS_X86_PARTITION is not set
4657+# CONFIG_UNIXWARE_DISKLABEL is not set
4658+# CONFIG_LDM_PARTITION is not set
4659+# CONFIG_SGI_PARTITION is not set
4660+# CONFIG_ULTRIX_PARTITION is not set
4661+# CONFIG_SUN_PARTITION is not set
4662+# CONFIG_KARMA_PARTITION is not set
4663+# CONFIG_EFI_PARTITION is not set
4664+# CONFIG_SYSV68_PARTITION is not set
4665+CONFIG_NLS=y
4666+CONFIG_NLS_DEFAULT="iso8859-1"
4667+CONFIG_NLS_CODEPAGE_437=y
4668+# CONFIG_NLS_CODEPAGE_737 is not set
4669+# CONFIG_NLS_CODEPAGE_775 is not set
4670+# CONFIG_NLS_CODEPAGE_850 is not set
4671+# CONFIG_NLS_CODEPAGE_852 is not set
4672+# CONFIG_NLS_CODEPAGE_855 is not set
4673+# CONFIG_NLS_CODEPAGE_857 is not set
4674+# CONFIG_NLS_CODEPAGE_860 is not set
4675+# CONFIG_NLS_CODEPAGE_861 is not set
4676+# CONFIG_NLS_CODEPAGE_862 is not set
4677+# CONFIG_NLS_CODEPAGE_863 is not set
4678+# CONFIG_NLS_CODEPAGE_864 is not set
4679+# CONFIG_NLS_CODEPAGE_865 is not set
4680+# CONFIG_NLS_CODEPAGE_866 is not set
4681+# CONFIG_NLS_CODEPAGE_869 is not set
4682+# CONFIG_NLS_CODEPAGE_936 is not set
4683+# CONFIG_NLS_CODEPAGE_950 is not set
4684+# CONFIG_NLS_CODEPAGE_932 is not set
4685+# CONFIG_NLS_CODEPAGE_949 is not set
4686+# CONFIG_NLS_CODEPAGE_874 is not set
4687+# CONFIG_NLS_ISO8859_8 is not set
4688+# CONFIG_NLS_CODEPAGE_1250 is not set
4689+# CONFIG_NLS_CODEPAGE_1251 is not set
4690+# CONFIG_NLS_ASCII is not set
4691+CONFIG_NLS_ISO8859_1=y
4692+# CONFIG_NLS_ISO8859_2 is not set
4693+# CONFIG_NLS_ISO8859_3 is not set
4694+# CONFIG_NLS_ISO8859_4 is not set
4695+# CONFIG_NLS_ISO8859_5 is not set
4696+# CONFIG_NLS_ISO8859_6 is not set
4697+# CONFIG_NLS_ISO8859_7 is not set
4698+# CONFIG_NLS_ISO8859_9 is not set
4699+# CONFIG_NLS_ISO8859_13 is not set
4700+# CONFIG_NLS_ISO8859_14 is not set
4701+# CONFIG_NLS_ISO8859_15 is not set
4702+# CONFIG_NLS_KOI8_R is not set
4703+# CONFIG_NLS_KOI8_U is not set
4704+# CONFIG_NLS_UTF8 is not set
4705+# CONFIG_DLM is not set
4706+
4707+#
4708+# Kernel hacking
4709+#
4710+# CONFIG_PRINTK_TIME is not set
4711+CONFIG_ENABLE_WARN_DEPRECATED=y
4712+CONFIG_ENABLE_MUST_CHECK=y
4713+CONFIG_FRAME_WARN=1024
4714+CONFIG_MAGIC_SYSRQ=y
4715+# CONFIG_UNUSED_SYMBOLS is not set
4716+CONFIG_DEBUG_FS=y
4717+# CONFIG_HEADERS_CHECK is not set
4718+CONFIG_DEBUG_KERNEL=y
4719+# CONFIG_DEBUG_SHIRQ is not set
4720+CONFIG_DETECT_SOFTLOCKUP=y
4721+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
4722+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
4723+CONFIG_SCHED_DEBUG=y
4724+CONFIG_SCHEDSTATS=y
4725+CONFIG_TIMER_STATS=y
4726+# CONFIG_DEBUG_OBJECTS is not set
4727+# CONFIG_SLUB_DEBUG_ON is not set
4728+# CONFIG_SLUB_STATS is not set
4729+# CONFIG_DEBUG_RT_MUTEXES is not set
4730+# CONFIG_RT_MUTEX_TESTER is not set
4731+# CONFIG_DEBUG_SPINLOCK is not set
4732+CONFIG_DEBUG_MUTEXES=y
4733+# CONFIG_DEBUG_LOCK_ALLOC is not set
4734+# CONFIG_PROVE_LOCKING is not set
4735+# CONFIG_LOCK_STAT is not set
4736+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
4737+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
4738+CONFIG_STACKTRACE=y
4739+# CONFIG_DEBUG_KOBJECT is not set
4740+CONFIG_DEBUG_BUGVERBOSE=y
4741+# CONFIG_DEBUG_INFO is not set
4742+# CONFIG_DEBUG_VM is not set
4743+# CONFIG_DEBUG_WRITECOUNT is not set
4744+# CONFIG_DEBUG_MEMORY_INIT is not set
4745+# CONFIG_DEBUG_LIST is not set
4746+# CONFIG_DEBUG_SG is not set
4747+# CONFIG_DEBUG_NOTIFIERS is not set
4748+CONFIG_FRAME_POINTER=y
4749+# CONFIG_BOOT_PRINTK_DELAY is not set
4750+# CONFIG_RCU_TORTURE_TEST is not set
4751+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
4752+# CONFIG_BACKTRACE_SELF_TEST is not set
4753+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
4754+# CONFIG_FAULT_INJECTION is not set
4755+# CONFIG_LATENCYTOP is not set
4756+CONFIG_NOP_TRACER=y
4757+CONFIG_HAVE_FUNCTION_TRACER=y
4758+CONFIG_RING_BUFFER=y
4759+CONFIG_TRACING=y
4760+
4761+#
4762+# Tracers
4763+#
4764+# CONFIG_FUNCTION_TRACER is not set
4765+# CONFIG_IRQSOFF_TRACER is not set
4766+# CONFIG_SCHED_TRACER is not set
4767+# CONFIG_CONTEXT_SWITCH_TRACER is not set
4768+# CONFIG_BOOT_TRACER is not set
4769+# CONFIG_TRACE_BRANCH_PROFILING is not set
4770+# CONFIG_STACK_TRACER is not set
4771+# CONFIG_FTRACE_STARTUP_TEST is not set
4772+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
4773+# CONFIG_SAMPLES is not set
4774+CONFIG_HAVE_ARCH_KGDB=y
4775+# CONFIG_KGDB is not set
4776+CONFIG_DEBUG_USER=y
4777+CONFIG_DEBUG_ERRORS=y
4778+# CONFIG_DEBUG_STACK_USAGE is not set
4779+# CONFIG_DEBUG_LL is not set
4780+
4781+#
4782+# Security options
4783+#
4784+# CONFIG_KEYS is not set
4785+# CONFIG_SECURITY is not set
4786+# CONFIG_SECURITYFS is not set
4787+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
4788+CONFIG_XOR_BLOCKS=m
4789+CONFIG_ASYNC_CORE=m
4790+CONFIG_ASYNC_MEMCPY=m
4791+CONFIG_ASYNC_XOR=m
4792+CONFIG_CRYPTO=y
4793+
4794+#
4795+# Crypto core or helper
4796+#
4797+# CONFIG_CRYPTO_FIPS is not set
4798+CONFIG_CRYPTO_ALGAPI=y
4799+CONFIG_CRYPTO_ALGAPI2=y
4800+CONFIG_CRYPTO_AEAD2=y
4801+CONFIG_CRYPTO_BLKCIPHER=y
4802+CONFIG_CRYPTO_BLKCIPHER2=y
4803+CONFIG_CRYPTO_HASH=y
4804+CONFIG_CRYPTO_HASH2=y
4805+CONFIG_CRYPTO_RNG2=y
4806+CONFIG_CRYPTO_MANAGER=y
4807+CONFIG_CRYPTO_MANAGER2=y
4808+CONFIG_CRYPTO_GF128MUL=m
4809+CONFIG_CRYPTO_NULL=m
4810+CONFIG_CRYPTO_CRYPTD=m
4811+# CONFIG_CRYPTO_AUTHENC is not set
4812+CONFIG_CRYPTO_TEST=m
4813+
4814+#
4815+# Authenticated Encryption with Associated Data
4816+#
4817+# CONFIG_CRYPTO_CCM is not set
4818+# CONFIG_CRYPTO_GCM is not set
4819+# CONFIG_CRYPTO_SEQIV is not set
4820+
4821+#
4822+# Block modes
4823+#
4824+CONFIG_CRYPTO_CBC=y
4825+# CONFIG_CRYPTO_CTR is not set
4826+# CONFIG_CRYPTO_CTS is not set
4827+CONFIG_CRYPTO_ECB=y
4828+CONFIG_CRYPTO_LRW=m
4829+CONFIG_CRYPTO_PCBC=m
4830+# CONFIG_CRYPTO_XTS is not set
4831+
4832+#
4833+# Hash modes
4834+#
4835+CONFIG_CRYPTO_HMAC=m
4836+CONFIG_CRYPTO_XCBC=m
4837+
4838+#
4839+# Digest
4840+#
4841+CONFIG_CRYPTO_CRC32C=y
4842+CONFIG_CRYPTO_MD4=m
4843+CONFIG_CRYPTO_MD5=y
4844+CONFIG_CRYPTO_MICHAEL_MIC=y
4845+# CONFIG_CRYPTO_RMD128 is not set
4846+# CONFIG_CRYPTO_RMD160 is not set
4847+# CONFIG_CRYPTO_RMD256 is not set
4848+# CONFIG_CRYPTO_RMD320 is not set
4849+CONFIG_CRYPTO_SHA1=m
4850+CONFIG_CRYPTO_SHA256=m
4851+CONFIG_CRYPTO_SHA512=m
4852+CONFIG_CRYPTO_TGR192=m
4853+CONFIG_CRYPTO_WP512=m
4854+
4855+#
4856+# Ciphers
4857+#
4858+CONFIG_CRYPTO_AES=y
4859+CONFIG_CRYPTO_ANUBIS=m
4860+CONFIG_CRYPTO_ARC4=y
4861+CONFIG_CRYPTO_BLOWFISH=m
4862+CONFIG_CRYPTO_CAMELLIA=m
4863+CONFIG_CRYPTO_CAST5=m
4864+CONFIG_CRYPTO_CAST6=m
4865+CONFIG_CRYPTO_DES=y
4866+CONFIG_CRYPTO_FCRYPT=m
4867+CONFIG_CRYPTO_KHAZAD=m
4868+# CONFIG_CRYPTO_SALSA20 is not set
4869+# CONFIG_CRYPTO_SEED is not set
4870+CONFIG_CRYPTO_SERPENT=m
4871+CONFIG_CRYPTO_TEA=m
4872+CONFIG_CRYPTO_TWOFISH=m
4873+CONFIG_CRYPTO_TWOFISH_COMMON=m
4874+
4875+#
4876+# Compression
4877+#
4878+CONFIG_CRYPTO_DEFLATE=m
4879+# CONFIG_CRYPTO_LZO is not set
4880+
4881+#
4882+# Random Number Generation
4883+#
4884+# CONFIG_CRYPTO_ANSI_CPRNG is not set
4885+CONFIG_CRYPTO_HW=y
4886+
4887+#
4888+# Library routines
4889+#
4890+CONFIG_BITREVERSE=y
4891+CONFIG_GENERIC_FIND_LAST_BIT=y
4892+CONFIG_CRC_CCITT=y
4893+CONFIG_CRC16=m
4894+CONFIG_CRC_T10DIF=y
4895+CONFIG_CRC_ITU_T=y
4896+CONFIG_CRC32=y
4897+CONFIG_CRC7=y
4898+CONFIG_LIBCRC32C=y
4899+CONFIG_ZLIB_INFLATE=y
4900+CONFIG_ZLIB_DEFLATE=y
4901+CONFIG_LZO_COMPRESS=y
4902+CONFIG_LZO_DECOMPRESS=y
4903+CONFIG_PLIST=y
4904+CONFIG_HAS_IOMEM=y
4905+CONFIG_HAS_IOPORT=y
4906+CONFIG_HAS_DMA=y
4907diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
4908index 0a1099e..3c664a9 100644
4909--- a/arch/arm/mach-omap2/board-3430sdp.c
4910+++ b/arch/arm/mach-omap2/board-3430sdp.c
4911@@ -37,6 +37,7 @@
4912 #include <mach/common.h>
4913 #include <mach/dma.h>
4914 #include <mach/gpmc.h>
4915+#include <mach/display.h>
4916
4917 #include <mach/control.h>
4918
4919@@ -242,6 +243,35 @@ static struct spi_board_info sdp3430_spi_board_info[] __initdata = {
4920 },
4921 };
4922
4923+
4924+#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91
4925+#define SDP2430_LCD_PANEL_ENABLE_GPIO 154
4926+#if 0
4927+#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 24
4928+#define SDP3430_LCD_PANEL_ENABLE_GPIO 28
4929+#else
4930+#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
4931+#define SDP3430_LCD_PANEL_ENABLE_GPIO 5
4932+#endif
4933+
4934+#define PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
4935+#define ENABLE_VAUX2_DEDICATED 0x09
4936+#define ENABLE_VAUX2_DEV_GRP 0x20
4937+#define ENABLE_VAUX3_DEDICATED 0x03
4938+#define ENABLE_VAUX3_DEV_GRP 0x20
4939+
4940+#define ENABLE_VPLL2_DEDICATED 0x05
4941+#define ENABLE_VPLL2_DEV_GRP 0xE0
4942+#define TWL4030_VPLL2_DEV_GRP 0x33
4943+#define TWL4030_VPLL2_DEDICATED 0x36
4944+
4945+#define t2_out(c, r, v) twl4030_i2c_write_u8(c, r, v)
4946+
4947+static unsigned backlight_gpio;
4948+static unsigned enable_gpio;
4949+static int lcd_enabled;
4950+static int dvi_enabled;
4951+
4952 static struct platform_device sdp3430_lcd_device = {
4953 .name = "sdp2430_lcd",
4954 .id = -1,
4955@@ -257,9 +287,198 @@ static struct regulator_consumer_supply sdp3430_vdvi_supply = {
4956 .dev = &sdp3430_lcd_device.dev,
4957 };
4958
4959+static void enable_vpll2(int enable)
4960+{
4961+ u8 ded_val, grp_val;
4962+
4963+ if (enable) {
4964+ ded_val = ENABLE_VPLL2_DEDICATED;
4965+ grp_val = ENABLE_VPLL2_DEV_GRP;
4966+ } else {
4967+ ded_val = 0;
4968+ grp_val = 0;
4969+ }
4970+
4971+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
4972+ ded_val, TWL4030_VPLL2_DEDICATED);
4973+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
4974+ grp_val, TWL4030_VPLL2_DEV_GRP);
4975+}
4976+
4977+static int sdp3430_dsi_power_up(void)
4978+{
4979+ if (omap_rev() > OMAP3430_REV_ES1_0)
4980+ enable_vpll2(1);
4981+ return 0;
4982+}
4983+
4984+static void sdp3430_dsi_power_down(void)
4985+{
4986+ if (omap_rev() > OMAP3430_REV_ES1_0)
4987+ enable_vpll2(0);
4988+}
4989+
4990+static void __init sdp3430_display_init(void)
4991+{
4992+ int r;
4993+
4994+ enable_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO;
4995+ backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO;
4996+
4997+ r = gpio_request(enable_gpio, "LCD reset");
4998+ if (r) {
4999+ printk(KERN_ERR "failed to get LCD reset GPIO\n");
5000+ goto err0;
5001+ }
5002+
5003+ r = gpio_request(backlight_gpio, "LCD Backlight");
5004+ if (r) {
5005+ printk(KERN_ERR "failed to get LCD backlight GPIO\n");
5006+ goto err1;
5007+ }
5008+
5009+ gpio_direction_output(enable_gpio, 0);
5010+ gpio_direction_output(backlight_gpio, 0);
5011+
5012+ return;
5013+err1:
5014+ gpio_free(enable_gpio);
5015+err0:
5016+ return;
5017+}
5018+
5019+static int sdp3430_panel_enable_lcd(struct omap_display *display)
5020+{
5021+ u8 ded_val, ded_reg;
5022+ u8 grp_val, grp_reg;
5023+
5024+ if (dvi_enabled) {
5025+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
5026+ return -EINVAL;
5027+ }
5028+
5029+ ded_reg = TWL4030_VAUX3_DEDICATED;
5030+ ded_val = ENABLE_VAUX3_DEDICATED;
5031+ grp_reg = TWL4030_VAUX3_DEV_GRP;
5032+ grp_val = ENABLE_VAUX3_DEV_GRP;
5033+
5034+ gpio_direction_output(enable_gpio, 1);
5035+ gpio_direction_output(backlight_gpio, 1);
5036+
5037+ if (0 != t2_out(PM_RECEIVER, ded_val, ded_reg))
5038+ return -EIO;
5039+ if (0 != t2_out(PM_RECEIVER, grp_val, grp_reg))
5040+ return -EIO;
5041+
5042+ sdp3430_dsi_power_up();
5043+
5044+ lcd_enabled = 1;
5045+
5046+ return 0;
5047+}
5048+
5049+static void sdp3430_panel_disable_lcd(struct omap_display *display)
5050+{
5051+ lcd_enabled = 0;
5052+
5053+ sdp3430_dsi_power_down();
5054+
5055+ gpio_direction_output(enable_gpio, 0);
5056+ gpio_direction_output(backlight_gpio, 0);
5057+}
5058+
5059+static struct omap_dss_display_config sdp3430_display_data = {
5060+ .type = OMAP_DISPLAY_TYPE_DPI,
5061+ .name = "lcd",
5062+ .panel_name = "sharp-ls037v7dw01",
5063+ .u.dpi.data_lines = 16,
5064+ .panel_enable = sdp3430_panel_enable_lcd,
5065+ .panel_disable = sdp3430_panel_disable_lcd,
5066+};
5067+
5068+static int sdp3430_panel_enable_dvi(struct omap_display *display)
5069+{
5070+ if (lcd_enabled) {
5071+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
5072+ return -EINVAL;
5073+ }
5074+
5075+ sdp3430_dsi_power_up();
5076+
5077+ dvi_enabled = 1;
5078+
5079+ return 0;
5080+}
5081+
5082+static void sdp3430_panel_disable_dvi(struct omap_display *display)
5083+{
5084+ sdp3430_dsi_power_down();
5085+
5086+ dvi_enabled = 0;
5087+}
5088+
5089+
5090+static struct omap_dss_display_config sdp3430_display_data_dvi = {
5091+ .type = OMAP_DISPLAY_TYPE_DPI,
5092+ .name = "dvi",
5093+ .panel_name = "panel-generic",
5094+ .u.dpi.data_lines = 24,
5095+ .panel_enable = sdp3430_panel_enable_dvi,
5096+ .panel_disable = sdp3430_panel_disable_dvi,
5097+};
5098+
5099+static int sdp3430_panel_enable_tv(struct omap_display *display)
5100+{
5101+#define ENABLE_VDAC_DEDICATED 0x03
5102+#define ENABLE_VDAC_DEV_GRP 0x20
5103+
5104+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
5105+ ENABLE_VDAC_DEDICATED,
5106+ TWL4030_VDAC_DEDICATED);
5107+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
5108+ ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
5109+
5110+ return 0;
5111+}
5112+
5113+static void sdp3430_panel_disable_tv(struct omap_display *display)
5114+{
5115+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
5116+ TWL4030_VDAC_DEDICATED);
5117+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
5118+ TWL4030_VDAC_DEV_GRP);
5119+}
5120+
5121+static struct omap_dss_display_config sdp3430_display_data_tv = {
5122+ .type = OMAP_DISPLAY_TYPE_VENC,
5123+ .name = "tv",
5124+ .u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
5125+ .panel_enable = sdp3430_panel_enable_tv,
5126+ .panel_disable = sdp3430_panel_disable_tv,
5127+};
5128+
5129+static struct omap_dss_board_info sdp3430_dss_data = {
5130+ .dsi_power_up = sdp3430_dsi_power_up,
5131+ .dsi_power_down = sdp3430_dsi_power_down,
5132+ .num_displays = 3,
5133+ .displays = {
5134+ &sdp3430_display_data,
5135+ &sdp3430_display_data_dvi,
5136+ &sdp3430_display_data_tv,
5137+ }
5138+};
5139+
5140+static struct platform_device sdp3430_dss_device = {
5141+ .name = "omapdss",
5142+ .id = -1,
5143+ .dev = {
5144+ .platform_data = &sdp3430_dss_data,
5145+ },
5146+};
5147+
5148 static struct platform_device *sdp3430_devices[] __initdata = {
5149 &sdp3430_smc91x_device,
5150- &sdp3430_lcd_device,
5151+ &sdp3430_dss_device,
5152 };
5153
5154 static inline void __init sdp3430_init_smc91x(void)
5155@@ -306,13 +525,8 @@ static struct omap_uart_config sdp3430_uart_config __initdata = {
5156 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
5157 };
5158
5159-static struct omap_lcd_config sdp3430_lcd_config __initdata = {
5160- .ctrl_name = "internal",
5161-};
5162-
5163 static struct omap_board_config_kernel sdp3430_config[] __initdata = {
5164 { OMAP_TAG_UART, &sdp3430_uart_config },
5165- { OMAP_TAG_LCD, &sdp3430_lcd_config },
5166 };
5167
5168 static int sdp3430_batt_table[] = {
5169@@ -681,6 +895,7 @@ static void __init omap_3430sdp_init(void)
5170 omap_serial_init();
5171 usb_musb_init();
5172 usb_ehci_init();
5173+ sdp3430_display_init();
5174 }
5175
5176 static void __init omap_3430sdp_map_io(void)
5177diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
5178index 346351e..b67e7a5 100644
5179--- a/arch/arm/mach-omap2/board-omap3beagle.c
5180+++ b/arch/arm/mach-omap2/board-omap3beagle.c
5181@@ -30,6 +30,7 @@
5182
5183 #include <linux/regulator/machine.h>
5184 #include <linux/i2c/twl4030.h>
5185+#include <linux/omapfb.h>
5186
5187 #include <mach/hardware.h>
5188 #include <asm/mach-types.h>
5189@@ -43,6 +44,7 @@
5190 #include <mach/gpmc.h>
5191 #include <mach/nand.h>
5192 #include <mach/mux.h>
5193+#include <mach/display.h>
5194
5195 #include "twl4030-generic-scripts.h"
5196 #include "mmc-twl4030.h"
5197@@ -312,10 +314,6 @@ static void __init omap3_beagle_init_irq(void)
5198 omap_gpio_init();
5199 }
5200
5201-static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
5202- .ctrl_name = "internal",
5203-};
5204-
5205 static struct gpio_led gpio_leds[] = {
5206 {
5207 .name = "beagleboard::usr0",
5208@@ -369,13 +367,94 @@ static struct platform_device keys_gpio = {
5209 },
5210 };
5211
5212+/* DSS */
5213+
5214+static int beagle_enable_dvi(struct omap_display *display)
5215+{
5216+ if (display->hw_config.panel_reset_gpio != -1)
5217+ gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
5218+
5219+ return 0;
5220+}
5221+
5222+static void beagle_disable_dvi(struct omap_display *display)
5223+{
5224+ if (display->hw_config.panel_reset_gpio != -1)
5225+ gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
5226+}
5227+
5228+static struct omap_dss_display_config beagle_display_data_dvi = {
5229+ .type = OMAP_DISPLAY_TYPE_DPI,
5230+ .name = "dvi",
5231+ .panel_name = "panel-generic",
5232+ .u.dpi.data_lines = 24,
5233+ .panel_reset_gpio = 170,
5234+ .panel_enable = beagle_enable_dvi,
5235+ .panel_disable = beagle_disable_dvi,
5236+};
5237+
5238+
5239+static int beagle_panel_enable_tv(struct omap_display *display)
5240+{
5241+#define ENABLE_VDAC_DEDICATED 0x03
5242+#define ENABLE_VDAC_DEV_GRP 0x20
5243+
5244+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
5245+ ENABLE_VDAC_DEDICATED,
5246+ TWL4030_VDAC_DEDICATED);
5247+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
5248+ ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
5249+
5250+ return 0;
5251+}
5252+
5253+static void beagle_panel_disable_tv(struct omap_display *display)
5254+{
5255+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
5256+ TWL4030_VDAC_DEDICATED);
5257+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
5258+ TWL4030_VDAC_DEV_GRP);
5259+}
5260+
5261+static struct omap_dss_display_config beagle_display_data_tv = {
5262+ .type = OMAP_DISPLAY_TYPE_VENC,
5263+ .name = "tv",
5264+ .u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
5265+ .panel_enable = beagle_panel_enable_tv,
5266+ .panel_disable = beagle_panel_disable_tv,
5267+};
5268+
5269+static struct omap_dss_board_info beagle_dss_data = {
5270+ .num_displays = 2,
5271+ .displays = {
5272+ &beagle_display_data_dvi,
5273+ &beagle_display_data_tv,
5274+ }
5275+};
5276+
5277+static struct platform_device beagle_dss_device = {
5278+ .name = "omapdss",
5279+ .id = -1,
5280+ .dev = {
5281+ .platform_data = &beagle_dss_data,
5282+ },
5283+};
5284+
5285+static void __init beagle_display_init(void)
5286+{
5287+ int r;
5288+
5289+ r = gpio_request(beagle_display_data_dvi.panel_reset_gpio, "DVI reset");
5290+ if (r < 0)
5291+ printk(KERN_ERR "Unable to get DVI reset GPIO\n");
5292+}
5293+
5294 static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
5295 { OMAP_TAG_UART, &omap3_beagle_uart_config },
5296- { OMAP_TAG_LCD, &omap3_beagle_lcd_config },
5297 };
5298
5299 static struct platform_device *omap3_beagle_devices[] __initdata = {
5300- &omap3_beagle_lcd_device,
5301+ &beagle_dss_device,
5302 &leds_gpio,
5303 &keys_gpio,
5304 };
5305@@ -428,13 +507,11 @@ static void __init omap3_beagle_init(void)
5306 omap_serial_init();
5307
5308 omap_cfg_reg(J25_34XX_GPIO170);
5309- gpio_request(170, "DVI_nPD");
5310- /* REVISIT leave DVI powered down until it's needed ... */
5311- gpio_direction_output(170, true);
5312
5313 usb_musb_init();
5314 usb_ehci_init();
5315 omap3beagle_flash_init();
5316+ beagle_display_init();
5317 }
5318
5319 static void __init omap3_beagle_map_io(void)
5320diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
5321index 024d7c4..6f5a866 100644
5322--- a/arch/arm/mach-omap2/board-omap3evm.c
5323+++ b/arch/arm/mach-omap2/board-omap3evm.c
5324@@ -36,6 +36,7 @@
5325 #include <mach/usb.h>
5326 #include <mach/common.h>
5327 #include <mach/mcspi.h>
5328+#include <mach/display.h>
5329
5330 #include "sdram-micron-mt46h32m32lf-6.h"
5331 #include "twl4030-generic-scripts.h"
5332@@ -216,13 +217,215 @@ static int __init omap3_evm_i2c_init(void)
5333 return 0;
5334 }
5335
5336-static struct platform_device omap3_evm_lcd_device = {
5337- .name = "omap3evm_lcd",
5338- .id = -1,
5339+#define LCD_PANEL_LR 2
5340+#define LCD_PANEL_UD 3
5341+#define LCD_PANEL_INI 152
5342+#define LCD_PANEL_ENABLE_GPIO 153
5343+#define LCD_PANEL_QVGA 154
5344+#define LCD_PANEL_RESB 155
5345+
5346+#define ENABLE_VDAC_DEDICATED 0x03
5347+#define ENABLE_VDAC_DEV_GRP 0x20
5348+#define ENABLE_VPLL2_DEDICATED 0x05
5349+#define ENABLE_VPLL2_DEV_GRP 0xE0
5350+
5351+#define TWL4030_GPIODATA_IN3 0x03
5352+#define TWL4030_GPIODATA_DIR3 0x06
5353+#define TWL4030_VPLL2_DEV_GRP 0x33
5354+#define TWL4030_VPLL2_DEDICATED 0x36
5355+
5356+static int lcd_enabled;
5357+static int dvi_enabled;
5358+
5359+static void __init omap3_evm_display_init(void)
5360+{
5361+ int r;
5362+ r = gpio_request(LCD_PANEL_LR, "lcd_panel_lr");
5363+ if (r) {
5364+ printk(KERN_ERR "failed to get LCD_PANEL_LR\n");
5365+ return;
5366+ }
5367+ r = gpio_request(LCD_PANEL_UD, "lcd_panel_ud");
5368+ if (r) {
5369+ printk(KERN_ERR "failed to get LCD_PANEL_UD\n");
5370+ goto err_1;
5371+ }
5372+
5373+ r = gpio_request(LCD_PANEL_INI, "lcd_panel_ini");
5374+ if (r) {
5375+ printk(KERN_ERR "failed to get LCD_PANEL_INI\n");
5376+ goto err_2;
5377+ }
5378+ r = gpio_request(LCD_PANEL_RESB, "lcd_panel_resb");
5379+ if (r) {
5380+ printk(KERN_ERR "failed to get LCD_PANEL_RESB\n");
5381+ goto err_3;
5382+ }
5383+ r = gpio_request(LCD_PANEL_QVGA, "lcd_panel_qvga");
5384+ if (r) {
5385+ printk(KERN_ERR "failed to get LCD_PANEL_QVGA\n");
5386+ goto err_4;
5387+ }
5388+
5389+ gpio_direction_output(LCD_PANEL_LR, 0);
5390+ gpio_direction_output(LCD_PANEL_UD, 0);
5391+ gpio_direction_output(LCD_PANEL_INI, 0);
5392+ gpio_direction_output(LCD_PANEL_RESB, 0);
5393+ gpio_direction_output(LCD_PANEL_QVGA, 0);
5394+
5395+#define TWL_LED_LEDEN 0x00
5396+#define TWL_PWMA_PWMAON 0x00
5397+#define TWL_PWMA_PWMAOFF 0x01
5398+
5399+ twl4030_i2c_write_u8(TWL4030_MODULE_LED, 0x11, TWL_LED_LEDEN);
5400+ twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x01, TWL_PWMA_PWMAON);
5401+ twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x02, TWL_PWMA_PWMAOFF);
5402+
5403+ gpio_direction_output(LCD_PANEL_RESB, 1);
5404+ gpio_direction_output(LCD_PANEL_INI, 1);
5405+ gpio_direction_output(LCD_PANEL_QVGA, 0);
5406+ gpio_direction_output(LCD_PANEL_LR, 1);
5407+ gpio_direction_output(LCD_PANEL_UD, 1);
5408+
5409+ return;
5410+
5411+err_4:
5412+ gpio_free(LCD_PANEL_RESB);
5413+err_3:
5414+ gpio_free(LCD_PANEL_INI);
5415+err_2:
5416+ gpio_free(LCD_PANEL_UD);
5417+err_1:
5418+ gpio_free(LCD_PANEL_LR);
5419+
5420+}
5421+
5422+static int omap3_evm_panel_enable_lcd(struct omap_display *display)
5423+{
5424+ if (dvi_enabled) {
5425+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
5426+ return -EINVAL;
5427+ }
5428+ if (omap_rev() > OMAP3430_REV_ES1_0) {
5429+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
5430+ ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
5431+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
5432+ ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
5433+ }
5434+ gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0);
5435+ lcd_enabled = 1;
5436+ return 0;
5437+}
5438+
5439+static void omap3_evm_panel_disable_lcd(struct omap_display *display)
5440+{
5441+ if (omap_rev() > OMAP3430_REV_ES1_0) {
5442+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
5443+ TWL4030_VPLL2_DEDICATED);
5444+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
5445+ TWL4030_VPLL2_DEV_GRP);
5446+ }
5447+ gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 1);
5448+ lcd_enabled = 0;
5449+}
5450+
5451+static struct omap_dss_display_config omap3_evm_display_data = {
5452+ .type = OMAP_DISPLAY_TYPE_DPI,
5453+ .name = "lcd",
5454+ .panel_name = "sharp-ls037v7dw01",
5455+ .u.dpi.data_lines = 18,
5456+ .panel_enable = omap3_evm_panel_enable_lcd,
5457+ .panel_disable = omap3_evm_panel_disable_lcd,
5458 };
5459
5460-static struct omap_lcd_config omap3_evm_lcd_config __initdata = {
5461- .ctrl_name = "internal",
5462+static int omap3_evm_panel_enable_tv(struct omap_display *display)
5463+{
5464+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
5465+ ENABLE_VDAC_DEDICATED, TWL4030_VDAC_DEDICATED);
5466+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
5467+ ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
5468+ return 0;
5469+}
5470+
5471+static void omap3_evm_panel_disable_tv(struct omap_display *display)
5472+{
5473+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
5474+ TWL4030_VDAC_DEDICATED);
5475+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
5476+ TWL4030_VDAC_DEV_GRP);
5477+}
5478+
5479+static struct omap_dss_display_config omap3_evm_display_data_tv = {
5480+ .type = OMAP_DISPLAY_TYPE_VENC,
5481+ .name = "tv",
5482+ .u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
5483+ .panel_enable = omap3_evm_panel_enable_tv,
5484+ .panel_disable = omap3_evm_panel_disable_tv,
5485+};
5486+
5487+
5488+static int omap3_evm_panel_enable_dvi(struct omap_display *display)
5489+{
5490+ if (lcd_enabled) {
5491+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
5492+ return -EINVAL;
5493+ }
5494+ if (omap_rev() > OMAP3430_REV_ES1_0) {
5495+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
5496+ ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
5497+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
5498+ ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
5499+ }
5500+
5501+ twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
5502+ TWL4030_GPIODATA_IN3);
5503+ twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
5504+ TWL4030_GPIODATA_DIR3);
5505+ dvi_enabled = 1;
5506+
5507+ return 0;
5508+}
5509+
5510+static void omap3_evm_panel_disable_dvi(struct omap_display *display)
5511+{
5512+ if (omap_rev() > OMAP3430_REV_ES1_0) {
5513+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
5514+ TWL4030_VPLL2_DEDICATED);
5515+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
5516+ TWL4030_VPLL2_DEV_GRP);
5517+ }
5518+
5519+ twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
5520+ TWL4030_GPIODATA_IN3);
5521+ twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
5522+ TWL4030_GPIODATA_DIR3);
5523+ dvi_enabled = 0;
5524+}
5525+
5526+
5527+static struct omap_dss_display_config omap3_evm_display_data_dvi = {
5528+ .type = OMAP_DISPLAY_TYPE_DPI,
5529+ .name = "dvi",
5530+ .panel_name = "panel-generic",
5531+ .u.dpi.data_lines = 24,
5532+ .panel_enable = omap3_evm_panel_enable_dvi,
5533+ .panel_disable = omap3_evm_panel_disable_dvi,
5534+};
5535+
5536+static struct omap_dss_board_info omap3_evm_dss_data = {
5537+ .num_displays = 3,
5538+ .displays = {
5539+ &omap3_evm_display_data,
5540+ &omap3_evm_display_data_dvi,
5541+ &omap3_evm_display_data_tv,
5542+ }
5543+};
5544+static struct platform_device omap3_evm_dss_device = {
5545+ .name = "omapdss",
5546+ .id = -1,
5547+ .dev = {
5548+ .platform_data = &omap3_evm_dss_data,
5549+ },
5550 };
5551
5552 static void ads7846_dev_init(void)
5553@@ -281,11 +484,10 @@ static void __init omap3_evm_init_irq(void)
5554
5555 static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
5556 { OMAP_TAG_UART, &omap3_evm_uart_config },
5557- { OMAP_TAG_LCD, &omap3_evm_lcd_config },
5558 };
5559
5560 static struct platform_device *omap3_evm_devices[] __initdata = {
5561- &omap3_evm_lcd_device,
5562+ &omap3_evm_dss_device,
5563 &omap3evm_smc911x_device,
5564 };
5565
5566@@ -305,6 +507,7 @@ static void __init omap3_evm_init(void)
5567 usb_ehci_init();
5568 omap3evm_flash_init();
5569 ads7846_dev_init();
5570+ omap3_evm_display_init();
5571 }
5572
5573 static void __init omap3_evm_map_io(void)
5574diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
5575index 071f4b0..267bb6b 100644
5576--- a/arch/arm/mach-omap2/board-overo.c
5577+++ b/arch/arm/mach-omap2/board-overo.c
5578@@ -41,6 +41,7 @@
5579 #include <mach/board-overo.h>
5580 #include <mach/board.h>
5581 #include <mach/common.h>
5582+#include <mach/display.h>
5583 #include <mach/gpio.h>
5584 #include <mach/gpmc.h>
5585 #include <mach/hardware.h>
5586@@ -176,6 +177,9 @@ static void __init overo_ads7846_init(void)
5587 static inline void __init overo_ads7846_init(void) { return; }
5588 #endif
5589
5590+static int lcd_enabled;
5591+static int dvi_enabled;
5592+
5593 static struct mtd_partition overo_nand_partitions[] = {
5594 {
5595 .name = "xloader",
5596@@ -360,22 +364,101 @@ static void __init overo_init_irq(void)
5597 omap_gpio_init();
5598 }
5599
5600-static struct platform_device overo_lcd_device = {
5601- .name = "overo_lcd",
5602- .id = -1,
5603+/* DSS */
5604+
5605+#define OVERO_GPIO_LCD_EN 144
5606+
5607+static void __init overo_display_init(void)
5608+{
5609+ int r;
5610+
5611+ r = gpio_request(OVERO_GPIO_LCD_EN, "display enable");
5612+ if (r)
5613+ printk("fail1\n");
5614+ r = gpio_direction_output(OVERO_GPIO_LCD_EN, 1);
5615+ if (r)
5616+ printk("fail2\n");
5617+ gpio_export(OVERO_GPIO_LCD_EN, 0);
5618+}
5619+
5620+static int overo_panel_enable_dvi(struct omap_display *display)
5621+{
5622+ if (lcd_enabled) {
5623+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
5624+ return -EINVAL;
5625+ }
5626+ dvi_enabled = 1;
5627+
5628+ gpio_set_value(OVERO_GPIO_LCD_EN, 1);
5629+
5630+ return 0;
5631+}
5632+
5633+static void overo_panel_disable_dvi(struct omap_display *display)
5634+{
5635+ gpio_set_value(OVERO_GPIO_LCD_EN, 0);
5636+
5637+ dvi_enabled = 0;
5638+}
5639+
5640+static struct omap_dss_display_config overo_display_data_dvi = {
5641+ .type = OMAP_DISPLAY_TYPE_DPI,
5642+ .name = "dvi",
5643+ .panel_name = "panel-generic",
5644+ .u.dpi.data_lines = 24,
5645+ .panel_enable = overo_panel_enable_dvi,
5646+ .panel_disable = overo_panel_disable_dvi,
5647 };
5648
5649-static struct omap_lcd_config overo_lcd_config __initdata = {
5650- .ctrl_name = "internal",
5651+static int overo_panel_enable_lcd(struct omap_display *display)
5652+{
5653+ if (dvi_enabled) {
5654+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
5655+ return -EINVAL;
5656+ }
5657+
5658+ gpio_set_value(OVERO_GPIO_LCD_EN, 1);
5659+ lcd_enabled = 1;
5660+ return 0;
5661+}
5662+
5663+static void overo_panel_disable_lcd(struct omap_display *display)
5664+{
5665+ gpio_set_value(OVERO_GPIO_LCD_EN, 0);
5666+ lcd_enabled = 0;
5667+}
5668+
5669+static struct omap_dss_display_config overo_display_data_lcd = {
5670+ .type = OMAP_DISPLAY_TYPE_DPI,
5671+ .name = "lcd43",
5672+ .panel_name = "samsung-lte430wq-f0c",
5673+ .u.dpi.data_lines = 24,
5674+ .panel_enable = overo_panel_enable_lcd,
5675+ .panel_disable = overo_panel_disable_lcd,
5676+ };
5677+
5678+static struct omap_dss_board_info overo_dss_data = {
5679+ .num_displays = 2,
5680+ .displays = {
5681+ &overo_display_data_dvi,
5682+ &overo_display_data_lcd,
5683+ }
5684+};
5685+
5686+static struct platform_device overo_dss_device = {
5687+ .name = "omapdss",
5688+ .id = -1,
5689+ .dev = {
5690+ .platform_data = &overo_dss_data,
5691+ },
5692 };
5693
5694 static struct omap_board_config_kernel overo_config[] __initdata = {
5695 { OMAP_TAG_UART, &overo_uart_config },
5696- { OMAP_TAG_LCD, &overo_lcd_config },
5697 };
5698
5699 static struct platform_device *overo_devices[] __initdata = {
5700- &overo_lcd_device,
5701+ &overo_dss_device,
5702 };
5703
5704 static void __init overo_init(void)
5705@@ -390,6 +473,7 @@ static void __init overo_init(void)
5706 overo_flash_init();
5707 overo_init_smsc911x();
5708 overo_ads7846_init();
5709+ overo_display_init();
5710
5711 if ((gpio_request(OVERO_GPIO_W2W_NRESET,
5712 "OVERO_GPIO_W2W_NRESET") == 0) &&
5713--
57141.5.6.5
5715
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0008-DSS2-Add-function-to-display-object-to-get-the-back.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0008-DSS2-Add-function-to-display-object-to-get-the-back.patch
new file mode 100644
index 0000000000..4c8d432dd5
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0008-DSS2-Add-function-to-display-object-to-get-the-back.patch
@@ -0,0 +1,39 @@
1From 4741076cae4f4284e1fff9a03f35475b8455af54 Mon Sep 17 00:00:00 2001
2From: Imre Deak <imre.deak@nokia.com>
3Date: Wed, 1 Apr 2009 14:36:39 +0200
4Subject: [PATCH] DSS2: Add function to display object to get the backlight level
5
6This is needed by an upcoming patch that changes the backlight
7initialization to use the backlight level set by the bootloader.
8
9Also add a field for the maximum backlight level.
10
11Signed-off-by: Imre Deak <imre.deak@nokia.com>
12---
13 arch/arm/plat-omap/include/mach/display.h | 3 +++
14 1 files changed, 3 insertions(+), 0 deletions(-)
15
16diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
17index 6288353..6b702c7 100644
18--- a/arch/arm/plat-omap/include/mach/display.h
19+++ b/arch/arm/plat-omap/include/mach/display.h
20@@ -211,6 +211,8 @@ struct omap_dss_display_config {
21 int panel_reset_gpio;
22 int ctrl_reset_gpio;
23
24+ int max_backlight_level;
25+
26 const char *name; /* for debug */
27 const char *ctrl_name;
28 const char *panel_name;
29@@ -225,6 +227,7 @@ struct omap_dss_display_config {
30 void (*ctrl_disable)(struct omap_display *display);
31 int (*set_backlight)(struct omap_display *display,
32 int level);
33+ int (*get_backlight)(struct omap_display *display);
34 };
35
36 struct device;
37--
381.5.6.5
39
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0009-DSS2-Add-acx565akm-panel.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0009-DSS2-Add-acx565akm-panel.patch
new file mode 100644
index 0000000000..3f55f04460
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0009-DSS2-Add-acx565akm-panel.patch
@@ -0,0 +1,778 @@
1From 66e16f86d3f4c5b34b37e965c65102b7192371de Mon Sep 17 00:00:00 2001
2From: Imre Deak <imre.deak@nokia.com>
3Date: Thu, 2 Apr 2009 11:47:13 +0300
4Subject: [PATCH] DSS2: Add acx565akm panel
5
6Signed-off-by: Imre Deak <imre.deak@nokia.com>
7---
8 drivers/video/omap2/displays/Kconfig | 8 +
9 drivers/video/omap2/displays/Makefile | 2 +
10 drivers/video/omap2/displays/panel-acx565akm.c | 712 ++++++++++++++++++++++++
11 drivers/video/omap2/displays/panel-acx565akm.h | 9 +
12 4 files changed, 731 insertions(+), 0 deletions(-)
13 create mode 100644 drivers/video/omap2/displays/panel-acx565akm.c
14 create mode 100644 drivers/video/omap2/displays/panel-acx565akm.h
15
16diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
17index 356ceb1..3feecee 100644
18--- a/drivers/video/omap2/displays/Kconfig
19+++ b/drivers/video/omap2/displays/Kconfig
20@@ -28,4 +28,12 @@ config CTRL_BLIZZARD
21 tristate "Blizzard Controller"
22 help
23 Blizzard Controller (hack)
24+
25+config PANEL_ACX565AKM
26+ tristate "ACX565AKM LCD Panel"
27+ depends on OMAP2_DSS_SDI
28+ select BACKLIGHT_CLASS_DEVICE
29+ help
30+ LCD Panel used in RX51
31+
32 endmenu
33diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
34index 1b74b7e..9bafcb6 100644
35--- a/drivers/video/omap2/displays/Makefile
36+++ b/drivers/video/omap2/displays/Makefile
37@@ -4,3 +4,5 @@ obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
38
39 obj-$(CONFIG_CTRL_BLIZZARD) += ctrl-blizzard.o
40 obj-$(CONFIG_PANEL_N800) += panel-n800.o
41+
42+obj-$(CONFIG_PANEL_ACX565AKM) += panel-acx565akm.o
43diff --git a/drivers/video/omap2/displays/panel-acx565akm.c b/drivers/video/omap2/displays/panel-acx565akm.c
44new file mode 100644
45index 0000000..2679d6c
46--- /dev/null
47+++ b/drivers/video/omap2/displays/panel-acx565akm.c
48@@ -0,0 +1,712 @@
49+#include <linux/kernel.h>
50+#include <linux/module.h>
51+#include <linux/clk.h>
52+#include <linux/platform_device.h>
53+#include <linux/delay.h>
54+#include <linux/spi/spi.h>
55+#include <linux/jiffies.h>
56+#include <linux/sched.h>
57+#include <linux/backlight.h>
58+#include <linux/fb.h>
59+
60+#include <mach/display.h>
61+#include <mach/dma.h>
62+
63+#include "panel-acx565akm.h"
64+
65+#define MIPID_CMD_READ_DISP_ID 0x04
66+#define MIPID_CMD_READ_RED 0x06
67+#define MIPID_CMD_READ_GREEN 0x07
68+#define MIPID_CMD_READ_BLUE 0x08
69+#define MIPID_CMD_READ_DISP_STATUS 0x09
70+#define MIPID_CMD_RDDSDR 0x0F
71+#define MIPID_CMD_SLEEP_IN 0x10
72+#define MIPID_CMD_SLEEP_OUT 0x11
73+#define MIPID_CMD_DISP_OFF 0x28
74+#define MIPID_CMD_DISP_ON 0x29
75+#define MIPID_CMD_WRITE_DISP_BRIGHTNESS 0x51
76+#define MIPID_CMD_READ_DISP_BRIGHTNESS 0x52
77+#define MIPID_CMD_WRITE_CTRL_DISP 0x53
78+
79+#define CTRL_DISP_BRIGHTNESS_CTRL_ON (1 << 5)
80+#define CTRL_DISP_AMBIENT_LIGHT_CTRL_ON (1 << 4)
81+#define CTRL_DISP_BACKLIGHT_ON (1 << 2)
82+#define CTRL_DISP_AUTO_BRIGHTNESS_ON (1 << 1)
83+
84+#define MIPID_CMD_READ_CTRL_DISP 0x54
85+#define MIPID_CMD_WRITE_CABC 0x55
86+#define MIPID_CMD_READ_CABC 0x56
87+
88+#define MIPID_VER_LPH8923 3
89+#define MIPID_VER_LS041Y3 4
90+#define MIPID_VER_L4F00311 8
91+#define MIPID_VER_ACX565AKM 9
92+
93+struct acx565akm_device {
94+ struct backlight_device *bl_dev;
95+ int enabled;
96+ int model;
97+ int revision;
98+ u8 display_id[3];
99+ int has_bc:1;
100+ int has_cabc:1;
101+ unsigned int saved_bklight_level;
102+ unsigned long hw_guard_end; /* next value of jiffies
103+ when we can issue the
104+ next sleep in/out command */
105+ unsigned long hw_guard_wait; /* max guard time in jiffies */
106+
107+ struct spi_device *spi;
108+ struct mutex mutex;
109+ struct omap_panel panel;
110+ struct omap_display *display;
111+};
112+
113+static int acx565akm_bl_update_status(struct backlight_device *dev);
114+
115+static void acx565akm_transfer(struct acx565akm_device *md, int cmd,
116+ const u8 *wbuf, int wlen, u8 *rbuf, int rlen)
117+{
118+ struct spi_message m;
119+ struct spi_transfer *x, xfer[5];
120+ int r;
121+
122+ BUG_ON(md->spi == NULL);
123+
124+ spi_message_init(&m);
125+
126+ memset(xfer, 0, sizeof(xfer));
127+ x = &xfer[0];
128+
129+ cmd &= 0xff;
130+ x->tx_buf = &cmd;
131+ x->bits_per_word = 9;
132+ x->len = 2;
133+
134+ if (rlen > 1 && wlen == 0) {
135+ /*
136+ * Between the command and the response data there is a
137+ * dummy clock cycle. Add an extra bit after the command
138+ * word to account for this.
139+ */
140+ x->bits_per_word = 10;
141+ cmd <<= 1;
142+ }
143+ spi_message_add_tail(x, &m);
144+
145+ if (wlen) {
146+ x++;
147+ x->tx_buf = wbuf;
148+ x->len = wlen;
149+ x->bits_per_word = 9;
150+ spi_message_add_tail(x, &m);
151+ }
152+
153+ if (rlen) {
154+ x++;
155+ x->rx_buf = rbuf;
156+ x->len = rlen;
157+ spi_message_add_tail(x, &m);
158+ }
159+
160+ r = spi_sync(md->spi, &m);
161+ if (r < 0)
162+ dev_dbg(&md->spi->dev, "spi_sync %d\n", r);
163+}
164+
165+static inline void acx565akm_cmd(struct acx565akm_device *md, int cmd)
166+{
167+ acx565akm_transfer(md, cmd, NULL, 0, NULL, 0);
168+}
169+
170+static inline void acx565akm_write(struct acx565akm_device *md,
171+ int reg, const u8 *buf, int len)
172+{
173+ acx565akm_transfer(md, reg, buf, len, NULL, 0);
174+}
175+
176+static inline void acx565akm_read(struct acx565akm_device *md,
177+ int reg, u8 *buf, int len)
178+{
179+ acx565akm_transfer(md, reg, NULL, 0, buf, len);
180+}
181+
182+static void hw_guard_start(struct acx565akm_device *md, int guard_msec)
183+{
184+ md->hw_guard_wait = msecs_to_jiffies(guard_msec);
185+ md->hw_guard_end = jiffies + md->hw_guard_wait;
186+}
187+
188+static void hw_guard_wait(struct acx565akm_device *md)
189+{
190+ unsigned long wait = md->hw_guard_end - jiffies;
191+
192+ if ((long)wait > 0 && wait <= md->hw_guard_wait) {
193+ set_current_state(TASK_UNINTERRUPTIBLE);
194+ schedule_timeout(wait);
195+ }
196+}
197+
198+static void set_sleep_mode(struct acx565akm_device *md, int on)
199+{
200+ int cmd, sleep_time = 50;
201+
202+ if (on)
203+ cmd = MIPID_CMD_SLEEP_IN;
204+ else
205+ cmd = MIPID_CMD_SLEEP_OUT;
206+ hw_guard_wait(md);
207+ acx565akm_cmd(md, cmd);
208+ hw_guard_start(md, 120);
209+ /*
210+ * When we enable the panel, it seems we _have_ to sleep
211+ * 120 ms before sending the init string. When disabling the
212+ * panel we'll sleep for the duration of 2 frames, so that the
213+ * controller can still provide the PCLK,HS,VS signals. */
214+ if (!on)
215+ sleep_time = 120;
216+ msleep(sleep_time);
217+}
218+
219+static void set_display_state(struct acx565akm_device *md, int enabled)
220+{
221+ int cmd = enabled ? MIPID_CMD_DISP_ON : MIPID_CMD_DISP_OFF;
222+
223+ acx565akm_cmd(md, cmd);
224+}
225+
226+static int panel_enabled(struct acx565akm_device *md)
227+{
228+ u32 disp_status;
229+ int enabled;
230+
231+ acx565akm_read(md, MIPID_CMD_READ_DISP_STATUS, (u8 *)&disp_status, 4);
232+ disp_status = __be32_to_cpu(disp_status);
233+ enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
234+ dev_dbg(&md->spi->dev,
235+ "LCD panel %senabled by bootloader (status 0x%04x)\n",
236+ enabled ? "" : "not ", disp_status);
237+ return enabled;
238+}
239+
240+static void enable_backlight_ctrl(struct acx565akm_device *md, int enable)
241+{
242+ u16 ctrl;
243+
244+ acx565akm_read(md, MIPID_CMD_READ_CTRL_DISP, (u8 *)&ctrl, 1);
245+ if (enable) {
246+ ctrl |= CTRL_DISP_BRIGHTNESS_CTRL_ON |
247+ CTRL_DISP_BACKLIGHT_ON;
248+ } else {
249+ ctrl &= ~(CTRL_DISP_BRIGHTNESS_CTRL_ON |
250+ CTRL_DISP_BACKLIGHT_ON);
251+ }
252+
253+ ctrl |= 1 << 8;
254+ acx565akm_write(md, MIPID_CMD_WRITE_CTRL_DISP, (u8 *)&ctrl, 2);
255+}
256+
257+static void set_cabc_mode(struct acx565akm_device *md, int mode)
258+{
259+ u16 cabc_ctrl;
260+
261+ cabc_ctrl = 0;
262+ acx565akm_read(md, MIPID_CMD_READ_CABC, (u8 *)&cabc_ctrl, 1);
263+ cabc_ctrl &= ~3;
264+ cabc_ctrl |= (1 << 8) | (mode & 3);
265+ acx565akm_write(md, MIPID_CMD_WRITE_CABC, (u8 *)&cabc_ctrl, 2);
266+}
267+
268+static int get_cabc_mode(struct acx565akm_device *md)
269+{
270+ u8 cabc_ctrl;
271+
272+ acx565akm_read(md, MIPID_CMD_READ_CABC, &cabc_ctrl, 1);
273+ return cabc_ctrl & 3;
274+}
275+
276+static int panel_detect(struct acx565akm_device *md)
277+{
278+ acx565akm_read(md, MIPID_CMD_READ_DISP_ID, md->display_id, 3);
279+ dev_dbg(&md->spi->dev, "MIPI display ID: %02x%02x%02x\n",
280+ md->display_id[0], md->display_id[1], md->display_id[2]);
281+
282+ switch (md->display_id[0]) {
283+ case 0x10:
284+ md->model = MIPID_VER_ACX565AKM;
285+ md->panel.name = "acx565akm";
286+ md->has_bc = 1;
287+ md->has_cabc = 1;
288+ break;
289+ case 0x29:
290+ md->model = MIPID_VER_L4F00311;
291+ md->panel.name = "l4f00311";
292+ break;
293+ case 0x45:
294+ md->model = MIPID_VER_LPH8923;
295+ md->panel.name = "lph8923";
296+ break;
297+ case 0x83:
298+ md->model = MIPID_VER_LS041Y3;
299+ md->panel.name = "ls041y3";
300+ break;
301+ default:
302+ md->panel.name = "unknown";
303+ dev_err(&md->spi->dev, "invalid display ID\n");
304+ return -ENODEV;
305+ }
306+
307+ md->revision = md->display_id[1];
308+
309+ pr_info("omapfb: %s rev %02x LCD detected\n",
310+ md->panel.name, md->revision);
311+
312+ return 0;
313+}
314+
315+static int acx565akm_panel_enable(struct omap_display *display)
316+{
317+ struct acx565akm_device *md =
318+ (struct acx565akm_device *)display->panel->priv;
319+
320+ dev_dbg(&md->spi->dev, "%s\n", __func__);
321+
322+ mutex_lock(&md->mutex);
323+
324+ if (display->hw_config.panel_enable)
325+ display->hw_config.panel_enable(display);
326+
327+ md->enabled = panel_enabled(md);
328+
329+ if (md->enabled) {
330+ dev_dbg(&md->spi->dev, "panel already enabled\n");
331+ mutex_unlock(&md->mutex);
332+ return 0;
333+ }
334+
335+ set_sleep_mode(md, 0);
336+ md->enabled = 1;
337+ set_display_state(md, 1);
338+
339+ mutex_unlock(&md->mutex);
340+
341+ return acx565akm_bl_update_status(md->bl_dev);
342+}
343+
344+static void acx565akm_panel_disable(struct omap_display *display)
345+{
346+ struct acx565akm_device *md =
347+ (struct acx565akm_device *)display->panel->priv;
348+
349+ dev_dbg(&md->spi->dev, "%s\n", __func__);
350+
351+ mutex_lock(&md->mutex);
352+
353+ if (!md->enabled) {
354+ mutex_unlock(&md->mutex);
355+ return;
356+ }
357+ set_display_state(md, 0);
358+ set_sleep_mode(md, 1);
359+ md->enabled = 0;
360+
361+ if (display->hw_config.panel_disable)
362+ display->hw_config.panel_disable(display);
363+
364+ mutex_unlock(&md->mutex);
365+}
366+
367+#if 0
368+static void acx565akm_set_mode(struct omap_display *display,
369+ int x_res, int y_res, int bpp)
370+{
371+ struct acx565akm_device *md =
372+ (struct acx565akm_device *)display->panel->priv;
373+ u16 par;
374+
375+ switch (bpp) {
376+ case 16:
377+ par = 0x150;
378+ break;
379+ case 18:
380+ par = 0x160;
381+ break;
382+ case 24:
383+ par = 0x170;
384+ break;
385+ }
386+
387+ acx565akm_write(md, 0x3a, (u8 *)&par, 2);
388+}
389+#endif
390+
391+static int acx565akm_panel_suspend(struct omap_display *display)
392+{
393+ acx565akm_panel_disable(display);
394+ return 0;
395+}
396+
397+static int acx565akm_panel_resume(struct omap_display *display)
398+{
399+ return acx565akm_panel_enable(display);
400+}
401+
402+static void acx565akm_set_brightness(struct acx565akm_device *md, int level)
403+{
404+ int bv;
405+
406+ bv = level | (1 << 8);
407+ acx565akm_write(md, MIPID_CMD_WRITE_DISP_BRIGHTNESS, (u8 *)&bv, 2);
408+
409+ if (level)
410+ enable_backlight_ctrl(md, 1);
411+ else
412+ enable_backlight_ctrl(md, 0);
413+}
414+
415+static int acx565akm_get_actual_brightness(struct acx565akm_device *md)
416+{
417+ u8 bv;
418+
419+ acx565akm_read(md, MIPID_CMD_READ_DISP_BRIGHTNESS, &bv, 1);
420+
421+ return bv;
422+}
423+
424+static int acx565akm_bl_update_status(struct backlight_device *dev)
425+{
426+ struct acx565akm_device *md = dev_get_drvdata(&dev->dev);
427+ struct omap_display *display = md->display;
428+ int r;
429+ int level;
430+
431+ dev_dbg(&md->spi->dev, "%s\n", __func__);
432+
433+ if (display->hw_config.set_backlight == NULL)
434+ return -ENODEV;
435+
436+ mutex_lock(&md->mutex);
437+
438+ if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
439+ dev->props.power == FB_BLANK_UNBLANK)
440+ level = dev->props.brightness;
441+ else
442+ level = 0;
443+
444+ r = 0;
445+ if (md->has_bc)
446+ acx565akm_set_brightness(md, level);
447+ else
448+ if (display->hw_config.set_backlight != NULL)
449+ r = display->hw_config.set_backlight(display, level);
450+ else
451+ r = -ENODEV;
452+
453+ mutex_unlock(&md->mutex);
454+
455+ return r;
456+}
457+
458+static int acx565akm_bl_get_intensity(struct backlight_device *dev)
459+{
460+ struct acx565akm_device *md = dev_get_drvdata(&dev->dev);
461+ struct omap_display *display = md->display;
462+
463+ dev_dbg(&dev->dev, "%s\n", __func__);
464+
465+ if (md->has_bc && display->hw_config.set_backlight == NULL)
466+ return -ENODEV;
467+
468+ if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
469+ dev->props.power == FB_BLANK_UNBLANK) {
470+ if (md->has_bc)
471+ return acx565akm_get_actual_brightness(md);
472+ else
473+ return dev->props.brightness;
474+ }
475+
476+ return 0;
477+}
478+
479+static struct backlight_ops acx565akm_bl_ops = {
480+ .get_brightness = acx565akm_bl_get_intensity,
481+ .update_status = acx565akm_bl_update_status,
482+};
483+
484+static const char *cabc_modes[] = {
485+ "off", /* used also always when CABC is not supported */
486+ "ui",
487+ "still-image",
488+ "moving-image",
489+};
490+
491+static ssize_t show_cabc_mode(struct device *dev,
492+ struct device_attribute *attr,
493+ char *buf)
494+{
495+ struct acx565akm_device *md = dev_get_drvdata(dev);
496+ const char *mode_str;
497+ int mode;
498+ int len;
499+
500+ if (!md->has_cabc)
501+ mode = 0;
502+ else
503+ mode = get_cabc_mode(md);
504+ mode_str = "unknown";
505+ if (mode >= 0 && mode < ARRAY_SIZE(cabc_modes))
506+ mode_str = cabc_modes[mode];
507+ len = snprintf(buf, PAGE_SIZE, "%s\n", mode_str);
508+
509+ return len < PAGE_SIZE - 1 ? len : PAGE_SIZE - 1;
510+}
511+
512+static ssize_t store_cabc_mode(struct device *dev,
513+ struct device_attribute *attr,
514+ const char *buf, size_t count)
515+{
516+ struct acx565akm_device *md = dev_get_drvdata(dev);
517+ int i;
518+
519+ for (i = 0; i < ARRAY_SIZE(cabc_modes); i++) {
520+ const char *mode_str = cabc_modes[i];
521+ int cmp_len = strlen(mode_str);
522+
523+ if (count > 0 && buf[count - 1] == '\n')
524+ count--;
525+ if (count != cmp_len)
526+ continue;
527+
528+ if (strncmp(buf, mode_str, cmp_len) == 0)
529+ break;
530+ }
531+
532+ if (i == ARRAY_SIZE(cabc_modes))
533+ return -EINVAL;
534+
535+ if (!md->has_cabc && i != 0)
536+ return -EINVAL;
537+
538+ mutex_lock(&md->mutex);
539+ set_cabc_mode(md, i);
540+ mutex_unlock(&md->mutex);
541+
542+ return count;
543+}
544+
545+static ssize_t show_cabc_available_modes(struct device *dev,
546+ struct device_attribute *attr,
547+ char *buf)
548+{
549+ struct acx565akm_device *md = dev_get_drvdata(dev);
550+ int len;
551+ int i;
552+
553+ if (!md->has_cabc)
554+ return snprintf(buf, PAGE_SIZE, "%s\n", cabc_modes[0]);
555+
556+ for (i = 0, len = 0;
557+ len < PAGE_SIZE && i < ARRAY_SIZE(cabc_modes); i++)
558+ len += snprintf(&buf[len], PAGE_SIZE - len, "%s%s%s",
559+ i ? " " : "", cabc_modes[i],
560+ i == ARRAY_SIZE(cabc_modes) - 1 ? "\n" : "");
561+
562+ return len < PAGE_SIZE ? len : PAGE_SIZE - 1;
563+}
564+
565+static DEVICE_ATTR(cabc_mode, S_IRUGO | S_IWUSR,
566+ show_cabc_mode, store_cabc_mode);
567+static DEVICE_ATTR(cabc_available_modes, S_IRUGO,
568+ show_cabc_available_modes, NULL);
569+
570+static struct attribute *bldev_attrs[] = {
571+ &dev_attr_cabc_mode.attr,
572+ &dev_attr_cabc_available_modes.attr,
573+ NULL,
574+};
575+
576+static struct attribute_group bldev_attr_group = {
577+ .attrs = bldev_attrs,
578+};
579+
580+static int acx565akm_panel_init(struct omap_display *display)
581+{
582+ struct omap_panel *panel = display->panel;
583+ struct acx565akm_panel_data *panel_data = display->hw_config.panel_data;
584+ struct acx565akm_device *md = (struct acx565akm_device *)panel->priv;
585+
586+ struct backlight_device *bldev;
587+ int brightness;
588+ int max_brightness;
589+ int r;
590+
591+ dev_dbg(&md->spi->dev, "%s\n", __func__);
592+
593+ if (!panel_data) {
594+ dev_err(&md->spi->dev, "no panel data\n");
595+ return -ENODEV;
596+ }
597+
598+ mutex_init(&md->mutex);
599+ md->display = display;
600+
601+ if (display->hw_config.panel_enable)
602+ display->hw_config.panel_enable(display);
603+
604+ md->enabled = panel_enabled(md);
605+
606+ r = panel_detect(md);
607+ if (r) {
608+ if (!md->enabled && display->hw_config.panel_disable)
609+ display->hw_config.panel_disable(display);
610+ mutex_unlock(&md->mutex);
611+ return r;
612+ }
613+
614+ if (!panel_data->bc_connected) {
615+ md->has_bc = 0;
616+ md->has_cabc = 0;
617+ }
618+
619+#if 0
620+ acx565akm_set_mode(display, panel->timings.x_res, panel->timings.y_res,
621+ panel->bpp);
622+#endif
623+
624+ if (!md->enabled)
625+ display->hw_config.panel_disable(display);
626+
627+ bldev = backlight_device_register("acx565akm", &md->spi->dev,
628+ md, &acx565akm_bl_ops);
629+ md->bl_dev = bldev;
630+
631+ if (md->has_cabc) {
632+ r = sysfs_create_group(&bldev->dev.kobj, &bldev_attr_group);
633+ if (r) {
634+ dev_err(&bldev->dev, "failed to create sysfs files\n");
635+ backlight_device_unregister(bldev);
636+ return r;
637+ }
638+ }
639+
640+ bldev->props.fb_blank = FB_BLANK_UNBLANK;
641+ bldev->props.power = FB_BLANK_UNBLANK;
642+
643+ if (md->has_bc)
644+ max_brightness = 255;
645+ else
646+ max_brightness = display->hw_config.max_backlight_level;
647+
648+ if (md->has_bc)
649+ brightness = acx565akm_get_actual_brightness(md);
650+ else {
651+ if (display->hw_config.get_backlight != NULL)
652+ brightness = display->hw_config.get_backlight(display);
653+ else
654+ brightness = 0;
655+ }
656+
657+ bldev->props.max_brightness = max_brightness;
658+ bldev->props.brightness = brightness;
659+ acx565akm_bl_update_status(bldev);
660+
661+ return 0;
662+}
663+
664+static struct omap_panel acx565akm_panel = {
665+ .name = "panel-acx565akm",
666+ .init = acx565akm_panel_init,
667+ .suspend = acx565akm_panel_suspend,
668+ .resume = acx565akm_panel_resume,
669+ .enable = acx565akm_panel_enable,
670+ .disable = acx565akm_panel_disable,
671+
672+ .timings = {
673+ .x_res = 800,
674+ .y_res = 480,
675+
676+ .pixel_clock = 24000,
677+
678+ .hsw = 4,
679+ .hfp = 16,
680+ .hbp = 12,
681+
682+ .vsw = 3,
683+ .vfp = 3,
684+ .vbp = 3,
685+ },
686+
687+ .config = OMAP_DSS_LCD_TFT,
688+
689+ .recommended_bpp = 16,
690+
691+ /*
692+ * supported modes: 12bpp(444), 16bpp(565), 18bpp(666), 24bpp(888)
693+ * resolutions.
694+ */
695+};
696+
697+static int acx565akm_spi_probe(struct spi_device *spi)
698+{
699+ struct acx565akm_device *md;
700+
701+ dev_dbg(&md->spi->dev, "%s\n", __func__);
702+
703+ md = kzalloc(sizeof(*md), GFP_KERNEL);
704+ if (md == NULL) {
705+ dev_err(&spi->dev, "out of memory\n");
706+ return -ENOMEM;
707+ }
708+
709+ spi->mode = SPI_MODE_3;
710+ md->spi = spi;
711+ dev_set_drvdata(&spi->dev, md);
712+ md->panel = acx565akm_panel;
713+ acx565akm_panel.priv = md;
714+
715+ omap_dss_register_panel(&acx565akm_panel);
716+
717+ return 0;
718+}
719+
720+static int acx565akm_spi_remove(struct spi_device *spi)
721+{
722+ struct acx565akm_device *md = dev_get_drvdata(&spi->dev);
723+
724+ dev_dbg(&md->spi->dev, "%s\n", __func__);
725+
726+ sysfs_remove_group(&md->bl_dev->dev.kobj, &bldev_attr_group);
727+ backlight_device_unregister(md->bl_dev);
728+ omap_dss_unregister_panel(&acx565akm_panel);
729+
730+ kfree(md);
731+
732+ return 0;
733+}
734+
735+static struct spi_driver acx565akm_spi_driver = {
736+ .driver = {
737+ .name = "acx565akm",
738+ .bus = &spi_bus_type,
739+ .owner = THIS_MODULE,
740+ },
741+ .probe = acx565akm_spi_probe,
742+ .remove = __devexit_p(acx565akm_spi_remove),
743+};
744+
745+static int __init acx565akm_init(void)
746+{
747+ return spi_register_driver(&acx565akm_spi_driver);
748+}
749+
750+static void __exit acx565akm_exit(void)
751+{
752+ spi_unregister_driver(&acx565akm_spi_driver);
753+}
754+
755+module_init(acx565akm_init);
756+module_exit(acx565akm_exit);
757+
758+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
759+MODULE_DESCRIPTION("acx565akm LCD Driver");
760+MODULE_LICENSE("GPL");
761diff --git a/drivers/video/omap2/displays/panel-acx565akm.h b/drivers/video/omap2/displays/panel-acx565akm.h
762new file mode 100644
763index 0000000..6d3727b
764--- /dev/null
765+++ b/drivers/video/omap2/displays/panel-acx565akm.h
766@@ -0,0 +1,9 @@
767+#ifndef __DRIVERS_VIDEO_OMAP2_DISPLAYS_PANEL_ACX565AKM_H
768+#define __DRIVERS_VIDEO_OMAP2_DISPLAYS_PANEL_ACX565AKM_H
769+
770+struct acx565akm_panel_data {
771+ unsigned bc_connected:1;
772+};
773+
774+#endif
775+
776--
7771.5.6.5
778
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0010-DSS2-Small-VRFB-context-allocation-bug-fixed.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0010-DSS2-Small-VRFB-context-allocation-bug-fixed.patch
new file mode 100644
index 0000000000..c7efc58a05
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0010-DSS2-Small-VRFB-context-allocation-bug-fixed.patch
@@ -0,0 +1,28 @@
1From 370510e24ddbf539392ebb6a1e43280965fcb19b Mon Sep 17 00:00:00 2001
2From: Vaibhav Hiremath <hvaibhav@ti.com>
3Date: Tue, 31 Mar 2009 18:47:32 +0530
4Subject: [PATCH] DSS2: Small VRFB context allocation bug fixed
5
6This is minor bug while requesting and mapping memory for
7VRFB space.
8
9Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
10---
11 drivers/video/omap2/omapfb/omapfb-main.c | 1 +
12 1 files changed, 1 insertions(+), 0 deletions(-)
13
14diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
15index 852abe5..44febef 100644
16--- a/drivers/video/omap2/omapfb/omapfb-main.c
17+++ b/drivers/video/omap2/omapfb/omapfb-main.c
18@@ -1193,6 +1193,7 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
19
20 if(!va) {
21 printk(KERN_ERR "vrfb: ioremap failed\n");
22+ omap_vrfb_release_ctx(&rg->vrfb);
23 return -ENOMEM;
24 }
25
26--
271.5.6.5
28
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0011-DSS2-Allocated-memory-for-Color-Look-up-table.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0011-DSS2-Allocated-memory-for-Color-Look-up-table.patch
new file mode 100644
index 0000000000..1a82ed2a22
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0011-DSS2-Allocated-memory-for-Color-Look-up-table.patch
@@ -0,0 +1,37 @@
1From 370d1f93a32e8fcaeac5c16574417e354af21d08 Mon Sep 17 00:00:00 2001
2From: Vaibhav Hiremath <hvaibhav@ti.com>
3Date: Tue, 31 Mar 2009 18:38:31 +0530
4Subject: [PATCH] DSS2: Allocated memory for Color Look-up-table
5
6We were not allocating memory for CMAP buffer and due to that
7G_CMAP was failing, since it does check for size of CMAP buffer.
8
9Called "fb_alloc_cmap" for llocating memory for CMAP.
10
11We are currently not supporting 1,2,4,8 bpp, so meaning less
12for us as of now. But for completeness this is required.
13
14Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
15---
16 drivers/video/omap2/omapfb/omapfb-main.c | 5 +++++
17 1 files changed, 5 insertions(+), 0 deletions(-)
18
19diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
20index 44febef..afe40a9 100644
21--- a/drivers/video/omap2/omapfb/omapfb-main.c
22+++ b/drivers/video/omap2/omapfb/omapfb-main.c
23@@ -1525,6 +1525,11 @@ int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
24 goto err;
25
26 set_fb_fix(fbi);
27+
28+ r = fb_alloc_cmap(&fbi->cmap, 256, 0);
29+ if (r)
30+ dev_err(fbdev->dev, "unable to allocate color map memory\n");
31+
32 err:
33 return r;
34 }
35--
361.5.6.5
37
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0012-DSS2-Fix-DMA-rotation.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0012-DSS2-Fix-DMA-rotation.patch
new file mode 100644
index 0000000000..22add6efd2
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0012-DSS2-Fix-DMA-rotation.patch
@@ -0,0 +1,65 @@
1From 9c93bcab724b5935d745604773ed43825efefd87 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 2 Apr 2009 13:47:11 +0300
4Subject: [PATCH] DSS2: Fix DMA rotation
5
6u16 was not a good type for offsets. First, they need to be signed,
7and second, 16 bits is not enough.
8---
9 drivers/video/omap2/dss/dispc.c | 12 ++++++------
10 1 files changed, 6 insertions(+), 6 deletions(-)
11
12diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
13index ffb5648..6cea545 100644
14--- a/drivers/video/omap2/dss/dispc.c
15+++ b/drivers/video/omap2/dss/dispc.c
16@@ -778,7 +778,7 @@ static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
17 dispc_write_reg(vsi_reg[plane-1], val);
18 }
19
20-static void _dispc_set_pix_inc(enum omap_plane plane, u16 inc)
21+static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
22 {
23 const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
24 DISPC_VID_PIXEL_INC(0),
25@@ -787,7 +787,7 @@ static void _dispc_set_pix_inc(enum omap_plane plane, u16 inc)
26 dispc_write_reg(ri_reg[plane], inc);
27 }
28
29-static void _dispc_set_row_inc(enum omap_plane plane, u16 inc)
30+static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
31 {
32 const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
33 DISPC_VID_ROW_INC(0),
34@@ -1123,7 +1123,7 @@ static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
35 }
36 }
37
38-static int pixinc(int pixels, u8 ps)
39+static s32 pixinc(int pixels, u8 ps)
40 {
41 if (pixels == 1)
42 return 1;
43@@ -1140,7 +1140,7 @@ static void calc_rotation_offset(u8 rotation, bool mirror,
44 u16 width, u16 height,
45 enum omap_color_mode color_mode, bool fieldmode,
46 unsigned *offset0, unsigned *offset1,
47- u16 *row_inc, u16 *pix_inc)
48+ s32 *row_inc, s32 *pix_inc)
49 {
50 u8 ps;
51 u16 fbw, fbh;
52@@ -1298,8 +1298,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
53 bool fieldmode = 0;
54 int cconv = 0;
55 unsigned offset0, offset1;
56- u16 row_inc;
57- u16 pix_inc;
58+ s32 row_inc;
59+ s32 pix_inc;
60
61 if (plane == OMAP_DSS_GFX) {
62 if (width != out_width || height != out_height)
63--
641.5.6.5
65
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0013-DSS2-Verify-that-overlay-paddr-0.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0013-DSS2-Verify-that-overlay-paddr-0.patch
new file mode 100644
index 0000000000..76b8c73630
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0013-DSS2-Verify-that-overlay-paddr-0.patch
@@ -0,0 +1,41 @@
1From 360a55ddd309e3a45b227a4a905ae7120dd16169 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 2 Apr 2009 14:21:12 +0300
4Subject: [PATCH] DSS2: Verify that overlay paddr != 0
5
6---
7 drivers/video/omap2/dss/dispc.c | 3 +++
8 drivers/video/omap2/dss/overlay.c | 3 +++
9 2 files changed, 6 insertions(+), 0 deletions(-)
10
11diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
12index 6cea545..2480a03 100644
13--- a/drivers/video/omap2/dss/dispc.c
14+++ b/drivers/video/omap2/dss/dispc.c
15@@ -1301,6 +1301,9 @@ static int _dispc_setup_plane(enum omap_plane plane,
16 s32 row_inc;
17 s32 pix_inc;
18
19+ if (paddr == 0)
20+ return -EINVAL;
21+
22 if (plane == OMAP_DSS_GFX) {
23 if (width != out_width || height != out_height)
24 return -EINVAL;
25diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
26index 968edbe..9209acf 100644
27--- a/drivers/video/omap2/dss/overlay.c
28+++ b/drivers/video/omap2/dss/overlay.c
29@@ -331,6 +331,9 @@ static int dss_ovl_set_overlay_info(struct omap_overlay *ovl,
30 int r;
31 struct omap_overlay_info old_info;
32
33+ if (info->paddr == 0)
34+ return -EINVAL;
35+
36 old_info = ovl->info;
37 ovl->info = *info;
38
39--
401.5.6.5
41
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0014-DSS2-Add-function-to-get-DSS-logic-clock-rate.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0014-DSS2-Add-function-to-get-DSS-logic-clock-rate.patch
new file mode 100644
index 0000000000..3b3fd77a9a
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0014-DSS2-Add-function-to-get-DSS-logic-clock-rate.patch
@@ -0,0 +1,51 @@
1From 832b763db235da8e62f7b6ab02bcb8ad6bcb7a01 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 2 Apr 2009 16:48:41 +0300
4Subject: [PATCH] DSS2: Add function to get DSS logic clock rate
5
6---
7 drivers/video/omap2/dss/dispc.c | 15 +++++++++++++++
8 drivers/video/omap2/dss/dss.h | 1 +
9 2 files changed, 16 insertions(+), 0 deletions(-)
10
11diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
12index 2480a03..1bc23f7 100644
13--- a/drivers/video/omap2/dss/dispc.c
14+++ b/drivers/video/omap2/dss/dispc.c
15@@ -1850,6 +1850,21 @@ unsigned long dispc_fclk_rate(void)
16 return r;
17 }
18
19+unsigned long dispc_lclk_rate(void)
20+{
21+ int lcd;
22+ unsigned long r;
23+ u32 l;
24+
25+ l = dispc_read_reg(DISPC_DIVISOR);
26+
27+ lcd = FLD_GET(l, 23, 16);
28+
29+ r = dispc_fclk_rate();
30+
31+ return r / lcd;
32+}
33+
34 unsigned long dispc_pclk_rate(void)
35 {
36 int lcd, pcd;
37diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
38index bac5ece..0be42b6 100644
39--- a/drivers/video/omap2/dss/dss.h
40+++ b/drivers/video/omap2/dss/dss.h
41@@ -294,6 +294,7 @@ bool dispc_trans_key_enabled(enum omap_channel ch);
42
43 void dispc_set_lcd_timings(struct omap_video_timings *timings);
44 unsigned long dispc_fclk_rate(void);
45+unsigned long dispc_lclk_rate(void);
46 unsigned long dispc_pclk_rate(void);
47 void dispc_set_pol_freq(struct omap_panel *panel);
48 void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
49--
501.5.6.5
51
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch
new file mode 100644
index 0000000000..d6b0cbbb41
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch
@@ -0,0 +1,68 @@
1From a5c235a6f0094494ae1fc1a1ba4728e0d33dfd3b Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 2 Apr 2009 16:49:27 +0300
4Subject: [PATCH] DSS2: DSI: calculate VP_CLK_RATIO properly
5
6---
7 drivers/video/omap2/dss/dsi.c | 17 +++++++++++------
8 1 files changed, 11 insertions(+), 6 deletions(-)
9
10diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
11index 4442931..aecb89d 100644
12--- a/drivers/video/omap2/dss/dsi.c
13+++ b/drivers/video/omap2/dss/dsi.c
14@@ -1104,7 +1104,10 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
15 enable_clocks(1);
16 dsi_enable_pll_clock(1);
17
18- /* configure dispc fck and pixel clock to something sane */
19+ /* XXX this should be calculated depending on the screen size,
20+ * required framerate and DSI speed.
21+ * For now 48MHz is enough for 864x480@60 with 360Mbps/lane
22+ * with two lanes */
23 r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
24 if (r)
25 goto err0;
26@@ -1119,7 +1122,7 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
27 if (r)
28 goto err0;
29
30- /* PLL does not come out of reset without this... */
31+ /* XXX PLL does not come out of reset without this... */
32 dispc_pck_free_enable(1);
33
34 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
35@@ -1128,8 +1131,8 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
36 goto err1;
37 }
38
39- /* ... but if left on, we get problems when planes do not
40- * fill the whole display. No idea about this XXX */
41+ /* XXX ... but if left on, we get problems when planes do not
42+ * fill the whole display. No idea about this */
43 dispc_pck_free_enable(0);
44
45 if (enable_hsclk && enable_hsdiv)
46@@ -2214,6 +2217,7 @@ static int dsi_proto_config(struct omap_display *display)
47 {
48 u32 r;
49 int buswidth = 0;
50+ int div;
51
52 dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
53 DSI_FIFO_SIZE_0,
54@@ -2254,8 +2258,9 @@ static int dsi_proto_config(struct omap_display *display)
55 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
56 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
57 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
58- /* XXX what should the ratio be */
59- r = FLD_MOD(r, 0, 4, 4); /* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
60+
61+ div = dispc_lclk_rate() / dispc_pclk_rate();
62+ r = FLD_MOD(r, div == 2 ? 0 : 1, 4, 4); /* VP_CLK_RATIO */
63 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
64 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
65 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
66--
671.5.6.5
68
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0016-DSS2-DSI-improve-packet-len-calculation.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0016-DSS2-DSI-improve-packet-len-calculation.patch
new file mode 100644
index 0000000000..bca449f169
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0016-DSS2-DSI-improve-packet-len-calculation.patch
@@ -0,0 +1,58 @@
1From 6b2c9d84c7accdfe1067fcdc8a00e50674aab4bb Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 2 Apr 2009 17:42:26 +0300
4Subject: [PATCH] DSS2: DSI: improve packet len calculation
5
6---
7 drivers/video/omap2/dss/dsi.c | 21 ++++++++++++++++-----
8 1 files changed, 16 insertions(+), 5 deletions(-)
9
10diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
11index aecb89d..66ac6ea 100644
12--- a/drivers/video/omap2/dss/dsi.c
13+++ b/drivers/video/omap2/dss/dsi.c
14@@ -2624,17 +2624,28 @@ static void dsi_update_screen_dispc(struct omap_display *display,
15 u16 x, u16 y, u16 w, u16 h)
16 {
17 int bytespp = 3;
18+ int len;
19 int total_len;
20- int line_packet_len;
21+ int packet_payload;
22+ int packet_len;
23 u32 l;
24
25 if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
26 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
27 x, y, w, h);
28
29- /* TODO: one packet could be longer, I think? Max is the line buffer */
30- line_packet_len = w * bytespp + 1; /* 1 byte for DCS cmd */
31- total_len = line_packet_len * h;
32+ len = w * h * bytespp;
33+
34+ /* XXX: one packet could be longer, I think? Line buffer is
35+ * 1024 x 24bits, but we have to put DCS cmd there also.
36+ * 1023 * 3 should work, but causes strange color effects. */
37+ packet_payload = min(w, (u16)1020) * bytespp;
38+
39+ packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
40+ total_len = (len / packet_payload) * packet_len;
41+
42+ if (len % packet_payload)
43+ total_len += (len % packet_payload) + 1;
44
45 display->ctrl->setup_update(display, x, y, w, h);
46
47@@ -2646,7 +2657,7 @@ static void dsi_update_screen_dispc(struct omap_display *display,
48 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
49 dsi_write_reg(DSI_VC_TE(1), l);
50
51- dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, line_packet_len, 0);
52+ dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
53
54 if (dsi.use_te)
55 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
56--
571.5.6.5
58
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0017-DSS2-Disable-video-planes-on-sync-lost-error.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0017-DSS2-Disable-video-planes-on-sync-lost-error.patch
new file mode 100644
index 0000000000..5b68b57da9
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0017-DSS2-Disable-video-planes-on-sync-lost-error.patch
@@ -0,0 +1,103 @@
1From 85848d329ca3a2d6ee6841cdc11cc5951d187931 Mon Sep 17 00:00:00 2001
2From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
3Date: Fri, 3 Apr 2009 19:09:20 +0200
4Subject: [PATCH] DSS2: Disable video planes on sync lost error
5MIME-Version: 1.0
6Content-Type: text/plain; charset=utf-8
7Content-Transfer-Encoding: 8bit
8
9When encountering the sync lost error disable the display and all video
10planes on the affected manager. Afterwards re-enable the display.
11
12Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
13---
14 drivers/video/omap2/dss/dispc.c | 50 +++++++++++++++++++++++++++++++++++++++
15 1 files changed, 50 insertions(+), 0 deletions(-)
16
17diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
18index 1bc23f7..41734f3 100644
19--- a/drivers/video/omap2/dss/dispc.c
20+++ b/drivers/video/omap2/dss/dispc.c
21@@ -2518,29 +2518,79 @@ static void dispc_error_worker(struct work_struct *work)
22 }
23
24 if (errors & DISPC_IRQ_SYNC_LOST) {
25+ struct omap_overlay_manager *manager = NULL;
26+ bool enable = false;
27+
28 DSSERR("SYNC_LOST, disabling LCD\n");
29+
30 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
31 struct omap_overlay_manager *mgr;
32 mgr = omap_dss_get_overlay_manager(i);
33
34 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
35+ manager = mgr;
36+ enable = mgr->display->state ==
37+ OMAP_DSS_DISPLAY_ACTIVE;
38 mgr->display->disable(mgr->display);
39 break;
40 }
41 }
42+
43+ if (manager) {
44+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
45+ struct omap_overlay *ovl;
46+ ovl = omap_dss_get_overlay(i);
47+
48+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
49+ continue;
50+
51+ if (ovl->id != 0 && ovl->manager == manager)
52+ dispc_enable_plane(ovl->id, 0);
53+ }
54+
55+ dispc_go(manager->id);
56+ mdelay(50);
57+ if (enable)
58+ manager->display->enable(manager->display);
59+ }
60 }
61
62 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
63+ struct omap_overlay_manager *manager = NULL;
64+ bool enable = false;
65+
66 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
67+
68 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
69 struct omap_overlay_manager *mgr;
70 mgr = omap_dss_get_overlay_manager(i);
71
72 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
73+ manager = mgr;
74+ enable = mgr->display->state ==
75+ OMAP_DSS_DISPLAY_ACTIVE;
76 mgr->display->disable(mgr->display);
77 break;
78 }
79 }
80+
81+ if (manager) {
82+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
83+ struct omap_overlay *ovl;
84+ ovl = omap_dss_get_overlay(i);
85+
86+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
87+ continue;
88+
89+ if (ovl->id != 0 && ovl->manager == manager)
90+ dispc_enable_plane(ovl->id, 0);
91+ }
92+
93+ dispc_go(manager->id);
94+ mdelay(50);
95+ if (enable)
96+ manager->display->enable(manager->display);
97+ }
98 }
99
100 if (errors & DISPC_IRQ_OCP_ERR) {
101--
1021.5.6.5
103
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0018-DSS2-check-for-ovl-paddr-only-when-enabling.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0018-DSS2-check-for-ovl-paddr-only-when-enabling.patch
new file mode 100644
index 0000000000..088135c0a8
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0018-DSS2-check-for-ovl-paddr-only-when-enabling.patch
@@ -0,0 +1,40 @@
1From 63e15ba8d5f95b13d3abf359da718537d769f112 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Tue, 7 Apr 2009 10:01:58 +0300
4Subject: [PATCH] DSS2: check for ovl paddr only when enabling
5
6It seems Xvideo uses SETUP_PLANE ioctl even when
7the fb memory has not been allocated. Sigh.
8---
9 drivers/video/omap2/dss/overlay.c | 8 +++++---
10 1 files changed, 5 insertions(+), 3 deletions(-)
11
12diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
13index 9209acf..c047206 100644
14--- a/drivers/video/omap2/dss/overlay.c
15+++ b/drivers/video/omap2/dss/overlay.c
16@@ -281,6 +281,11 @@ int dss_check_overlay(struct omap_overlay *ovl, struct omap_display *display)
17
18 info = &ovl->info;
19
20+ if (info->paddr == 0) {
21+ DSSDBG("check_overlay failed: paddr 0\n");
22+ return -EINVAL;
23+ }
24+
25 display->get_resolution(display, &dw, &dh);
26
27 DSSDBG("check_overlay %d: (%d,%d %dx%d -> %dx%d) disp (%dx%d)\n",
28@@ -331,9 +336,6 @@ static int dss_ovl_set_overlay_info(struct omap_overlay *ovl,
29 int r;
30 struct omap_overlay_info old_info;
31
32- if (info->paddr == 0)
33- return -EINVAL;
34-
35 old_info = ovl->info;
36 ovl->info = *info;
37
38--
391.5.6.5
40
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0019-DSS2-Check-fclk-limits-when-configuring-video-plane.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0019-DSS2-Check-fclk-limits-when-configuring-video-plane.patch
new file mode 100644
index 0000000000..daa95ca50d
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0019-DSS2-Check-fclk-limits-when-configuring-video-plane.patch
@@ -0,0 +1,183 @@
1From 67f3fc050ab4e2006d5b7ec6ec341896627181ab Mon Sep 17 00:00:00 2001
2From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
3Date: Mon, 6 Apr 2009 17:32:04 +0200
4Subject: [PATCH] DSS2: Check fclk limits when configuring video planes
5MIME-Version: 1.0
6Content-Type: text/plain; charset=utf-8
7Content-Transfer-Encoding: 8bit
8
9Check that the currect functional clock is fast enough to support
10the requested scaling ratios. Also check if 5-tap filtering can be
11used even though the downscaling ratio is less than 1:2 since the
12functional clock rate required for 5-tap filtering can be less than
13the requirement for 3-tap filtering, and 5-tap filtering should look
14better.
15
16Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
17---
18 drivers/video/omap2/dss/dispc.c | 104 ++++++++++++++++++++++++++++++++++++---
19 1 files changed, 97 insertions(+), 7 deletions(-)
20
21diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
22index 41734f3..61861d8 100644
23--- a/drivers/video/omap2/dss/dispc.c
24+++ b/drivers/video/omap2/dss/dispc.c
25@@ -1026,11 +1026,11 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
26 static void _dispc_set_scaling(enum omap_plane plane,
27 u16 orig_width, u16 orig_height,
28 u16 out_width, u16 out_height,
29- bool ilace)
30+ bool ilace, bool five_taps)
31 {
32 int fir_hinc;
33 int fir_vinc;
34- int hscaleup, vscaleup, five_taps;
35+ int hscaleup, vscaleup;
36 int fieldmode = 0;
37 int accu0 = 0;
38 int accu1 = 0;
39@@ -1040,7 +1040,6 @@ static void _dispc_set_scaling(enum omap_plane plane,
40
41 hscaleup = orig_width <= out_width;
42 vscaleup = orig_height <= out_height;
43- five_taps = orig_height > out_height * 2;
44
45 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
46
47@@ -1283,6 +1282,73 @@ static void calc_rotation_offset(u8 rotation, bool mirror,
48 }
49 }
50
51+static unsigned long calc_fclk_five_taps(u16 width, u16 height,
52+ u16 out_width, u16 out_height, enum omap_color_mode color_mode)
53+{
54+ u32 fclk = 0;
55+ /* FIXME venc pclk? */
56+ u64 tmp, pclk = dispc_pclk_rate();
57+
58+ if (height > out_height) {
59+ /* FIXME get real display PPL */
60+ unsigned int ppl = 800;
61+
62+ tmp = pclk * height * out_width;
63+ do_div(tmp, 2 * out_height * ppl);
64+ fclk = tmp;
65+
66+ if (height > 2 * out_height) {
67+ tmp = pclk * (height - 2 * out_height) * out_width;
68+ do_div(tmp, 2 * out_height * (ppl - out_width));
69+ fclk = max(fclk, (u32) tmp);
70+ }
71+ }
72+
73+ if (width > out_width) {
74+ tmp = pclk * width;
75+ do_div(tmp, out_width);
76+ fclk = max(fclk, (u32) tmp);
77+
78+ if (color_mode == OMAP_DSS_COLOR_RGB24U)
79+ fclk <<= 1;
80+ }
81+
82+ return fclk;
83+}
84+
85+static unsigned long calc_fclk(u16 width, u16 height,
86+ u16 out_width, u16 out_height,
87+ enum omap_color_mode color_mode, bool five_taps)
88+{
89+ unsigned int hf, vf;
90+
91+ if (five_taps)
92+ return calc_fclk_five_taps(width, height,
93+ out_width, out_height, color_mode);
94+
95+ /*
96+ * FIXME how to determine the 'A' factor
97+ * for the no downscaling case ?
98+ */
99+
100+ if (width > 3 * out_width)
101+ hf = 4;
102+ else if (width > 2 * out_width)
103+ hf = 3;
104+ else if (width > out_width)
105+ hf = 2;
106+ else
107+ hf = 1;
108+
109+ if (height > out_height)
110+ vf = 2;
111+ else
112+ vf = 1;
113+
114+ /* FIXME venc pclk? */
115+ return dispc_pclk_rate() * vf * hf;
116+}
117+
118 static int _dispc_setup_plane(enum omap_plane plane,
119 enum omap_channel channel_out,
120 u32 paddr, u16 screen_width,
121@@ -1294,7 +1360,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
122 u8 rotation, int mirror)
123 {
124 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
125- bool five_taps = height > out_height * 2;
126+ bool five_taps = 0;
127 bool fieldmode = 0;
128 int cconv = 0;
129 unsigned offset0, offset1;
130@@ -1323,8 +1389,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
131 }
132 } else {
133 /* video plane */
134- if (width > (2048 >> five_taps))
135- return -EINVAL;
136+
137+ unsigned long fclk;
138
139 if (out_width < width / maxdownscale ||
140 out_width > width * 8)
141@@ -1356,6 +1422,30 @@ static int _dispc_setup_plane(enum omap_plane plane,
142 default:
143 return -EINVAL;
144 }
145+
146+ /* Must use 5-tap filter? */
147+ five_taps = height > out_height * 2;
148+
149+ /* Try to use 5-tap filter whenever possible. */
150+ if (cpu_is_omap34xx() && !five_taps &&
151+ height > out_height && width <= 1024) {
152+ fclk = calc_fclk_five_taps(width, height,
153+ out_width, out_height, color_mode);
154+ if (fclk <= dispc_fclk_rate())
155+ five_taps = true;
156+ }
157+
158+ if (width > (2048 >> five_taps))
159+ return -EINVAL;
160+
161+ fclk = calc_fclk(width, height, out_width, out_height,
162+ color_mode, five_taps);
163+
164+ DSSDBG("required fclk rate = %lu Hz\n", fclk);
165+ DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
166+
167+ if (fclk > dispc_fclk_rate())
168+ return -EINVAL;
169 }
170
171 if (ilace && height >= out_height)
172@@ -1399,7 +1489,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
173 if (plane != OMAP_DSS_GFX) {
174 _dispc_set_scaling(plane, width, height,
175 out_width, out_height,
176- ilace);
177+ ilace, five_taps);
178 _dispc_set_vid_size(plane, out_width, out_height);
179 _dispc_set_vid_color_conv(plane, cconv);
180 }
181--
1821.5.6.5
183
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0020-DSS2-Check-scaling-limits-against-proper-values.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0020-DSS2-Check-scaling-limits-against-proper-values.patch
new file mode 100644
index 0000000000..b3248527e8
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0020-DSS2-Check-scaling-limits-against-proper-values.patch
@@ -0,0 +1,79 @@
1From 9f8f1613253656f155b3844c8255a560f86e0acd Mon Sep 17 00:00:00 2001
2From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
3Date: Mon, 6 Apr 2009 17:32:05 +0200
4Subject: [PATCH] DSS2: Check scaling limits against proper values
5MIME-Version: 1.0
6Content-Type: text/plain; charset=utf-8
7Content-Transfer-Encoding: 8bit
8
9Move the ilace and fieldmode related height adjustments to be performed
10before checking the scaling limits.
11
12Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
13---
14 drivers/video/omap2/dss/dispc.c | 31 ++++++++++++++++---------------
15 1 files changed, 16 insertions(+), 15 deletions(-)
16
17diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
18index 61861d8..ae7be3d 100644
19--- a/drivers/video/omap2/dss/dispc.c
20+++ b/drivers/video/omap2/dss/dispc.c
21@@ -1366,10 +1366,25 @@ static int _dispc_setup_plane(enum omap_plane plane,
22 unsigned offset0, offset1;
23 s32 row_inc;
24 s32 pix_inc;
25+ u16 frame_height = height;
26
27 if (paddr == 0)
28 return -EINVAL;
29
30+ if (ilace && height >= out_height)
31+ fieldmode = 1;
32+
33+ if (ilace) {
34+ if (fieldmode)
35+ height /= 2;
36+ pos_y /= 2;
37+ out_height /= 2;
38+
39+ DSSDBG("adjusting for ilace: height %d, pos_y %d, "
40+ "out_height %d\n",
41+ height, pos_y, out_height);
42+ }
43+
44 if (plane == OMAP_DSS_GFX) {
45 if (width != out_width || height != out_height)
46 return -EINVAL;
47@@ -1448,28 +1463,14 @@ static int _dispc_setup_plane(enum omap_plane plane,
48 return -EINVAL;
49 }
50
51- if (ilace && height >= out_height)
52- fieldmode = 1;
53-
54 calc_rotation_offset(rotation, mirror,
55- screen_width, width, height, color_mode,
56+ screen_width, width, frame_height, color_mode,
57 fieldmode,
58 &offset0, &offset1, &row_inc, &pix_inc);
59
60 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
61 offset0, offset1, row_inc, pix_inc);
62
63- if (ilace) {
64- if (fieldmode)
65- height /= 2;
66- pos_y /= 2;
67- out_height /= 2;
68-
69- DSSDBG("adjusting for ilace: height %d, pos_y %d, "
70- "out_height %d\n",
71- height, pos_y, out_height);
72- }
73-
74 _dispc_set_channel_out(plane, channel_out);
75 _dispc_set_color_mode(plane, color_mode);
76
77--
781.5.6.5
79
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0021-DSS2-Add-venc-register-dump.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0021-DSS2-Add-venc-register-dump.patch
new file mode 100644
index 0000000000..31ff180228
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0021-DSS2-Add-venc-register-dump.patch
@@ -0,0 +1,96 @@
1From c5e71be877e71c7df329205307e830f158c403bf Mon Sep 17 00:00:00 2001
2From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
3Date: Mon, 6 Apr 2009 17:32:06 +0200
4Subject: [PATCH] DSS2: Add venc register dump
5MIME-Version: 1.0
6Content-Type: text/plain; charset=utf-8
7Content-Transfer-Encoding: 8bit
8
9Add a new file to debugfs to dump the VENC registers. The function
10prototype was already there but the implementation was missing.
11
12Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
13---
14 drivers/video/omap2/dss/venc.c | 55 ++++++++++++++++++++++++++++++++++++++++
15 1 files changed, 55 insertions(+), 0 deletions(-)
16
17diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
18index aceed9f..b655df4 100644
19--- a/drivers/video/omap2/dss/venc.c
20+++ b/drivers/video/omap2/dss/venc.c
21@@ -30,6 +30,7 @@
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/string.h>
25+#include <linux/seq_file.h>
26
27 #include <mach/display.h>
28 #include <mach/cpu.h>
29@@ -81,6 +82,7 @@
30 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
31 #define VENC_GEN_CTRL 0xB8
32 #define VENC_OUTPUT_CONTROL 0xC4
33+#define VENC_OUTPUT_TEST 0xC8
34 #define VENC_DAC_B__DAC_C 0xC8
35
36 struct venc_config {
37@@ -598,3 +600,56 @@ void venc_init_display(struct omap_display *display)
38 display->set_timings = venc_set_timings;
39 display->check_timings = venc_check_timings;
40 }
41+
42+void venc_dump_regs(struct seq_file *s)
43+{
44+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
45+
46+ venc_enable_clocks(1);
47+
48+ DUMPREG(VENC_F_CONTROL);
49+ DUMPREG(VENC_VIDOUT_CTRL);
50+ DUMPREG(VENC_SYNC_CTRL);
51+ DUMPREG(VENC_LLEN);
52+ DUMPREG(VENC_FLENS);
53+ DUMPREG(VENC_HFLTR_CTRL);
54+ DUMPREG(VENC_CC_CARR_WSS_CARR);
55+ DUMPREG(VENC_C_PHASE);
56+ DUMPREG(VENC_GAIN_U);
57+ DUMPREG(VENC_GAIN_V);
58+ DUMPREG(VENC_GAIN_Y);
59+ DUMPREG(VENC_BLACK_LEVEL);
60+ DUMPREG(VENC_BLANK_LEVEL);
61+ DUMPREG(VENC_X_COLOR);
62+ DUMPREG(VENC_M_CONTROL);
63+ DUMPREG(VENC_BSTAMP_WSS_DATA);
64+ DUMPREG(VENC_S_CARR);
65+ DUMPREG(VENC_LINE21);
66+ DUMPREG(VENC_LN_SEL);
67+ DUMPREG(VENC_L21__WC_CTL);
68+ DUMPREG(VENC_HTRIGGER_VTRIGGER);
69+ DUMPREG(VENC_SAVID__EAVID);
70+ DUMPREG(VENC_FLEN__FAL);
71+ DUMPREG(VENC_LAL__PHASE_RESET);
72+ DUMPREG(VENC_HS_INT_START_STOP_X);
73+ DUMPREG(VENC_HS_EXT_START_STOP_X);
74+ DUMPREG(VENC_VS_INT_START_X);
75+ DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
76+ DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
77+ DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
78+ DUMPREG(VENC_VS_EXT_STOP_Y);
79+ DUMPREG(VENC_AVID_START_STOP_X);
80+ DUMPREG(VENC_AVID_START_STOP_Y);
81+ DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
82+ DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
83+ DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
84+ DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
85+ DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
86+ DUMPREG(VENC_GEN_CTRL);
87+ DUMPREG(VENC_OUTPUT_CONTROL);
88+ DUMPREG(VENC_OUTPUT_TEST);
89+
90+ venc_enable_clocks(0);
91+
92+#undef DUMPREG
93+}
94--
951.5.6.5
96
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0022-DSS2-FB-remove-unused-var-warning.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0022-DSS2-FB-remove-unused-var-warning.patch
new file mode 100644
index 0000000000..d4fb327c76
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0022-DSS2-FB-remove-unused-var-warning.patch
@@ -0,0 +1,27 @@
1From facfd479bb6efad76eec1e74048cb7a31da7287d Mon Sep 17 00:00:00 2001
2From: Imre Deak <imre.deak@nokia.com>
3Date: Mon, 6 Apr 2009 22:26:04 +0200
4Subject: [PATCH] DSS2: FB: remove unused var warning
5
6Signed-off-by: Imre Deak <imre.deak@nokia.com>
7---
8 drivers/video/omap2/omapfb/omapfb-main.c | 2 ++
9 1 files changed, 2 insertions(+), 0 deletions(-)
10
11diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
12index afe40a9..12ce0c3 100644
13--- a/drivers/video/omap2/omapfb/omapfb-main.c
14+++ b/drivers/video/omap2/omapfb/omapfb-main.c
15@@ -1246,7 +1246,9 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
16 display->get_resolution(display, &w, &h);
17
18 if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
19+#ifdef DEBUG
20 int oldw = w, oldh = h;
21+#endif
22
23 omap_vrfb_adjust_size(&w, &h, bytespp);
24
25--
261.5.6.5
27
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0023-DSS2-pass-the-default-FB-color-format-through-board.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0023-DSS2-pass-the-default-FB-color-format-through-board.patch
new file mode 100644
index 0000000000..6492905530
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0023-DSS2-pass-the-default-FB-color-format-through-board.patch
@@ -0,0 +1,214 @@
1From c02b843c2732bc7b15a3e35b5dd715d68225bbd1 Mon Sep 17 00:00:00 2001
2From: Imre Deak <imre.deak@nokia.com>
3Date: Wed, 8 Apr 2009 12:51:46 +0200
4Subject: [PATCH] DSS2: pass the default FB color format through board info
5
6Add a field to the FB memory region platform data, so that board
7init code can pass a default color format to the driver. Set this
8format as an initial setting for the given FB.
9
10This is needed for an upcoming patch that adds detection of the
11color format set by the bootloader.
12
13Signed-off-by: Imre Deak <imre.deak@nokia.com>
14---
15 drivers/video/omap2/omapfb/omapfb-main.c | 121 +++++++++++++++++++++++++++---
16 drivers/video/omap2/omapfb/omapfb.h | 2 +
17 include/linux/omapfb.h | 5 +
18 3 files changed, 117 insertions(+), 11 deletions(-)
19
20diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
21index 12ce0c3..67c67c2 100644
22--- a/drivers/video/omap2/omapfb/omapfb-main.c
23+++ b/drivers/video/omap2/omapfb/omapfb-main.c
24@@ -370,6 +370,21 @@ static enum omap_color_mode fb_mode_to_dss_mode(struct fb_var_screeninfo *var)
25 return -EINVAL;
26 }
27
28+static int dss_mode_to_fb_mode(enum omap_color_mode dssmode,
29+ struct fb_var_screeninfo *var)
30+{
31+ int i;
32+
33+ for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
34+ struct omapfb_colormode *mode = &omapfb_colormodes[i];
35+ if (dssmode == mode->dssmode) {
36+ assign_colormode_to_var(var, mode);
37+ return 0;
38+ }
39+ }
40+ return -ENOENT;
41+}
42+
43 void set_fb_fix(struct fb_info *fbi)
44 {
45 struct fb_fix_screeninfo *fix = &fbi->fix;
46@@ -1267,6 +1282,60 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
47 return omapfb_alloc_fbmem(fbi, size, paddr);
48 }
49
50+static enum omap_color_mode fb_format_to_dss_mode(enum omapfb_color_format format)
51+{
52+ enum omap_color_mode mode;
53+
54+ switch (format) {
55+ case OMAPFB_COLOR_RGB565:
56+ mode = OMAP_DSS_COLOR_RGB16;
57+ break;
58+ case OMAPFB_COLOR_YUV422:
59+ mode = OMAP_DSS_COLOR_YUV2;
60+ break;
61+ case OMAPFB_COLOR_CLUT_8BPP:
62+ mode = OMAP_DSS_COLOR_CLUT8;
63+ break;
64+ case OMAPFB_COLOR_CLUT_4BPP:
65+ mode = OMAP_DSS_COLOR_CLUT4;
66+ break;
67+ case OMAPFB_COLOR_CLUT_2BPP:
68+ mode = OMAP_DSS_COLOR_CLUT2;
69+ break;
70+ case OMAPFB_COLOR_CLUT_1BPP:
71+ mode = OMAP_DSS_COLOR_CLUT1;
72+ break;
73+ case OMAPFB_COLOR_RGB444:
74+ mode = OMAP_DSS_COLOR_RGB12U;
75+ break;
76+ case OMAPFB_COLOR_YUY422:
77+ mode = OMAP_DSS_COLOR_UYVY;
78+ break;
79+ case OMAPFB_COLOR_ARGB16:
80+ mode = OMAP_DSS_COLOR_ARGB16;
81+ break;
82+ case OMAPFB_COLOR_RGB24U:
83+ mode = OMAP_DSS_COLOR_RGB24U;
84+ break;
85+ case OMAPFB_COLOR_RGB24P:
86+ mode = OMAP_DSS_COLOR_RGB24P;
87+ break;
88+ case OMAPFB_COLOR_ARGB32:
89+ mode = OMAP_DSS_COLOR_ARGB32;
90+ break;
91+ case OMAPFB_COLOR_RGBA32:
92+ mode = OMAP_DSS_COLOR_RGBA32;
93+ break;
94+ case OMAPFB_COLOR_RGBX32:
95+ mode = OMAP_DSS_COLOR_RGBX32;
96+ break;
97+ default:
98+ mode = -EINVAL;
99+ }
100+
101+ return mode;
102+}
103+
104 static int omapfb_parse_vram_param(const char *param, int max_entries,
105 unsigned long *sizes, unsigned long *paddrs)
106 {
107@@ -1483,9 +1552,36 @@ int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
108 }
109
110 var->nonstd = 0;
111+ var->bits_per_pixel = 0;
112
113 var->rotate = ofbi->rotation;
114
115+ /*
116+ * Check if there is a default color format set in the board file,
117+ * and use this format instead the default deducted from the
118+ * display bpp.
119+ */
120+ if (fbdev->dev->platform_data) {
121+ struct omapfb_platform_data *opd;
122+ int id = ofbi->id;
123+
124+ opd = fbdev->dev->platform_data;
125+ if (opd->mem_desc.region[id].format_used) {
126+ enum omap_color_mode mode;
127+ enum omapfb_color_format format;
128+
129+ format = opd->mem_desc.region[id].format;
130+ mode = fb_format_to_dss_mode(format);
131+ if (mode < 0) {
132+ r = mode;
133+ goto err;
134+ }
135+ r = dss_mode_to_fb_mode(mode, var);
136+ if (r < 0)
137+ goto err;
138+ }
139+ }
140+
141 if (display) {
142 u16 w, h;
143 display->get_resolution(display, &w, &h);
144@@ -1502,16 +1598,18 @@ int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
145 var->xres_virtual = var->xres;
146 var->yres_virtual = var->yres;
147
148- switch (display->get_recommended_bpp(display)) {
149- case 16:
150- var->bits_per_pixel = 16;
151- break;
152- case 24:
153- var->bits_per_pixel = 32;
154- break;
155- default:
156- dev_err(fbdev->dev, "illegal display bpp\n");
157- return -EINVAL;
158+ if (!var->bits_per_pixel) {
159+ switch (display->get_recommended_bpp(display)) {
160+ case 16:
161+ var->bits_per_pixel = 16;
162+ break;
163+ case 24:
164+ var->bits_per_pixel = 32;
165+ break;
166+ default:
167+ dev_err(fbdev->dev, "illegal display bpp\n");
168+ return -EINVAL;
169+ }
170 }
171 } else {
172 /* if there's no display, let's just guess some basic values */
173@@ -1519,7 +1617,8 @@ int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
174 var->yres = 240;
175 var->xres_virtual = var->xres;
176 var->yres_virtual = var->yres;
177- var->bits_per_pixel = 16;
178+ if (!var->bits_per_pixel)
179+ var->bits_per_pixel = 16;
180 }
181
182 r = check_fb_var(fbi, var);
183diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h
184index 65e9e6e..2607def 100644
185--- a/drivers/video/omap2/omapfb/omapfb.h
186+++ b/drivers/video/omap2/omapfb/omapfb.h
187@@ -27,6 +27,8 @@
188 #define DEBUG
189 #endif
190
191+#include <mach/display.h>
192+
193 #ifdef DEBUG
194 extern unsigned int omapfb_debug;
195 #define DBG(format, ...) \
196diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
197index 96190b2..7a34f22 100644
198--- a/include/linux/omapfb.h
199+++ b/include/linux/omapfb.h
200@@ -298,6 +298,11 @@ struct omapfb_mem_region {
201 void __iomem *vaddr;
202 unsigned long size;
203 u8 type; /* OMAPFB_PLANE_MEM_* */
204+ enum omapfb_color_format format;/* OMAPFB_COLOR_* */
205+ unsigned format_used:1; /* Must be set when format is set.
206+ * Needed b/c of the badly chosen 0
207+ * base for OMAPFB_COLOR_* values
208+ */
209 unsigned alloc:1; /* allocated by the driver */
210 unsigned map:1; /* kernel mapped by the driver */
211 };
212--
2131.5.6.5
214
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0024-DSS2-Beagle-Use-gpio_set_value.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0024-DSS2-Beagle-Use-gpio_set_value.patch
new file mode 100644
index 0000000000..559e49f40a
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0024-DSS2-Beagle-Use-gpio_set_value.patch
@@ -0,0 +1,48 @@
1From 2710416c43572652cb5355a5eaf68038c95659e8 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 9 Apr 2009 12:10:46 +0300
4Subject: [PATCH] DSS2: Beagle: Use gpio_set_value
5
6---
7 arch/arm/mach-omap2/board-omap3beagle.c | 10 +++++++---
8 1 files changed, 7 insertions(+), 3 deletions(-)
9
10diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
11index b67e7a5..8c1961d 100644
12--- a/arch/arm/mach-omap2/board-omap3beagle.c
13+++ b/arch/arm/mach-omap2/board-omap3beagle.c
14@@ -372,7 +372,7 @@ static struct platform_device keys_gpio = {
15 static int beagle_enable_dvi(struct omap_display *display)
16 {
17 if (display->hw_config.panel_reset_gpio != -1)
18- gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
19+ gpio_set_value(display->hw_config.panel_reset_gpio, 1);
20
21 return 0;
22 }
23@@ -380,7 +380,7 @@ static int beagle_enable_dvi(struct omap_display *display)
24 static void beagle_disable_dvi(struct omap_display *display)
25 {
26 if (display->hw_config.panel_reset_gpio != -1)
27- gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
28+ gpio_set_value(display->hw_config.panel_reset_gpio, 0);
29 }
30
31 static struct omap_dss_display_config beagle_display_data_dvi = {
32@@ -445,8 +445,12 @@ static void __init beagle_display_init(void)
33 int r;
34
35 r = gpio_request(beagle_display_data_dvi.panel_reset_gpio, "DVI reset");
36- if (r < 0)
37+ if (r < 0) {
38 printk(KERN_ERR "Unable to get DVI reset GPIO\n");
39+ return;
40+ }
41+
42+ gpio_direction_output(beagle_display_data_dvi.panel_reset_gpio, 0);
43 }
44
45 static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
46--
471.5.6.5
48
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0025-DSS2-VRFB-Macro-for-calculating-base-address-of-th.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0025-DSS2-VRFB-Macro-for-calculating-base-address-of-th.patch
new file mode 100644
index 0000000000..e81b1331bb
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0025-DSS2-VRFB-Macro-for-calculating-base-address-of-th.patch
@@ -0,0 +1,28 @@
1From 990f3160d33361c135ee72e91f202e05a8c378fc Mon Sep 17 00:00:00 2001
2From: Hardik Shah <hardik.shah@ti.com>
3Date: Mon, 13 Apr 2009 18:50:24 +0530
4Subject: [PATCH] DSS2: VRFB: Macro for calculating base address of the VRFB context was faulty
5
6Signed-off-by: Hardik Shah <hardik.shah@ti.com>
7---
8 arch/arm/plat-omap/vrfb.c | 4 ++--
9 1 files changed, 2 insertions(+), 2 deletions(-)
10
11diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
12index 7e0f8fc..d68065f 100644
13--- a/arch/arm/plat-omap/vrfb.c
14+++ b/arch/arm/plat-omap/vrfb.c
15@@ -16,8 +16,8 @@
16
17 #define SMS_ROT_VIRT_BASE(context, rot) \
18 (((context >= 4) ? 0xD0000000 : 0x70000000) \
19- | 0x4000000 * (context) \
20- | 0x1000000 * (rot))
21+ + (0x4000000 * (context)) \
22+ + (0x1000000 * (rot)))
23
24 #define OMAP_VRFB_SIZE (2048 * 2048 * 4)
25
26--
271.5.6.5
28
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0026-DSS2-DSI-sidlemode-to-noidle-while-sending-frame.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0026-DSS2-DSI-sidlemode-to-noidle-while-sending-frame.patch
new file mode 100644
index 0000000000..6ee3908d10
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0026-DSS2-DSI-sidlemode-to-noidle-while-sending-frame.patch
@@ -0,0 +1,78 @@
1From a1e8018c0806a1a0579eda4b93b7d6764a2ff643 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Wed, 15 Apr 2009 14:06:54 +0300
4Subject: [PATCH] DSS2: DSI: sidlemode to noidle while sending frame
5
6DISPC interrupts are not wake-up capable. Smart-idle in DISPC_SIDLEMODE
7causes DSS interface to go to idle at the end of the frame, and the
8FRAMEDONE interrupt is then delayed until something wakes up the DSS
9interface.
10
11So we set SIDLEMODE to no-idle when we start sending the frame, and
12set it back to smart-idle after receiving FRAMEDONE.
13---
14 drivers/video/omap2/dss/dispc.c | 10 ++++++++++
15 drivers/video/omap2/dss/dsi.c | 4 ++++
16 drivers/video/omap2/dss/dss.h | 3 +++
17 3 files changed, 17 insertions(+), 0 deletions(-)
18
19diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
20index ae7be3d..16c68b8 100644
21--- a/drivers/video/omap2/dss/dispc.c
22+++ b/drivers/video/omap2/dss/dispc.c
23@@ -2791,6 +2791,16 @@ static void _omap_dispc_initialize_irq(void)
24 omap_dispc_set_irqs();
25 }
26
27+void dispc_enable_sidle(void)
28+{
29+ REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
30+}
31+
32+void dispc_disable_sidle(void)
33+{
34+ REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
35+}
36+
37 static void _omap_dispc_initial_config(void)
38 {
39 u32 l;
40diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
41index 66ac6ea..50af925 100644
42--- a/drivers/video/omap2/dss/dsi.c
43+++ b/drivers/video/omap2/dss/dsi.c
44@@ -2665,6 +2665,8 @@ static void dsi_update_screen_dispc(struct omap_display *display,
45 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
46 dsi_write_reg(DSI_VC_TE(1), l);
47
48+ dispc_disable_sidle();
49+
50 dispc_enable_lcd_out(1);
51
52 if (dsi.use_te)
53@@ -2678,6 +2680,8 @@ static void framedone_callback(void *data, u32 mask)
54 return;
55 }
56
57+ dispc_enable_sidle();
58+
59 dsi.framedone_scheduled = 1;
60
61 /* We get FRAMEDONE when DISPC has finished sending pixels and turns
62diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
63index 0be42b6..d0917a8 100644
64--- a/drivers/video/omap2/dss/dss.h
65+++ b/drivers/video/omap2/dss/dss.h
66@@ -244,6 +244,9 @@ void dispc_fake_vsync_irq(void);
67 void dispc_save_context(void);
68 void dispc_restore_context(void);
69
70+void dispc_enable_sidle(void);
71+void dispc_disable_sidle(void);
72+
73 void dispc_lcd_enable_signal_polarity(bool act_high);
74 void dispc_lcd_enable_signal(bool enable);
75 void dispc_pck_free_enable(bool enable);
76--
771.5.6.5
78
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0027-DSS2-VRFB-rotation-and-mirroring-implemented.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0027-DSS2-VRFB-rotation-and-mirroring-implemented.patch
new file mode 100644
index 0000000000..b56e32a11c
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0027-DSS2-VRFB-rotation-and-mirroring-implemented.patch
@@ -0,0 +1,324 @@
1From 77e848eeba461e9b55b09d39fd0d640caea13e19 Mon Sep 17 00:00:00 2001
2From: Hardik Shah <hardik.shah@ti.com>
3Date: Thu, 9 Apr 2009 12:09:44 +0530
4Subject: [PATCH] DSS2: VRFB rotation and mirroring implemented.
5
6DSS2 modified to accept the rotation_type input
7to get the dma or VRFB rotation.
8
9DSS2: VRFB: Changed to pass DSS mode to vrfb_setup instead of Bpp.
10
11VRFB size registers requires the width to be halved when the
12mode is YUV or UYVY. So modifed to pass the mode to omap_vrfb_setup
13function.
14
15Code added by Tim Yamin for few bug fixes
16
17Signed-off-by: Tim Yamin <plasm@roo.me.uk>
18Signed-off-by: Hardik Shah <hardik.shah@ti.com>
19---
20 arch/arm/plat-omap/include/mach/display.h | 6 ++
21 arch/arm/plat-omap/include/mach/vrfb.h | 3 +-
22 arch/arm/plat-omap/vrfb.c | 36 +++++++++-
23 drivers/video/omap2/dss/dispc.c | 109 +++++++++++++++++++++++++++--
24 drivers/video/omap2/dss/dss.h | 1 +
25 drivers/video/omap2/dss/manager.c | 1 +
26 6 files changed, 144 insertions(+), 12 deletions(-)
27
28diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
29index 6b702c7..b0a6272 100644
30--- a/arch/arm/plat-omap/include/mach/display.h
31+++ b/arch/arm/plat-omap/include/mach/display.h
32@@ -341,6 +341,11 @@ enum omap_dss_overlay_managers {
33
34 struct omap_overlay_manager;
35
36+enum omap_dss_rotation_type {
37+ OMAP_DSS_ROT_DMA = 0,
38+ OMAP_DSS_ROT_VRFB = 1,
39+};
40+
41 struct omap_overlay_info {
42 bool enabled;
43
44@@ -351,6 +356,7 @@ struct omap_overlay_info {
45 u16 height;
46 enum omap_color_mode color_mode;
47 u8 rotation;
48+ enum omap_dss_rotation_type rotation_type;
49 bool mirror;
50
51 u16 pos_x;
52diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
53index 2047862..12c7fab 100644
54--- a/arch/arm/plat-omap/include/mach/vrfb.h
55+++ b/arch/arm/plat-omap/include/mach/vrfb.h
56@@ -24,6 +24,7 @@
57 #ifndef __VRFB_H
58 #define __VRFB_H
59
60+#include <mach/display.h>
61 #define OMAP_VRFB_LINE_LEN 2048
62
63 struct vrfb
64@@ -42,6 +43,6 @@ extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
65 u8 bytespp);
66 extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
67 u16 width, u16 height,
68- u8 bytespp);
69+ enum omap_color_mode color_mode);
70
71 #endif /* __VRFB_H */
72diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
73index d68065f..2f08f6d 100644
74--- a/arch/arm/plat-omap/vrfb.c
75+++ b/arch/arm/plat-omap/vrfb.c
76@@ -5,7 +5,6 @@
77
78 #include <mach/io.h>
79 #include <mach/vrfb.h>
80-
81 /*#define DEBUG*/
82
83 #ifdef DEBUG
84@@ -50,19 +49,48 @@ EXPORT_SYMBOL(omap_vrfb_adjust_size);
85
86 void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
87 u16 width, u16 height,
88- u8 bytespp)
89+ enum omap_color_mode color_mode)
90 {
91 unsigned pixel_size_exp;
92 u16 vrfb_width;
93 u16 vrfb_height;
94 u8 ctx = vrfb->context;
95+ u8 bytespp;
96
97 DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
98 width, height, bytespp);
99
100- if (bytespp == 4)
101+ switch (color_mode) {
102+ case OMAP_DSS_COLOR_RGB16:
103+ case OMAP_DSS_COLOR_ARGB16:
104+ bytespp = 2;
105+ break;
106+
107+ case OMAP_DSS_COLOR_RGB24P:
108+ bytespp = 3;
109+ break;
110+
111+ case OMAP_DSS_COLOR_RGB24U:
112+ case OMAP_DSS_COLOR_ARGB32:
113+ case OMAP_DSS_COLOR_RGBA32:
114+ case OMAP_DSS_COLOR_RGBX32:
115+ case OMAP_DSS_COLOR_YUV2:
116+ case OMAP_DSS_COLOR_UYVY:
117+ bytespp = 4;
118+ break;
119+
120+ default:
121+ BUG();
122+ return;
123+ }
124+
125+ if (color_mode == OMAP_DSS_COLOR_YUV2 ||
126+ color_mode == OMAP_DSS_COLOR_UYVY)
127+ width >>= 1;
128+
129+ if (bytespp == 4) {
130 pixel_size_exp = 2;
131- else if (bytespp == 2)
132+ } else if (bytespp == 2)
133 pixel_size_exp = 1;
134 else
135 BUG();
136diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
137index 16c68b8..23a8155 100644
138--- a/drivers/video/omap2/dss/dispc.c
139+++ b/drivers/video/omap2/dss/dispc.c
140@@ -1106,7 +1106,7 @@ static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
141 case 0: vidrot = 0; break;
142 case 1: vidrot = 1; break;
143 case 2: vidrot = 2; break;
144- case 3: vidrot = 1; break;
145+ case 3: vidrot = 3; break;
146 }
147 }
148
149@@ -1134,7 +1134,92 @@ static s32 pixinc(int pixels, u8 ps)
150 BUG();
151 }
152
153-static void calc_rotation_offset(u8 rotation, bool mirror,
154+static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
155+ u16 screen_width,
156+ u16 width, u16 height,
157+ enum omap_color_mode color_mode, bool fieldmode,
158+ unsigned *offset0, unsigned *offset1,
159+ s32 *row_inc, s32 *pix_inc)
160+{
161+ u8 ps;
162+
163+ switch (color_mode) {
164+ case OMAP_DSS_COLOR_RGB16:
165+ case OMAP_DSS_COLOR_ARGB16:
166+ ps = 2;
167+ break;
168+
169+ case OMAP_DSS_COLOR_RGB24P:
170+ ps = 3;
171+ break;
172+
173+ case OMAP_DSS_COLOR_RGB24U:
174+ case OMAP_DSS_COLOR_ARGB32:
175+ case OMAP_DSS_COLOR_RGBA32:
176+ case OMAP_DSS_COLOR_RGBX32:
177+ case OMAP_DSS_COLOR_YUV2:
178+ case OMAP_DSS_COLOR_UYVY:
179+ ps = 4;
180+ break;
181+
182+ default:
183+ BUG();
184+ return;
185+ }
186+
187+ DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
188+ width, height);
189+ switch (rotation + mirror * 4) {
190+ case 0:
191+ case 2:
192+ /*
193+ * If the pixel format is YUV or UYVY divide the width
194+ * of the image by 2 for 0 and 180 degree rotation.
195+ */
196+ if (color_mode == OMAP_DSS_COLOR_YUV2 ||
197+ color_mode == OMAP_DSS_COLOR_UYVY)
198+ width = width >> 1;
199+ case 1:
200+ case 3:
201+ *offset0 = 0;
202+ if (fieldmode)
203+ *offset1 = screen_width * ps;
204+ else
205+ *offset1 = 0;
206+
207+ *row_inc = pixinc(1 + (screen_width - width) +
208+ (fieldmode ? screen_width : 0),
209+ ps);
210+ *pix_inc = pixinc(1, ps);
211+ break;
212+
213+ case 4:
214+ case 6:
215+ /* If the pixel format is YUV or UYVY divide the width
216+ * of the image by 2 for 0 degree and 180 degree
217+ */
218+ if (color_mode == OMAP_DSS_COLOR_YUV2 ||
219+ color_mode == OMAP_DSS_COLOR_UYVY)
220+ width = width >> 1;
221+ case 5:
222+ case 7:
223+ *offset0 = 0;
224+ if (fieldmode)
225+ *offset1 = screen_width * ps;
226+ else
227+ *offset1 = 0;
228+ *row_inc = pixinc(1 - (screen_width + width) -
229+ (fieldmode ? screen_width : 0),
230+ ps);
231+ *pix_inc = pixinc(1, ps);
232+ break;
233+
234+ default:
235+ BUG();
236+ }
237+}
238+
239+static void calc_dma_rotation_offset(u8 rotation, bool mirror,
240 u16 screen_width,
241 u16 width, u16 height,
242 enum omap_color_mode color_mode, bool fieldmode,
243@@ -1357,6 +1442,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
244 u16 out_width, u16 out_height,
245 enum omap_color_mode color_mode,
246 bool ilace,
247+ enum omap_dss_rotation_type rotation_type,
248 u8 rotation, int mirror)
249 {
250 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
251@@ -1463,10 +1549,16 @@ static int _dispc_setup_plane(enum omap_plane plane,
252 return -EINVAL;
253 }
254
255- calc_rotation_offset(rotation, mirror,
256- screen_width, width, frame_height, color_mode,
257- fieldmode,
258- &offset0, &offset1, &row_inc, &pix_inc);
259+ if (rotation_type == OMAP_DSS_ROT_DMA)
260+ calc_dma_rotation_offset(rotation, mirror,
261+ screen_width, width, frame_height, color_mode,
262+ fieldmode,
263+ &offset0, &offset1, &row_inc, &pix_inc);
264+ else
265+ calc_vrfb_rotation_offset(rotation, mirror,
266+ screen_width, width, frame_height, color_mode,
267+ fieldmode,
268+ &offset0, &offset1, &row_inc, &pix_inc);
269
270 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
271 offset0, offset1, row_inc, pix_inc);
272@@ -2889,6 +2981,7 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
273 u16 out_width, u16 out_height,
274 enum omap_color_mode color_mode,
275 bool ilace,
276+ enum omap_dss_rotation_type rotation_type,
277 u8 rotation, bool mirror)
278 {
279 int r = 0;
280@@ -2909,6 +3002,7 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
281 width, height,
282 out_width, out_height,
283 color_mode, ilace,
284+ rotation_type,
285 rotation, mirror);
286
287 enable_clocks(0);
288@@ -3122,7 +3216,8 @@ void dispc_setup_partial_planes(struct omap_display *display,
289 pw, ph,
290 pow, poh,
291 pi->color_mode, 0,
292- pi->rotation, // XXX rotation probably wrong
293+ pi->rotation_type,
294+ pi->rotation,
295 pi->mirror);
296
297 dispc_enable_plane(ovl->id, 1);
298diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
299index d0917a8..584dce6 100644
300--- a/drivers/video/omap2/dss/dss.h
301+++ b/drivers/video/omap2/dss/dss.h
302@@ -272,6 +272,7 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
303 u16 out_width, u16 out_height,
304 enum omap_color_mode color_mode,
305 bool ilace,
306+ enum omap_dss_rotation_type rotation_type,
307 u8 rotation, bool mirror);
308
309 void dispc_go(enum omap_channel channel);
310diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
311index b0fee80..8ca0bbb 100644
312--- a/drivers/video/omap2/dss/manager.c
313+++ b/drivers/video/omap2/dss/manager.c
314@@ -395,6 +395,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
315 outh,
316 ovl->info.color_mode,
317 ilace,
318+ ovl->info.rotation_type,
319 ovl->info.rotation,
320 ovl->info.mirror);
321
322--
3231.5.6.5
324
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0028-DSS2-OMAPFB-Added-support-for-the-YUV-VRFB-rotatio.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0028-DSS2-OMAPFB-Added-support-for-the-YUV-VRFB-rotatio.patch
new file mode 100644
index 0000000000..6400da3c24
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0028-DSS2-OMAPFB-Added-support-for-the-YUV-VRFB-rotatio.patch
@@ -0,0 +1,236 @@
1From c09f1a0642fd58a1b081594ea36dfd1bf71aec52 Mon Sep 17 00:00:00 2001
2From: Hardik Shah <hardik.shah@ti.com>
3Date: Thu, 9 Apr 2009 12:13:07 +0530
4Subject: [PATCH] DSS2: OMAPFB: Added support for the YUV VRFB rotation and mirroring.
5
6DSS2 now requires roatation_type to be specified by driver.
7Added support for that.
8DSS2 OMAPFB: Modified to pass the dss mode to omap_vrfb_setup function.
9
10VRFB size register requires the width to be halved when the
11mode is YUV or UYVY. So VRFB is modifed to pass the mode to omap_vrfb_setup
12function.
13
14Few changes done by Tim Yamin
15Signed-off-by: Tim Yamin <plasm@roo.me.uk>
16Signed-off-by: Hardik Shah <hardik.shah@ti.com>
17---
18 arch/arm/plat-omap/vrfb.c | 4 +-
19 drivers/video/omap2/omapfb/omapfb-main.c | 59 ++++++++++++++----------------
20 drivers/video/omap2/omapfb/omapfb.h | 7 +---
21 3 files changed, 30 insertions(+), 40 deletions(-)
22
23diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
24index 2f08f6d..2ae0d68 100644
25--- a/arch/arm/plat-omap/vrfb.c
26+++ b/arch/arm/plat-omap/vrfb.c
27@@ -88,9 +88,9 @@ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
28 color_mode == OMAP_DSS_COLOR_UYVY)
29 width >>= 1;
30
31- if (bytespp == 4) {
32+ if (bytespp == 4)
33 pixel_size_exp = 2;
34- } else if (bytespp == 2)
35+ else if (bytespp == 2)
36 pixel_size_exp = 1;
37 else
38 BUG();
39diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
40index 67c67c2..57f5900 100644
41--- a/drivers/video/omap2/omapfb/omapfb-main.c
42+++ b/drivers/video/omap2/omapfb/omapfb-main.c
43@@ -176,15 +176,9 @@ static unsigned omapfb_get_vrfb_offset(struct omapfb_info *ofbi, int rot)
44
45 static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi)
46 {
47- if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
48- unsigned offset;
49- int rot;
50-
51- rot = ofbi->rotation;
52-
53- offset = omapfb_get_vrfb_offset(ofbi, rot);
54-
55- return ofbi->region.vrfb.paddr[rot] + offset;
56+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
57+ return ofbi->region.vrfb.paddr[ofbi->rotation]
58+ + omapfb_get_vrfb_offset(ofbi, ofbi->rotation);
59 } else {
60 return ofbi->region.paddr;
61 }
62@@ -192,7 +186,7 @@ static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi)
63
64 u32 omapfb_get_region_paddr(struct omapfb_info *ofbi)
65 {
66- if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
67+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
68 return ofbi->region.vrfb.paddr[0];
69 else
70 return ofbi->region.paddr;
71@@ -200,7 +194,7 @@ u32 omapfb_get_region_paddr(struct omapfb_info *ofbi)
72
73 void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi)
74 {
75- if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
76+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
77 return ofbi->region.vrfb.vaddr[0];
78 else
79 return ofbi->region.vaddr;
80@@ -398,7 +392,7 @@ void set_fb_fix(struct fb_info *fbi)
81 fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi);
82
83 /* used by mmap in fbmem.c */
84- if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
85+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
86 fix->line_length =
87 (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
88 else
89@@ -434,11 +428,14 @@ void set_fb_fix(struct fb_info *fbi)
90 fix->xpanstep = 1;
91 fix->ypanstep = 1;
92
93- if (rg->size) {
94- if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
95- omap_vrfb_setup(&rg->vrfb, rg->paddr,
96- var->xres_virtual, var->yres_virtual,
97- var->bits_per_pixel >> 3);
98+ if (rg->size && ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
99+ enum omap_color_mode mode = 0;
100+ mode = fb_mode_to_dss_mode(var);
101+
102+ omap_vrfb_setup(&rg->vrfb, rg->paddr,
103+ var->xres_virtual,
104+ var->yres_virtual,
105+ mode);
106 }
107 }
108
109@@ -527,7 +524,7 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
110 if (var->yres > var->yres_virtual)
111 var->yres = var->yres_virtual;
112
113- if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
114+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
115 line_size = OMAP_VRFB_LINE_LEN * bytespp;
116 else
117 line_size = var->xres_virtual * bytespp;
118@@ -549,7 +546,7 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
119
120 if (line_size * var->yres_virtual > max_frame_size) {
121 DBG("can't fit FB into memory, reducing x\n");
122- if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
123+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
124 return -EINVAL;
125
126 var->xres_virtual = max_frame_size / var->yres_virtual /
127@@ -672,7 +669,7 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
128 struct omap_overlay_info info;
129 int xres, yres;
130 int screen_width;
131- int rot, mirror;
132+ int mirror;
133
134 DBG("setup_overlay %d, posx %d, posy %d, outw %d, outh %d\n", ofbi->id,
135 posx, posy, outw, outh);
136@@ -688,7 +685,7 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
137 offset = ((var->yoffset * var->xres_virtual +
138 var->xoffset) * var->bits_per_pixel) >> 3;
139
140- if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
141+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
142 data_start_p = omapfb_get_region_rot_paddr(ofbi);
143 data_start_v = NULL;
144 } else {
145@@ -711,13 +708,10 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
146
147 ovl->get_overlay_info(ovl, &info);
148
149- if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
150- rot = 0;
151+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
152 mirror = 0;
153- } else {
154- rot = ofbi->rotation;
155+ else
156 mirror = ofbi->mirror;
157- }
158
159 info.paddr = data_start_p;
160 info.vaddr = data_start_v;
161@@ -725,7 +719,8 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
162 info.width = xres;
163 info.height = yres;
164 info.color_mode = mode;
165- info.rotation = rot;
166+ info.rotation_type = ofbi->rotation_type;
167+ info.rotation = ofbi->rotation;
168 info.mirror = mirror;
169
170 info.pos_x = posx;
171@@ -1121,7 +1116,7 @@ static void omapfb_free_fbmem(struct fb_info *fbi)
172 if (rg->vaddr)
173 iounmap(rg->vaddr);
174
175- if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
176+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
177 /* unmap the 0 angle rotation */
178 if (rg->vrfb.vaddr[0]) {
179 iounmap(rg->vrfb.vaddr[0]);
180@@ -1181,7 +1176,7 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
181 return -ENOMEM;
182 }
183
184- if (ofbi->rotation_type != OMAPFB_ROT_VRFB) {
185+ if (ofbi->rotation_type != OMAP_DSS_ROT_VRFB) {
186 vaddr = ioremap_wc(paddr, size);
187
188 if (!vaddr) {
189@@ -1260,7 +1255,7 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
190
191 display->get_resolution(display, &w, &h);
192
193- if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
194+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
195 #ifdef DEBUG
196 int oldw = w, oldh = h;
197 #endif
198@@ -1701,8 +1696,8 @@ static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
199 ofbi->id = i;
200
201 /* assign these early, so that fb alloc can use them */
202- ofbi->rotation_type = def_vrfb ? OMAPFB_ROT_VRFB :
203- OMAPFB_ROT_DMA;
204+ ofbi->rotation_type = def_vrfb ? OMAP_DSS_ROT_VRFB :
205+ OMAP_DSS_ROT_DMA;
206 ofbi->rotation = def_rotate;
207 ofbi->mirror = def_mirror;
208
209diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h
210index 2607def..43f6922 100644
211--- a/drivers/video/omap2/omapfb/omapfb.h
212+++ b/drivers/video/omap2/omapfb/omapfb.h
213@@ -53,11 +53,6 @@ struct omapfb2_mem_region {
214 bool map; /* kernel mapped by the driver */
215 };
216
217-enum omapfb_rotation_type {
218- OMAPFB_ROT_DMA = 0,
219- OMAPFB_ROT_VRFB = 1,
220-};
221-
222 /* appended to fb_info */
223 struct omapfb_info {
224 int id;
225@@ -66,7 +61,7 @@ struct omapfb_info {
226 int num_overlays;
227 struct omap_overlay *overlays[OMAPFB_MAX_OVL_PER_FB];
228 struct omapfb2_device *fbdev;
229- enum omapfb_rotation_type rotation_type;
230+ enum omap_dss_rotation_type rotation_type;
231 u8 rotation;
232 bool mirror;
233 };
234--
2351.5.6.5
236
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0029-DSS2-OMAPFB-Set-line_length-correctly-for-YUV-with.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0029-DSS2-OMAPFB-Set-line_length-correctly-for-YUV-with.patch
new file mode 100644
index 0000000000..072978670b
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0029-DSS2-OMAPFB-Set-line_length-correctly-for-YUV-with.patch
@@ -0,0 +1,61 @@
1From a8a37babe4856170f4cba86c425a8f21975d9e9e Mon Sep 17 00:00:00 2001
2From: Tim Yamin <plasm@roo.me.uk>
3Date: Mon, 13 Apr 2009 13:57:42 -0700
4Subject: [PATCH] DSS2: OMAPFB: Set line_length correctly for YUV with VRFB.
5
6Signed-off-by: Tim Yamin <plasm@roo.me.uk>
7---
8 drivers/video/omap2/omapfb/omapfb-main.c | 30 +++++++++++++++++++++++++-----
9 1 files changed, 25 insertions(+), 5 deletions(-)
10
11diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
12index 57f5900..cd63740 100644
13--- a/drivers/video/omap2/omapfb/omapfb-main.c
14+++ b/drivers/video/omap2/omapfb/omapfb-main.c
15@@ -392,10 +392,19 @@ void set_fb_fix(struct fb_info *fbi)
16 fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi);
17
18 /* used by mmap in fbmem.c */
19- if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
20- fix->line_length =
21- (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
22- else
23+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
24+ switch (var->nonstd) {
25+ case OMAPFB_COLOR_YUV422:
26+ case OMAPFB_COLOR_YUY422:
27+ fix->line_length =
28+ (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 2;
29+ break;
30+ default:
31+ fix->line_length =
32+ (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
33+ break;
34+ }
35+ } else
36 fix->line_length =
37 (var->xres_virtual * var->bits_per_pixel) >> 3;
38 fix->smem_start = omapfb_get_region_paddr(ofbi);
39@@ -704,7 +713,18 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
40 goto err;
41 }
42
43- screen_width = fix->line_length / (var->bits_per_pixel >> 3);
44+ switch (var->nonstd) {
45+ case OMAPFB_COLOR_YUV422:
46+ case OMAPFB_COLOR_YUY422:
47+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
48+ screen_width = fix->line_length
49+ / (var->bits_per_pixel >> 2);
50+ break;
51+ }
52+ default:
53+ screen_width = fix->line_length / (var->bits_per_pixel >> 3);
54+ break;
55+ }
56
57 ovl->get_overlay_info(ovl, &info);
58
59--
601.5.6.5
61
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0030-DSS2-dispc_get_trans_key-was-returning-wrong-key-ty.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0030-DSS2-dispc_get_trans_key-was-returning-wrong-key-ty.patch
new file mode 100644
index 0000000000..7e2bb48938
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0030-DSS2-dispc_get_trans_key-was-returning-wrong-key-ty.patch
@@ -0,0 +1,29 @@
1From bda19b9359d9dc60f8b0beb5685e173e236ee30f Mon Sep 17 00:00:00 2001
2From: Hardik Shah <hardik.shah@ti.com>
3Date: Wed, 15 Apr 2009 17:05:18 +0530
4Subject: [PATCH] DSS2: dispc_get_trans_key was returning wrong key type
5
6Signed-off-by: Hardik Shah <hardik.shah@ti.com>
7---
8 drivers/video/omap2/dss/dispc.c | 4 ++--
9 1 files changed, 2 insertions(+), 2 deletions(-)
10
11diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
12index 23a8155..076d3d4 100644
13--- a/drivers/video/omap2/dss/dispc.c
14+++ b/drivers/video/omap2/dss/dispc.c
15@@ -1826,9 +1826,9 @@ void dispc_get_trans_key(enum omap_channel ch,
16 enable_clocks(1);
17 if (type) {
18 if (ch == OMAP_DSS_CHANNEL_LCD)
19- *type = REG_GET(DISPC_CONFIG, 11, 11) >> 11;
20+ *type = REG_GET(DISPC_CONFIG, 11, 11);
21 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
22- *type = REG_GET(DISPC_CONFIG, 13, 13) >> 13;
23+ *type = REG_GET(DISPC_CONFIG, 13, 13);
24 else
25 BUG();
26 }
27--
281.5.6.5
29
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0031-DSS2-do-bootmem-reserve-for-exclusive-access.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0031-DSS2-do-bootmem-reserve-for-exclusive-access.patch
new file mode 100644
index 0000000000..ae777ed04e
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0031-DSS2-do-bootmem-reserve-for-exclusive-access.patch
@@ -0,0 +1,33 @@
1From 30c40f5e6b1794430f678bf23d3319354321cab7 Mon Sep 17 00:00:00 2001
2From: Imre Deak <imre.deak@nokia.com>
3Date: Tue, 14 Apr 2009 14:50:11 +0200
4Subject: [PATCH] DSS2: do bootmem reserve for exclusive access
5
6BOOTMEM_DEFAULT would allow multiple reservations for the same location,
7we need to reserve the region for our exclusive use. Also check if the
8reserve succeeded.
9
10Signed-off-by: Imre Deak <imre.deak@nokia.com>
11---
12 arch/arm/plat-omap/vram.c | 5 ++++-
13 1 files changed, 4 insertions(+), 1 deletions(-)
14
15diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
16index f24a110..520f260 100644
17--- a/arch/arm/plat-omap/vram.c
18+++ b/arch/arm/plat-omap/vram.c
19@@ -524,7 +524,10 @@ void __init omapfb_reserve_sdram(void)
20 return;
21 }
22
23- reserve_bootmem(paddr, size, BOOTMEM_DEFAULT);
24+ if (reserve_bootmem(paddr, size, BOOTMEM_EXCLUSIVE) < 0) {
25+ pr_err("FB: failed to reserve VRAM\n");
26+ return;
27+ }
28 } else {
29 if (size > sdram_size) {
30 printk(KERN_ERR "Illegal SDRAM size for VRAM\n");
31--
321.5.6.5
33
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0032-DSS2-Fix-DISPC_VID_FIR-value-for-omap34xx.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0032-DSS2-Fix-DISPC_VID_FIR-value-for-omap34xx.patch
new file mode 100644
index 0000000000..4959a760b1
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0032-DSS2-Fix-DISPC_VID_FIR-value-for-omap34xx.patch
@@ -0,0 +1,35 @@
1From ed7a9223f6785be03951c55f3b0695b0d5635c80 Mon Sep 17 00:00:00 2001
2From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
3Date: Thu, 9 Apr 2009 15:04:44 +0200
4Subject: [PATCH] DSS2: Fix DISPC_VID_FIR value for omap34xx
5MIME-Version: 1.0
6Content-Type: text/plain; charset=utf-8
7Content-Transfer-Encoding: 8bit
8
9The msbs of the DISPC_VID_FIR fields were incorrectly masked out on
10omap34xx and thus 4:1 downscale did not work correctly.
11
12Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
13---
14 drivers/video/omap2/dss/dispc.c | 5 ++++-
15 1 files changed, 4 insertions(+), 1 deletions(-)
16
17diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
18index 076d3d4..b8a3329 100644
19--- a/drivers/video/omap2/dss/dispc.c
20+++ b/drivers/video/omap2/dss/dispc.c
21@@ -994,7 +994,10 @@ static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
22
23 BUG_ON(plane == OMAP_DSS_GFX);
24
25- val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
26+ if (cpu_is_omap24xx())
27+ val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
28+ else
29+ val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
30 dispc_write_reg(fir_reg[plane-1], val);
31 }
32
33--
341.5.6.5
35
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0033-DSS2-Prefer-3-tap-filter.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0033-DSS2-Prefer-3-tap-filter.patch
new file mode 100644
index 0000000000..f643ca64f3
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0033-DSS2-Prefer-3-tap-filter.patch
@@ -0,0 +1,82 @@
1From 5390230ed12585a79683733209db34e9130b8e3b Mon Sep 17 00:00:00 2001
2From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
3Date: Thu, 9 Apr 2009 15:04:43 +0200
4Subject: [PATCH] DSS2: Prefer 3-tap filter
5MIME-Version: 1.0
6Content-Type: text/plain; charset=utf-8
7Content-Transfer-Encoding: 8bit
8
9The 5-tap filter seems rather unstable. With some scaling settings it
10works and with some it doesn't even though the functional clock remains
11within the TRM limits. So prefer the 3-tap filter unless the functional
12clock required for it is too high.
13
14Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
15---
16 drivers/video/omap2/dss/dispc.c | 27 ++++++++++++---------------
17 1 files changed, 12 insertions(+), 15 deletions(-)
18
19diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
20index b8a3329..b631dd8 100644
21--- a/drivers/video/omap2/dss/dispc.c
22+++ b/drivers/video/omap2/dss/dispc.c
23@@ -1405,15 +1405,10 @@ static unsigned long calc_fclk_five_taps(u16 width, u16 height,
24 }
25
26 static unsigned long calc_fclk(u16 width, u16 height,
27- u16 out_width, u16 out_height,
28- enum omap_color_mode color_mode, bool five_taps)
29+ u16 out_width, u16 out_height)
30 {
31 unsigned int hf, vf;
32
33- if (five_taps)
34- return calc_fclk_five_taps(width, height,
35- out_width, out_height, color_mode);
36-
37 /*
38 * FIXME how to determine the 'A' factor
39 * for the no downscaling case ?
40@@ -1494,7 +1489,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
41 } else {
42 /* video plane */
43
44- unsigned long fclk;
45+ unsigned long fclk = 0;
46
47 if (out_width < width / maxdownscale ||
48 out_width > width * 8)
49@@ -1530,20 +1525,22 @@ static int _dispc_setup_plane(enum omap_plane plane,
50 /* Must use 5-tap filter? */
51 five_taps = height > out_height * 2;
52
53- /* Try to use 5-tap filter whenever possible. */
54- if (cpu_is_omap34xx() && !five_taps &&
55- height > out_height && width <= 1024) {
56- fclk = calc_fclk_five_taps(width, height,
57- out_width, out_height, color_mode);
58- if (fclk <= dispc_fclk_rate())
59+ if (!five_taps) {
60+ fclk = calc_fclk(width, height,
61+ out_width, out_height);
62+
63+ /* Try 5-tap filter if 3-tap fclk is too high */
64+ if (cpu_is_omap34xx() && height > out_height &&
65+ fclk > dispc_fclk_rate())
66 five_taps = true;
67 }
68
69 if (width > (2048 >> five_taps))
70 return -EINVAL;
71
72- fclk = calc_fclk(width, height, out_width, out_height,
73- color_mode, five_taps);
74+ if (five_taps)
75+ fclk = calc_fclk_five_taps(width, height,
76+ out_width, out_height, color_mode);
77
78 DSSDBG("required fclk rate = %lu Hz\n", fclk);
79 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
80--
811.5.6.5
82
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0034-DSS2-VRAM-improve-omap_vram_add_region.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0034-DSS2-VRAM-improve-omap_vram_add_region.patch
new file mode 100644
index 0000000000..fdfc25fb47
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0034-DSS2-VRAM-improve-omap_vram_add_region.patch
@@ -0,0 +1,135 @@
1From 946eb774e95cdc2f2fa5cdc24aa69229f82814b8 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 16 Apr 2009 17:56:00 +0300
4Subject: [PATCH] DSS2: VRAM: improve omap_vram_add_region()
5
6Combine postponed and non-posponed versions of omap_vram_add_region.
7Make the func non-static, so it can be called from board files.
8---
9 arch/arm/plat-omap/include/mach/vram.h | 1 +
10 arch/arm/plat-omap/vram.c | 54 +++++++++++++------------------
11 2 files changed, 24 insertions(+), 31 deletions(-)
12
13diff --git a/arch/arm/plat-omap/include/mach/vram.h b/arch/arm/plat-omap/include/mach/vram.h
14index f176562..8639e08 100644
15--- a/arch/arm/plat-omap/include/mach/vram.h
16+++ b/arch/arm/plat-omap/include/mach/vram.h
17@@ -24,6 +24,7 @@
18
19 #include <asm/types.h>
20
21+extern int omap_vram_add_region(unsigned long paddr, size_t size);
22 extern int omap_vram_free(unsigned long paddr, size_t size);
23 extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
24 extern int omap_vram_reserve(unsigned long paddr, size_t size);
25diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
26index 520f260..8e9fe77 100644
27--- a/arch/arm/plat-omap/vram.c
28+++ b/arch/arm/plat-omap/vram.c
29@@ -60,6 +60,7 @@
30 * time when we cannot yet allocate the region list */
31 #define MAX_POSTPONED_REGIONS 10
32
33+static bool vram_initialized;
34 static int postponed_cnt __initdata;
35 static struct {
36 unsigned long paddr;
37@@ -145,39 +146,32 @@ static void omap_vram_free_allocation(struct vram_alloc *va)
38 kfree(va);
39 }
40
41-static __init int omap_vram_add_region_postponed(unsigned long paddr,
42- size_t size)
43-{
44- if (postponed_cnt == MAX_POSTPONED_REGIONS)
45- return -ENOMEM;
46-
47- postponed_regions[postponed_cnt].paddr = paddr;
48- postponed_regions[postponed_cnt].size = size;
49-
50- ++postponed_cnt;
51-
52- return 0;
53-}
54-
55-/* add/remove_region can be exported if there's need to add/remove regions
56- * runtime */
57-static int omap_vram_add_region(unsigned long paddr, size_t size)
58+int omap_vram_add_region(unsigned long paddr, size_t size)
59 {
60 struct vram_region *rm;
61 unsigned pages;
62
63- DBG("adding region paddr %08lx size %d\n",
64- paddr, size);
65+ if (vram_initialized) {
66+ DBG("adding region paddr %08lx size %d\n",
67+ paddr, size);
68
69- size &= PAGE_MASK;
70- pages = size >> PAGE_SHIFT;
71+ size &= PAGE_MASK;
72+ pages = size >> PAGE_SHIFT;
73
74- rm = omap_vram_create_region(paddr, pages);
75- if (rm == NULL)
76- return -ENOMEM;
77+ rm = omap_vram_create_region(paddr, pages);
78+ if (rm == NULL)
79+ return -ENOMEM;
80+
81+ list_add(&rm->list, &region_list);
82+ } else {
83+ if (postponed_cnt == MAX_POSTPONED_REGIONS)
84+ return -ENOMEM;
85
86- list_add(&rm->list, &region_list);
87+ postponed_regions[postponed_cnt].paddr = paddr;
88+ postponed_regions[postponed_cnt].size = size;
89
90+ ++postponed_cnt;
91+ }
92 return 0;
93 }
94
95@@ -438,6 +432,8 @@ static __init int omap_vram_init(void)
96 {
97 int i, r;
98
99+ vram_initialized = 1;
100+
101 for (i = 0; i < postponed_cnt; i++)
102 omap_vram_add_region(postponed_regions[i].paddr,
103 postponed_regions[i].size);
104@@ -472,10 +468,6 @@ static void __init omapfb_early_vram(char **p)
105 omapfb_def_sdram_vram_size = memparse(*p, p);
106 if (**p == ',')
107 omapfb_def_sdram_vram_start = simple_strtoul((*p) + 1, p, 16);
108-
109- printk("omapfb_early_vram, %d, 0x%x\n",
110- omapfb_def_sdram_vram_size,
111- omapfb_def_sdram_vram_start);
112 }
113 __early_param("vram=", omapfb_early_vram);
114
115@@ -538,7 +530,7 @@ void __init omapfb_reserve_sdram(void)
116 BUG_ON(paddr & ~PAGE_MASK);
117 }
118
119- omap_vram_add_region_postponed(paddr, size);
120+ omap_vram_add_region(paddr, size);
121
122 pr_info("Reserving %u bytes SDRAM for VRAM\n", size);
123 }
124@@ -594,7 +586,7 @@ unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
125 reserved = pend_avail - paddr;
126 size_avail = pend_avail - reserved - pstart_avail;
127
128- omap_vram_add_region_postponed(paddr, size);
129+ omap_vram_add_region(paddr, size);
130
131 if (reserved)
132 pr_info("Reserving %lu bytes SRAM for VRAM\n", reserved);
133--
1341.5.6.5
135
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0035-DSS2-Added-the-function-pointer-for-getting-default.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0035-DSS2-Added-the-function-pointer-for-getting-default.patch
new file mode 100644
index 0000000000..b7b395458f
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0035-DSS2-Added-the-function-pointer-for-getting-default.patch
@@ -0,0 +1,66 @@
1From f825cafd5ee5c600218740507f85594c825b0c00 Mon Sep 17 00:00:00 2001
2From: Hardik Shah <hardik.shah@ti.com>
3Date: Thu, 16 Apr 2009 18:47:49 +0530
4Subject: [PATCH] DSS2: Added the function pointer for getting default color.
5
6V4L2 Framework has a CID for getting/setting default color.
7So added the function pointer for doing same.
8SYSFS based getting the default color will remain same
9
10Signed-off-by: Hardik Shah <hardik.shah@ti.com>
11---
12 arch/arm/plat-omap/include/mach/display.h | 1 +
13 drivers/video/omap2/dss/manager.c | 11 +++++++----
14 2 files changed, 8 insertions(+), 4 deletions(-)
15
16diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
17index b0a6272..073cdda 100644
18--- a/arch/arm/plat-omap/include/mach/display.h
19+++ b/arch/arm/plat-omap/include/mach/display.h
20@@ -414,6 +414,7 @@ struct omap_overlay_manager {
21 int (*apply)(struct omap_overlay_manager *mgr);
22
23 void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
24+ u32 (*get_default_color)(struct omap_overlay_manager *mgr);
25 void (*set_trans_key)(struct omap_overlay_manager *mgr,
26 enum omap_dss_color_key_type type,
27 u32 trans_key);
28diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
29index 8ca0bbb..12cf7b0 100644
30--- a/drivers/video/omap2/dss/manager.c
31+++ b/drivers/video/omap2/dss/manager.c
32@@ -98,10 +98,8 @@ static ssize_t manager_display_store(struct omap_overlay_manager *mgr, const cha
33 static ssize_t manager_default_color_show(struct omap_overlay_manager *mgr,
34 char *buf)
35 {
36- u32 default_color;
37-
38- default_color = dispc_get_default_color(mgr->id);
39- return snprintf(buf, PAGE_SIZE, "%d", default_color);
40+ return snprintf(buf, PAGE_SIZE, "%d",
41+ mgr->get_default_color(mgr));
42 }
43
44 static ssize_t manager_default_color_store(struct omap_overlay_manager *mgr,
45@@ -470,6 +468,10 @@ static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
46 {
47 dispc_enable_trans_key(mgr->id, enable);
48 }
49+static u32 omap_dss_mgr_get_default_color(struct omap_overlay_manager *mgr)
50+{
51+ return dispc_get_default_color(mgr->id);
52+}
53
54 static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager)
55 {
56@@ -512,6 +514,7 @@ int dss_init_overlay_managers(struct platform_device *pdev)
57 mgr->set_default_color = &omap_dss_mgr_set_def_color,
58 mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
59 mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
60+ mgr->get_default_color = &omap_dss_mgr_get_default_color;
61 mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
62
63 dss_overlay_setup_dispc_manager(mgr);
64--
651.5.6.5
66
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0036-DSS2-Added-support-for-setting-and-querying-alpha-b.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0036-DSS2-Added-support-for-setting-and-querying-alpha-b.patch
new file mode 100644
index 0000000000..c6e9f16b3a
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0036-DSS2-Added-support-for-setting-and-querying-alpha-b.patch
@@ -0,0 +1,118 @@
1From 6c56dc10226c84f41917ac2117b0e654fa080d40 Mon Sep 17 00:00:00 2001
2From: Hardik Shah <hardik.shah@ti.com>
3Date: Thu, 16 Apr 2009 19:00:11 +0530
4Subject: [PATCH] DSS2: Added support for setting and querying alpha blending.
5
6Signed-off-by: Hardik Shah <hardik.shah@ti.com>
7---
8 arch/arm/plat-omap/include/mach/display.h | 3 +++
9 drivers/video/omap2/dss/dispc.c | 26 ++++++++++++++++++++++++++
10 drivers/video/omap2/dss/dss.h | 2 ++
11 drivers/video/omap2/dss/manager.c | 14 ++++++++++++++
12 4 files changed, 45 insertions(+), 0 deletions(-)
13
14diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
15index 073cdda..e1f615a 100644
16--- a/arch/arm/plat-omap/include/mach/display.h
17+++ b/arch/arm/plat-omap/include/mach/display.h
18@@ -415,11 +415,14 @@ struct omap_overlay_manager {
19
20 void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
21 u32 (*get_default_color)(struct omap_overlay_manager *mgr);
22+ bool (*get_alpha_blending_status)(struct omap_overlay_manager *mgr);
23 void (*set_trans_key)(struct omap_overlay_manager *mgr,
24 enum omap_dss_color_key_type type,
25 u32 trans_key);
26 void (*enable_trans_key)(struct omap_overlay_manager *mgr,
27 bool enable);
28+ void (*enable_alpha_blending)(struct omap_overlay_manager *mgr,
29+ bool enable);
30 };
31
32 enum omap_display_caps {
33diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
34index b631dd8..7e551c2 100644
35--- a/drivers/video/omap2/dss/dispc.c
36+++ b/drivers/video/omap2/dss/dispc.c
37@@ -1847,6 +1847,32 @@ void dispc_enable_trans_key(enum omap_channel ch, bool enable)
38 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
39 enable_clocks(0);
40 }
41+void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
42+{
43+ enable_clocks(1);
44+ if (ch == OMAP_DSS_CHANNEL_LCD)
45+ REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
46+ else /* OMAP_DSS_CHANNEL_DIGIT */
47+ REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
48+ enable_clocks(0);
49+}
50+bool dispc_alpha_blending_enabled(enum omap_channel ch)
51+{
52+ bool enabled;
53+
54+ enable_clocks(1);
55+ if (ch == OMAP_DSS_CHANNEL_LCD)
56+ enabled = REG_GET(DISPC_CONFIG, 18, 18);
57+ else if (ch == OMAP_DSS_CHANNEL_DIGIT)
58+ enabled = REG_GET(DISPC_CONFIG, 18, 18);
59+ else
60+ BUG();
61+ enable_clocks(0);
62+
63+ return enabled;
64+
65+}
66+
67
68 bool dispc_trans_key_enabled(enum omap_channel ch)
69 {
70diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
71index 584dce6..1d01ff6 100644
72--- a/drivers/video/omap2/dss/dss.h
73+++ b/drivers/video/omap2/dss/dss.h
74@@ -294,7 +294,9 @@ void dispc_get_trans_key(enum omap_channel ch,
75 enum omap_dss_color_key_type *type,
76 u32 *trans_key);
77 void dispc_enable_trans_key(enum omap_channel ch, bool enable);
78+void dispc_enable_alpha_blending(enum omap_channel ch, bool enable);
79 bool dispc_trans_key_enabled(enum omap_channel ch);
80+bool dispc_alpha_blending_enabled(enum omap_channel ch);
81
82 void dispc_set_lcd_timings(struct omap_video_timings *timings);
83 unsigned long dispc_fclk_rate(void);
84diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
85index 12cf7b0..90acd28 100644
86--- a/drivers/video/omap2/dss/manager.c
87+++ b/drivers/video/omap2/dss/manager.c
88@@ -468,6 +468,16 @@ static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
89 {
90 dispc_enable_trans_key(mgr->id, enable);
91 }
92+static void omap_dss_mgr_enable_alpha_blending(struct omap_overlay_manager *mgr,
93+ bool enable)
94+{
95+ dispc_enable_alpha_blending(mgr->id, enable);
96+}
97+static bool omap_dss_mgr_get_alpha_blending_status(
98+ struct omap_overlay_manager *mgr)
99+{
100+ return dispc_alpha_blending_enabled(mgr->id);
101+}
102 static u32 omap_dss_mgr_get_default_color(struct omap_overlay_manager *mgr)
103 {
104 return dispc_get_default_color(mgr->id);
105@@ -514,6 +524,10 @@ int dss_init_overlay_managers(struct platform_device *pdev)
106 mgr->set_default_color = &omap_dss_mgr_set_def_color,
107 mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
108 mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
109+ mgr->enable_alpha_blending =
110+ &omap_dss_mgr_enable_alpha_blending;
111+ mgr->get_alpha_blending_status =
112+ omap_dss_mgr_get_alpha_blending_status;
113 mgr->get_default_color = &omap_dss_mgr_get_default_color;
114 mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
115
116--
1171.5.6.5
118
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0037-DSS2-Added-support-for-querying-color-keying.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0037-DSS2-Added-support-for-querying-color-keying.patch
new file mode 100644
index 0000000000..fc62b09512
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0037-DSS2-Added-support-for-querying-color-keying.patch
@@ -0,0 +1,150 @@
1From 2c9edd6af31a812a9487dd8bc12322e105a29f44 Mon Sep 17 00:00:00 2001
2From: Hardik Shah <hardik.shah@ti.com>
3Date: Fri, 17 Apr 2009 09:42:36 +0530
4Subject: [PATCH] DSS2: Added support for querying color keying.
5
6V4L2 Framework has a ioctl for getting/setting color keying.
7So added the function manager pointers for doing same.
8
9Modifed the color keying sysfs entries to use manager
10function pointer. Earlier they were calling direcly
11dispc function to set/enable color keying.
12
13Some of color-keying function pointers in the overlay_manager
14structure re-named to be more specific.
15
16Signed-off-by: Hardik Shah <hardik.shah@ti.com>
17---
18 arch/arm/plat-omap/include/mach/display.h | 6 ++++-
19 drivers/video/omap2/dss/manager.c | 36 +++++++++++++++++++++--------
20 2 files changed, 31 insertions(+), 11 deletions(-)
21
22diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
23index e1f615a..d0b4c83 100644
24--- a/arch/arm/plat-omap/include/mach/display.h
25+++ b/arch/arm/plat-omap/include/mach/display.h
26@@ -416,7 +416,11 @@ struct omap_overlay_manager {
27 void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
28 u32 (*get_default_color)(struct omap_overlay_manager *mgr);
29 bool (*get_alpha_blending_status)(struct omap_overlay_manager *mgr);
30- void (*set_trans_key)(struct omap_overlay_manager *mgr,
31+ bool (*get_trans_key_status)(struct omap_overlay_manager *mgr);
32+ void (*get_trans_key_type_and_value)(struct omap_overlay_manager *mgr,
33+ enum omap_dss_color_key_type *type,
34+ u32 *trans_key);
35+ void (*set_trans_key_type_and_value)(struct omap_overlay_manager *mgr,
36 enum omap_dss_color_key_type type,
37 u32 trans_key);
38 void (*enable_trans_key)(struct omap_overlay_manager *mgr,
39diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
40index 90acd28..e0501c4 100644
41--- a/drivers/video/omap2/dss/manager.c
42+++ b/drivers/video/omap2/dss/manager.c
43@@ -124,7 +124,7 @@ static ssize_t manager_color_key_type_show(struct omap_overlay_manager *mgr,
44 {
45 enum omap_dss_color_key_type key_type;
46
47- dispc_get_trans_key(mgr->id, &key_type, NULL);
48+ mgr->get_trans_key_type_and_value(mgr, &key_type, NULL);
49 BUG_ON(key_type >= ARRAY_SIZE(color_key_type_str));
50
51 return snprintf(buf, PAGE_SIZE, "%s\n", color_key_type_str[key_type]);
52@@ -143,8 +143,8 @@ static ssize_t manager_color_key_type_store(struct omap_overlay_manager *mgr,
53 }
54 if (key_type == ARRAY_SIZE(color_key_type_str))
55 return -EINVAL;
56- dispc_get_trans_key(mgr->id, NULL, &key_value);
57- dispc_set_trans_key(mgr->id, key_type, key_value);
58+ mgr->get_trans_key_type_and_value(mgr, NULL, &key_value);
59+ mgr->set_trans_key_type_and_value(mgr, key_type, key_value);
60
61 return size;
62 }
63@@ -154,7 +154,7 @@ static ssize_t manager_color_key_value_show(struct omap_overlay_manager *mgr,
64 {
65 u32 key_value;
66
67- dispc_get_trans_key(mgr->id, NULL, &key_value);
68+ mgr->get_trans_key_type_and_value(mgr, NULL, &key_value);
69
70 return snprintf(buf, PAGE_SIZE, "%d\n", key_value);
71 }
72@@ -167,8 +167,8 @@ static ssize_t manager_color_key_value_store(struct omap_overlay_manager *mgr,
73
74 if (sscanf(buf, "%d", &key_value) != 1)
75 return -EINVAL;
76- dispc_get_trans_key(mgr->id, &key_type, NULL);
77- dispc_set_trans_key(mgr->id, key_type, key_value);
78+ mgr->get_trans_key_type_and_value(mgr, &key_type, NULL);
79+ mgr->set_trans_key_type_and_value(mgr, key_type, key_value);
80
81 return size;
82 }
83@@ -177,7 +177,7 @@ static ssize_t manager_color_key_enabled_show(struct omap_overlay_manager *mgr,
84 char *buf)
85 {
86 return snprintf(buf, PAGE_SIZE, "%d\n",
87- dispc_trans_key_enabled(mgr->id));
88+ mgr->get_trans_key_status(mgr));
89 }
90
91 static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
92@@ -188,7 +188,7 @@ static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
93 if (sscanf(buf, "%d", &enable) != 1)
94 return -EINVAL;
95
96- dispc_enable_trans_key(mgr->id, enable);
97+ mgr->enable_trans_key(mgr, enable);
98
99 return size;
100 }
101@@ -456,12 +456,20 @@ static void omap_dss_mgr_set_def_color(struct omap_overlay_manager *mgr,
102 dispc_set_default_color(mgr->id, color);
103 }
104
105-static void omap_dss_mgr_set_trans_key(struct omap_overlay_manager *mgr,
106+static void omap_dss_mgr_set_trans_key_type_and_value(
107+ struct omap_overlay_manager *mgr,
108 enum omap_dss_color_key_type type,
109 u32 trans_key)
110 {
111 dispc_set_trans_key(mgr->id, type, trans_key);
112 }
113+static void omap_dss_mgr_get_trans_key_type_and_value(
114+ struct omap_overlay_manager *mgr,
115+ enum omap_dss_color_key_type *type,
116+ u32 *trans_key)
117+{
118+ dispc_get_trans_key(mgr->id, type, trans_key);
119+}
120
121 static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
122 bool enable)
123@@ -482,6 +490,10 @@ static u32 omap_dss_mgr_get_default_color(struct omap_overlay_manager *mgr)
124 {
125 return dispc_get_default_color(mgr->id);
126 }
127+static bool omap_dss_mgr_get_trans_key_status(struct omap_overlay_manager *mgr)
128+{
129+ return dispc_trans_key_enabled(mgr->id);
130+}
131
132 static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager)
133 {
134@@ -522,8 +534,12 @@ int dss_init_overlay_managers(struct platform_device *pdev)
135 mgr->unset_display = &omap_dss_unset_display,
136 mgr->apply = &omap_dss_mgr_apply,
137 mgr->set_default_color = &omap_dss_mgr_set_def_color,
138- mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
139+ mgr->set_trans_key_type_and_value =
140+ &omap_dss_mgr_set_trans_key_type_and_value,
141+ mgr->get_trans_key_type_and_value =
142+ &omap_dss_mgr_get_trans_key_type_and_value,
143 mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
144+ mgr->get_trans_key_status = &omap_dss_mgr_get_trans_key_status,
145 mgr->enable_alpha_blending =
146 &omap_dss_mgr_enable_alpha_blending;
147 mgr->get_alpha_blending_status =
148--
1491.5.6.5
150
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0038-DSS2-OMAPFB-Some-color-keying-pointerd-renamed-in-D.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0038-DSS2-OMAPFB-Some-color-keying-pointerd-renamed-in-D.patch
new file mode 100644
index 0000000000..65cb113574
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0038-DSS2-OMAPFB-Some-color-keying-pointerd-renamed-in-D.patch
@@ -0,0 +1,56 @@
1From 9e8877f0e5b17d3ddd101d6a63aa86fdb14d35d5 Mon Sep 17 00:00:00 2001
2From: Hardik Shah <hardik.shah@ti.com>
3Date: Fri, 17 Apr 2009 09:51:25 +0530
4Subject: [PATCH] DSS2:OMAPFB: Some color keying pointerd renamed in DSS2. Replicated in FB
5
6Signed-off-by: Hardik Shah <hardik.shah@ti.com>
7---
8 drivers/video/omap2/omapfb/omapfb-ioctl.c | 11 +++++++----
9 1 files changed, 7 insertions(+), 4 deletions(-)
10
11diff --git a/drivers/video/omap2/omapfb/omapfb-ioctl.c b/drivers/video/omap2/omapfb/omapfb-ioctl.c
12index 7f18d2a..79d8916 100644
13--- a/drivers/video/omap2/omapfb/omapfb-ioctl.c
14+++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c
15@@ -288,7 +288,8 @@ static int _omapfb_set_color_key(struct omap_overlay_manager *mgr,
16 {
17 enum omap_dss_color_key_type kt;
18
19- if(!mgr->set_default_color || !mgr->set_trans_key ||
20+ if (!mgr->set_default_color ||
21+ !mgr->set_trans_key_type_and_value ||
22 !mgr->enable_trans_key)
23 return 0;
24
25@@ -310,7 +311,7 @@ static int _omapfb_set_color_key(struct omap_overlay_manager *mgr,
26 }
27
28 mgr->set_default_color(mgr, ck->background);
29- mgr->set_trans_key(mgr, kt, ck->trans_key);
30+ mgr->set_trans_key_type_and_value(mgr, kt, ck->trans_key);
31 mgr->enable_trans_key(mgr, 1);
32
33 omapfb_color_keys[mgr->id] = *ck;
34@@ -341,7 +342,8 @@ static int omapfb_set_color_key(struct fb_info *fbi,
35 goto err;
36 }
37
38- if(!mgr->set_default_color || !mgr->set_trans_key ||
39+ if (!mgr->set_default_color ||
40+ !mgr->set_trans_key_type_and_value ||
41 !mgr->enable_trans_key) {
42 r = -ENODEV;
43 goto err;
44@@ -377,7 +379,8 @@ static int omapfb_get_color_key(struct fb_info *fbi,
45 goto err;
46 }
47
48- if(!mgr->set_default_color || !mgr->set_trans_key ||
49+ if (!mgr->set_default_color ||
50+ !mgr->set_trans_key_type_and_value ||
51 !mgr->enable_trans_key) {
52 r = -ENODEV;
53 goto err;
54--
551.5.6.5
56
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0039-DSS2-Add-sysfs-entry-to-for-the-alpha-blending-supp.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0039-DSS2-Add-sysfs-entry-to-for-the-alpha-blending-supp.patch
new file mode 100644
index 0000000000..af8c2cd09b
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0039-DSS2-Add-sysfs-entry-to-for-the-alpha-blending-supp.patch
@@ -0,0 +1,59 @@
1From 6f1f0c7b19ecb468824b79f9d181ef0da41b7d7d Mon Sep 17 00:00:00 2001
2From: Hardik Shah <hardik.shah@ti.com>
3Date: Fri, 17 Apr 2009 13:58:21 +0530
4Subject: [PATCH] DSS2: Add sysfs entry to for the alpha blending support.
5
6Signed-off-by: Hardik Shah <hardik.shah@ti.com>
7---
8 drivers/video/omap2/dss/manager.c | 21 +++++++++++++++++++++
9 1 files changed, 21 insertions(+), 0 deletions(-)
10
11diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
12index e0501c4..7965a84 100644
13--- a/drivers/video/omap2/dss/manager.c
14+++ b/drivers/video/omap2/dss/manager.c
15@@ -192,6 +192,22 @@ static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
16
17 return size;
18 }
19+static ssize_t manager_alpha_blending_enabled_show(
20+ struct omap_overlay_manager *mgr, char *buf)
21+{
22+ return snprintf(buf, PAGE_SIZE, "%d\n",
23+ mgr->get_alpha_blending_status(mgr));
24+}
25+static ssize_t manager_alpha_blending_enabled_store(
26+ struct omap_overlay_manager *mgr,
27+ const char *buf, size_t size)
28+{
29+ int enable;
30+ if (sscanf(buf, "%d", &enable) != 1)
31+ return -EINVAL;
32+ mgr->enable_alpha_blending(mgr, enable);
33+ return size;
34+}
35
36
37 struct manager_attribute {
38@@ -215,6 +231,10 @@ static MANAGER_ATTR(color_key_value, S_IRUGO|S_IWUSR,
39 manager_color_key_value_show, manager_color_key_value_store);
40 static MANAGER_ATTR(color_key_enabled, S_IRUGO|S_IWUSR,
41 manager_color_key_enabled_show, manager_color_key_enabled_store);
42+static MANAGER_ATTR(alpha_blending_enabled, S_IRUGO|S_IWUSR,
43+ manager_alpha_blending_enabled_show,
44+ manager_alpha_blending_enabled_store);
45+
46
47 static struct attribute *manager_sysfs_attrs[] = {
48 &manager_attr_name.attr,
49@@ -223,6 +243,7 @@ static struct attribute *manager_sysfs_attrs[] = {
50 &manager_attr_color_key_type.attr,
51 &manager_attr_color_key_value.attr,
52 &manager_attr_color_key_enabled.attr,
53+ &manager_attr_alpha_blending_enabled.attr,
54 NULL
55 };
56
57--
581.5.6.5
59
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0040-DSS2-Provided-proper-exclusion-for-destination-colo.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0040-DSS2-Provided-proper-exclusion-for-destination-colo.patch
new file mode 100644
index 0000000000..66be75f3f7
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0040-DSS2-Provided-proper-exclusion-for-destination-colo.patch
@@ -0,0 +1,97 @@
1From a5129f272a48aa22629137c9c31e60eddb8c3f5d Mon Sep 17 00:00:00 2001
2From: Hardik Shah <hardik.shah@ti.com>
3Date: Fri, 17 Apr 2009 14:24:46 +0530
4Subject: [PATCH] DSS2: Provided proper exclusion for destination color keying and alpha blending.
5
6OMAP does not support destination color key and alpha blending
7simultaneously. So this patch does not allow the user
8so set both at a time.
9
10Signed-off-by: Hardik Shah <hardik.shah@ti.com>
11---
12 drivers/video/omap2/dss/manager.c | 50 ++++++++++++++++++++++++++++++++++++-
13 1 files changed, 49 insertions(+), 1 deletions(-)
14
15diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
16index 7965a84..108489c 100644
17--- a/drivers/video/omap2/dss/manager.c
18+++ b/drivers/video/omap2/dss/manager.c
19@@ -137,12 +137,26 @@ static ssize_t manager_color_key_type_store(struct omap_overlay_manager *mgr,
20 u32 key_value;
21
22 for (key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
23- key_type < ARRAY_SIZE(color_key_type_str); key_type++) {
24+ key_type < ARRAY_SIZE(color_key_type_str); key_type++) {
25 if (sysfs_streq(buf, color_key_type_str[key_type]))
26 break;
27 }
28 if (key_type == ARRAY_SIZE(color_key_type_str))
29 return -EINVAL;
30+ /* OMAP does not support destination color key and alpha blending
31+ * simultaneously. So if alpha blending and color keying both are
32+ * enabled then refrain from setting the color key type to
33+ * gfx-destination
34+ */
35+ if (!key_type) {
36+ bool color_key_enabled;
37+ bool alpha_blending_enabled;
38+ color_key_enabled = mgr->get_trans_key_status(mgr);
39+ alpha_blending_enabled = mgr->get_alpha_blending_status(mgr);
40+ if (color_key_enabled && alpha_blending_enabled)
41+ return -EINVAL;
42+ }
43+
44 mgr->get_trans_key_type_and_value(mgr, NULL, &key_value);
45 mgr->set_trans_key_type_and_value(mgr, key_type, key_value);
46
47@@ -188,6 +202,23 @@ static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
48 if (sscanf(buf, "%d", &enable) != 1)
49 return -EINVAL;
50
51+ /* OMAP does not support destination color keying and
52+ * alpha blending simultaneously. so if alpha blending
53+ * is enabled refrain from enabling destination color
54+ * keying.
55+ */
56+ if (enable) {
57+ bool enabled;
58+ enabled = mgr->get_alpha_blending_status(mgr);
59+ if (enabled) {
60+ enum omap_dss_color_key_type key_type;
61+ mgr->get_trans_key_type_and_value(mgr,
62+ &key_type, NULL);
63+ if (!key_type)
64+ return -EINVAL;
65+ }
66+
67+ }
68 mgr->enable_trans_key(mgr, enable);
69
70 return size;
71@@ -205,6 +236,23 @@ static ssize_t manager_alpha_blending_enabled_store(
72 int enable;
73 if (sscanf(buf, "%d", &enable) != 1)
74 return -EINVAL;
75+ /* OMAP does not support destination color keying and
76+ * alpha blending simultaneously. so if destination
77+ * color keying is enabled refrain from enabling
78+ * alpha blending
79+ */
80+ if (enable) {
81+ bool enabled;
82+ enabled = mgr->get_trans_key_status(mgr);
83+ if (enabled) {
84+ enum omap_dss_color_key_type key_type;
85+ mgr->get_trans_key_type_and_value(mgr, &key_type, NULL);
86+ if (!key_type)
87+ return -EINVAL;
88+
89+ }
90+
91+ }
92 mgr->enable_alpha_blending(mgr, enable);
93 return size;
94 }
95--
961.5.6.5
97
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0041-DSS2-Disable-vertical-offset-with-fieldmode.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0041-DSS2-Disable-vertical-offset-with-fieldmode.patch
new file mode 100644
index 0000000000..6785ade279
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0041-DSS2-Disable-vertical-offset-with-fieldmode.patch
@@ -0,0 +1,71 @@
1From 9bcac9b9e678f476c83b5679b1215b6bc946130a Mon Sep 17 00:00:00 2001
2From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
3Date: Mon, 20 Apr 2009 16:26:18 +0200
4Subject: [PATCH] DSS2: Disable vertical offset with fieldmode
5MIME-Version: 1.0
6Content-Type: text/plain; charset=utf-8
7Content-Transfer-Encoding: 8bit
8
9When using fieldmode each field is basically a separate picture so the
10vertical filter should start at phase 0 for both fields.
11
12Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
13---
14 drivers/video/omap2/dss/dispc.c | 23 +++++++++--------------
15 1 files changed, 9 insertions(+), 14 deletions(-)
16
17diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
18index 7e551c2..f15614b 100644
19--- a/drivers/video/omap2/dss/dispc.c
20+++ b/drivers/video/omap2/dss/dispc.c
21@@ -1029,12 +1029,12 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
22 static void _dispc_set_scaling(enum omap_plane plane,
23 u16 orig_width, u16 orig_height,
24 u16 out_width, u16 out_height,
25- bool ilace, bool five_taps)
26+ bool ilace, bool five_taps,
27+ bool fieldmode)
28 {
29 int fir_hinc;
30 int fir_vinc;
31 int hscaleup, vscaleup;
32- int fieldmode = 0;
33 int accu0 = 0;
34 int accu1 = 0;
35 u32 l;
36@@ -1072,17 +1072,12 @@ static void _dispc_set_scaling(enum omap_plane plane,
37
38 dispc_write_reg(dispc_reg_att[plane], l);
39
40- if (ilace) {
41- if (fieldmode) {
42- accu0 = fir_vinc / 2;
43- accu1 = 0;
44- } else {
45- accu0 = 0;
46- accu1 = fir_vinc / 2;
47- if (accu1 >= 1024/2) {
48- accu0 = 1024/2;
49- accu1 -= accu0;
50- }
51+ if (ilace && !fieldmode) {
52+ accu0 = 0;
53+ accu1 = fir_vinc / 2;
54+ if (accu1 >= 1024/2) {
55+ accu0 = 1024/2;
56+ accu1 -= accu0;
57 }
58 }
59
60@@ -1582,7 +1577,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
61 if (plane != OMAP_DSS_GFX) {
62 _dispc_set_scaling(plane, width, height,
63 out_width, out_height,
64- ilace, five_taps);
65+ ilace, five_taps, fieldmode);
66 _dispc_set_vid_size(plane, out_width, out_height);
67 _dispc_set_vid_color_conv(plane, cconv);
68 }
69--
701.5.6.5
71
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0042-DSS2-Don-t-enable-fieldmode-automatically.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0042-DSS2-Don-t-enable-fieldmode-automatically.patch
new file mode 100644
index 0000000000..5264911b41
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0042-DSS2-Don-t-enable-fieldmode-automatically.patch
@@ -0,0 +1,34 @@
1From 9c6de0fed6e8a598d026d348533fdf731b737d55 Mon Sep 17 00:00:00 2001
2From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
3Date: Mon, 20 Apr 2009 16:26:19 +0200
4Subject: [PATCH] DSS2: Don't enable fieldmode automatically
5MIME-Version: 1.0
6Content-Type: text/plain; charset=utf-8
7Content-Transfer-Encoding: 8bit
8
9The only case where enabling fieldmode automatically seems reasonable
10is when source and destination heights are equal. Some kind of user
11controllable knob should be added so the user could enable field mode
12when the source is interlaced.
13
14Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
15---
16 drivers/video/omap2/dss/dispc.c | 2 +-
17 1 files changed, 1 insertions(+), 1 deletions(-)
18
19diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
20index f15614b..1c036c1 100644
21--- a/drivers/video/omap2/dss/dispc.c
22+++ b/drivers/video/omap2/dss/dispc.c
23@@ -1450,7 +1450,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
24 if (paddr == 0)
25 return -EINVAL;
26
27- if (ilace && height >= out_height)
28+ if (ilace && height == out_height)
29 fieldmode = 1;
30
31 if (ilace) {
32--
331.5.6.5
34
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0043-DSS2-Swap-field-0-and-field-1-registers.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0043-DSS2-Swap-field-0-and-field-1-registers.patch
new file mode 100644
index 0000000000..76e37817c4
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0043-DSS2-Swap-field-0-and-field-1-registers.patch
@@ -0,0 +1,170 @@
1From 35e88797e93b107ba602dee1e2ac8ea761dccd4b Mon Sep 17 00:00:00 2001
2From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
3Date: Mon, 20 Apr 2009 16:26:20 +0200
4Subject: [PATCH] DSS2: Swap field 0 and field 1 registers
5MIME-Version: 1.0
6Content-Type: text/plain; charset=utf-8
7Content-Transfer-Encoding: 8bit
8
9The values for the registers which have alternate values for each field
10were reveresed to what the hardware expects. For the hardware field 0
11is the even field or the bottom field, field 1 is the odd field or the
12top field. So simply swap the register values.
13
14Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
15---
16 drivers/video/omap2/dss/dispc.c | 66 ++++++++++++++++++++++-----------------
17 1 files changed, 37 insertions(+), 29 deletions(-)
18
19diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
20index 1c036c1..9bab6cf 100644
21--- a/drivers/video/omap2/dss/dispc.c
22+++ b/drivers/video/omap2/dss/dispc.c
23@@ -1072,12 +1072,16 @@ static void _dispc_set_scaling(enum omap_plane plane,
24
25 dispc_write_reg(dispc_reg_att[plane], l);
26
27+ /*
28+ * field 0 = even field = bottom field
29+ * field 1 = odd field = top field
30+ */
31 if (ilace && !fieldmode) {
32- accu0 = 0;
33- accu1 = fir_vinc / 2;
34- if (accu1 >= 1024/2) {
35- accu0 = 1024/2;
36- accu1 -= accu0;
37+ accu1 = 0;
38+ accu0 = fir_vinc / 2;
39+ if (accu0 >= 1024/2) {
40+ accu1 = 1024/2;
41+ accu0 -= accu1;
42 }
43 }
44
45@@ -1266,34 +1270,38 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
46 fbh = width;
47 }
48
49+ /*
50+ * field 0 = even field = bottom field
51+ * field 1 = odd field = top field
52+ */
53 switch (rotation + mirror * 4) {
54 case 0:
55- *offset0 = 0;
56+ *offset1 = 0;
57 if (fieldmode)
58- *offset1 = screen_width * ps;
59+ *offset0 = screen_width * ps;
60 else
61- *offset1 = 0;
62+ *offset0 = 0;
63 *row_inc = pixinc(1 + (screen_width - fbw) +
64 (fieldmode ? screen_width : 0),
65 ps);
66 *pix_inc = pixinc(1, ps);
67 break;
68 case 1:
69- *offset0 = screen_width * (fbh - 1) * ps;
70+ *offset1 = screen_width * (fbh - 1) * ps;
71 if (fieldmode)
72- *offset1 = *offset0 + ps;
73+ *offset0 = *offset1 + ps;
74 else
75- *offset1 = *offset0;
76+ *offset0 = *offset1;
77 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
78 (fieldmode ? 1 : 0), ps);
79 *pix_inc = pixinc(-screen_width, ps);
80 break;
81 case 2:
82- *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
83+ *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
84 if (fieldmode)
85- *offset1 = *offset0 - screen_width * ps;
86+ *offset0 = *offset1 - screen_width * ps;
87 else
88- *offset1 = *offset0;
89+ *offset0 = *offset1;
90 *row_inc = pixinc(-1 -
91 (screen_width - fbw) -
92 (fieldmode ? screen_width : 0),
93@@ -1301,11 +1309,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
94 *pix_inc = pixinc(-1, ps);
95 break;
96 case 3:
97- *offset0 = (fbw - 1) * ps;
98+ *offset1 = (fbw - 1) * ps;
99 if (fieldmode)
100- *offset1 = *offset0 - ps;
101+ *offset0 = *offset1 - ps;
102 else
103- *offset1 = *offset0;
104+ *offset0 = *offset1;
105 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
106 (fieldmode ? 1 : 0), ps);
107 *pix_inc = pixinc(screen_width, ps);
108@@ -1313,11 +1321,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
109
110 /* mirroring */
111 case 0 + 4:
112- *offset0 = (fbw - 1) * ps;
113+ *offset1 = (fbw - 1) * ps;
114 if (fieldmode)
115- *offset1 = *offset0 + screen_width * ps;
116+ *offset0 = *offset1 + screen_width * ps;
117 else
118- *offset1 = *offset0;
119+ *offset0 = *offset1;
120 *row_inc = pixinc(screen_width * 2 - 1 +
121 (fieldmode ? screen_width : 0),
122 ps);
123@@ -1325,11 +1333,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
124 break;
125
126 case 1 + 4:
127- *offset0 = 0;
128+ *offset1 = 0;
129 if (fieldmode)
130- *offset1 = *offset0 + screen_width * ps;
131+ *offset0 = *offset1 + screen_width * ps;
132 else
133- *offset1 = *offset0;
134+ *offset0 = *offset1;
135 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
136 (fieldmode ? 1 : 0),
137 ps);
138@@ -1337,11 +1345,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
139 break;
140
141 case 2 + 4:
142- *offset0 = screen_width * (fbh - 1) * ps;
143+ *offset1 = screen_width * (fbh - 1) * ps;
144 if (fieldmode)
145- *offset1 = *offset0 + screen_width * ps;
146+ *offset0 = *offset1 + screen_width * ps;
147 else
148- *offset1 = *offset0;
149+ *offset0 = *offset1;
150 *row_inc = pixinc(1 - screen_width * 2 -
151 (fieldmode ? screen_width : 0),
152 ps);
153@@ -1349,11 +1357,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
154 break;
155
156 case 3 + 4:
157- *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
158+ *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
159 if (fieldmode)
160- *offset1 = *offset0 + screen_width * ps;
161+ *offset0 = *offset1 + screen_width * ps;
162 else
163- *offset1 = *offset0;
164+ *offset0 = *offset1;
165 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
166 (fieldmode ? 1 : 0),
167 ps);
168--
1691.5.6.5
170
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0044-DSS2-add-sysfs-entry-for-seting-the-rotate-type.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0044-DSS2-add-sysfs-entry-for-seting-the-rotate-type.patch
new file mode 100644
index 0000000000..32def9e8d5
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0044-DSS2-add-sysfs-entry-for-seting-the-rotate-type.patch
@@ -0,0 +1,76 @@
1From a9b3500bd14609750a2337e866e1df62627c1bac Mon Sep 17 00:00:00 2001
2From: Imre Deak <imre.deak@nokia.com>
3Date: Mon, 20 Apr 2009 14:55:33 +0200
4Subject: [PATCH] DSS2: add sysfs entry for seting the rotate type
5
6This can help in utilizing VRAM memory better. Since with VRFB rotation
7we waste a lot of physical memory due to the VRFB HW design, provide the
8possibility to turn it off and free the extra memory for the use by other
9planes for example.
10---
11 drivers/video/omap2/omapfb/omapfb-sysfs.c | 42 ++++++++++++++++++++++++++++-
12 1 files changed, 41 insertions(+), 1 deletions(-)
13
14diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
15index 2c88718..4e3da42 100644
16--- a/drivers/video/omap2/omapfb/omapfb-sysfs.c
17+++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
18@@ -43,6 +43,46 @@ static ssize_t show_rotate_type(struct device *dev,
19 return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->rotation_type);
20 }
21
22+static ssize_t store_rotate_type(struct device *dev,
23+ struct device_attribute *attr,
24+ const char *buf, size_t count)
25+{
26+ struct fb_info *fbi = dev_get_drvdata(dev);
27+ struct omapfb_info *ofbi = FB2OFB(fbi);
28+ struct omapfb2_device *fbdev = ofbi->fbdev;
29+ enum omap_dss_rotation_type rot_type;
30+ int r;
31+
32+ rot_type = simple_strtoul(buf, NULL, 0);
33+
34+ if (rot_type != OMAP_DSS_ROT_DMA && rot_type != OMAP_DSS_ROT_VRFB)
35+ return -EINVAL;
36+
37+ omapfb_lock(fbdev);
38+
39+ r = 0;
40+ if (rot_type == ofbi->rotation_type)
41+ goto out;
42+
43+ r = -EBUSY;
44+ if (ofbi->region.size)
45+ goto out;
46+
47+ ofbi->rotation_type = rot_type;
48+
49+ /*
50+ * Since the VRAM for this FB is not allocated at the moment we don't need to
51+ * do any further parameter checking at this point.
52+ */
53+
54+ r = count;
55+out:
56+ omapfb_unlock(fbdev);
57+
58+ return r;
59+}
60+
61+
62 static ssize_t show_mirror(struct device *dev,
63 struct device_attribute *attr, char *buf)
64 {
65@@ -327,7 +367,7 @@ static ssize_t show_virt(struct device *dev,
66 }
67
68 static struct device_attribute omapfb_attrs[] = {
69- __ATTR(rotate_type, S_IRUGO, show_rotate_type, NULL),
70+ __ATTR(rotate_type, S_IRUGO | S_IWUSR, show_rotate_type, store_rotate_type),
71 __ATTR(mirror, S_IRUGO | S_IWUSR, show_mirror, store_mirror),
72 __ATTR(size, S_IRUGO | S_IWUSR, show_size, store_size),
73 __ATTR(overlays, S_IRUGO | S_IWUSR, show_overlays, store_overlays),
74--
751.5.6.5
76
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0045-DSS2-Fixed-line-endings-from-to.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0045-DSS2-Fixed-line-endings-from-to.patch
new file mode 100644
index 0000000000..9382469850
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0045-DSS2-Fixed-line-endings-from-to.patch
@@ -0,0 +1,48 @@
1From b0e081456a9b094109c04467d041ff693843ca47 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Tue, 21 Apr 2009 09:25:16 +0300
4Subject: [PATCH] DSS2: Fixed line endings from , to ;
5
6---
7 drivers/video/omap2/dss/manager.c | 18 +++++++++---------
8 1 files changed, 9 insertions(+), 9 deletions(-)
9
10diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
11index 108489c..bf059e0 100644
12--- a/drivers/video/omap2/dss/manager.c
13+++ b/drivers/video/omap2/dss/manager.c
14@@ -599,22 +599,22 @@ int dss_init_overlay_managers(struct platform_device *pdev)
15 break;
16 }
17
18- mgr->set_display = &omap_dss_set_display,
19- mgr->unset_display = &omap_dss_unset_display,
20- mgr->apply = &omap_dss_mgr_apply,
21- mgr->set_default_color = &omap_dss_mgr_set_def_color,
22+ mgr->set_display = &omap_dss_set_display;
23+ mgr->unset_display = &omap_dss_unset_display;
24+ mgr->apply = &omap_dss_mgr_apply;
25+ mgr->set_default_color = &omap_dss_mgr_set_def_color;
26 mgr->set_trans_key_type_and_value =
27- &omap_dss_mgr_set_trans_key_type_and_value,
28+ &omap_dss_mgr_set_trans_key_type_and_value;
29 mgr->get_trans_key_type_and_value =
30- &omap_dss_mgr_get_trans_key_type_and_value,
31- mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
32- mgr->get_trans_key_status = &omap_dss_mgr_get_trans_key_status,
33+ &omap_dss_mgr_get_trans_key_type_and_value;
34+ mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key;
35+ mgr->get_trans_key_status = &omap_dss_mgr_get_trans_key_status;
36 mgr->enable_alpha_blending =
37 &omap_dss_mgr_enable_alpha_blending;
38 mgr->get_alpha_blending_status =
39 omap_dss_mgr_get_alpha_blending_status;
40 mgr->get_default_color = &omap_dss_mgr_get_default_color;
41- mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
42+ mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC;
43
44 dss_overlay_setup_dispc_manager(mgr);
45
46--
471.5.6.5
48
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0046-DSS2-DSI-decrease-sync-timeout-from-60s-to-2s.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0046-DSS2-DSI-decrease-sync-timeout-from-60s-to-2s.patch
new file mode 100644
index 0000000000..4ae5fbdd9a
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0046-DSS2-DSI-decrease-sync-timeout-from-60s-to-2s.patch
@@ -0,0 +1,26 @@
1From 0f88992b2681aed4f31dc7dd3926b357bbc95154 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Tue, 21 Apr 2009 10:11:55 +0300
4Subject: [PATCH] DSS2: DSI: decrease sync timeout from 60s to 2s
5
6The framedone-problem should be ok now, so we shouldn't get long waits.
7---
8 drivers/video/omap2/dss/dsi.c | 2 +-
9 1 files changed, 1 insertions(+), 1 deletions(-)
10
11diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
12index 50af925..d59ad38 100644
13--- a/drivers/video/omap2/dss/dsi.c
14+++ b/drivers/video/omap2/dss/dsi.c
15@@ -3216,7 +3216,7 @@ static void dsi_push_set_mirror(struct omap_display *display, int mirror)
16
17 static int dsi_wait_sync(struct omap_display *display)
18 {
19- long wait = msecs_to_jiffies(60000);
20+ long wait = msecs_to_jiffies(2000);
21 struct completion compl;
22
23 DSSDBGF("");
24--
251.5.6.5
26
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0047-DSS2-fix-return-value-for-rotate_type-sysfs-functio.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0047-DSS2-fix-return-value-for-rotate_type-sysfs-functio.patch
new file mode 100644
index 0000000000..0b0f104b30
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0047-DSS2-fix-return-value-for-rotate_type-sysfs-functio.patch
@@ -0,0 +1,44 @@
1From 7ddd5eaa7bc345c3719d613a46a95b7e8052ad2c Mon Sep 17 00:00:00 2001
2From: Imre Deak <imre.deak@nokia.com>
3Date: Tue, 21 Apr 2009 15:18:36 +0200
4Subject: [PATCH] DSS2: fix return value for rotate_type sysfs function
5
6Signed-off-by: Imre Deak <imre.deak@nokia.com>
7---
8 drivers/video/omap2/omapfb/omapfb-sysfs.c | 9 ++++-----
9 1 files changed, 4 insertions(+), 5 deletions(-)
10
11diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
12index 4e3da42..13028ae 100644
13--- a/drivers/video/omap2/omapfb/omapfb-sysfs.c
14+++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
15@@ -64,9 +64,10 @@ static ssize_t store_rotate_type(struct device *dev,
16 if (rot_type == ofbi->rotation_type)
17 goto out;
18
19- r = -EBUSY;
20- if (ofbi->region.size)
21+ if (ofbi->region.size) {
22+ r = -EBUSY;
23 goto out;
24+ }
25
26 ofbi->rotation_type = rot_type;
27
28@@ -74,12 +75,10 @@ static ssize_t store_rotate_type(struct device *dev,
29 * Since the VRAM for this FB is not allocated at the moment we don't need to
30 * do any further parameter checking at this point.
31 */
32-
33- r = count;
34 out:
35 omapfb_unlock(fbdev);
36
37- return r;
38+ return r ? r : count;
39 }
40
41
42--
431.5.6.5
44
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0048-OMAP2-3-DMA-implement-trans-copy-and-const-fill.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0048-OMAP2-3-DMA-implement-trans-copy-and-const-fill.patch
new file mode 100644
index 0000000000..cc6663fa21
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0048-OMAP2-3-DMA-implement-trans-copy-and-const-fill.patch
@@ -0,0 +1,123 @@
1From e34564db95627ad20e918b240c45e2bd5555f7e8 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Wed, 22 Apr 2009 10:06:08 +0300
4Subject: [PATCH] OMAP2/3: DMA: implement trans copy and const fill
5
6Implement transparent copy and constant fill features for OMAP2/3.
7
8Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
9---
10 arch/arm/plat-omap/dma.c | 81 +++++++++++++++++++++------------
11 arch/arm/plat-omap/include/mach/dma.h | 1 +
12 2 files changed, 52 insertions(+), 30 deletions(-)
13
14diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
15index 3fd0e77..060ac71 100755
16--- a/arch/arm/plat-omap/dma.c
17+++ b/arch/arm/plat-omap/dma.c
18@@ -310,41 +310,62 @@ EXPORT_SYMBOL(omap_set_dma_transfer_params);
19
20 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
21 {
22- u16 w;
23-
24 BUG_ON(omap_dma_in_1510_mode());
25
26- if (cpu_class_is_omap2()) {
27- REVISIT_24XX();
28- return;
29- }
30+ if (cpu_class_is_omap1()) {
31+ u16 w;
32
33- w = dma_read(CCR2(lch));
34- w &= ~0x03;
35+ w = dma_read(CCR2(lch));
36+ w &= ~0x03;
37
38- switch (mode) {
39- case OMAP_DMA_CONSTANT_FILL:
40- w |= 0x01;
41- break;
42- case OMAP_DMA_TRANSPARENT_COPY:
43- w |= 0x02;
44- break;
45- case OMAP_DMA_COLOR_DIS:
46- break;
47- default:
48- BUG();
49+ switch (mode) {
50+ case OMAP_DMA_CONSTANT_FILL:
51+ w |= 0x01;
52+ break;
53+ case OMAP_DMA_TRANSPARENT_COPY:
54+ w |= 0x02;
55+ break;
56+ case OMAP_DMA_COLOR_DIS:
57+ break;
58+ default:
59+ BUG();
60+ }
61+ dma_write(w, CCR2(lch));
62+
63+ w = dma_read(LCH_CTRL(lch));
64+ w &= ~0x0f;
65+ /* Default is channel type 2D */
66+ if (mode) {
67+ dma_write((u16)color, COLOR_L(lch));
68+ dma_write((u16)(color >> 16), COLOR_U(lch));
69+ w |= 1; /* Channel type G */
70+ }
71+ dma_write(w, LCH_CTRL(lch));
72 }
73- dma_write(w, CCR2(lch));
74
75- w = dma_read(LCH_CTRL(lch));
76- w &= ~0x0f;
77- /* Default is channel type 2D */
78- if (mode) {
79- dma_write((u16)color, COLOR_L(lch));
80- dma_write((u16)(color >> 16), COLOR_U(lch));
81- w |= 1; /* Channel type G */
82+ if (cpu_class_is_omap2()) {
83+ u32 val;
84+
85+ val = dma_read(CCR(lch));
86+ val &= ~((1 << 17) | (1 << 16));
87+
88+ switch (mode) {
89+ case OMAP_DMA_CONSTANT_FILL:
90+ val |= 1 << 16;
91+ break;
92+ case OMAP_DMA_TRANSPARENT_COPY:
93+ val |= 1 << 17;
94+ break;
95+ case OMAP_DMA_COLOR_DIS:
96+ break;
97+ default:
98+ BUG();
99+ }
100+ dma_write(val, CCR(lch));
101+
102+ color &= 0xffffff;
103+ dma_write(color, COLOR(lch));
104 }
105- dma_write(w, LCH_CTRL(lch));
106 }
107 EXPORT_SYMBOL(omap_set_dma_color_mode);
108
109diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
110index 224b077..4e34f47 100644
111--- a/arch/arm/plat-omap/include/mach/dma.h
112+++ b/arch/arm/plat-omap/include/mach/dma.h
113@@ -144,6 +144,7 @@
114 #define OMAP_DMA4_CSSA_U(n) 0
115 #define OMAP_DMA4_CDSA_L(n) 0
116 #define OMAP_DMA4_CDSA_U(n) 0
117+#define OMAP1_DMA_COLOR(n) 0
118
119 /*----------------------------------------------------------------------------*/
120
121--
1221.5.6.5
123
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0049-DSS2-VRAM-clear-allocated-area-with-DMA.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0049-DSS2-VRAM-clear-allocated-area-with-DMA.patch
new file mode 100644
index 0000000000..e9fc76ce15
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0049-DSS2-VRAM-clear-allocated-area-with-DMA.patch
@@ -0,0 +1,101 @@
1From 02034cc79f69512a6037f03ad1243c28f59fdd8a Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Wed, 22 Apr 2009 10:25:20 +0300
4Subject: [PATCH] DSS2: VRAM: clear allocated area with DMA
5
6Use DMA constant fill feature to clear VRAM area when
7someone allocates it.
8---
9 arch/arm/plat-omap/vram.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
10 1 files changed, 57 insertions(+), 0 deletions(-)
11
12diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
13index 8e9fe77..90276ac 100644
14--- a/arch/arm/plat-omap/vram.c
15+++ b/arch/arm/plat-omap/vram.c
16@@ -31,11 +31,13 @@
17 #include <linux/seq_file.h>
18 #include <linux/bootmem.h>
19 #include <linux/omapfb.h>
20+#include <linux/completion.h>
21
22 #include <asm/setup.h>
23
24 #include <mach/sram.h>
25 #include <mach/vram.h>
26+#include <mach/dma.h>
27
28 #ifdef DEBUG
29 #define DBG(format, ...) printk(KERN_DEBUG "VRAM: " format, ## __VA_ARGS__)
30@@ -276,6 +278,59 @@ int omap_vram_reserve(unsigned long paddr, size_t size)
31 }
32 EXPORT_SYMBOL(omap_vram_reserve);
33
34+static void _omap_vram_dma_cb(int lch, u16 ch_status, void *data)
35+{
36+ struct completion *compl = data;
37+ complete(compl);
38+}
39+
40+static int _omap_vram_clear(u32 paddr, unsigned pages)
41+{
42+ struct completion compl;
43+ unsigned elem_count;
44+ unsigned frame_count;
45+ int r;
46+ int lch;
47+
48+ init_completion(&compl);
49+
50+ r = omap_request_dma(OMAP_DMA_NO_DEVICE, "VRAM DMA",
51+ _omap_vram_dma_cb,
52+ &compl, &lch);
53+ if (r) {
54+ pr_err("VRAM: request_dma failed for memory clear\n");
55+ return -EBUSY;
56+ }
57+
58+ elem_count = pages * PAGE_SIZE / 4;
59+ frame_count = 1;
60+
61+ omap_set_dma_transfer_params(lch, OMAP_DMA_DATA_TYPE_S32,
62+ elem_count, frame_count,
63+ OMAP_DMA_SYNC_ELEMENT,
64+ 0, 0);
65+
66+ omap_set_dma_dest_params(lch, 0, OMAP_DMA_AMODE_POST_INC,
67+ paddr, 0, 0);
68+
69+ omap_set_dma_color_mode(lch, OMAP_DMA_CONSTANT_FILL, 0x000000);
70+
71+ omap_start_dma(lch);
72+
73+ if (wait_for_completion_timeout(&compl, msecs_to_jiffies(1000)) == 0) {
74+ omap_stop_dma(lch);
75+ pr_err("VRAM: dma timeout while clearing memory\n");
76+ r = -EIO;
77+ goto err;
78+ }
79+
80+ r = 0;
81+err:
82+ omap_free_dma(lch);
83+
84+ return r;
85+}
86+
87 static int _omap_vram_alloc(int mtype, unsigned pages, unsigned long *paddr)
88 {
89 struct vram_region *rm;
90@@ -313,6 +368,8 @@ found:
91
92 *paddr = start;
93
94+ _omap_vram_clear(start, pages);
95+
96 return 0;
97 }
98
99--
1001.5.6.5
101
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0050-DSS2-OMAPFB-remove-fb-clearing-code.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0050-DSS2-OMAPFB-remove-fb-clearing-code.patch
new file mode 100644
index 0000000000..8c5edd0c3d
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0050-DSS2-OMAPFB-remove-fb-clearing-code.patch
@@ -0,0 +1,53 @@
1From 07482193cccdfe9ede1f47d72790dfbe54343505 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Wed, 22 Apr 2009 10:26:06 +0300
4Subject: [PATCH] DSS2: OMAPFB: remove fb clearing code
5
6VRAM manager does the clearing now when the area is allocated.
7---
8 drivers/video/omap2/omapfb/omapfb-main.c | 8 --------
9 1 files changed, 0 insertions(+), 8 deletions(-)
10
11diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
12index cd63740..76e7c6c 100644
13--- a/drivers/video/omap2/omapfb/omapfb-main.c
14+++ b/drivers/video/omap2/omapfb/omapfb-main.c
15@@ -1174,7 +1174,6 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
16 struct omapfb2_mem_region *rg;
17 void __iomem *vaddr;
18 int r;
19- int clear = 0;
20
21 rg = &ofbi->region;
22 memset(rg, 0, sizeof(*rg));
23@@ -1184,7 +1183,6 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
24 if (!paddr) {
25 DBG("allocating %lu bytes for fb %d\n", size, ofbi->id);
26 r = omap_vram_alloc(OMAPFB_MEMTYPE_SDRAM, size, &paddr);
27- clear = 1;
28 } else {
29 DBG("reserving %lu bytes at %lx for fb %d\n", size, paddr,
30 ofbi->id);
31@@ -1206,9 +1204,6 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
32 }
33
34 DBG("allocated VRAM paddr %lx, vaddr %p\n", paddr, vaddr);
35-
36- if (clear)
37- memset_io(vaddr, 0, size);
38 } else {
39 void __iomem *va;
40
41@@ -1232,9 +1227,6 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
42 rg->vrfb.vaddr[0] = va;
43
44 vaddr = NULL;
45-
46- if (clear)
47- memset_io(va, 0, size);
48 }
49
50 rg->paddr = paddr;
51--
521.5.6.5
53
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0051-DSS2-VRAM-use-debugfs-not-procfs.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0051-DSS2-VRAM-use-debugfs-not-procfs.patch
new file mode 100644
index 0000000000..93ff3205d3
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0051-DSS2-VRAM-use-debugfs-not-procfs.patch
@@ -0,0 +1,170 @@
1From b47aef28536f3c276d232c41cd3084c69389dca4 Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Wed, 22 Apr 2009 14:11:52 +0300
4Subject: [PATCH] DSS2: VRAM: use debugfs, not procfs
5
6---
7 arch/arm/plat-omap/vram.c | 103 +++++++++++++++------------------------------
8 1 files changed, 34 insertions(+), 69 deletions(-)
9
10diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
11index 90276ac..e847579 100644
12--- a/arch/arm/plat-omap/vram.c
13+++ b/arch/arm/plat-omap/vram.c
14@@ -27,11 +27,11 @@
15 #include <linux/mm.h>
16 #include <linux/list.h>
17 #include <linux/dma-mapping.h>
18-#include <linux/proc_fs.h>
19 #include <linux/seq_file.h>
20 #include <linux/bootmem.h>
21 #include <linux/omapfb.h>
22 #include <linux/completion.h>
23+#include <linux/debugfs.h>
24
25 #include <asm/setup.h>
26
27@@ -398,88 +398,54 @@ int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr)
28 }
29 EXPORT_SYMBOL(omap_vram_alloc);
30
31-#ifdef CONFIG_PROC_FS
32-static void *r_next(struct seq_file *m, void *v, loff_t *pos)
33-{
34- struct list_head *l = v;
35-
36- (*pos)++;
37-
38- if (list_is_last(l, &region_list))
39- return NULL;
40-
41- return l->next;
42-}
43-
44-static void *r_start(struct seq_file *m, loff_t *pos)
45-{
46- loff_t p = *pos;
47- struct list_head *l = &region_list;
48-
49- mutex_lock(&region_mutex);
50-
51- do {
52- l = l->next;
53- if (l == &region_list)
54- return NULL;
55- } while (p--);
56-
57- return l;
58-}
59-
60-static void r_stop(struct seq_file *m, void *v)
61-{
62- mutex_unlock(&region_mutex);
63-}
64-
65-static int r_show(struct seq_file *m, void *v)
66+#if defined(CONFIG_DEBUG_FS)
67+static int vram_debug_show(struct seq_file *s, void *unused)
68 {
69 struct vram_region *vr;
70 struct vram_alloc *va;
71 unsigned size;
72
73- vr = list_entry(v, struct vram_region, list);
74-
75- size = vr->pages << PAGE_SHIFT;
76-
77- seq_printf(m, "%08lx-%08lx (%d bytes)\n",
78- vr->paddr, vr->paddr + size - 1,
79- size);
80+ mutex_lock(&region_mutex);
81
82- list_for_each_entry(va, &vr->alloc_list, list) {
83- size = va->pages << PAGE_SHIFT;
84- seq_printf(m, " %08lx-%08lx (%d bytes)\n",
85- va->paddr, va->paddr + size - 1,
86+ list_for_each_entry(vr, &region_list, list) {
87+ size = vr->pages << PAGE_SHIFT;
88+ seq_printf(s, "%08lx-%08lx (%d bytes)\n",
89+ vr->paddr, vr->paddr + size - 1,
90 size);
91- }
92
93+ list_for_each_entry(va, &vr->alloc_list, list) {
94+ size = va->pages << PAGE_SHIFT;
95+ seq_printf(s, " %08lx-%08lx (%d bytes)\n",
96+ va->paddr, va->paddr + size - 1,
97+ size);
98+ }
99+ }
100
101+ mutex_unlock(&region_mutex);
102
103 return 0;
104 }
105
106-static const struct seq_operations resource_op = {
107- .start = r_start,
108- .next = r_next,
109- .stop = r_stop,
110- .show = r_show,
111-};
112-
113-static int vram_open(struct inode *inode, struct file *file)
114+static int vram_debug_open(struct inode *inode, struct file *file)
115 {
116- return seq_open(file, &resource_op);
117+ return single_open(file, vram_debug_show, inode->i_private);
118 }
119
120-static const struct file_operations proc_vram_operations = {
121- .open = vram_open,
122- .read = seq_read,
123- .llseek = seq_lseek,
124- .release = seq_release,
125+static const struct file_operations vram_debug_fops = {
126+ .open = vram_debug_open,
127+ .read = seq_read,
128+ .llseek = seq_lseek,
129+ .release = single_release,
130 };
131
132-static int __init omap_vram_create_proc(void)
133+static int __init omap_vram_create_debugfs(void)
134 {
135- proc_create("omap-vram", 0, NULL, &proc_vram_operations);
136+ struct dentry *d;
137+
138+ d = debugfs_create_file("vram", S_IRUGO, NULL,
139+ NULL, &vram_debug_fops);
140+ if (IS_ERR(d))
141+ return PTR_ERR(d);
142
143 return 0;
144 }
145@@ -487,7 +453,7 @@ static int __init omap_vram_create_proc(void)
146
147 static __init int omap_vram_init(void)
148 {
149- int i, r;
150+ int i;
151
152 vram_initialized = 1;
153
154@@ -495,10 +461,9 @@ static __init int omap_vram_init(void)
155 omap_vram_add_region(postponed_regions[i].paddr,
156 postponed_regions[i].size);
157
158-#ifdef CONFIG_PROC_FS
159- r = omap_vram_create_proc();
160- if (r)
161- return -ENOMEM;
162+#ifdef CONFIG_DEBUG_FS
163+ if (omap_vram_create_debugfs())
164+ pr_err("VRAM: Failed to create debugfs file\n");
165 #endif
166
167 return 0;
168--
1691.5.6.5
170
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0052-DSS2-VRAM-fix-section-mismatch-warning.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0052-DSS2-VRAM-fix-section-mismatch-warning.patch
new file mode 100644
index 0000000000..b8f89b6239
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0052-DSS2-VRAM-fix-section-mismatch-warning.patch
@@ -0,0 +1,34 @@
1From 635fa66abe6e502c9b78b1dc66757bf67fd163e1 Mon Sep 17 00:00:00 2001
2From: Imre Deak <imre.deak@nokia.com>
3Date: Wed, 22 Apr 2009 14:40:48 +0200
4Subject: [PATCH] DSS2: VRAM: fix section mismatch warning
5
6postponed_regions are accessed from the non __init
7omap_vram_add_region().
8
9Signed-off-by: Imre Deak <imre.deak@nokia.com>
10---
11 arch/arm/plat-omap/vram.c | 4 ++--
12 1 files changed, 2 insertions(+), 2 deletions(-)
13
14diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
15index e847579..b126a64 100644
16--- a/arch/arm/plat-omap/vram.c
17+++ b/arch/arm/plat-omap/vram.c
18@@ -63,11 +63,11 @@
19 #define MAX_POSTPONED_REGIONS 10
20
21 static bool vram_initialized;
22-static int postponed_cnt __initdata;
23+static int postponed_cnt;
24 static struct {
25 unsigned long paddr;
26 size_t size;
27-} postponed_regions[MAX_POSTPONED_REGIONS] __initdata;
28+} postponed_regions[MAX_POSTPONED_REGIONS];
29
30 struct vram_alloc {
31 struct list_head list;
32--
331.5.6.5
34
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0053-DSS2-disable-LCD-DIGIT-before-resetting-DSS.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0053-DSS2-disable-LCD-DIGIT-before-resetting-DSS.patch
new file mode 100644
index 0000000000..f591fb700a
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0053-DSS2-disable-LCD-DIGIT-before-resetting-DSS.patch
@@ -0,0 +1,41 @@
1From c7ce3c5e9f7e28900b8ea9c3e1afe41dcdc0863d Mon Sep 17 00:00:00 2001
2From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
3Date: Thu, 23 Apr 2009 10:46:53 +0300
4Subject: [PATCH] DSS2: disable LCD & DIGIT before resetting DSS
5
6This seems to fix the synclost problem that we get, if the bootloader
7starts the DSS and the kernel resets it.
8---
9 drivers/video/omap2/dss/dss.c | 8 +++++---
10 1 files changed, 5 insertions(+), 3 deletions(-)
11
12diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
13index adc1f34..aab9758 100644
14--- a/drivers/video/omap2/dss/dss.c
15+++ b/drivers/video/omap2/dss/dss.c
16@@ -285,6 +285,11 @@ int dss_init(bool skip_init)
17 }
18
19 if (!skip_init) {
20+ /* disable LCD and DIGIT output. This seems to fix the synclost
21+ * problem that we get, if the bootloader starts the DSS and
22+ * the kernel resets it */
23+ omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
24+
25 /* We need to wait here a bit, otherwise we sometimes start to
26 * get synclost errors, and after that only power cycle will
27 * restore DSS functionality. I have no idea why this happens.
28@@ -294,10 +299,7 @@ int dss_init(bool skip_init)
29 msleep(50);
30
31 _omap_dss_reset();
32-
33 }
34- else
35- printk("DSS SKIP RESET\n");
36
37 /* autoidle */
38 REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
39--
401.5.6.5
41
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-09 01:23:32 +0000