diff options
Diffstat (limited to 'meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch')
-rw-r--r-- | meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch new file mode 100644 index 0000000000..d6b0cbbb41 --- /dev/null +++ b/meta/recipes-kernel/linux/linux-omap-2.6.29/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch | |||
@@ -0,0 +1,68 @@ | |||
1 | From a5c235a6f0094494ae1fc1a1ba4728e0d33dfd3b Mon Sep 17 00:00:00 2001 | ||
2 | From: Tomi Valkeinen <tomi.valkeinen@nokia.com> | ||
3 | Date: Thu, 2 Apr 2009 16:49:27 +0300 | ||
4 | Subject: [PATCH] DSS2: DSI: calculate VP_CLK_RATIO properly | ||
5 | |||
6 | --- | ||
7 | drivers/video/omap2/dss/dsi.c | 17 +++++++++++------ | ||
8 | 1 files changed, 11 insertions(+), 6 deletions(-) | ||
9 | |||
10 | diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c | ||
11 | index 4442931..aecb89d 100644 | ||
12 | --- a/drivers/video/omap2/dss/dsi.c | ||
13 | +++ b/drivers/video/omap2/dss/dsi.c | ||
14 | @@ -1104,7 +1104,10 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv) | ||
15 | enable_clocks(1); | ||
16 | dsi_enable_pll_clock(1); | ||
17 | |||
18 | - /* configure dispc fck and pixel clock to something sane */ | ||
19 | + /* XXX this should be calculated depending on the screen size, | ||
20 | + * required framerate and DSI speed. | ||
21 | + * For now 48MHz is enough for 864x480@60 with 360Mbps/lane | ||
22 | + * with two lanes */ | ||
23 | r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo); | ||
24 | if (r) | ||
25 | goto err0; | ||
26 | @@ -1119,7 +1122,7 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv) | ||
27 | if (r) | ||
28 | goto err0; | ||
29 | |||
30 | - /* PLL does not come out of reset without this... */ | ||
31 | + /* XXX PLL does not come out of reset without this... */ | ||
32 | dispc_pck_free_enable(1); | ||
33 | |||
34 | if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) { | ||
35 | @@ -1128,8 +1131,8 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv) | ||
36 | goto err1; | ||
37 | } | ||
38 | |||
39 | - /* ... but if left on, we get problems when planes do not | ||
40 | - * fill the whole display. No idea about this XXX */ | ||
41 | + /* XXX ... but if left on, we get problems when planes do not | ||
42 | + * fill the whole display. No idea about this */ | ||
43 | dispc_pck_free_enable(0); | ||
44 | |||
45 | if (enable_hsclk && enable_hsdiv) | ||
46 | @@ -2214,6 +2217,7 @@ static int dsi_proto_config(struct omap_display *display) | ||
47 | { | ||
48 | u32 r; | ||
49 | int buswidth = 0; | ||
50 | + int div; | ||
51 | |||
52 | dsi_config_tx_fifo(DSI_FIFO_SIZE_128, | ||
53 | DSI_FIFO_SIZE_0, | ||
54 | @@ -2254,8 +2258,9 @@ static int dsi_proto_config(struct omap_display *display) | ||
55 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ | ||
56 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ | ||
57 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ | ||
58 | - /* XXX what should the ratio be */ | ||
59 | - r = FLD_MOD(r, 0, 4, 4); /* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */ | ||
60 | + | ||
61 | + div = dispc_lclk_rate() / dispc_pclk_rate(); | ||
62 | + r = FLD_MOD(r, div == 2 ? 0 : 1, 4, 4); /* VP_CLK_RATIO */ | ||
63 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ | ||
64 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ | ||
65 | r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */ | ||
66 | -- | ||
67 | 1.5.6.5 | ||
68 | |||