diff options
Diffstat (limited to 'meta/recipes-devtools/qemu/qemu')
-rw-r--r-- | meta/recipes-devtools/qemu/qemu/37ed3bf1ee07bb1a26adca0df8718f601f231c0b.patch | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/meta/recipes-devtools/qemu/qemu/37ed3bf1ee07bb1a26adca0df8718f601f231c0b.patch b/meta/recipes-devtools/qemu/qemu/37ed3bf1ee07bb1a26adca0df8718f601f231c0b.patch new file mode 100644 index 0000000000..8609e3fe99 --- /dev/null +++ b/meta/recipes-devtools/qemu/qemu/37ed3bf1ee07bb1a26adca0df8718f601f231c0b.patch | |||
@@ -0,0 +1,59 @@ | |||
1 | Without this patch, x86_64 images would show invalid EDSCA key errors | ||
2 | with sshd from openssh (but not dropbear) during init. | ||
3 | |||
4 | This would cause problems with operation with some distros where EDSCA | ||
5 | keys were mandatory. The issue was present in qemu 2.2.1 and not in | ||
6 | 2.3.0-rc0, bisected to this commit which was then backported. | ||
7 | |||
8 | From 37ed3bf1ee07bb1a26adca0df8718f601f231c0b Mon Sep 17 00:00:00 2001 | ||
9 | From: Richard Henderson <rth@twiddle.net> | ||
10 | Date: Fri, 20 Feb 2015 11:13:50 -0800 | ||
11 | Subject: [PATCH] tcg: Complete handling of ALWAYS and NEVER | ||
12 | |||
13 | Missing from movcond | ||
14 | |||
15 | Signed-off-by: Richard Henderson <rth@twiddle.net> | ||
16 | --- | ||
17 | tcg/tcg-op.c | 22 +++++++++++++++++----- | ||
18 | 1 files changed, 17 insertions(+), 5 deletions(-) | ||
19 | |||
20 | Upstream-Status: Backport | ||
21 | RP 2015/3/24 | ||
22 | |||
23 | Index: qemu-2.2.0/tcg/tcg-op.h | ||
24 | =================================================================== | ||
25 | --- qemu-2.2.0.orig/tcg/tcg-op.h | ||
26 | +++ qemu-2.2.0/tcg/tcg-op.h | ||
27 | @@ -2186,7 +2186,11 @@ static inline void tcg_gen_movcond_i32(T | ||
28 | TCGv_i32 c1, TCGv_i32 c2, | ||
29 | TCGv_i32 v1, TCGv_i32 v2) | ||
30 | { | ||
31 | - if (TCG_TARGET_HAS_movcond_i32) { | ||
32 | + if (cond == TCG_COND_ALWAYS) { | ||
33 | + tcg_gen_mov_i32(ret, v1); | ||
34 | + } else if (cond == TCG_COND_NEVER) { | ||
35 | + tcg_gen_mov_i32(ret, v2); | ||
36 | + } else if (TCG_TARGET_HAS_movcond_i32) { | ||
37 | tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond); | ||
38 | } else { | ||
39 | TCGv_i32 t0 = tcg_temp_new_i32(); | ||
40 | @@ -2205,6 +2209,11 @@ static inline void tcg_gen_movcond_i64(T | ||
41 | TCGv_i64 c1, TCGv_i64 c2, | ||
42 | TCGv_i64 v1, TCGv_i64 v2) | ||
43 | { | ||
44 | + if (cond == TCG_COND_ALWAYS) { | ||
45 | + tcg_gen_mov_i64(ret, v1); | ||
46 | + } else if (cond == TCG_COND_NEVER) { | ||
47 | + tcg_gen_mov_i64(ret, v2); | ||
48 | + } else { | ||
49 | #if TCG_TARGET_REG_BITS == 32 | ||
50 | TCGv_i32 t0 = tcg_temp_new_i32(); | ||
51 | TCGv_i32 t1 = tcg_temp_new_i32(); | ||
52 | @@ -2246,6 +2255,7 @@ static inline void tcg_gen_movcond_i64(T | ||
53 | tcg_temp_free_i64(t1); | ||
54 | } | ||
55 | #endif | ||
56 | + } | ||
57 | } | ||
58 | |||
59 | static inline void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, | ||