1 files changed, 0 insertions, 59 deletions

diff --git a/meta/recipes-devtools/qemu/qemu/37ed3bf1ee07bb1a26adca0df8718f601f231c0b.patch b/meta/recipes-devtools/qemu/qemu/37ed3bf1ee07bb1a26adca0df8718f601f231c0b.patch
deleted file mode 100644
index 8609e3fe99..0000000000
--- a/meta/recipes-devtools/qemu/qemu/37ed3bf1ee07bb1a26adca0df8718f601f231c0b.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-Without this patch, x86_64 images would show invalid EDSCA key errors
-with sshd from openssh (but not dropbear) during init. 
-
-This would cause problems with operation with some distros where EDSCA 
-keys were mandatory. The issue was present in qemu 2.2.1 and not in 
-2.3.0-rc0, bisected to this commit which was then backported.
-
-From 37ed3bf1ee07bb1a26adca0df8718f601f231c0b Mon Sep 17 00:00:00 2001
-From: Richard Henderson <rth@twiddle.net>
-Date: Fri, 20 Feb 2015 11:13:50 -0800
-Subject: [PATCH] tcg: Complete handling of ALWAYS and NEVER
-
-Missing from movcond
-
-Signed-off-by: Richard Henderson <rth@twiddle.net>
----
- tcg/tcg-op.c |   22 +++++++++++++++++-----
- 1 files changed, 17 insertions(+), 5 deletions(-)
-
-Upstream-Status: Backport
-RP 2015/3/24
-
-Index: qemu-2.2.0/tcg/tcg-op.h
-===================================================================
---- qemu-2.2.0.orig/tcg/tcg-op.h
-+++ qemu-2.2.0/tcg/tcg-op.h
-@@ -2186,7 +2186,11 @@ static inline void tcg_gen_movcond_i32(T
-                                        TCGv_i32 c1, TCGv_i32 c2,
-                                        TCGv_i32 v1, TCGv_i32 v2)
- {
--    if (TCG_TARGET_HAS_movcond_i32) {
-+    if (cond == TCG_COND_ALWAYS) {
-+        tcg_gen_mov_i32(ret, v1);
-+    } else if (cond == TCG_COND_NEVER) {
-+        tcg_gen_mov_i32(ret, v2);
-+    } else if (TCG_TARGET_HAS_movcond_i32) {
-         tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond);
-     } else {
-         TCGv_i32 t0 = tcg_temp_new_i32();
-@@ -2205,6 +2209,11 @@ static inline void tcg_gen_movcond_i64(T
-                                        TCGv_i64 c1, TCGv_i64 c2,
-                                        TCGv_i64 v1, TCGv_i64 v2)
- {
-+    if (cond == TCG_COND_ALWAYS) {
-+        tcg_gen_mov_i64(ret, v1);
-+    } else if (cond == TCG_COND_NEVER) {
-+        tcg_gen_mov_i64(ret, v2);
-+    } else {
- #if TCG_TARGET_REG_BITS == 32
-     TCGv_i32 t0 = tcg_temp_new_i32();
-     TCGv_i32 t1 = tcg_temp_new_i32();
-@@ -2246,6 +2255,7 @@ static inline void tcg_gen_movcond_i64(T
-         tcg_temp_free_i64(t1);
-     }
- #endif
-+    }
- }
- 
- static inline void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,