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-rw-r--r--meta/recipes-devtools/qemu/qemu/10-xen-pt-add-a-few-PCI-config-space-field-descriptions-CVE-2015-4106.patch77
1 files changed, 0 insertions, 77 deletions
diff --git a/meta/recipes-devtools/qemu/qemu/10-xen-pt-add-a-few-PCI-config-space-field-descriptions-CVE-2015-4106.patch b/meta/recipes-devtools/qemu/qemu/10-xen-pt-add-a-few-PCI-config-space-field-descriptions-CVE-2015-4106.patch
deleted file mode 100644
index f30b40a93e..0000000000
--- a/meta/recipes-devtools/qemu/qemu/10-xen-pt-add-a-few-PCI-config-space-field-descriptions-CVE-2015-4106.patch
+++ /dev/null
@@ -1,77 +0,0 @@
1Upstream-Status: Backport
2
3Signed-off-by: Kai Kang <kai.kang@windriver.com>
4
5From a88a3f887181605f4487a22bdfb7d87ffafde5d9 Mon Sep 17 00:00:00 2001
6From: Jan Beulich <jbeulich@suse.com>
7Date: Tue, 2 Jun 2015 15:07:01 +0000
8Subject: xen/pt: add a few PCI config space field descriptions
9Bug-Debian: http://bugs.debian.org/787547
10
11Since the next patch will turn all not explicitly described fields
12read-only by default, those fields that have guest writable bits need
13to be given explicit descriptors.
14
15This is a preparatory patch for XSA-131.
16
17Signed-off-by: Jan Beulich <jbeulich@suse.com>
18---
19 hw/xen/xen_pt_config_init.c | 28 ++++++++++++++++++++++++++++
20 1 file changed, 28 insertions(+)
21
22diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
23index efd8bac..19f926b 100644
24--- a/hw/xen/xen_pt_config_init.c
25+++ b/hw/xen/xen_pt_config_init.c
26@@ -754,6 +754,15 @@ static XenPTRegInfo xen_pt_emu_reg_vpd[] = {
27 .u.b.write = xen_pt_byte_reg_write,
28 },
29 {
30+ .offset = PCI_VPD_ADDR,
31+ .size = 2,
32+ .ro_mask = 0x0003,
33+ .emu_mask = 0x0003,
34+ .init = xen_pt_common_reg_init,
35+ .u.w.read = xen_pt_word_reg_read,
36+ .u.w.write = xen_pt_word_reg_write,
37+ },
38+ {
39 .size = 0,
40 },
41 };
42@@ -889,6 +898,16 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
43 .u.w.read = xen_pt_word_reg_read,
44 .u.w.write = xen_pt_word_reg_write,
45 },
46+ /* Device Status reg */
47+ {
48+ .offset = PCI_EXP_DEVSTA,
49+ .size = 2,
50+ .res_mask = 0xFFC0,
51+ .ro_mask = 0x0030,
52+ .init = xen_pt_common_reg_init,
53+ .u.w.read = xen_pt_word_reg_read,
54+ .u.w.write = xen_pt_word_reg_write,
55+ },
56 /* Link Control reg */
57 {
58 .offset = PCI_EXP_LNKCTL,
59@@ -900,6 +919,15 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
60 .u.w.read = xen_pt_word_reg_read,
61 .u.w.write = xen_pt_word_reg_write,
62 },
63+ /* Link Status reg */
64+ {
65+ .offset = PCI_EXP_LNKSTA,
66+ .size = 2,
67+ .ro_mask = 0x3FFF,
68+ .init = xen_pt_common_reg_init,
69+ .u.w.read = xen_pt_word_reg_read,
70+ .u.w.write = xen_pt_word_reg_write,
71+ },
72 /* Device Control 2 reg */
73 {
74 .offset = 0x28,
75--
762.1.4
77