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-rw-r--r--meta/recipes-devtools/qemu/qemu/05-xen-pt-consolidate-PM-capability-emu_mask-CVE-2015-4106.patch86
1 files changed, 0 insertions, 86 deletions
diff --git a/meta/recipes-devtools/qemu/qemu/05-xen-pt-consolidate-PM-capability-emu_mask-CVE-2015-4106.patch b/meta/recipes-devtools/qemu/qemu/05-xen-pt-consolidate-PM-capability-emu_mask-CVE-2015-4106.patch
deleted file mode 100644
index e9e4fccb4d..0000000000
--- a/meta/recipes-devtools/qemu/qemu/05-xen-pt-consolidate-PM-capability-emu_mask-CVE-2015-4106.patch
+++ /dev/null
@@ -1,86 +0,0 @@
1Upstream-Status: Backport
2
3Signed-off-by: Kai Kang <kai.kang@windriver.com>
4
5From d61bb2482dc0c7426f451f23ba7e2748ae2cc06d Mon Sep 17 00:00:00 2001
6From: Jan Beulich <jbeulich@suse.com>
7Date: Tue, 2 Jun 2015 15:07:01 +0000
8Subject: xen/pt: consolidate PM capability emu_mask
9Bug-Debian: http://bugs.debian.org/787547
10
11There's no point in xen_pt_pmcsr_reg_{read,write}() each ORing
12PCI_PM_CTRL_STATE_MASK and PCI_PM_CTRL_NO_SOFT_RESET into a local
13emu_mask variable - we can have the same effect by setting the field
14descriptor's emu_mask member suitably right away. Note that
15xen_pt_pmcsr_reg_write() is being retained in order to allow later
16patches to be less intrusive.
17
18This is a preparatory patch for XSA-131.
19
20Signed-off-by: Jan Beulich <jbeulich@suse.com>
21Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
22Acked-by: Ian Campbell <ian.campbell@citrix.com>
23---
24 hw/xen/xen_pt_config_init.c | 25 ++++---------------------
25 1 file changed, 4 insertions(+), 21 deletions(-)
26
27diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
28index 436d0fd..516236a 100644
29--- a/hw/xen/xen_pt_config_init.c
30+++ b/hw/xen/xen_pt_config_init.c
31@@ -933,38 +933,21 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
32 * Power Management Capability
33 */
34
35-/* read Power Management Control/Status register */
36-static int xen_pt_pmcsr_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
37- uint16_t *value, uint16_t valid_mask)
38-{
39- XenPTRegInfo *reg = cfg_entry->reg;
40- uint16_t valid_emu_mask = reg->emu_mask;
41-
42- valid_emu_mask |= PCI_PM_CTRL_STATE_MASK | PCI_PM_CTRL_NO_SOFT_RESET;
43-
44- valid_emu_mask = valid_emu_mask & valid_mask;
45- *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
46-
47- return 0;
48-}
49 /* write Power Management Control/Status register */
50 static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s,
51 XenPTReg *cfg_entry, uint16_t *val,
52 uint16_t dev_value, uint16_t valid_mask)
53 {
54 XenPTRegInfo *reg = cfg_entry->reg;
55- uint16_t emu_mask = reg->emu_mask;
56 uint16_t writable_mask = 0;
57 uint16_t throughable_mask = 0;
58
59- emu_mask |= PCI_PM_CTRL_STATE_MASK | PCI_PM_CTRL_NO_SOFT_RESET;
60-
61 /* modify emulate register */
62- writable_mask = emu_mask & ~reg->ro_mask & valid_mask;
63+ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
64 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
65
66 /* create value for writing to I/O device register */
67- throughable_mask = ~emu_mask & valid_mask;
68+ throughable_mask = ~reg->emu_mask & valid_mask;
69 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
70
71 return 0;
72@@ -1000,9 +983,9 @@ static XenPTRegInfo xen_pt_emu_reg_pm[] = {
73 .size = 2,
74 .init_val = 0x0008,
75 .ro_mask = 0xE1FC,
76- .emu_mask = 0x8100,
77+ .emu_mask = 0x810B,
78 .init = xen_pt_common_reg_init,
79- .u.w.read = xen_pt_pmcsr_reg_read,
80+ .u.w.read = xen_pt_word_reg_read,
81 .u.w.write = xen_pt_pmcsr_reg_write,
82 },
83 {
84--
852.1.4
86