diff options
Diffstat (limited to 'meta/recipes-devtools/qemu/qemu-0.13.0/port92_fix.patch')
-rw-r--r-- | meta/recipes-devtools/qemu/qemu-0.13.0/port92_fix.patch | 196 |
1 files changed, 196 insertions, 0 deletions
diff --git a/meta/recipes-devtools/qemu/qemu-0.13.0/port92_fix.patch b/meta/recipes-devtools/qemu/qemu-0.13.0/port92_fix.patch new file mode 100644 index 0000000000..e101c687c0 --- /dev/null +++ b/meta/recipes-devtools/qemu/qemu-0.13.0/port92_fix.patch | |||
@@ -0,0 +1,196 @@ | |||
1 | With qemu 0.13.0, poky failed to start on ppc arch because both ppc_prep_init | ||
2 | and i8042_initfn try to register to port 0x92 then cause conflict. Introduce | ||
3 | this patch from upstream to fix it. | ||
4 | |||
5 | Could remove it in future if necessary. | ||
6 | |||
7 | Signed-off-by: Zhai, Edwin <edwin.zhai@intel.com> | ||
8 | |||
9 | commit 4b78a802ffaabb325a0f7b773031da92d173bde1 | ||
10 | Author: Blue Swirl <blauwirbel@gmail.com> | ||
11 | Date: Thu Jan 6 18:24:35 2011 +0000 | ||
12 | |||
13 | pc: move port 92 stuff back to pc.c from pckbd.c | ||
14 | |||
15 | 956a3e6bb7386de48b642d4fee11f7f86a2fcf9a introduced a bug concerning | ||
16 | reset bit for port 92. | ||
17 | |||
18 | Since the keyboard output port and port 92 are not compatible anyway, | ||
19 | let's separate them. | ||
20 | |||
21 | Reported-by: Peter Lieven <pl@dlh.net> | ||
22 | Signed-off-by: Blue Swirl <blauwirbel@gmail.com> | ||
23 | -- | ||
24 | v2: added reset handler and VMState | ||
25 | |||
26 | Index: qemu-0.13.0/hw/pc.c | ||
27 | =================================================================== | ||
28 | --- qemu-0.13.0.orig/hw/pc.c 2010-10-16 04:56:09.000000000 +0800 | ||
29 | +++ qemu-0.13.0/hw/pc.c 2011-01-20 20:37:37.000000000 +0800 | ||
30 | @@ -409,11 +409,91 @@ | ||
31 | qemu_register_reset(pc_cmos_init_late, &arg); | ||
32 | } | ||
33 | |||
34 | +/* port 92 stuff: could be split off */ | ||
35 | +typedef struct Port92State { | ||
36 | + ISADevice dev; | ||
37 | + uint8_t outport; | ||
38 | + qemu_irq *a20_out; | ||
39 | +} Port92State; | ||
40 | + | ||
41 | +static void port92_write(void *opaque, uint32_t addr, uint32_t val) | ||
42 | +{ | ||
43 | + Port92State *s = opaque; | ||
44 | + | ||
45 | + DPRINTF("port92: write 0x%02x\n", val); | ||
46 | + s->outport = val; | ||
47 | + qemu_set_irq(*s->a20_out, (val >> 1) & 1); | ||
48 | + if (val & 1) { | ||
49 | + qemu_system_reset_request(); | ||
50 | + } | ||
51 | +} | ||
52 | + | ||
53 | +static uint32_t port92_read(void *opaque, uint32_t addr) | ||
54 | +{ | ||
55 | + Port92State *s = opaque; | ||
56 | + uint32_t ret; | ||
57 | + | ||
58 | + ret = s->outport; | ||
59 | + DPRINTF("port92: read 0x%02x\n", ret); | ||
60 | + return ret; | ||
61 | +} | ||
62 | + | ||
63 | +static void port92_init(ISADevice *dev, qemu_irq *a20_out) | ||
64 | +{ | ||
65 | + Port92State *s = DO_UPCAST(Port92State, dev, dev); | ||
66 | + | ||
67 | + s->a20_out = a20_out; | ||
68 | +} | ||
69 | + | ||
70 | +static const VMStateDescription vmstate_port92_isa = { | ||
71 | + .name = "port92", | ||
72 | + .version_id = 1, | ||
73 | + .minimum_version_id = 1, | ||
74 | + .minimum_version_id_old = 1, | ||
75 | + .fields = (VMStateField []) { | ||
76 | + VMSTATE_UINT8(outport, Port92State), | ||
77 | + VMSTATE_END_OF_LIST() | ||
78 | + } | ||
79 | +}; | ||
80 | + | ||
81 | +static void port92_reset(DeviceState *d) | ||
82 | +{ | ||
83 | + Port92State *s = container_of(d, Port92State, dev.qdev); | ||
84 | + | ||
85 | + s->outport &= ~1; | ||
86 | +} | ||
87 | + | ||
88 | +static int port92_initfn(ISADevice *dev) | ||
89 | +{ | ||
90 | + Port92State *s = DO_UPCAST(Port92State, dev, dev); | ||
91 | + | ||
92 | + register_ioport_read(0x92, 1, 1, port92_read, s); | ||
93 | + register_ioport_write(0x92, 1, 1, port92_write, s); | ||
94 | + s->outport = 0; | ||
95 | + return 0; | ||
96 | +} | ||
97 | + | ||
98 | +static ISADeviceInfo port92_info = { | ||
99 | + .qdev.name = "port92", | ||
100 | + .qdev.size = sizeof(Port92State), | ||
101 | + .qdev.vmsd = &vmstate_port92_isa, | ||
102 | + .qdev.no_user = 1, | ||
103 | + .qdev.reset = port92_reset, | ||
104 | + .init = port92_initfn, | ||
105 | +}; | ||
106 | + | ||
107 | +static void port92_register(void) | ||
108 | +{ | ||
109 | + isa_qdev_register(&port92_info); | ||
110 | +} | ||
111 | +device_init(port92_register) | ||
112 | + | ||
113 | static void handle_a20_line_change(void *opaque, int irq, int level) | ||
114 | { | ||
115 | CPUState *cpu = opaque; | ||
116 | |||
117 | /* XXX: send to all CPUs ? */ | ||
118 | + /* XXX: add logic to handle multiple A20 line sources */ | ||
119 | cpu_x86_set_a20(cpu, level); | ||
120 | } | ||
121 | |||
122 | @@ -1017,7 +1097,7 @@ | ||
123 | PITState *pit; | ||
124 | qemu_irq rtc_irq = NULL; | ||
125 | qemu_irq *a20_line; | ||
126 | - ISADevice *i8042; | ||
127 | + ISADevice *i8042, *port92; | ||
128 | qemu_irq *cpu_exit_irq; | ||
129 | |||
130 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); | ||
131 | @@ -1051,10 +1131,12 @@ | ||
132 | } | ||
133 | } | ||
134 | |||
135 | - a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1); | ||
136 | + a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); | ||
137 | i8042 = isa_create_simple("i8042"); | ||
138 | - i8042_setup_a20_line(i8042, a20_line); | ||
139 | + i8042_setup_a20_line(i8042, &a20_line[0]); | ||
140 | vmmouse_init(i8042); | ||
141 | + port92 = isa_create_simple("port92"); | ||
142 | + port92_init(port92, &a20_line[1]); | ||
143 | |||
144 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); | ||
145 | DMA_init(0, cpu_exit_irq); | ||
146 | Index: qemu-0.13.0/hw/pckbd.c | ||
147 | =================================================================== | ||
148 | --- qemu-0.13.0.orig/hw/pckbd.c 2010-10-16 04:56:09.000000000 +0800 | ||
149 | +++ qemu-0.13.0/hw/pckbd.c 2011-01-20 20:33:44.000000000 +0800 | ||
150 | @@ -209,10 +209,8 @@ | ||
151 | ps2_queue(s->kbd, b); | ||
152 | } | ||
153 | |||
154 | -static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) | ||
155 | +static void outport_write(KBDState *s, uint32_t val) | ||
156 | { | ||
157 | - KBDState *s = opaque; | ||
158 | - | ||
159 | DPRINTF("kbd: write outport=0x%02x\n", val); | ||
160 | s->outport = val; | ||
161 | if (s->a20_out) { | ||
162 | @@ -223,16 +221,6 @@ | ||
163 | } | ||
164 | } | ||
165 | |||
166 | -static uint32_t ioport92_read(void *opaque, uint32_t addr) | ||
167 | -{ | ||
168 | - KBDState *s = opaque; | ||
169 | - uint32_t ret; | ||
170 | - | ||
171 | - ret = s->outport; | ||
172 | - DPRINTF("kbd: read outport=0x%02x\n", ret); | ||
173 | - return ret; | ||
174 | -} | ||
175 | - | ||
176 | static void kbd_write_command(void *opaque, uint32_t addr, uint32_t val) | ||
177 | { | ||
178 | KBDState *s = opaque; | ||
179 | @@ -340,7 +328,7 @@ | ||
180 | kbd_queue(s, val, 1); | ||
181 | break; | ||
182 | case KBD_CCMD_WRITE_OUTPORT: | ||
183 | - ioport92_write(s, 0, val); | ||
184 | + outport_write(s, val); | ||
185 | break; | ||
186 | case KBD_CCMD_WRITE_MOUSE: | ||
187 | ps2_write_mouse(s->mouse, val); | ||
188 | @@ -469,8 +457,6 @@ | ||
189 | register_ioport_write(0x60, 1, 1, kbd_write_data, s); | ||
190 | register_ioport_read(0x64, 1, 1, kbd_read_status, s); | ||
191 | register_ioport_write(0x64, 1, 1, kbd_write_command, s); | ||
192 | - register_ioport_read(0x92, 1, 1, ioport92_read, s); | ||
193 | - register_ioport_write(0x92, 1, 1, ioport92_write, s); | ||
194 | |||
195 | s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); | ||
196 | s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); | ||