diff options
Diffstat (limited to 'meta/recipes-devtools/gcc')
-rw-r--r-- | meta/recipes-devtools/gcc/gcc-4.6.inc | 5 | ||||
-rw-r--r-- | meta/recipes-devtools/gcc/gcc-4.6/gcc.e6500-FSF46.patch | 4015 | ||||
-rw-r--r-- | meta/recipes-devtools/gcc/gcc-4.6/gcc.no_power_builtins.patch | 30 | ||||
-rw-r--r-- | meta/recipes-devtools/gcc/gcc-4.6/powerpc-e5500.patch | 465 |
4 files changed, 4048 insertions, 467 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.6.inc b/meta/recipes-devtools/gcc/gcc-4.6.inc index 4c6fe28f5d..c9529f02c6 100644 --- a/meta/recipes-devtools/gcc/gcc-4.6.inc +++ b/meta/recipes-devtools/gcc/gcc-4.6.inc | |||
@@ -1,6 +1,6 @@ | |||
1 | require gcc-common.inc | 1 | require gcc-common.inc |
2 | 2 | ||
3 | PR = "r28" | 3 | PR = "r29" |
4 | 4 | ||
5 | # Third digit in PV should be incremented after a minor release | 5 | # Third digit in PV should be incremented after a minor release |
6 | # happens from this branch on gcc e.g. currently its 4.6.0 | 6 | # happens from this branch on gcc e.g. currently its 4.6.0 |
@@ -64,7 +64,6 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \ | |||
64 | file://disable_relax_pic_calls_flag.patch \ | 64 | file://disable_relax_pic_calls_flag.patch \ |
65 | file://COLLECT_GCC_OPTIONS.patch \ | 65 | file://COLLECT_GCC_OPTIONS.patch \ |
66 | file://use-defaults.h-and-t-oe-in-B.patch \ | 66 | file://use-defaults.h-and-t-oe-in-B.patch \ |
67 | file://powerpc-e5500.patch \ | ||
68 | file://fix-for-ice-50099.patch \ | 67 | file://fix-for-ice-50099.patch \ |
69 | file://gcc-with-linker-hash-style.patch \ | 68 | file://gcc-with-linker-hash-style.patch \ |
70 | file://pr46934.patch \ | 69 | file://pr46934.patch \ |
@@ -74,6 +73,8 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \ | |||
74 | file://GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch \ | 73 | file://GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch \ |
75 | file://fortran-cross-compile-hack.patch \ | 74 | file://fortran-cross-compile-hack.patch \ |
76 | file://cpp-honour-sysroot.patch \ | 75 | file://cpp-honour-sysroot.patch \ |
76 | file://gcc.e6500-FSF46.patch \ | ||
77 | file://gcc.no_power_builtins.patch \ | ||
77 | " | 78 | " |
78 | 79 | ||
79 | SRC_URI_append_sh3 = " file://sh3-installfix-fixheaders.patch " | 80 | SRC_URI_append_sh3 = " file://sh3-installfix-fixheaders.patch " |
diff --git a/meta/recipes-devtools/gcc/gcc-4.6/gcc.e6500-FSF46.patch b/meta/recipes-devtools/gcc/gcc-4.6/gcc.e6500-FSF46.patch new file mode 100644 index 0000000000..2de5f778e4 --- /dev/null +++ b/meta/recipes-devtools/gcc/gcc-4.6/gcc.e6500-FSF46.patch | |||
@@ -0,0 +1,4015 @@ | |||
1 | Upstream-Status: Pending | ||
2 | |||
3 | People are working to include this fixes upstream | ||
4 | |||
5 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/altivec.h gcc-4.6.2/gcc/config/rs6000/altivec.h | ||
6 | --- gcc-4.6.2-orig/gcc/config/rs6000/altivec.h 2011-02-02 23:42:19.000000000 -0600 | ||
7 | +++ gcc-4.6.2/gcc/config/rs6000/altivec.h 2012-03-06 12:33:43.943038996 -0600 | ||
8 | @@ -322,6 +322,30 @@ | ||
9 | #define vec_vsx_st __builtin_vec_vsx_st | ||
10 | #endif | ||
11 | |||
12 | +#ifdef __ALTIVEC2__ | ||
13 | +/* New Altivec instructions */ | ||
14 | +#define vec_absd __builtin_vec_absd | ||
15 | +#define vec_lvexbx __builtin_vec_lvexbx | ||
16 | +#define vec_lvexhx __builtin_vec_lvexhx | ||
17 | +#define vec_lvexwx __builtin_vec_lvexwx | ||
18 | +#define vec_stvexbx __builtin_vec_stvexbx | ||
19 | +#define vec_stvexhx __builtin_vec_stvexhx | ||
20 | +#define vec_stvexwx __builtin_vec_stvexwx | ||
21 | +#define vec_lvswx __builtin_vec_lvswx | ||
22 | +#define vec_lvswxl __builtin_vec_lvswxl | ||
23 | +#define vec_stvswx __builtin_vec_stvswx | ||
24 | +#define vec_stvswxl __builtin_vec_stvswxl | ||
25 | +#define vec_lvsm __builtin_vec_lvsm | ||
26 | +#define vec_lvtlx __builtin_vec_lvtlx | ||
27 | +#define vec_lvtlxl __builtin_vec_lvtlxl | ||
28 | +#define vec_lvtrx __builtin_vec_lvtrx | ||
29 | +#define vec_lvtrxl __builtin_vec_lvtrxl | ||
30 | +#define vec_stvflx __builtin_vec_stvflx | ||
31 | +#define vec_stvflxl __builtin_vec_stvflxl | ||
32 | +#define vec_stvfrx __builtin_vec_stvfrx | ||
33 | +#define vec_stvfrxl __builtin_vec_stvfrxl | ||
34 | +#endif | ||
35 | + | ||
36 | /* Predicates. | ||
37 | For C++, we use templates in order to allow non-parenthesized arguments. | ||
38 | For C, instead, we use macros since non-parenthesized arguments were | ||
39 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/altivec.md gcc-4.6.2/gcc/config/rs6000/altivec.md | ||
40 | --- gcc-4.6.2-orig/gcc/config/rs6000/altivec.md 2011-07-08 15:10:18.000000000 -0500 | ||
41 | +++ gcc-4.6.2/gcc/config/rs6000/altivec.md 2012-03-06 12:24:35.058038999 -0600 | ||
42 | @@ -91,9 +91,11 @@ | ||
43 | (UNSPEC_LVSL 194) | ||
44 | (UNSPEC_LVSR 195) | ||
45 | (UNSPEC_LVE 196) | ||
46 | + (UNSPEC_LVEX 197) | ||
47 | (UNSPEC_STVX 201) | ||
48 | (UNSPEC_STVXL 202) | ||
49 | (UNSPEC_STVE 203) | ||
50 | + (UNSPEC_STVEX 204) | ||
51 | (UNSPEC_SET_VSCR 213) | ||
52 | (UNSPEC_GET_VRSAVE 214) | ||
53 | (UNSPEC_LVX 215) | ||
54 | @@ -123,6 +125,19 @@ | ||
55 | (UNSPEC_STVLXL 241) | ||
56 | (UNSPEC_STVRX 242) | ||
57 | (UNSPEC_STVRXL 243) | ||
58 | + (UNSPEC_LVTLX 244) | ||
59 | + (UNSPEC_LVTLXL 245) | ||
60 | + (UNSPEC_LVTRX 246) | ||
61 | + (UNSPEC_LVTRXL 247) | ||
62 | + (UNSPEC_STVFLX 248) | ||
63 | + (UNSPEC_STVFLXL 249) | ||
64 | + (UNSPEC_STVFRX 250) | ||
65 | + (UNSPEC_STVFRXL 251) | ||
66 | + (UNSPEC_LVSWX 252) | ||
67 | + (UNSPEC_LVSWXL 253) | ||
68 | + (UNSPEC_LVSM 254) | ||
69 | + (UNSPEC_STVSWX 255) | ||
70 | + (UNSPEC_STVSWXL 256) | ||
71 | (UNSPEC_VMULWHUB 308) | ||
72 | (UNSPEC_VMULWLUB 309) | ||
73 | (UNSPEC_VMULWHSB 310) | ||
74 | @@ -143,6 +158,9 @@ | ||
75 | (UNSPEC_VUPKLS_V4SF 325) | ||
76 | (UNSPEC_VUPKHU_V4SF 326) | ||
77 | (UNSPEC_VUPKLU_V4SF 327) | ||
78 | + (UNSPEC_VABSDUB 328) | ||
79 | + (UNSPEC_VABSDUH 329) | ||
80 | + (UNSPEC_VABSDUW 330) | ||
81 | ]) | ||
82 | |||
83 | (define_constants | ||
84 | @@ -323,6 +341,34 @@ | ||
85 | |||
86 | ;; Simple binary operations. | ||
87 | |||
88 | +;; absd | ||
89 | +(define_insn "altivec_vabsduw" | ||
90 | + [(set (match_operand:V4SI 0 "register_operand" "=v") | ||
91 | + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | ||
92 | + (match_operand:V4SI 2 "register_operand" "v")] | ||
93 | + UNSPEC_VABSDUW))] | ||
94 | + "TARGET_ALTIVEC2" | ||
95 | + "vabsduw %0,%1,%2" | ||
96 | + [(set_attr "type" "vecsimple")]) | ||
97 | + | ||
98 | +(define_insn "altivec_vabsduh" | ||
99 | + [(set (match_operand:V8HI 0 "register_operand" "=v") | ||
100 | + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | ||
101 | + (match_operand:V8HI 2 "register_operand" "v")] | ||
102 | + UNSPEC_VABSDUH))] | ||
103 | + "TARGET_ALTIVEC2" | ||
104 | + "vabsduh %0,%1,%2" | ||
105 | + [(set_attr "type" "vecsimple")]) | ||
106 | + | ||
107 | +(define_insn "altivec_vabsdub" | ||
108 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
109 | + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | ||
110 | + (match_operand:V16QI 2 "register_operand" "v")] | ||
111 | + UNSPEC_VABSDUB))] | ||
112 | + "TARGET_ALTIVEC2" | ||
113 | + "vabsdub %0,%1,%2" | ||
114 | + [(set_attr "type" "vecsimple")]) | ||
115 | + | ||
116 | ;; add | ||
117 | (define_insn "add<mode>3" | ||
118 | [(set (match_operand:VI 0 "register_operand" "=v") | ||
119 | @@ -1741,6 +1787,15 @@ | ||
120 | "lvewx %0,%y1" | ||
121 | [(set_attr "type" "vecload")]) | ||
122 | |||
123 | +(define_insn "altivec_lvex<VI_char>x" | ||
124 | + [(parallel | ||
125 | + [(set (match_operand:VI 0 "register_operand" "=v") | ||
126 | + (match_operand:VI 1 "memory_operand" "Z")) | ||
127 | + (unspec [(const_int 0)] UNSPEC_LVEX)])] | ||
128 | + "TARGET_ALTIVEC2" | ||
129 | + "lvex<VI_char>x %0,%y1" | ||
130 | + [(set_attr "type" "vecload")]) | ||
131 | + | ||
132 | (define_insn "altivec_lvxl" | ||
133 | [(parallel | ||
134 | [(set (match_operand:V4SI 0 "register_operand" "=v") | ||
135 | @@ -1791,6 +1846,13 @@ | ||
136 | "stvewx %1,%y0" | ||
137 | [(set_attr "type" "vecstore")]) | ||
138 | |||
139 | +(define_insn "altivec_stvex<VI_char>x" | ||
140 | + [(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z") | ||
141 | + (unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVEX))] | ||
142 | + "TARGET_ALTIVEC2" | ||
143 | + "stvex<VI_char>x %1,%y0" | ||
144 | + [(set_attr "type" "vecstore")]) | ||
145 | + | ||
146 | ;; Generate | ||
147 | ;; vspltis? SCRATCH0,0 | ||
148 | ;; vsubu?m SCRATCH2,SCRATCH1,%1 | ||
149 | @@ -2358,7 +2420,7 @@ | ||
150 | DONE; | ||
151 | }") | ||
152 | |||
153 | -;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL, | ||
154 | +;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX1, LVRXL, | ||
155 | ;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell. | ||
156 | (define_insn "altivec_lvlx" | ||
157 | [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
158 | @@ -2394,8 +2456,8 @@ | ||
159 | |||
160 | (define_insn "altivec_stvlx" | ||
161 | [(parallel | ||
162 | - [(set (match_operand:V4SI 0 "memory_operand" "=Z") | ||
163 | - (match_operand:V4SI 1 "register_operand" "v")) | ||
164 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
165 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
166 | (unspec [(const_int 0)] UNSPEC_STVLX)])] | ||
167 | "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" | ||
168 | "stvlx %1,%y0" | ||
169 | @@ -2403,8 +2465,8 @@ | ||
170 | |||
171 | (define_insn "altivec_stvlxl" | ||
172 | [(parallel | ||
173 | - [(set (match_operand:V4SI 0 "memory_operand" "=Z") | ||
174 | - (match_operand:V4SI 1 "register_operand" "v")) | ||
175 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
176 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
177 | (unspec [(const_int 0)] UNSPEC_STVLXL)])] | ||
178 | "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" | ||
179 | "stvlxl %1,%y0" | ||
180 | @@ -2412,8 +2474,8 @@ | ||
181 | |||
182 | (define_insn "altivec_stvrx" | ||
183 | [(parallel | ||
184 | - [(set (match_operand:V4SI 0 "memory_operand" "=Z") | ||
185 | - (match_operand:V4SI 1 "register_operand" "v")) | ||
186 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
187 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
188 | (unspec [(const_int 0)] UNSPEC_STVRX)])] | ||
189 | "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" | ||
190 | "stvrx %1,%y0" | ||
191 | @@ -2421,13 +2483,123 @@ | ||
192 | |||
193 | (define_insn "altivec_stvrxl" | ||
194 | [(parallel | ||
195 | - [(set (match_operand:V4SI 0 "memory_operand" "=Z") | ||
196 | - (match_operand:V4SI 1 "register_operand" "v")) | ||
197 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
198 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
199 | (unspec [(const_int 0)] UNSPEC_STVRXL)])] | ||
200 | "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" | ||
201 | "stvrxl %1,%y0" | ||
202 | [(set_attr "type" "vecstore")]) | ||
203 | |||
204 | +(define_insn "altivec_lvtlx" | ||
205 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
206 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
207 | + UNSPEC_LVTLX))] | ||
208 | + "TARGET_ALTIVEC2" | ||
209 | + "lvtlx %0,%y1" | ||
210 | + [(set_attr "type" "vecload")]) | ||
211 | + | ||
212 | +(define_insn "altivec_lvtlxl" | ||
213 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
214 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
215 | + UNSPEC_LVTLXL))] | ||
216 | + "TARGET_ALTIVEC2" | ||
217 | + "lvtlxl %0,%y1" | ||
218 | + [(set_attr "type" "vecload")]) | ||
219 | + | ||
220 | +(define_insn "altivec_lvtrx" | ||
221 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
222 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
223 | + UNSPEC_LVTRX))] | ||
224 | + "TARGET_ALTIVEC2" | ||
225 | + "lvtrx %0,%y1" | ||
226 | + [(set_attr "type" "vecload")]) | ||
227 | + | ||
228 | +(define_insn "altivec_lvtrxl" | ||
229 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
230 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
231 | + UNSPEC_LVTRXL))] | ||
232 | + "TARGET_ALTIVEC2" | ||
233 | + "lvtrxl %0,%y1" | ||
234 | + [(set_attr "type" "vecload")]) | ||
235 | + | ||
236 | +(define_insn "altivec_stvflx" | ||
237 | + [(parallel | ||
238 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
239 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
240 | + (unspec [(const_int 0)] UNSPEC_STVFLX)])] | ||
241 | + "TARGET_ALTIVEC2" | ||
242 | + "stvflx %1,%y0" | ||
243 | + [(set_attr "type" "vecstore")]) | ||
244 | + | ||
245 | +(define_insn "altivec_stvflxl" | ||
246 | + [(parallel | ||
247 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
248 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
249 | + (unspec [(const_int 0)] UNSPEC_STVFLXL)])] | ||
250 | + "TARGET_ALTIVEC2" | ||
251 | + "stvflxl %1,%y0" | ||
252 | + [(set_attr "type" "vecstore")]) | ||
253 | + | ||
254 | +(define_insn "altivec_stvfrx" | ||
255 | + [(parallel | ||
256 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
257 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
258 | + (unspec [(const_int 0)] UNSPEC_STVFRX)])] | ||
259 | + "TARGET_ALTIVEC2" | ||
260 | + "stvfrx %1,%y0" | ||
261 | + [(set_attr "type" "vecstore")]) | ||
262 | + | ||
263 | +(define_insn "altivec_stvfrxl" | ||
264 | + [(parallel | ||
265 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
266 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
267 | + (unspec [(const_int 0)] UNSPEC_STVFRXL)])] | ||
268 | + "TARGET_ALTIVEC2" | ||
269 | + "stvfrxl %1,%y0" | ||
270 | + [(set_attr "type" "vecstore")]) | ||
271 | + | ||
272 | +(define_insn "altivec_lvswx" | ||
273 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
274 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
275 | + UNSPEC_LVSWX))] | ||
276 | + "TARGET_ALTIVEC2" | ||
277 | + "lvswx %0,%y1" | ||
278 | + [(set_attr "type" "vecload")]) | ||
279 | + | ||
280 | +(define_insn "altivec_lvswxl" | ||
281 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
282 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
283 | + UNSPEC_LVSWXL))] | ||
284 | + "TARGET_ALTIVEC2" | ||
285 | + "lvswxl %0,%y1" | ||
286 | + [(set_attr "type" "vecload")]) | ||
287 | + | ||
288 | +(define_insn "altivec_lvsm" | ||
289 | + [(set (match_operand:V16QI 0 "register_operand" "=v") | ||
290 | + (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] | ||
291 | + UNSPEC_LVSM))] | ||
292 | + "TARGET_ALTIVEC2" | ||
293 | + "lvsm %0,%y1" | ||
294 | + [(set_attr "type" "vecload")]) | ||
295 | + | ||
296 | +(define_insn "altivec_stvswx" | ||
297 | + [(parallel | ||
298 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
299 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
300 | + (unspec [(const_int 0)] UNSPEC_STVSWX)])] | ||
301 | + "TARGET_ALTIVEC2" | ||
302 | + "stvswx %1,%y0" | ||
303 | + [(set_attr "type" "vecstore")]) | ||
304 | + | ||
305 | +(define_insn "altivec_stvswxl" | ||
306 | + [(parallel | ||
307 | + [(set (match_operand:V16QI 0 "memory_operand" "=Z") | ||
308 | + (match_operand:V16QI 1 "register_operand" "v")) | ||
309 | + (unspec [(const_int 0)] UNSPEC_STVSWXL)])] | ||
310 | + "TARGET_ALTIVEC2" | ||
311 | + "stvswxl %1,%y0" | ||
312 | + [(set_attr "type" "vecstore")]) | ||
313 | + | ||
314 | (define_expand "vec_extract_evenv4si" | ||
315 | [(set (match_operand:V4SI 0 "register_operand" "") | ||
316 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "") | ||
317 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/e5500.md gcc-4.6.2/gcc/config/rs6000/e5500.md | ||
318 | --- gcc-4.6.2-orig/gcc/config/rs6000/e5500.md 1969-12-31 18:00:00.000000000 -0600 | ||
319 | +++ gcc-4.6.2/gcc/config/rs6000/e5500.md 2012-03-06 12:16:07.590039001 -0600 | ||
320 | @@ -0,0 +1,176 @@ | ||
321 | +;; Pipeline description for Freescale PowerPC e5500 core. | ||
322 | +;; Copyright (C) 2011 Free Software Foundation, Inc. | ||
323 | +;; Contributed by Edmar Wienskoski (edmar@freescale.com) | ||
324 | +;; | ||
325 | +;; This file is part of GCC. | ||
326 | +;; | ||
327 | +;; GCC is free software; you can redistribute it and/or modify it | ||
328 | +;; under the terms of the GNU General Public License as published | ||
329 | +;; by the Free Software Foundation; either version 3, or (at your | ||
330 | +;; option) any later version. | ||
331 | +;; | ||
332 | +;; GCC is distributed in the hope that it will be useful, but WITHOUT | ||
333 | +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
334 | +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | ||
335 | +;; License for more details. | ||
336 | +;; | ||
337 | +;; You should have received a copy of the GNU General Public License | ||
338 | +;; along with GCC; see the file COPYING3. If not see | ||
339 | +;; <http://www.gnu.org/licenses/>. | ||
340 | +;; | ||
341 | +;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU | ||
342 | +;; Max issue 3 insns/clock cycle (includes 1 branch) | ||
343 | + | ||
344 | +(define_automaton "e5500_most,e5500_long") | ||
345 | +(define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most") | ||
346 | + | ||
347 | +;; SFX. | ||
348 | +(define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most") | ||
349 | + | ||
350 | +;; CFX. | ||
351 | +(define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most") | ||
352 | + | ||
353 | +;; Non-pipelined division. | ||
354 | +(define_cpu_unit "e5500_cfx_div" "e5500_long") | ||
355 | + | ||
356 | +;; LSU. | ||
357 | +(define_cpu_unit "e5500_lsu" "e5500_most") | ||
358 | + | ||
359 | +;; FPU. | ||
360 | +(define_cpu_unit "e5500_fpu" "e5500_long") | ||
361 | + | ||
362 | +;; BU. | ||
363 | +(define_cpu_unit "e5500_bu" "e5500_most") | ||
364 | + | ||
365 | +;; The following units are used to make the automata deterministic. | ||
366 | +(define_cpu_unit "present_e5500_decode_0" "e5500_most") | ||
367 | +(define_cpu_unit "present_e5500_sfx_0" "e5500_most") | ||
368 | +(presence_set "present_e5500_decode_0" "e5500_decode_0") | ||
369 | +(presence_set "present_e5500_sfx_0" "e5500_sfx_0") | ||
370 | + | ||
371 | +;; Some useful abbreviations. | ||
372 | +(define_reservation "e5500_decode" | ||
373 | + "e5500_decode_0|e5500_decode_1+present_e5500_decode_0") | ||
374 | +(define_reservation "e5500_sfx" | ||
375 | + "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0") | ||
376 | + | ||
377 | +;; SFX. | ||
378 | +(define_insn_reservation "e5500_sfx" 1 | ||
379 | + (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\ | ||
380 | + shift,cntlz,exts") | ||
381 | + (eq_attr "cpu" "ppce5500")) | ||
382 | + "e5500_decode,e5500_sfx") | ||
383 | + | ||
384 | +(define_insn_reservation "e5500_sfx2" 2 | ||
385 | + (and (eq_attr "type" "cmp,compare,fast_compare,trap") | ||
386 | + (eq_attr "cpu" "ppce5500")) | ||
387 | + "e5500_decode,e5500_sfx") | ||
388 | + | ||
389 | +(define_insn_reservation "e5500_delayed" 2 | ||
390 | + (and (eq_attr "type" "var_shift_rotate,var_delayed_compare,popcnt") | ||
391 | + (eq_attr "cpu" "ppce5500")) | ||
392 | + "e5500_decode,e5500_sfx*2") | ||
393 | + | ||
394 | +(define_insn_reservation "e5500_two" 2 | ||
395 | + (and (eq_attr "type" "two") | ||
396 | + (eq_attr "cpu" "ppce5500")) | ||
397 | + "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx") | ||
398 | + | ||
399 | +(define_insn_reservation "e5500_three" 3 | ||
400 | + (and (eq_attr "type" "three") | ||
401 | + (eq_attr "cpu" "ppce5500")) | ||
402 | + "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx") | ||
403 | + | ||
404 | +;; SFX - Mfcr. | ||
405 | +(define_insn_reservation "e5500_mfcr" 4 | ||
406 | + (and (eq_attr "type" "mfcr") | ||
407 | + (eq_attr "cpu" "ppce5500")) | ||
408 | + "e5500_decode,e5500_sfx_0*4") | ||
409 | + | ||
410 | +;; SFX - Mtcrf. | ||
411 | +(define_insn_reservation "e5500_mtcrf" 1 | ||
412 | + (and (eq_attr "type" "mtcr") | ||
413 | + (eq_attr "cpu" "ppce5500")) | ||
414 | + "e5500_decode,e5500_sfx_0") | ||
415 | + | ||
416 | +;; SFX - Mtjmpr. | ||
417 | +(define_insn_reservation "e5500_mtjmpr" 1 | ||
418 | + (and (eq_attr "type" "mtjmpr,mfjmpr") | ||
419 | + (eq_attr "cpu" "ppce5500")) | ||
420 | + "e5500_decode,e5500_sfx") | ||
421 | + | ||
422 | +;; CFX - Multiply. | ||
423 | +(define_insn_reservation "e5500_multiply" 4 | ||
424 | + (and (eq_attr "type" "imul") | ||
425 | + (eq_attr "cpu" "ppce5500")) | ||
426 | + "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1") | ||
427 | + | ||
428 | +(define_insn_reservation "e5500_multiply_i" 5 | ||
429 | + (and (eq_attr "type" "imul2,imul3,imul_compare") | ||
430 | + (eq_attr "cpu" "ppce5500")) | ||
431 | + "e5500_decode,e5500_cfx_stage0,\ | ||
432 | + e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1") | ||
433 | + | ||
434 | +;; CFX - Divide. | ||
435 | +(define_insn_reservation "e5500_divide" 16 | ||
436 | + (and (eq_attr "type" "idiv") | ||
437 | + (eq_attr "cpu" "ppce5500")) | ||
438 | + "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\ | ||
439 | + e5500_cfx_div*15") | ||
440 | + | ||
441 | +(define_insn_reservation "e5500_divide_d" 26 | ||
442 | + (and (eq_attr "type" "ldiv") | ||
443 | + (eq_attr "cpu" "ppce5500")) | ||
444 | + "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\ | ||
445 | + e5500_cfx_div*25") | ||
446 | + | ||
447 | +;; LSU - Loads. | ||
448 | +(define_insn_reservation "e5500_load" 3 | ||
449 | + (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ | ||
450 | + load_l,sync") | ||
451 | + (eq_attr "cpu" "ppce5500")) | ||
452 | + "e5500_decode,e5500_lsu") | ||
453 | + | ||
454 | +(define_insn_reservation "e5500_fpload" 4 | ||
455 | + (and (eq_attr "type" "fpload,fpload_ux,fpload_u") | ||
456 | + (eq_attr "cpu" "ppce5500")) | ||
457 | + "e5500_decode,e5500_lsu") | ||
458 | + | ||
459 | +;; LSU - Stores. | ||
460 | +(define_insn_reservation "e5500_store" 3 | ||
461 | + (and (eq_attr "type" "store,store_ux,store_u,store_c") | ||
462 | + (eq_attr "cpu" "ppce5500")) | ||
463 | + "e5500_decode,e5500_lsu") | ||
464 | + | ||
465 | +(define_insn_reservation "e5500_fpstore" 3 | ||
466 | + (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") | ||
467 | + (eq_attr "cpu" "ppce5500")) | ||
468 | + "e5500_decode,e5500_lsu") | ||
469 | + | ||
470 | +;; FP. | ||
471 | +(define_insn_reservation "e5500_float" 7 | ||
472 | + (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul") | ||
473 | + (eq_attr "cpu" "ppce5500")) | ||
474 | + "e5500_decode,e5500_fpu") | ||
475 | + | ||
476 | +(define_insn_reservation "e5500_sdiv" 20 | ||
477 | + (and (eq_attr "type" "sdiv") | ||
478 | + (eq_attr "cpu" "ppce5500")) | ||
479 | + "e5500_decode,e5500_fpu*20") | ||
480 | + | ||
481 | +(define_insn_reservation "e5500_ddiv" 35 | ||
482 | + (and (eq_attr "type" "ddiv") | ||
483 | + (eq_attr "cpu" "ppce5500")) | ||
484 | + "e5500_decode,e5500_fpu*35") | ||
485 | + | ||
486 | +;; BU. | ||
487 | +(define_insn_reservation "e5500_branch" 1 | ||
488 | + (and (eq_attr "type" "jmpreg,branch,isync") | ||
489 | + (eq_attr "cpu" "ppce5500")) | ||
490 | + "e5500_decode,e5500_bu") | ||
491 | + | ||
492 | +;; BU - CR logical. | ||
493 | +(define_insn_reservation "e5500_cr_logical" 1 | ||
494 | + (and (eq_attr "type" "cr_logical,delayed_cr") | ||
495 | + (eq_attr "cpu" "ppce5500")) | ||
496 | + "e5500_decode,e5500_bu") | ||
497 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/e6500.md gcc-4.6.2/gcc/config/rs6000/e6500.md | ||
498 | --- gcc-4.6.2-orig/gcc/config/rs6000/e6500.md 1969-12-31 18:00:00.000000000 -0600 | ||
499 | +++ gcc-4.6.2/gcc/config/rs6000/e6500.md 2012-03-06 12:16:25.573039002 -0600 | ||
500 | @@ -0,0 +1,213 @@ | ||
501 | +;; Pipeline description for Freescale PowerPC e6500 core. | ||
502 | +;; Copyright (C) 2011 Free Software Foundation, Inc. | ||
503 | +;; Contributed by Edmar Wienskoski (edmar@freescale.com) | ||
504 | +;; | ||
505 | +;; This file is part of GCC. | ||
506 | +;; | ||
507 | +;; GCC is free software; you can redistribute it and/or modify it | ||
508 | +;; under the terms of the GNU General Public License as published | ||
509 | +;; by the Free Software Foundation; either version 3, or (at your | ||
510 | +;; option) any later version. | ||
511 | +;; | ||
512 | +;; GCC is distributed in the hope that it will be useful, but WITHOUT | ||
513 | +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
514 | +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | ||
515 | +;; License for more details. | ||
516 | +;; | ||
517 | +;; You should have received a copy of the GNU General Public License | ||
518 | +;; along with GCC; see the file COPYING3. If not see | ||
519 | +;; <http://www.gnu.org/licenses/>. | ||
520 | +;; | ||
521 | +;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM | ||
522 | +;; Max issue 3 insns/clock cycle (includes 1 branch) | ||
523 | + | ||
524 | +(define_automaton "e6500_most,e6500_long,e6500_vec") | ||
525 | +(define_cpu_unit "e6500_decode_0,e6500_decode_1" "e6500_most") | ||
526 | + | ||
527 | +;; SFX. | ||
528 | +(define_cpu_unit "e6500_sfx_0,e6500_sfx_1" "e6500_most") | ||
529 | + | ||
530 | +;; CFX. | ||
531 | +(define_cpu_unit "e6500_cfx_stage0,e6500_cfx_stage1" "e6500_most") | ||
532 | + | ||
533 | +;; Non-pipelined division. | ||
534 | +(define_cpu_unit "e6500_cfx_div" "e6500_long") | ||
535 | + | ||
536 | +;; LSU. | ||
537 | +(define_cpu_unit "e6500_lsu" "e6500_most") | ||
538 | + | ||
539 | +;; FPU. | ||
540 | +(define_cpu_unit "e6500_fpu" "e6500_long") | ||
541 | + | ||
542 | +;; BU. | ||
543 | +(define_cpu_unit "e6500_bu" "e6500_most") | ||
544 | + | ||
545 | +;; Altivec unit | ||
546 | +(define_cpu_unit "e6500_vec,e6500_vecperm" "e6500_vec") | ||
547 | + | ||
548 | +;; The following units are used to make the automata deterministic. | ||
549 | +(define_cpu_unit "present_e6500_decode_0" "e6500_most") | ||
550 | +(define_cpu_unit "present_e6500_sfx_0" "e6500_most") | ||
551 | +(presence_set "present_e6500_decode_0" "e6500_decode_0") | ||
552 | +(presence_set "present_e6500_sfx_0" "e6500_sfx_0") | ||
553 | + | ||
554 | +;; Some useful abbreviations. | ||
555 | +(define_reservation "e6500_decode" | ||
556 | + "e6500_decode_0|e6500_decode_1+present_e6500_decode_0") | ||
557 | +(define_reservation "e6500_sfx" | ||
558 | + "e6500_sfx_0|e6500_sfx_1+present_e6500_sfx_0") | ||
559 | + | ||
560 | +;; SFX. | ||
561 | +(define_insn_reservation "e6500_sfx" 1 | ||
562 | + (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\ | ||
563 | + shift,cntlz,exts") | ||
564 | + (eq_attr "cpu" "ppce6500")) | ||
565 | + "e6500_decode,e6500_sfx") | ||
566 | + | ||
567 | +(define_insn_reservation "e6500_sfx2" 2 | ||
568 | + (and (eq_attr "type" "cmp,compare,fast_compare,trap") | ||
569 | + (eq_attr "cpu" "ppce6500")) | ||
570 | + "e6500_decode,e6500_sfx") | ||
571 | + | ||
572 | +(define_insn_reservation "e6500_delayed" 2 | ||
573 | + (and (eq_attr "type" "var_shift_rotate,var_delayed_compare,popcnt") | ||
574 | + (eq_attr "cpu" "ppce6500")) | ||
575 | + "e6500_decode,e6500_sfx*2") | ||
576 | + | ||
577 | +(define_insn_reservation "e6500_two" 2 | ||
578 | + (and (eq_attr "type" "two") | ||
579 | + (eq_attr "cpu" "ppce6500")) | ||
580 | + "e6500_decode,e6500_decode+e6500_sfx,e6500_sfx") | ||
581 | + | ||
582 | +(define_insn_reservation "e6500_three" 3 | ||
583 | + (and (eq_attr "type" "three") | ||
584 | + (eq_attr "cpu" "ppce6500")) | ||
585 | + "e6500_decode,(e6500_decode+e6500_sfx)*2,e6500_sfx") | ||
586 | + | ||
587 | +;; SFX - Mfcr. | ||
588 | +(define_insn_reservation "e6500_mfcr" 4 | ||
589 | + (and (eq_attr "type" "mfcr") | ||
590 | + (eq_attr "cpu" "ppce6500")) | ||
591 | + "e6500_decode,e6500_sfx_0*4") | ||
592 | + | ||
593 | +;; SFX - Mtcrf. | ||
594 | +(define_insn_reservation "e6500_mtcrf" 1 | ||
595 | + (and (eq_attr "type" "mtcr") | ||
596 | + (eq_attr "cpu" "ppce6500")) | ||
597 | + "e6500_decode,e6500_sfx_0") | ||
598 | + | ||
599 | +;; SFX - Mtjmpr. | ||
600 | +(define_insn_reservation "e6500_mtjmpr" 1 | ||
601 | + (and (eq_attr "type" "mtjmpr,mfjmpr") | ||
602 | + (eq_attr "cpu" "ppce6500")) | ||
603 | + "e6500_decode,e6500_sfx") | ||
604 | + | ||
605 | +;; CFX - Multiply. | ||
606 | +(define_insn_reservation "e6500_multiply" 4 | ||
607 | + (and (eq_attr "type" "imul") | ||
608 | + (eq_attr "cpu" "ppce6500")) | ||
609 | + "e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1") | ||
610 | + | ||
611 | +(define_insn_reservation "e6500_multiply_i" 5 | ||
612 | + (and (eq_attr "type" "imul2,imul3,imul_compare") | ||
613 | + (eq_attr "cpu" "ppce6500")) | ||
614 | + "e6500_decode,e6500_cfx_stage0,\ | ||
615 | + e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1") | ||
616 | + | ||
617 | +;; CFX - Divide. | ||
618 | +(define_insn_reservation "e6500_divide" 16 | ||
619 | + (and (eq_attr "type" "idiv") | ||
620 | + (eq_attr "cpu" "ppce6500")) | ||
621 | + "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\ | ||
622 | + e6500_cfx_div*15") | ||
623 | + | ||
624 | +(define_insn_reservation "e6500_divide_d" 26 | ||
625 | + (and (eq_attr "type" "ldiv") | ||
626 | + (eq_attr "cpu" "ppce6500")) | ||
627 | + "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\ | ||
628 | + e6500_cfx_div*25") | ||
629 | + | ||
630 | +;; LSU - Loads. | ||
631 | +(define_insn_reservation "e6500_load" 3 | ||
632 | + (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ | ||
633 | + load_l,sync") | ||
634 | + (eq_attr "cpu" "ppce6500")) | ||
635 | + "e6500_decode,e6500_lsu") | ||
636 | + | ||
637 | +(define_insn_reservation "e6500_fpload" 4 | ||
638 | + (and (eq_attr "type" "fpload,fpload_ux,fpload_u") | ||
639 | + (eq_attr "cpu" "ppce6500")) | ||
640 | + "e6500_decode,e6500_lsu") | ||
641 | + | ||
642 | +(define_insn_reservation "e6500_vecload" 4 | ||
643 | + (and (eq_attr "type" "vecload") | ||
644 | + (eq_attr "cpu" "ppce6500")) | ||
645 | + "e6500_decode,e6500_lsu") | ||
646 | + | ||
647 | +;; LSU - Stores. | ||
648 | +(define_insn_reservation "e6500_store" 3 | ||
649 | + (and (eq_attr "type" "store,store_ux,store_u,store_c") | ||
650 | + (eq_attr "cpu" "ppce6500")) | ||
651 | + "e6500_decode,e6500_lsu") | ||
652 | + | ||
653 | +(define_insn_reservation "e6500_fpstore" 3 | ||
654 | + (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") | ||
655 | + (eq_attr "cpu" "ppce6500")) | ||
656 | + "e6500_decode,e6500_lsu") | ||
657 | + | ||
658 | +(define_insn_reservation "e6500_vecstore" 4 | ||
659 | + (and (eq_attr "type" "vecstore") | ||
660 | + (eq_attr "cpu" "ppce6500")) | ||
661 | + "e6500_decode,e6500_lsu") | ||
662 | + | ||
663 | +;; FP. | ||
664 | +(define_insn_reservation "e6500_float" 7 | ||
665 | + (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul") | ||
666 | + (eq_attr "cpu" "ppce6500")) | ||
667 | + "e6500_decode,e6500_fpu") | ||
668 | + | ||
669 | +(define_insn_reservation "e6500_sdiv" 20 | ||
670 | + (and (eq_attr "type" "sdiv") | ||
671 | + (eq_attr "cpu" "ppce6500")) | ||
672 | + "e6500_decode,e6500_fpu*20") | ||
673 | + | ||
674 | +(define_insn_reservation "e6500_ddiv" 35 | ||
675 | + (and (eq_attr "type" "ddiv") | ||
676 | + (eq_attr "cpu" "ppce6500")) | ||
677 | + "e6500_decode,e6500_fpu*35") | ||
678 | + | ||
679 | +;; BU. | ||
680 | +(define_insn_reservation "e6500_branch" 1 | ||
681 | + (and (eq_attr "type" "jmpreg,branch,isync") | ||
682 | + (eq_attr "cpu" "ppce6500")) | ||
683 | + "e6500_decode,e6500_bu") | ||
684 | + | ||
685 | +;; BU - CR logical. | ||
686 | +(define_insn_reservation "e6500_cr_logical" 1 | ||
687 | + (and (eq_attr "type" "cr_logical,delayed_cr") | ||
688 | + (eq_attr "cpu" "ppce6500")) | ||
689 | + "e6500_decode,e6500_bu") | ||
690 | + | ||
691 | +;; VSFX. | ||
692 | +(define_insn_reservation "e6500_vecsimple" 1 | ||
693 | + (and (eq_attr "type" "vecsimple,veccmp") | ||
694 | + (eq_attr "cpu" "ppce6500")) | ||
695 | + "e6500_decode,e6500_vec") | ||
696 | + | ||
697 | +;; VCFX. | ||
698 | +(define_insn_reservation "e6500_veccomplex" 4 | ||
699 | + (and (eq_attr "type" "veccomplex") | ||
700 | + (eq_attr "cpu" "ppce6500")) | ||
701 | + "e6500_decode,e6500_vec") | ||
702 | + | ||
703 | +;; VFPU. | ||
704 | +(define_insn_reservation "e6500_vecfloat" 6 | ||
705 | + (and (eq_attr "type" "vecfloat") | ||
706 | + (eq_attr "cpu" "ppce6500")) | ||
707 | + "e6500_decode,e6500_vec") | ||
708 | + | ||
709 | +;; VPERM. | ||
710 | +(define_insn_reservation "e6500_vecperm" 2 | ||
711 | + (and (eq_attr "type" "vecperm") | ||
712 | + (eq_attr "cpu" "ppce6500")) | ||
713 | + "e6500_decode,e6500_vecperm") | ||
714 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000-builtin.def gcc-4.6.2/gcc/config/rs6000/rs6000-builtin.def | ||
715 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000-builtin.def 2011-02-21 15:38:21.000000000 -0600 | ||
716 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000-builtin.def 2012-03-06 12:37:40.248039025 -0600 | ||
717 | @@ -224,6 +224,9 @@ | ||
718 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEBX, RS6000_BTC_MEM) | ||
719 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEHX, RS6000_BTC_MEM) | ||
720 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEWX, RS6000_BTC_MEM) | ||
721 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEXBX, RS6000_BTC_MEM) | ||
722 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEXHX, RS6000_BTC_MEM) | ||
723 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEXWX, RS6000_BTC_MEM) | ||
724 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVXL, RS6000_BTC_MEM) | ||
725 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVX, RS6000_BTC_MEM) | ||
726 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVX, RS6000_BTC_MEM) | ||
727 | @@ -231,14 +234,30 @@ | ||
728 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVLXL, RS6000_BTC_MEM) | ||
729 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVRX, RS6000_BTC_MEM) | ||
730 | RS6000_BUILTIN(ALTIVEC_BUILTIN_LVRXL, RS6000_BTC_MEM) | ||
731 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVTLX, RS6000_BTC_MEM) | ||
732 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVTLXL, RS6000_BTC_MEM) | ||
733 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVTRX, RS6000_BTC_MEM) | ||
734 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVTRXL, RS6000_BTC_MEM) | ||
735 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSWX, RS6000_BTC_MEM) | ||
736 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSWXL, RS6000_BTC_MEM) | ||
737 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSM, RS6000_BTC_MEM) | ||
738 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEBX, RS6000_BTC_MEM) | ||
739 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEHX, RS6000_BTC_MEM) | ||
740 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEWX, RS6000_BTC_MEM) | ||
741 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEXBX, RS6000_BTC_MEM) | ||
742 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEXHX, RS6000_BTC_MEM) | ||
743 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEXWX, RS6000_BTC_MEM) | ||
744 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVXL, RS6000_BTC_MEM) | ||
745 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVLX, RS6000_BTC_MEM) | ||
746 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVLXL, RS6000_BTC_MEM) | ||
747 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVRX, RS6000_BTC_MEM) | ||
748 | RS6000_BUILTIN(ALTIVEC_BUILTIN_STVRXL, RS6000_BTC_MEM) | ||
749 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVFLX, RS6000_BTC_MEM) | ||
750 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVFLXL, RS6000_BTC_MEM) | ||
751 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVFRX, RS6000_BTC_MEM) | ||
752 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVFRXL, RS6000_BTC_MEM) | ||
753 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVSWX, RS6000_BTC_MEM) | ||
754 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVSWXL, RS6000_BTC_MEM) | ||
755 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPBFP_P, RS6000_BTC_FP_PURE) | ||
756 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQFP_P, RS6000_BTC_FP_PURE) | ||
757 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUB_P, RS6000_BTC_CONST) | ||
758 | @@ -275,6 +294,9 @@ | ||
759 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V4SF, RS6000_BTC_CONST) | ||
760 | RS6000_BUILTIN(ALTIVEC_BUILTIN_COPYSIGN_V4SF, RS6000_BTC_CONST) | ||
761 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VRECIPFP, RS6000_BTC_FP_PURE) | ||
762 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSDUB, RS6000_BTC_CONST) | ||
763 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSDUH, RS6000_BTC_CONST) | ||
764 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSDUW, RS6000_BTC_CONST) | ||
765 | |||
766 | /* Altivec overloaded builtins. */ | ||
767 | /* For now, don't set the classification for overloaded functions. | ||
768 | @@ -286,6 +308,7 @@ | ||
769 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGT_P, RS6000_BTC_MISC) | ||
770 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGE_P, RS6000_BTC_MISC) | ||
771 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABS, RS6000_BTC_MISC) | ||
772 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABSD, RS6000_BTC_MISC) | ||
773 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABSS, RS6000_BTC_MISC) | ||
774 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ADD, RS6000_BTC_MISC) | ||
775 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ADDC, RS6000_BTC_MISC) | ||
776 | @@ -321,10 +344,20 @@ | ||
777 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEBX, RS6000_BTC_MISC) | ||
778 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEHX, RS6000_BTC_MISC) | ||
779 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEWX, RS6000_BTC_MISC) | ||
780 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEXBX, RS6000_BTC_MISC) | ||
781 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEXHX, RS6000_BTC_MISC) | ||
782 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEXWX, RS6000_BTC_MISC) | ||
783 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVLX, RS6000_BTC_MISC) | ||
784 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVLXL, RS6000_BTC_MISC) | ||
785 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVRX, RS6000_BTC_MISC) | ||
786 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVRXL, RS6000_BTC_MISC) | ||
787 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVTLX, RS6000_BTC_MISC) | ||
788 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVTLXL, RS6000_BTC_MISC) | ||
789 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVTRX, RS6000_BTC_MISC) | ||
790 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVTRXL, RS6000_BTC_MISC) | ||
791 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSWX, RS6000_BTC_MISC) | ||
792 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSWXL, RS6000_BTC_MISC) | ||
793 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSM, RS6000_BTC_MISC) | ||
794 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSL, RS6000_BTC_MISC) | ||
795 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSR, RS6000_BTC_MISC) | ||
796 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MADD, RS6000_BTC_MISC) | ||
797 | @@ -389,10 +422,19 @@ | ||
798 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEBX, RS6000_BTC_MISC) | ||
799 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEHX, RS6000_BTC_MISC) | ||
800 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEWX, RS6000_BTC_MISC) | ||
801 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEXBX, RS6000_BTC_MISC) | ||
802 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEXHX, RS6000_BTC_MISC) | ||
803 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEXWX, RS6000_BTC_MISC) | ||
804 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVLX, RS6000_BTC_MISC) | ||
805 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVLXL, RS6000_BTC_MISC) | ||
806 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVRX, RS6000_BTC_MISC) | ||
807 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVRXL, RS6000_BTC_MISC) | ||
808 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVFLX, RS6000_BTC_MISC) | ||
809 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVFLXL, RS6000_BTC_MISC) | ||
810 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVFRX, RS6000_BTC_MISC) | ||
811 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVFRXL, RS6000_BTC_MISC) | ||
812 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVSWX, RS6000_BTC_MISC) | ||
813 | +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVSWXL, RS6000_BTC_MISC) | ||
814 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUB, RS6000_BTC_MISC) | ||
815 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUBC, RS6000_BTC_MISC) | ||
816 | RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUBS, RS6000_BTC_MISC) | ||
817 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000.c gcc-4.6.2/gcc/config/rs6000/rs6000.c | ||
818 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000.c 2011-09-18 17:01:56.000000000 -0500 | ||
819 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000.c 2012-03-06 12:44:04.689039002 -0600 | ||
820 | @@ -779,6 +779,44 @@ | ||
821 | 1, /* prefetch streams /*/ | ||
822 | }; | ||
823 | |||
824 | +/* Instruction costs on PPCE5500 processors. */ | ||
825 | +static const | ||
826 | +struct processor_costs ppce5500_cost = { | ||
827 | + COSTS_N_INSNS (5), /* mulsi */ | ||
828 | + COSTS_N_INSNS (5), /* mulsi_const */ | ||
829 | + COSTS_N_INSNS (4), /* mulsi_const9 */ | ||
830 | + COSTS_N_INSNS (5), /* muldi */ | ||
831 | + COSTS_N_INSNS (14), /* divsi */ | ||
832 | + COSTS_N_INSNS (14), /* divdi */ | ||
833 | + COSTS_N_INSNS (7), /* fp */ | ||
834 | + COSTS_N_INSNS (10), /* dmul */ | ||
835 | + COSTS_N_INSNS (36), /* sdiv */ | ||
836 | + COSTS_N_INSNS (66), /* ddiv */ | ||
837 | + 64, /* cache line size */ | ||
838 | + 32, /* l1 cache */ | ||
839 | + 128, /* l2 cache */ | ||
840 | + 1, /* prefetch streams /*/ | ||
841 | +}; | ||
842 | + | ||
843 | +/* Instruction costs on PPCE6500 processors. */ | ||
844 | +static const | ||
845 | +struct processor_costs ppce6500_cost = { | ||
846 | + COSTS_N_INSNS (5), /* mulsi */ | ||
847 | + COSTS_N_INSNS (5), /* mulsi_const */ | ||
848 | + COSTS_N_INSNS (4), /* mulsi_const9 */ | ||
849 | + COSTS_N_INSNS (5), /* muldi */ | ||
850 | + COSTS_N_INSNS (14), /* divsi */ | ||
851 | + COSTS_N_INSNS (14), /* divdi */ | ||
852 | + COSTS_N_INSNS (7), /* fp */ | ||
853 | + COSTS_N_INSNS (10), /* dmul */ | ||
854 | + COSTS_N_INSNS (36), /* sdiv */ | ||
855 | + COSTS_N_INSNS (66), /* ddiv */ | ||
856 | + 64, /* cache line size */ | ||
857 | + 32, /* l1 cache */ | ||
858 | + 128, /* l2 cache */ | ||
859 | + 1, /* prefetch streams /*/ | ||
860 | +}; | ||
861 | + | ||
862 | /* Instruction costs on AppliedMicro Titan processors. */ | ||
863 | static const | ||
864 | struct processor_costs titan_cost = { | ||
865 | @@ -1690,7 +1728,7 @@ | ||
866 | | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW | ||
867 | | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP | ||
868 | | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE | ||
869 | - | MASK_RECIP_PRECISION) | ||
870 | + | MASK_RECIP_PRECISION | MASK_ALTIVEC2) | ||
871 | }; | ||
872 | |||
873 | /* Masks for instructions set at various powerpc ISAs. */ | ||
874 | @@ -1785,6 +1823,12 @@ | ||
875 | | MASK_ISEL}, | ||
876 | {"e500mc64", PROCESSOR_PPCE500MC64, POWERPC_BASE_MASK | MASK_POWERPC64 | ||
877 | | MASK_PPC_GFXOPT | MASK_ISEL}, | ||
878 | + {"e5500", PROCESSOR_PPCE5500, POWERPC_BASE_MASK | MASK_POWERPC64 | ||
879 | + | MASK_PPC_GFXOPT | MASK_ISEL | MASK_CMPB | MASK_POPCNTB | ||
880 | + | MASK_POPCNTD}, | ||
881 | + {"e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64 | ||
882 | + | MASK_MFCRF | MASK_ISEL | MASK_CMPB | MASK_POPCNTB | MASK_POPCNTD | ||
883 | + | MASK_ALTIVEC2}, | ||
884 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | ||
885 | {"970", PROCESSOR_POWER4, | ||
886 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, | ||
887 | @@ -2742,13 +2786,19 @@ | ||
888 | : PROCESSOR_DEFAULT)); | ||
889 | |||
890 | if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3 | ||
891 | - || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64) | ||
892 | + || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64 | ||
893 | + || rs6000_cpu == PROCESSOR_PPCE5500) | ||
894 | { | ||
895 | if (TARGET_ALTIVEC) | ||
896 | error ("AltiVec not supported in this target"); | ||
897 | if (TARGET_SPE) | ||
898 | error ("SPE not supported in this target"); | ||
899 | } | ||
900 | + if (rs6000_cpu == PROCESSOR_PPCE6500) | ||
901 | + { | ||
902 | + if (TARGET_SPE) | ||
903 | + error ("SPE not supported in this target"); | ||
904 | + } | ||
905 | |||
906 | /* Disable Cell microcode if we are optimizing for the Cell | ||
907 | and not optimizing for size. */ | ||
908 | @@ -2843,9 +2893,16 @@ | ||
909 | user's opinion, though. */ | ||
910 | if (rs6000_block_move_inline_limit == 0 | ||
911 | && (rs6000_cpu == PROCESSOR_PPCE500MC | ||
912 | - || rs6000_cpu == PROCESSOR_PPCE500MC64)) | ||
913 | + || rs6000_cpu == PROCESSOR_PPCE500MC64 | ||
914 | + || rs6000_cpu == PROCESSOR_PPCE5500 | ||
915 | + || rs6000_cpu == PROCESSOR_PPCE6500)) | ||
916 | rs6000_block_move_inline_limit = 128; | ||
917 | |||
918 | + /* Those machines does not have fsqrt instruction */ | ||
919 | + if (rs6000_cpu == PROCESSOR_PPCE5500 | ||
920 | + || rs6000_cpu == PROCESSOR_PPCE6500) | ||
921 | + target_flags &= ~MASK_PPC_GPOPT; | ||
922 | + | ||
923 | /* store_one_arg depends on expand_block_move to handle at least the | ||
924 | size of reg_parm_stack_space. */ | ||
925 | if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32)) | ||
926 | @@ -2977,7 +3034,9 @@ | ||
927 | #endif | ||
928 | |||
929 | if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC | ||
930 | - || rs6000_cpu == PROCESSOR_PPCE500MC64) | ||
931 | + || rs6000_cpu == PROCESSOR_PPCE500MC64 | ||
932 | + || rs6000_cpu == PROCESSOR_PPCE5500 | ||
933 | + || rs6000_cpu == PROCESSOR_PPCE6500) | ||
934 | { | ||
935 | /* The e500 and e500mc do not have string instructions, and we set | ||
936 | MASK_STRING above when optimizing for size. */ | ||
937 | @@ -3024,7 +3083,9 @@ | ||
938 | || rs6000_cpu == PROCESSOR_POWER6 | ||
939 | || rs6000_cpu == PROCESSOR_POWER7 | ||
940 | || rs6000_cpu == PROCESSOR_PPCE500MC | ||
941 | - || rs6000_cpu == PROCESSOR_PPCE500MC64); | ||
942 | + || rs6000_cpu == PROCESSOR_PPCE500MC64 | ||
943 | + || rs6000_cpu == PROCESSOR_PPCE5500 | ||
944 | + || rs6000_cpu == PROCESSOR_PPCE6500); | ||
945 | |||
946 | /* Allow debug switches to override the above settings. These are set to -1 | ||
947 | in rs6000.opt to indicate the user hasn't directly set the switch. */ | ||
948 | @@ -3246,6 +3307,14 @@ | ||
949 | rs6000_cost = &ppce500mc64_cost; | ||
950 | break; | ||
951 | |||
952 | + case PROCESSOR_PPCE5500: | ||
953 | + rs6000_cost = &ppce5500_cost; | ||
954 | + break; | ||
955 | + | ||
956 | + case PROCESSOR_PPCE6500: | ||
957 | + rs6000_cost = &ppce6500_cost; | ||
958 | + break; | ||
959 | + | ||
960 | case PROCESSOR_TITAN: | ||
961 | rs6000_cost = &titan_cost; | ||
962 | break; | ||
963 | @@ -10212,6 +10281,9 @@ | ||
964 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | ||
965 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | ||
966 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | ||
967 | + { MASK_ALTIVEC2, CODE_FOR_altivec_vabsdub, "__builtin_altivec_vabsdub", ALTIVEC_BUILTIN_ABSDUB }, | ||
968 | + { MASK_ALTIVEC2, CODE_FOR_altivec_vabsduh, "__builtin_altivec_vabsduh", ALTIVEC_BUILTIN_ABSDUH }, | ||
969 | + { MASK_ALTIVEC2, CODE_FOR_altivec_vabsduw, "__builtin_altivec_vabsduw", ALTIVEC_BUILTIN_ABSDUW }, | ||
970 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, | ||
971 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | ||
972 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | ||
973 | @@ -10372,6 +10444,7 @@ | ||
974 | { MASK_VSX, CODE_FOR_vec_interleave_highv2df, "__builtin_vsx_mergeh_2df", VSX_BUILTIN_VEC_MERGEH_V2DF }, | ||
975 | { MASK_VSX, CODE_FOR_vec_interleave_highv2di, "__builtin_vsx_mergeh_2di", VSX_BUILTIN_VEC_MERGEH_V2DI }, | ||
976 | |||
977 | + { MASK_ALTIVEC2, CODE_FOR_nothing, "__builtin_vec_absd", ALTIVEC_BUILTIN_VEC_ABSD }, | ||
978 | { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD }, | ||
979 | { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP }, | ||
980 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM }, | ||
981 | @@ -11803,6 +11876,12 @@ | ||
982 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp); | ||
983 | case ALTIVEC_BUILTIN_STVEWX: | ||
984 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp); | ||
985 | + case ALTIVEC_BUILTIN_STVEXBX: | ||
986 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvexbx, exp); | ||
987 | + case ALTIVEC_BUILTIN_STVEXHX: | ||
988 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvexhx, exp); | ||
989 | + case ALTIVEC_BUILTIN_STVEXWX: | ||
990 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvexwx, exp); | ||
991 | case ALTIVEC_BUILTIN_STVXL: | ||
992 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp); | ||
993 | |||
994 | @@ -11814,6 +11893,18 @@ | ||
995 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp); | ||
996 | case ALTIVEC_BUILTIN_STVRXL: | ||
997 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp); | ||
998 | + case ALTIVEC_BUILTIN_STVFLX: | ||
999 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvflx, exp); | ||
1000 | + case ALTIVEC_BUILTIN_STVFLXL: | ||
1001 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvflxl, exp); | ||
1002 | + case ALTIVEC_BUILTIN_STVFRX: | ||
1003 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvfrx, exp); | ||
1004 | + case ALTIVEC_BUILTIN_STVFRXL: | ||
1005 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvfrxl, exp); | ||
1006 | + case ALTIVEC_BUILTIN_STVSWX: | ||
1007 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvswx, exp); | ||
1008 | + case ALTIVEC_BUILTIN_STVSWXL: | ||
1009 | + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvswxl, exp); | ||
1010 | |||
1011 | case VSX_BUILTIN_STXVD2X_V2DF: | ||
1012 | return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp); | ||
1013 | @@ -11948,6 +12039,15 @@ | ||
1014 | case ALTIVEC_BUILTIN_LVEWX: | ||
1015 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, | ||
1016 | exp, target, false); | ||
1017 | + case ALTIVEC_BUILTIN_LVEXBX: | ||
1018 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvexbx, | ||
1019 | + exp, target, false); | ||
1020 | + case ALTIVEC_BUILTIN_LVEXHX: | ||
1021 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvexhx, | ||
1022 | + exp, target, false); | ||
1023 | + case ALTIVEC_BUILTIN_LVEXWX: | ||
1024 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvexwx, | ||
1025 | + exp, target, false); | ||
1026 | case ALTIVEC_BUILTIN_LVXL: | ||
1027 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, | ||
1028 | exp, target, false); | ||
1029 | @@ -11966,6 +12066,27 @@ | ||
1030 | case ALTIVEC_BUILTIN_LVRXL: | ||
1031 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl, | ||
1032 | exp, target, true); | ||
1033 | + case ALTIVEC_BUILTIN_LVTLX: | ||
1034 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvtlx, | ||
1035 | + exp, target, true); | ||
1036 | + case ALTIVEC_BUILTIN_LVTLXL: | ||
1037 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvtlxl, | ||
1038 | + exp, target, true); | ||
1039 | + case ALTIVEC_BUILTIN_LVTRX: | ||
1040 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvtrx, | ||
1041 | + exp, target, true); | ||
1042 | + case ALTIVEC_BUILTIN_LVTRXL: | ||
1043 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvtrxl, | ||
1044 | + exp, target, true); | ||
1045 | + case ALTIVEC_BUILTIN_LVSWX: | ||
1046 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvswx, | ||
1047 | + exp, target, true); | ||
1048 | + case ALTIVEC_BUILTIN_LVSWXL: | ||
1049 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvswxl, | ||
1050 | + exp, target, true); | ||
1051 | + case ALTIVEC_BUILTIN_LVSM: | ||
1052 | + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsm, | ||
1053 | + exp, target, true); | ||
1054 | case VSX_BUILTIN_LXVD2X_V2DF: | ||
1055 | return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df, | ||
1056 | exp, target, false); | ||
1057 | @@ -13278,6 +13399,9 @@ | ||
1058 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); | ||
1059 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); | ||
1060 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); | ||
1061 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvexbx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEXBX); | ||
1062 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvexhx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEXHX); | ||
1063 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvexwx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEXWX); | ||
1064 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); | ||
1065 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); | ||
1066 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); | ||
1067 | @@ -13285,6 +13409,9 @@ | ||
1068 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); | ||
1069 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); | ||
1070 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); | ||
1071 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvexbx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEXBX); | ||
1072 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvexhx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEXHX); | ||
1073 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvexwx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEXWX); | ||
1074 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD); | ||
1075 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE); | ||
1076 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL); | ||
1077 | @@ -13293,12 +13420,18 @@ | ||
1078 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX); | ||
1079 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX); | ||
1080 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX); | ||
1081 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvexbx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEXBX); | ||
1082 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvexhx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEXHX); | ||
1083 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvexwx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEXWX); | ||
1084 | def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST); | ||
1085 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE); | ||
1086 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL); | ||
1087 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX); | ||
1088 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX); | ||
1089 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX); | ||
1090 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvexwx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEXWX); | ||
1091 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvexbx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEXBX); | ||
1092 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvexhx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEXHX); | ||
1093 | |||
1094 | def_builtin (MASK_VSX, "__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid, | ||
1095 | VSX_BUILTIN_LXVD2X_V2DF); | ||
1096 | @@ -13351,6 +13484,33 @@ | ||
1097 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX); | ||
1098 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL); | ||
1099 | } | ||
1100 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvtlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVTLX); | ||
1101 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvtlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVTLXL); | ||
1102 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvtrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVTRX); | ||
1103 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvtrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVTRXL); | ||
1104 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvtlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVTLX); | ||
1105 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvtlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVTLXL); | ||
1106 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvtrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVTRX); | ||
1107 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvtrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVTRXL); | ||
1108 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvflx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVFLX); | ||
1109 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvflxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVFLXL); | ||
1110 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvfrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVFRX); | ||
1111 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvfrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVFRXL); | ||
1112 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvflx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVFLX); | ||
1113 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvflxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVFLXL); | ||
1114 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvfrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVFRX); | ||
1115 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvfrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVFRXL); | ||
1116 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvswx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSWX); | ||
1117 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvswxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSWXL); | ||
1118 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvswx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSWX); | ||
1119 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvswxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSWXL); | ||
1120 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_lvsm", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSM); | ||
1121 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_lvsm", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSM); | ||
1122 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvswx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVSWX); | ||
1123 | + def_builtin (MASK_ALTIVEC2, "__builtin_altivec_stvswxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVSWXL); | ||
1124 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvswx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVSWX); | ||
1125 | + def_builtin (MASK_ALTIVEC2, "__builtin_vec_stvswxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVSWXL); | ||
1126 | + | ||
1127 | def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP); | ||
1128 | def_builtin (MASK_ALTIVEC, "__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS); | ||
1129 | def_builtin (MASK_ALTIVEC, "__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE); | ||
1130 | @@ -13668,6 +13828,9 @@ | ||
1131 | case ALTIVEC_BUILTIN_VMULEUH_UNS: | ||
1132 | case ALTIVEC_BUILTIN_VMULOUB_UNS: | ||
1133 | case ALTIVEC_BUILTIN_VMULOUH_UNS: | ||
1134 | + case ALTIVEC_BUILTIN_ABSDUB: | ||
1135 | + case ALTIVEC_BUILTIN_ABSDUH: | ||
1136 | + case ALTIVEC_BUILTIN_ABSDUW: | ||
1137 | h.uns_p[0] = 1; | ||
1138 | h.uns_p[1] = 1; | ||
1139 | h.uns_p[2] = 1; | ||
1140 | @@ -23250,6 +23413,7 @@ | ||
1141 | || rs6000_cpu_attr == CPU_PPC750 | ||
1142 | || rs6000_cpu_attr == CPU_PPC7400 | ||
1143 | || rs6000_cpu_attr == CPU_PPC7450 | ||
1144 | + || rs6000_cpu_attr == CPU_PPCE5500 | ||
1145 | || rs6000_cpu_attr == CPU_POWER4 | ||
1146 | || rs6000_cpu_attr == CPU_POWER5 | ||
1147 | || rs6000_cpu_attr == CPU_POWER7 | ||
1148 | @@ -23794,6 +23958,8 @@ | ||
1149 | case CPU_PPCE300C3: | ||
1150 | case CPU_PPCE500MC: | ||
1151 | case CPU_PPCE500MC64: | ||
1152 | + case CPU_PPCE5500: | ||
1153 | + case CPU_PPCE6500: | ||
1154 | case CPU_TITAN: | ||
1155 | return 2; | ||
1156 | case CPU_RIOS2: | ||
1157 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000-c.c gcc-4.6.2/gcc/config/rs6000/rs6000-c.c | ||
1158 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000-c.c 2011-02-02 23:42:19.000000000 -0600 | ||
1159 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000-c.c 2012-03-06 12:54:55.964038969 -0600 | ||
1160 | @@ -310,6 +310,8 @@ | ||
1161 | /* Enable context-sensitive macros. */ | ||
1162 | cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand; | ||
1163 | } | ||
1164 | + if (TARGET_ALTIVEC2) | ||
1165 | + builtin_define ("__ALTIVEC2__"); | ||
1166 | } | ||
1167 | if (rs6000_cpu == PROCESSOR_CELL) | ||
1168 | builtin_define ("__PPU__"); | ||
1169 | @@ -569,6 +571,24 @@ | ||
1170 | RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, | ||
1171 | |||
1172 | /* Binary AltiVec/VSX builtins. */ | ||
1173 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUB, | ||
1174 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, | ||
1175 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUB, | ||
1176 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, | ||
1177 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUB, | ||
1178 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, | ||
1179 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUH, | ||
1180 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, | ||
1181 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUH, | ||
1182 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, | ||
1183 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUH, | ||
1184 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, | ||
1185 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUW, | ||
1186 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, | ||
1187 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUW, | ||
1188 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, | ||
1189 | + { ALTIVEC_BUILTIN_VEC_ABSD, ALTIVEC_BUILTIN_ABSDUW, | ||
1190 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, | ||
1191 | { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, | ||
1192 | RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, | ||
1193 | { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, | ||
1194 | @@ -1084,6 +1104,24 @@ | ||
1195 | RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1196 | { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, | ||
1197 | RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1198 | + { ALTIVEC_BUILTIN_VEC_LVEXWX, ALTIVEC_BUILTIN_LVEXWX, | ||
1199 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1200 | + { ALTIVEC_BUILTIN_VEC_LVEXWX, ALTIVEC_BUILTIN_LVEXWX, | ||
1201 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1202 | + { ALTIVEC_BUILTIN_VEC_LVEXWX, ALTIVEC_BUILTIN_LVEXWX, | ||
1203 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1204 | + { ALTIVEC_BUILTIN_VEC_LVEXWX, ALTIVEC_BUILTIN_LVEXWX, | ||
1205 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, | ||
1206 | + { ALTIVEC_BUILTIN_VEC_LVEXWX, ALTIVEC_BUILTIN_LVEXWX, | ||
1207 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, | ||
1208 | + { ALTIVEC_BUILTIN_VEC_LVEXHX, ALTIVEC_BUILTIN_LVEXHX, | ||
1209 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1210 | + { ALTIVEC_BUILTIN_VEC_LVEXHX, ALTIVEC_BUILTIN_LVEXHX, | ||
1211 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1212 | + { ALTIVEC_BUILTIN_VEC_LVEXBX, ALTIVEC_BUILTIN_LVEXBX, | ||
1213 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1214 | + { ALTIVEC_BUILTIN_VEC_LVEXBX, ALTIVEC_BUILTIN_LVEXBX, | ||
1215 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1216 | { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, | ||
1217 | RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1218 | { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, | ||
1219 | @@ -1336,6 +1374,258 @@ | ||
1220 | RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1221 | { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, | ||
1222 | RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1223 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1224 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1225 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1226 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1227 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1228 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1229 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1230 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1231 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1232 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1233 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1234 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1235 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1236 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1237 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1238 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1239 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1240 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1241 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1242 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1243 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1244 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1245 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1246 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1247 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1248 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1249 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1250 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1251 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1252 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1253 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1254 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1255 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1256 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1257 | + { ALTIVEC_BUILTIN_VEC_LVTLX, ALTIVEC_BUILTIN_LVTLX, | ||
1258 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1259 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1260 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1261 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1262 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1263 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1264 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1265 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1266 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1267 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1268 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1269 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1270 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1271 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1272 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1273 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1274 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1275 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1276 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1277 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1278 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1279 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1280 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1281 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1282 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1283 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1284 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1285 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1286 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1287 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1288 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1289 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1290 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1291 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1292 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1293 | + { ALTIVEC_BUILTIN_VEC_LVTLXL, ALTIVEC_BUILTIN_LVTLXL, | ||
1294 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1295 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1296 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1297 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1298 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1299 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1300 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1301 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1302 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1303 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1304 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1305 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1306 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1307 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1308 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1309 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1310 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1311 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1312 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1313 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1314 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1315 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1316 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1317 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1318 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1319 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1320 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1321 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1322 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1323 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1324 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1325 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1326 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1327 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1328 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1329 | + { ALTIVEC_BUILTIN_VEC_LVTRX, ALTIVEC_BUILTIN_LVTRX, | ||
1330 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1331 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1332 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1333 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1334 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1335 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1336 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1337 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1338 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1339 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1340 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1341 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1342 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1343 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1344 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1345 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1346 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1347 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1348 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1349 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1350 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1351 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1352 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1353 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1354 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1355 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1356 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1357 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1358 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1359 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1360 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1361 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1362 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1363 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1364 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1365 | + { ALTIVEC_BUILTIN_VEC_LVTRXL, ALTIVEC_BUILTIN_LVTRXL, | ||
1366 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1367 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1368 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1369 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1370 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1371 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1372 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1373 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1374 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1375 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1376 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1377 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1378 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1379 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1380 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1381 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1382 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1383 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1384 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1385 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1386 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1387 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1388 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1389 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1390 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1391 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1392 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1393 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1394 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1395 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1396 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1397 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1398 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1399 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1400 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1401 | + { ALTIVEC_BUILTIN_VEC_LVSWX, ALTIVEC_BUILTIN_LVSWX, | ||
1402 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1403 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1404 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1405 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1406 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1407 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1408 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1409 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1410 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1411 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1412 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1413 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1414 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1415 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1416 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1417 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1418 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1419 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1420 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1421 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1422 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1423 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1424 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1425 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1426 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1427 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1428 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1429 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1430 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1431 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1432 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1433 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1434 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1435 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1436 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1437 | + { ALTIVEC_BUILTIN_VEC_LVSWXL, ALTIVEC_BUILTIN_LVSWXL, | ||
1438 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1439 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1440 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, | ||
1441 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1442 | + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, | ||
1443 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1444 | + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, | ||
1445 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1446 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, | ||
1447 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1448 | + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, | ||
1449 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1450 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, | ||
1451 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1452 | + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, | ||
1453 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1454 | + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, | ||
1455 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1456 | + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, | ||
1457 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1458 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, | ||
1459 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1460 | + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, | ||
1461 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1462 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, | ||
1463 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1464 | + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, | ||
1465 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1466 | + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, | ||
1467 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1468 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, | ||
1469 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1470 | + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, | ||
1471 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1472 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, | ||
1473 | + { ALTIVEC_BUILTIN_VEC_LVSM, ALTIVEC_BUILTIN_LVSM, | ||
1474 | + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, | ||
1475 | { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, | ||
1476 | RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, | ||
1477 | { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, | ||
1478 | @@ -2812,6 +3102,46 @@ | ||
1479 | RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1480 | { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, | ||
1481 | RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1482 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1483 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1484 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1485 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1486 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1487 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1488 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1489 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1490 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1491 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1492 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1493 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1494 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1495 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1496 | + { ALTIVEC_BUILTIN_VEC_STVEXWX, ALTIVEC_BUILTIN_STVEXWX, | ||
1497 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1498 | + { ALTIVEC_BUILTIN_VEC_STVEXHX, ALTIVEC_BUILTIN_STVEXHX, | ||
1499 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1500 | + { ALTIVEC_BUILTIN_VEC_STVEXHX, ALTIVEC_BUILTIN_STVEXHX, | ||
1501 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1502 | + { ALTIVEC_BUILTIN_VEC_STVEXHX, ALTIVEC_BUILTIN_STVEXHX, | ||
1503 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1504 | + { ALTIVEC_BUILTIN_VEC_STVEXHX, ALTIVEC_BUILTIN_STVEXHX, | ||
1505 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1506 | + { ALTIVEC_BUILTIN_VEC_STVEXHX, ALTIVEC_BUILTIN_STVEXHX, | ||
1507 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1508 | + { ALTIVEC_BUILTIN_VEC_STVEXHX, ALTIVEC_BUILTIN_STVEXHX, | ||
1509 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1510 | + { ALTIVEC_BUILTIN_VEC_STVEXBX, ALTIVEC_BUILTIN_STVEXBX, | ||
1511 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1512 | + { ALTIVEC_BUILTIN_VEC_STVEXBX, ALTIVEC_BUILTIN_STVEXBX, | ||
1513 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1514 | + { ALTIVEC_BUILTIN_VEC_STVEXBX, ALTIVEC_BUILTIN_STVEXBX, | ||
1515 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1516 | + { ALTIVEC_BUILTIN_VEC_STVEXBX, ALTIVEC_BUILTIN_STVEXBX, | ||
1517 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1518 | + { ALTIVEC_BUILTIN_VEC_STVEXBX, ALTIVEC_BUILTIN_STVEXBX, | ||
1519 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1520 | + { ALTIVEC_BUILTIN_VEC_STVEXBX, ALTIVEC_BUILTIN_STVEXBX, | ||
1521 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, | ||
1522 | { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, | ||
1523 | RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1524 | { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, | ||
1525 | @@ -3016,6 +3346,222 @@ | ||
1526 | RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1527 | { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, | ||
1528 | RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1529 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1530 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1531 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1532 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1533 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1534 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, | ||
1535 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1536 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, | ||
1537 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1538 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1539 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1540 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, | ||
1541 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1542 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1543 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1544 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, | ||
1545 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1546 | + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, | ||
1547 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1548 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, | ||
1549 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1550 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1551 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1552 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, | ||
1553 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1554 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1555 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1556 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, | ||
1557 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1558 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, | ||
1559 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1560 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1561 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1562 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1563 | + { ALTIVEC_BUILTIN_VEC_STVFLX, ALTIVEC_BUILTIN_STVFLX, | ||
1564 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1565 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1566 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1567 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1568 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1569 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1570 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, | ||
1571 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1572 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, | ||
1573 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1574 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1575 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1576 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, | ||
1577 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1578 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1579 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1580 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, | ||
1581 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1582 | + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, | ||
1583 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1584 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, | ||
1585 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1586 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1587 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1588 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, | ||
1589 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1590 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1591 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1592 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, | ||
1593 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1594 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, | ||
1595 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1596 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1597 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1598 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1599 | + { ALTIVEC_BUILTIN_VEC_STVFLXL, ALTIVEC_BUILTIN_STVFLXL, | ||
1600 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1601 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1602 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1603 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1604 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1605 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1606 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, | ||
1607 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1608 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, | ||
1609 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1610 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1611 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1612 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, | ||
1613 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1614 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1615 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1616 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, | ||
1617 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1618 | + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, | ||
1619 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1620 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, | ||
1621 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1622 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1623 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1624 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, | ||
1625 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1626 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1627 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1628 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, | ||
1629 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1630 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, | ||
1631 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1632 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1633 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1634 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1635 | + { ALTIVEC_BUILTIN_VEC_STVFRX, ALTIVEC_BUILTIN_STVFRX, | ||
1636 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1637 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1638 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1639 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1640 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1641 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1642 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, | ||
1643 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1644 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, | ||
1645 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1646 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1647 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1648 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, | ||
1649 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1650 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1651 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1652 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, | ||
1653 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1654 | + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, | ||
1655 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1656 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, | ||
1657 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1658 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1659 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1660 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, | ||
1661 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1662 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1663 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1664 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, | ||
1665 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1666 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, | ||
1667 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1668 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1669 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1670 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1671 | + { ALTIVEC_BUILTIN_VEC_STVFRXL, ALTIVEC_BUILTIN_STVFRXL, | ||
1672 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1673 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1674 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1675 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1676 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1677 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1678 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, | ||
1679 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1680 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, | ||
1681 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1682 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1683 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1684 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, | ||
1685 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1686 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1687 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1688 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, | ||
1689 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1690 | + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, | ||
1691 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1692 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, | ||
1693 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1694 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1695 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1696 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, | ||
1697 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1698 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1699 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1700 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, | ||
1701 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1702 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, | ||
1703 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1704 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1705 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1706 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1707 | + { ALTIVEC_BUILTIN_VEC_STVSWX, ALTIVEC_BUILTIN_STVSWX, | ||
1708 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1709 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1710 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, | ||
1711 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1712 | + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, | ||
1713 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1714 | + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, | ||
1715 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1716 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, | ||
1717 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1718 | + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, | ||
1719 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1720 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, | ||
1721 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1722 | + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, | ||
1723 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1724 | + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, | ||
1725 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1726 | + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, | ||
1727 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1728 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, | ||
1729 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1730 | + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, | ||
1731 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1732 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, | ||
1733 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1734 | + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, | ||
1735 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1736 | + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, | ||
1737 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1738 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, | ||
1739 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1740 | + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, | ||
1741 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1742 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, | ||
1743 | + { ALTIVEC_BUILTIN_VEC_STVSWXL, ALTIVEC_BUILTIN_STVSWXL, | ||
1744 | + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, | ||
1745 | { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, | ||
1746 | RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, | ||
1747 | { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, | ||
1748 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000.h gcc-4.6.2/gcc/config/rs6000/rs6000.h | ||
1749 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000.h 2011-07-27 13:17:15.000000000 -0500 | ||
1750 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000.h 2012-03-06 12:16:25.582039002 -0600 | ||
1751 | @@ -168,6 +168,8 @@ | ||
1752 | %{mcpu=e300c3: -me300} \ | ||
1753 | %{mcpu=e500mc: -me500mc} \ | ||
1754 | %{mcpu=e500mc64: -me500mc64} \ | ||
1755 | +%{mcpu=e5500: -me5500} \ | ||
1756 | +%{mcpu=e6500: -me6500} \ | ||
1757 | %{maltivec: -maltivec} \ | ||
1758 | %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ | ||
1759 | -many" | ||
1760 | @@ -477,13 +479,15 @@ | ||
1761 | |||
1762 | #define TARGET_FCTIDZ TARGET_FCFID | ||
1763 | #define TARGET_STFIWX TARGET_PPC_GFXOPT | ||
1764 | -#define TARGET_LFIWAX TARGET_CMPB | ||
1765 | -#define TARGET_LFIWZX TARGET_POPCNTD | ||
1766 | -#define TARGET_FCFIDS TARGET_POPCNTD | ||
1767 | -#define TARGET_FCFIDU TARGET_POPCNTD | ||
1768 | -#define TARGET_FCFIDUS TARGET_POPCNTD | ||
1769 | -#define TARGET_FCTIDUZ TARGET_POPCNTD | ||
1770 | -#define TARGET_FCTIWUZ TARGET_POPCNTD | ||
1771 | +#define TARGET_LFIWAX (TARGET_CMPB && rs6000_cpu != PROCESSOR_PPCE5500 \ | ||
1772 | + && rs6000_cpu != PROCESSOR_PPCE6500) | ||
1773 | +#define TARGET_LFIWZX (TARGET_POPCNTD && rs6000_cpu != PROCESSOR_PPCE5500 \ | ||
1774 | + && rs6000_cpu != PROCESSOR_PPCE6500) | ||
1775 | +#define TARGET_FCFIDS TARGET_LFIWZX | ||
1776 | +#define TARGET_FCFIDU TARGET_LFIWZX | ||
1777 | +#define TARGET_FCFIDUS TARGET_LFIWZX | ||
1778 | +#define TARGET_FCTIDUZ TARGET_LFIWZX | ||
1779 | +#define TARGET_FCTIWUZ TARGET_LFIWZX | ||
1780 | |||
1781 | /* E500 processors only support plain "sync", not lwsync. */ | ||
1782 | #define TARGET_NO_LWSYNC TARGET_E500 | ||
1783 | @@ -494,10 +498,14 @@ | ||
1784 | |||
1785 | #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \ | ||
1786 | && TARGET_DOUBLE_FLOAT \ | ||
1787 | - && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) | ||
1788 | + && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)) \ | ||
1789 | + && rs6000_cpu != PROCESSOR_PPCE5500 \ | ||
1790 | + && rs6000_cpu != PROCESSOR_PPCE6500) | ||
1791 | |||
1792 | #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ | ||
1793 | - && TARGET_FPRS && TARGET_SINGLE_FLOAT) | ||
1794 | + && TARGET_FPRS && TARGET_SINGLE_FLOAT \ | ||
1795 | + && rs6000_cpu != PROCESSOR_PPCE5500 \ | ||
1796 | + && rs6000_cpu != PROCESSOR_PPCE6500) | ||
1797 | |||
1798 | #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \ | ||
1799 | && TARGET_DOUBLE_FLOAT \ | ||
1800 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000.md gcc-4.6.2/gcc/config/rs6000/rs6000.md | ||
1801 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000.md 2011-09-19 11:41:20.000000000 -0500 | ||
1802 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000.md 2012-03-06 12:16:25.584039002 -0600 | ||
1803 | @@ -126,7 +126,7 @@ | ||
1804 | |||
1805 | ;; Define an insn type attribute. This is used in function unit delay | ||
1806 | ;; computations. | ||
1807 | -(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel" | ||
1808 | +(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt" | ||
1809 | (const_string "integer")) | ||
1810 | |||
1811 | ;; Define floating point instruction sub-types for use with Xfpu.md | ||
1812 | @@ -148,7 +148,7 @@ | ||
1813 | ;; Processor type -- this attribute must exactly match the processor_type | ||
1814 | ;; enumeration in rs6000.h. | ||
1815 | |||
1816 | -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan" | ||
1817 | +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan" | ||
1818 | (const (symbol_ref "rs6000_cpu_attr"))) | ||
1819 | |||
1820 | |||
1821 | @@ -176,6 +176,8 @@ | ||
1822 | (include "e300c2c3.md") | ||
1823 | (include "e500mc.md") | ||
1824 | (include "e500mc64.md") | ||
1825 | +(include "e5500.md") | ||
1826 | +(include "e6500.md") | ||
1827 | (include "power4.md") | ||
1828 | (include "power5.md") | ||
1829 | (include "power6.md") | ||
1830 | @@ -2302,13 +2304,17 @@ | ||
1831 | (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] | ||
1832 | UNSPEC_POPCNTB))] | ||
1833 | "TARGET_POPCNTB" | ||
1834 | - "popcntb %0,%1") | ||
1835 | + "popcntb %0,%1" | ||
1836 | + [(set_attr "length" "4") | ||
1837 | + (set_attr "type" "popcnt")]) | ||
1838 | |||
1839 | (define_insn "popcntd<mode>2" | ||
1840 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | ||
1841 | (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] | ||
1842 | "TARGET_POPCNTD" | ||
1843 | - "popcnt<wd> %0,%1") | ||
1844 | + "popcnt<wd> %0,%1" | ||
1845 | + [(set_attr "length" "4") | ||
1846 | + (set_attr "type" "popcnt")]) | ||
1847 | |||
1848 | (define_expand "popcount<mode>2" | ||
1849 | [(set (match_operand:GPR 0 "gpc_reg_operand" "") | ||
1850 | @@ -5957,10 +5963,10 @@ | ||
1851 | && ((TARGET_PPC_GFXOPT | ||
1852 | && !HONOR_NANS (<MODE>mode) | ||
1853 | && !HONOR_SIGNED_ZEROS (<MODE>mode)) | ||
1854 | - || TARGET_CMPB | ||
1855 | + || TARGET_LFIWAX | ||
1856 | || VECTOR_UNIT_VSX_P (<MODE>mode))" | ||
1857 | { | ||
1858 | - if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode)) | ||
1859 | + if (TARGET_LFIWAX || VECTOR_UNIT_VSX_P (<MODE>mode)) | ||
1860 | { | ||
1861 | emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1], | ||
1862 | operands[2])); | ||
1863 | @@ -5979,7 +5985,7 @@ | ||
1864 | (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>") | ||
1865 | (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")] | ||
1866 | UNSPEC_COPYSIGN))] | ||
1867 | - "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)" | ||
1868 | + "TARGET_LFIWAX && !VECTOR_UNIT_VSX_P (<MODE>mode)" | ||
1869 | "fcpsgn %0,%2,%1" | ||
1870 | [(set_attr "type" "fp")]) | ||
1871 | |||
1872 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000.opt gcc-4.6.2/gcc/config/rs6000/rs6000.opt | ||
1873 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000.opt 2010-11-29 19:47:54.000000000 -0600 | ||
1874 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000.opt 2012-03-06 12:16:25.584039002 -0600 | ||
1875 | @@ -179,6 +179,10 @@ | ||
1876 | Target Report Mask(ALTIVEC) Save | ||
1877 | Use AltiVec instructions | ||
1878 | |||
1879 | +maltivec2 | ||
1880 | +Target Report Mask(ALTIVEC2) Save | ||
1881 | +Use AltiVec PowerPC V2.07 instructions | ||
1882 | + | ||
1883 | mhard-dfp | ||
1884 | Target Report Mask(DFP) Save | ||
1885 | Use decimal floating point instructions | ||
1886 | diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000-opts.h gcc-4.6.2/gcc/config/rs6000/rs6000-opts.h | ||
1887 | --- gcc-4.6.2-orig/gcc/config/rs6000/rs6000-opts.h 2010-11-19 11:27:18.000000000 -0600 | ||
1888 | +++ gcc-4.6.2/gcc/config/rs6000/rs6000-opts.h 2012-03-06 12:16:25.584039002 -0600 | ||
1889 | @@ -53,6 +53,8 @@ | ||
1890 | PROCESSOR_PPCE300C3, | ||
1891 | PROCESSOR_PPCE500MC, | ||
1892 | PROCESSOR_PPCE500MC64, | ||
1893 | + PROCESSOR_PPCE5500, | ||
1894 | + PROCESSOR_PPCE6500, | ||
1895 | PROCESSOR_POWER4, | ||
1896 | PROCESSOR_POWER5, | ||
1897 | PROCESSOR_POWER6, | ||
1898 | diff -ruN gcc-4.6.2-orig/gcc/config.gcc gcc-4.6.2/gcc/config.gcc | ||
1899 | --- gcc-4.6.2-orig/gcc/config.gcc 2011-07-22 11:44:50.000000000 -0500 | ||
1900 | +++ gcc-4.6.2/gcc/config.gcc 2012-03-06 12:16:25.585039002 -0600 | ||
1901 | @@ -396,7 +396,7 @@ | ||
1902 | extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h" | ||
1903 | need_64bit_hwint=yes | ||
1904 | case x$with_cpu in | ||
1905 | - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64) | ||
1906 | + xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500) | ||
1907 | cpu_is_64bit=yes | ||
1908 | ;; | ||
1909 | esac | ||
1910 | @@ -3501,8 +3501,8 @@ | ||
1911 | | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \ | ||
1912 | | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \ | ||
1913 | | 604 | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \ | ||
1914 | - | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | titan\ | ||
1915 | - | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell) | ||
1916 | + | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | e5500 | e6500 \ | ||
1917 | + | titan | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell) | ||
1918 | # OK | ||
1919 | ;; | ||
1920 | *) | ||
1921 | diff -ruN gcc-4.6.2-orig/gcc/doc/extend.texi gcc-4.6.2/gcc/doc/extend.texi | ||
1922 | --- gcc-4.6.2-orig/gcc/doc/extend.texi 2011-10-24 09:55:45.000000000 -0500 | ||
1923 | +++ gcc-4.6.2/gcc/doc/extend.texi 2012-03-06 12:56:49.399039002 -0600 | ||
1924 | @@ -12509,6 +12509,291 @@ | ||
1925 | @samp{vec_vsx_st} builtins will always generate the VSX @samp{LXVD2X}, | ||
1926 | @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions. | ||
1927 | |||
1928 | +Using @option{-maltivec2} will extend the Altivec interface with the | ||
1929 | +following additional functions: | ||
1930 | + | ||
1931 | +@smallexample | ||
1932 | +vector unsigned char vec_absd (vector unsigned char, vector unsigned char); | ||
1933 | +vector unsigned char vec_absd (vector bool char, vector unsigned char); | ||
1934 | +vector unsigned char vec_absd (vector unsigned char, vector bool char); | ||
1935 | +vector unsigned short vec_absd (vector unsigned short, vector unsigned short); | ||
1936 | +vector unsigned short vec_absd (vector bool short, vector unsigned short); | ||
1937 | +vector unsigned short vec_absd (vector unsigned short, vector bool short); | ||
1938 | +vector unsigned int vec_absd (vector unsigned int, vector unsigned int); | ||
1939 | +vector unsigned int vec_absd (vector bool int, vector unsigned int); | ||
1940 | +vector unsigned int vec_absd (vector unsigned int, vector bool int); | ||
1941 | + | ||
1942 | +vector signed char vec_lvexbx (long, signed char *); | ||
1943 | +vector unsigned char vec_lvexbx (long, unsigned char *); | ||
1944 | +vector signed short vec_lvexhx (long, signed short *); | ||
1945 | +vector unsigned short vec_lvexhx (long, unsigned short *); | ||
1946 | +vector float vec_lvexwx (long, float *); | ||
1947 | +vector signed int vec_lvexwx (long, signed int *); | ||
1948 | +vector unsigned int vec_lvexwx (long, unsigned int *); | ||
1949 | +vector signed int vec_lvexwx (long, signed long *); | ||
1950 | +vector unsigned int vec_lvexwx (long, unsigned long *); | ||
1951 | + | ||
1952 | +void vec_stvexbx (vector signed char, long, signed char *); | ||
1953 | +void vec_stvexbx (vector unsigned char, long, unsigned char *); | ||
1954 | +void vec_stvexbx (vector bool char, long, signed char *); | ||
1955 | +void vec_stvexbx (vector bool char, long, unsigned char *); | ||
1956 | +void vec_stvexbx (vector signed char, long, void *); | ||
1957 | +void vec_stvexbx (vector unsigned char, long, void *); | ||
1958 | +void vec_stvexhx (vector signed short, long, signed short *); | ||
1959 | +void vec_stvexhx (vector unsigned short, long, unsigned short *); | ||
1960 | +void vec_stvexhx (vector bool short, long, signed short *); | ||
1961 | +void vec_stvexhx (vector bool short, long, unsigned short *); | ||
1962 | +void vec_stvexhx (vector signed short, long, void *); | ||
1963 | +void vec_stvexhx (vector unsigned short, long, void *); | ||
1964 | +void vec_stvexwx (vector float, long, float *); | ||
1965 | +void vec_stvexwx (vector signed int, long, signed int *); | ||
1966 | +void vec_stvexwx (vector unsigned int, long, unsigned int *); | ||
1967 | +void vec_stvexwx (vector bool int, long, signed int *); | ||
1968 | +void vec_stvexwx (vector bool int, long, unsigned int *); | ||
1969 | +void vec_stvexwx (vector float, long, void *); | ||
1970 | +void vec_stvexwx (vector signed int, long, void *); | ||
1971 | +void vec_stvexwx (vector unsigned int, long, void *); | ||
1972 | + | ||
1973 | +vector float vec_lvtlx (long, vector float *); | ||
1974 | +vector float vec_lvtlx (long, float *); | ||
1975 | +vector bool int vec_lvtlx (long, vector bool int *); | ||
1976 | +vector signed int vec_lvtlx (long, vector signed int *); | ||
1977 | +vector signed int vec_lvtlx (long, signed int *); | ||
1978 | +vector unsigned int vec_lvtlx (long, vector unsigned int *); | ||
1979 | +vector unsigned int vec_lvtlx (long, unsigned int *); | ||
1980 | +vector bool short vec_lvtlx (long, vector bool short *); | ||
1981 | +vector pixel vec_lvtlx (long, vector pixel *); | ||
1982 | +vector signed short vec_lvtlx (long, vector signed short *); | ||
1983 | +vector signed short vec_lvtlx (long, signed short *); | ||
1984 | +vector unsigned short vec_lvtlx (long, vector unsigned short *); | ||
1985 | +vector unsigned short vec_lvtlx (long, unsigned short *); | ||
1986 | +vector bool char vec_lvtlx (long, vector bool char *); | ||
1987 | +vector signed char vec_lvtlx (long, vector signed char *); | ||
1988 | +vector signed char vec_lvtlx (long, signed char *); | ||
1989 | +vector unsigned char vec_lvtlx (long, vector unsigned char *); | ||
1990 | +vector unsigned char vec_lvtlx (long, unsigned char *); | ||
1991 | +vector float vec_lvtlxl (long, vector float *); | ||
1992 | +vector float vec_lvtlxl (long, float *); | ||
1993 | +vector bool int vec_lvtlxl (long, vector bool int *); | ||
1994 | +vector signed int vec_lvtlxl (long, vector signed int *); | ||
1995 | +vector signed int vec_lvtlxl (long, signed int *); | ||
1996 | +vector unsigned int vec_lvtlxl (long, vector unsigned int *); | ||
1997 | +vector unsigned int vec_lvtlxl (long, unsigned int *); | ||
1998 | +vector bool short vec_lvtlxl (long, vector bool short *); | ||
1999 | +vector pixel vec_lvtlxl (long, vector pixel *); | ||
2000 | +vector signed short vec_lvtlxl (long, vector signed short *); | ||
2001 | +vector signed short vec_lvtlxl (long, signed short *); | ||
2002 | +vector unsigned short vec_lvtlxl (long, vector unsigned short *); | ||
2003 | +vector unsigned short vec_lvtlxl (long, unsigned short *); | ||
2004 | +vector bool char vec_lvtlxl (long, vector bool char *); | ||
2005 | +vector signed char vec_lvtlxl (long, vector signed char *); | ||
2006 | +vector signed char vec_lvtlxl (long, signed char *); | ||
2007 | +vector unsigned char vec_lvtlxl (long, vector unsigned char *); | ||
2008 | +vector unsigned char vec_lvtlxl (long, unsigned char *); | ||
2009 | +vector float vec_lvtrx (long, vector float *); | ||
2010 | +vector float vec_lvtrx (long, float *); | ||
2011 | +vector bool int vec_lvtrx (long, vector bool int *); | ||
2012 | +vector signed int vec_lvtrx (long, vector signed int *); | ||
2013 | +vector signed int vec_lvtrx (long, signed int *); | ||
2014 | +vector unsigned int vec_lvtrx (long, vector unsigned int *); | ||
2015 | +vector unsigned int vec_lvtrx (long, unsigned int *); | ||
2016 | +vector bool short vec_lvtrx (long, vector bool short *); | ||
2017 | +vector pixel vec_lvtrx (long, vector pixel *); | ||
2018 | +vector signed short vec_lvtrx (long, vector signed short *); | ||
2019 | +vector signed short vec_lvtrx (long, signed short *); | ||
2020 | +vector unsigned short vec_lvtrx (long, vector unsigned short *); | ||
2021 | +vector unsigned short vec_lvtrx (long, unsigned short *); | ||
2022 | +vector bool char vec_lvtrx (long, vector bool char *); | ||
2023 | +vector signed char vec_lvtrx (long, vector signed char *); | ||
2024 | +vector signed char vec_lvtrx (long, signed char *); | ||
2025 | +vector unsigned char vec_lvtrx (long, vector unsigned char *); | ||
2026 | +vector unsigned char vec_lvtrx (long, unsigned char *); | ||
2027 | +vector float vec_lvtrxl (long, vector float *); | ||
2028 | +vector float vec_lvtrxl (long, float *); | ||
2029 | +vector bool int vec_lvtrxl (long, vector bool int *); | ||
2030 | +vector signed int vec_lvtrxl (long, vector signed int *); | ||
2031 | +vector signed int vec_lvtrxl (long, signed int *); | ||
2032 | +vector unsigned int vec_lvtrxl (long, vector unsigned int *); | ||
2033 | +vector unsigned int vec_lvtrxl (long, unsigned int *); | ||
2034 | +vector bool short vec_lvtrxl (long, vector bool short *); | ||
2035 | +vector pixel vec_lvtrxl (long, vector pixel *); | ||
2036 | +vector signed short vec_lvtrxl (long, vector signed short *); | ||
2037 | +vector signed short vec_lvtrxl (long, signed short *); | ||
2038 | +vector unsigned short vec_lvtrxl (long, vector unsigned short *); | ||
2039 | +vector unsigned short vec_lvtrxl (long, unsigned short *); | ||
2040 | +vector bool char vec_lvtrxl (long, vector bool char *); | ||
2041 | +vector signed char vec_lvtrxl (long, vector signed char *); | ||
2042 | +vector signed char vec_lvtrxl (long, signed char *); | ||
2043 | +vector unsigned char vec_lvtrxl (long, vector unsigned char *); | ||
2044 | +vector unsigned char vec_lvtrxl (long, unsigned char *); | ||
2045 | + | ||
2046 | +void vec_stvflx (vector float, long, vector float *); | ||
2047 | +void vec_stvflx (vector float, long, float *); | ||
2048 | +void vec_stvflx (vector bool int, long, vector bool int *); | ||
2049 | +void vec_stvflx (vector signed int, long, vector signed int *); | ||
2050 | +void vec_stvflx (vector signed int, long, signed int *); | ||
2051 | +void vec_stvflx (vector unsigned int, long, vector unsigned int *); | ||
2052 | +void vec_stvflx (vector unsigned int, long, unsigned int *); | ||
2053 | +void vec_stvflx (vector bool short, long, vector bool short *); | ||
2054 | +void vec_stvflx (vector pixel, long, vector pixel *); | ||
2055 | +void vec_stvflx (vector signed short, long, vector signed short *); | ||
2056 | +void vec_stvflx (vector signed short, long, signed short *); | ||
2057 | +void vec_stvflx (vector unsigned short, long, vector unsigned short *); | ||
2058 | +void vec_stvflx (vector unsigned short, long, unsigned short *); | ||
2059 | +void vec_stvflx (vector bool char, long, vector bool char *); | ||
2060 | +void vec_stvflx (vector signed char, long, vector signed char *); | ||
2061 | +void vec_stvflx (vector signed char, long, signed char *); | ||
2062 | +void vec_stvflx (vector unsigned char, long, vector unsigned char *); | ||
2063 | +void vec_stvflx (vector unsigned char, long, unsigned char *); | ||
2064 | +void vec_stvflxl (vector float, long, vector float *); | ||
2065 | +void vec_stvflxl (vector float, long, float *); | ||
2066 | +void vec_stvflxl (vector bool int, long, vector bool int *); | ||
2067 | +void vec_stvflxl (vector signed int, long, vector signed int *); | ||
2068 | +void vec_stvflxl (vector signed int, long, signed int *); | ||
2069 | +void vec_stvflxl (vector unsigned int, long, vector unsigned int *); | ||
2070 | +void vec_stvflxl (vector unsigned int, long, unsigned int *); | ||
2071 | +void vec_stvflxl (vector bool short, long, vector bool short *); | ||
2072 | +void vec_stvflxl (vector pixel, long, vector pixel *); | ||
2073 | +void vec_stvflxl (vector signed short, long, vector signed short *); | ||
2074 | +void vec_stvflxl (vector signed short, long, signed short *); | ||
2075 | +void vec_stvflxl (vector unsigned short, long, vector unsigned short *); | ||
2076 | +void vec_stvflxl (vector unsigned short, long, unsigned short *); | ||
2077 | +void vec_stvflxl (vector bool char, long, vector bool char *); | ||
2078 | +void vec_stvflxl (vector signed char, long, vector signed char *); | ||
2079 | +void vec_stvflxl (vector signed char, long, signed char *); | ||
2080 | +void vec_stvflxl (vector unsigned char, long, vector unsigned char *); | ||
2081 | +void vec_stvflxl (vector unsigned char, long, unsigned char *); | ||
2082 | +void vec_stvfrx (vector float, long, vector float *); | ||
2083 | +void vec_stvfrx (vector float, long, float *); | ||
2084 | +void vec_stvfrx (vector bool int, long, vector bool int *); | ||
2085 | +void vec_stvfrx (vector signed int, long, vector signed int *); | ||
2086 | +void vec_stvfrx (vector signed int, long, signed int *); | ||
2087 | +void vec_stvfrx (vector unsigned int, long, vector unsigned int *); | ||
2088 | +void vec_stvfrx (vector unsigned int, long, unsigned int *); | ||
2089 | +void vec_stvfrx (vector bool short, long, vector bool short *); | ||
2090 | +void vec_stvfrx (vector pixel, long, vector pixel *); | ||
2091 | +void vec_stvfrx (vector signed short, long, vector signed short *); | ||
2092 | +void vec_stvfrx (vector signed short, long, signed short *); | ||
2093 | +void vec_stvfrx (vector unsigned short, long, vector unsigned short *); | ||
2094 | +void vec_stvfrx (vector unsigned short, long, unsigned short *); | ||
2095 | +void vec_stvfrx (vector bool char, long, vector bool char *); | ||
2096 | +void vec_stvfrx (vector signed char, long, vector signed char *); | ||
2097 | +void vec_stvfrx (vector signed char, long, signed char *); | ||
2098 | +void vec_stvfrx (vector unsigned char, long, vector unsigned char *); | ||
2099 | +void vec_stvfrx (vector unsigned char, long, unsigned char *); | ||
2100 | +void vec_stvfrxl (vector float, long, vector float *); | ||
2101 | +void vec_stvfrxl (vector float, long, float *); | ||
2102 | +void vec_stvfrxl (vector bool int, long, vector bool int *); | ||
2103 | +void vec_stvfrxl (vector signed int, long, vector signed int *); | ||
2104 | +void vec_stvfrxl (vector signed int, long, signed int *); | ||
2105 | +void vec_stvfrxl (vector unsigned int, long, vector unsigned int *); | ||
2106 | +void vec_stvfrxl (vector unsigned int, long, unsigned int *); | ||
2107 | +void vec_stvfrxl (vector bool short, long, vector bool short *); | ||
2108 | +void vec_stvfrxl (vector pixel, long, vector pixel *); | ||
2109 | +void vec_stvfrxl (vector signed short, long, vector signed short *); | ||
2110 | +void vec_stvfrxl (vector signed short, long, signed short *); | ||
2111 | +void vec_stvfrxl (vector unsigned short, long, vector unsigned short *); | ||
2112 | +void vec_stvfrxl (vector unsigned short, long, unsigned short *); | ||
2113 | +void vec_stvfrxl (vector bool char, long, vector bool char *); | ||
2114 | +void vec_stvfrxl (vector signed char, long, vector signed char *); | ||
2115 | +void vec_stvfrxl (vector signed char, long, signed char *); | ||
2116 | +void vec_stvfrxl (vector unsigned char, long, vector unsigned char *); | ||
2117 | +void vec_stvfrxl (vector unsigned char, long, unsigned char *); | ||
2118 | + | ||
2119 | +vector float vec_lvswx (long, vector float *); | ||
2120 | +vector float vec_lvswx (long, float *); | ||
2121 | +vector bool int vec_lvswx (long, vector bool int *); | ||
2122 | +vector signed int vec_lvswx (long, vector signed int *); | ||
2123 | +vector signed int vec_lvswx (long, signed int *); | ||
2124 | +vector unsigned int vec_lvswx (long, vector unsigned int *); | ||
2125 | +vector unsigned int vec_lvswx (long, unsigned int *); | ||
2126 | +vector bool short vec_lvswx (long, vector bool short *); | ||
2127 | +vector pixel vec_lvswx (long, vector pixel *); | ||
2128 | +vector signed short vec_lvswx (long, vector signed short *); | ||
2129 | +vector signed short vec_lvswx (long, signed short *); | ||
2130 | +vector unsigned short vec_lvswx (long, vector unsigned short *); | ||
2131 | +vector unsigned short vec_lvswx (long, unsigned short *); | ||
2132 | +vector bool char vec_lvswx (long, vector bool char *); | ||
2133 | +vector signed char vec_lvswx (long, vector signed char *); | ||
2134 | +vector signed char vec_lvswx (long, signed char *); | ||
2135 | +vector unsigned char vec_lvswx (long, vector unsigned char *); | ||
2136 | +vector unsigned char vec_lvswx (long, unsigned char *); | ||
2137 | +vector float vec_lvswxl (long, vector float *); | ||
2138 | +vector float vec_lvswxl (long, float *); | ||
2139 | +vector bool int vec_lvswxl (long, vector bool int *); | ||
2140 | +vector signed int vec_lvswxl (long, vector signed int *); | ||
2141 | +vector signed int vec_lvswxl (long, signed int *); | ||
2142 | +vector unsigned int vec_lvswxl (long, vector unsigned int *); | ||
2143 | +vector unsigned int vec_lvswxl (long, unsigned int *); | ||
2144 | +vector bool short vec_lvswxl (long, vector bool short *); | ||
2145 | +vector pixel vec_lvswxl (long, vector pixel *); | ||
2146 | +vector signed short vec_lvswxl (long, vector signed short *); | ||
2147 | +vector signed short vec_lvswxl (long, signed short *); | ||
2148 | +vector unsigned short vec_lvswxl (long, vector unsigned short *); | ||
2149 | +vector unsigned short vec_lvswxl (long, unsigned short *); | ||
2150 | +vector bool char vec_lvswxl (long, vector bool char *); | ||
2151 | +vector signed char vec_lvswxl (long, vector signed char *); | ||
2152 | +vector signed char vec_lvswxl (long, signed char *); | ||
2153 | +vector unsigned char vec_lvswxl (long, vector unsigned char *); | ||
2154 | +vector unsigned char vec_lvswxl (long, unsigned char *); | ||
2155 | + | ||
2156 | +void vec_stvswx (vector float, long, vector float *); | ||
2157 | +void vec_stvswx (vector float, long, float *); | ||
2158 | +void vec_stvswx (vector bool int, long, vector bool int *); | ||
2159 | +void vec_stvswx (vector signed int, long, vector signed int *); | ||
2160 | +void vec_stvswx (vector signed int, long, signed int *); | ||
2161 | +void vec_stvswx (vector unsigned int, long, vector unsigned int *); | ||
2162 | +void vec_stvswx (vector unsigned int, long, unsigned int *); | ||
2163 | +void vec_stvswx (vector bool short, long, vector bool short *); | ||
2164 | +void vec_stvswx (vector pixel, long, vector pixel *); | ||
2165 | +void vec_stvswx (vector signed short, long, vector signed short *); | ||
2166 | +void vec_stvswx (vector signed short, long, signed short *); | ||
2167 | +void vec_stvswx (vector unsigned short, long, vector unsigned short *); | ||
2168 | +void vec_stvswx (vector unsigned short, long, unsigned short *); | ||
2169 | +void vec_stvswx (vector bool char, long, vector bool char *); | ||
2170 | +void vec_stvswx (vector signed char, long, vector signed char *); | ||
2171 | +void vec_stvswx (vector signed char, long, signed char *); | ||
2172 | +void vec_stvswx (vector unsigned char, long, vector unsigned char *); | ||
2173 | +void vec_stvswx (vector unsigned char, long, unsigned char *); | ||
2174 | +void vec_stvswxl (vector float, long, vector float *); | ||
2175 | +void vec_stvswxl (vector float, long, float *); | ||
2176 | +void vec_stvswxl (vector bool int, long, vector bool int *); | ||
2177 | +void vec_stvswxl (vector signed int, long, vector signed int *); | ||
2178 | +void vec_stvswxl (vector signed int, long, signed int *); | ||
2179 | +void vec_stvswxl (vector unsigned int, long, vector unsigned int *); | ||
2180 | +void vec_stvswxl (vector unsigned int, long, unsigned int *); | ||
2181 | +void vec_stvswxl (vector bool short, long, vector bool short *); | ||
2182 | +void vec_stvswxl (vector pixel, long, vector pixel *); | ||
2183 | +void vec_stvswxl (vector signed short, long, vector signed short *); | ||
2184 | +void vec_stvswxl (vector signed short, long, signed short *); | ||
2185 | +void vec_stvswxl (vector unsigned short, long, vector unsigned short *); | ||
2186 | +void vec_stvswxl (vector unsigned short, long, unsigned short *); | ||
2187 | +void vec_stvswxl (vector bool char, long, vector bool char *); | ||
2188 | +void vec_stvswxl (vector signed char, long, vector signed char *); | ||
2189 | +void vec_stvswxl (vector signed char, long, signed char *); | ||
2190 | +void vec_stvswxl (vector unsigned char, long, vector unsigned char *); | ||
2191 | +void vec_stvswxl (vector unsigned char, long, unsigned char *); | ||
2192 | + | ||
2193 | +vector float vec_lvsm (long, vector float *); | ||
2194 | +vector float vec_lvsm (long, float *); | ||
2195 | +vector bool int vec_lvsm (long, vector bool int *); | ||
2196 | +vector signed int vec_lvsm (long, vector signed int *); | ||
2197 | +vector signed int vec_lvsm (long, signed int *); | ||
2198 | +vector unsigned int vec_lvsm (long, vector unsigned int *); | ||
2199 | +vector unsigned int vec_lvsm (long, unsigned int *); | ||
2200 | +vector bool short vec_lvsm (long, vector bool short *); | ||
2201 | +vector pixel vec_lvsm (long, vector pixel *); | ||
2202 | +vector signed short vec_lvsm (long, vector signed short *); | ||
2203 | +vector signed short vec_lvsm (long, signed short *); | ||
2204 | +vector unsigned short vec_lvsm (long, vector unsigned short *); | ||
2205 | +vector unsigned short vec_lvsm (long, unsigned short *); | ||
2206 | +vector bool char vec_lvsm (long, vector bool char *); | ||
2207 | +vector signed char vec_lvsm (long, vector signed char *); | ||
2208 | +vector signed char vec_lvsm (long, signed char *); | ||
2209 | +vector unsigned char vec_lvsm (long, vector unsigned char *); | ||
2210 | +vector unsigned char vec_lvsm (long, unsigned char *); | ||
2211 | +@end smallexample | ||
2212 | + | ||
2213 | GCC provides a few other builtins on Powerpc to access certain instructions: | ||
2214 | @smallexample | ||
2215 | float __builtin_recipdivf (float, float); | ||
2216 | diff -ruN gcc-4.6.2-orig/gcc/doc/invoke.texi gcc-4.6.2/gcc/doc/invoke.texi | ||
2217 | --- gcc-4.6.2-orig/gcc/doc/invoke.texi 2011-10-24 07:22:21.000000000 -0500 | ||
2218 | +++ gcc-4.6.2/gcc/doc/invoke.texi 2012-03-06 12:56:49.402039002 -0600 | ||
2219 | @@ -770,7 +770,7 @@ | ||
2220 | -mcmodel=@var{code-model} @gol | ||
2221 | -mpower -mno-power -mpower2 -mno-power2 @gol | ||
2222 | -mpowerpc -mpowerpc64 -mno-powerpc @gol | ||
2223 | --maltivec -mno-altivec @gol | ||
2224 | +-maltivec -mno-altivec -maltivec2 -mno-altivec2 @gol | ||
2225 | -mpowerpc-gpopt -mno-powerpc-gpopt @gol | ||
2226 | -mpowerpc-gfxopt -mno-powerpc-gfxopt @gol | ||
2227 | -mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mpopcntd -mno-popcntd @gol | ||
2228 | @@ -15536,16 +15536,21 @@ | ||
2229 | The @option{-mpopcntb} option allows GCC to generate the popcount and | ||
2230 | double precision FP reciprocal estimate instruction implemented on the | ||
2231 | POWER5 processor and other processors that support the PowerPC V2.02 | ||
2232 | -architecture. | ||
2233 | -The @option{-mpopcntd} option allows GCC to generate the popcount | ||
2234 | -instruction implemented on the POWER7 processor and other processors | ||
2235 | -that support the PowerPC V2.06 architecture. | ||
2236 | +architecture. On the e5500 and e6500 processors, only the popcount | ||
2237 | +instruction is generated. | ||
2238 | +The @option{-mpopcntd} option allows GCC to generate the popcount and | ||
2239 | +double word to FP conversion instructions implemented on the POWER7 | ||
2240 | +processor and other processors that support the PowerPC V2.06 | ||
2241 | +architecture. On the e5500 and e6500 processors, only the popcount | ||
2242 | +instruction is generated. | ||
2243 | The @option{-mfprnd} option allows GCC to generate the FP round to | ||
2244 | integer instructions implemented on the POWER5+ processor and other | ||
2245 | processors that support the PowerPC V2.03 architecture. | ||
2246 | The @option{-mcmpb} option allows GCC to generate the compare bytes | ||
2247 | -instruction implemented on the POWER6 processor and other processors | ||
2248 | -that support the PowerPC V2.05 architecture. | ||
2249 | +and copy sign instructions implemented on the POWER6 processor and | ||
2250 | +other processors that support the PowerPC V2.05 architecture. On the | ||
2251 | +e5500 and e6500 processors, only the compare bytes instruction is | ||
2252 | +generated. | ||
2253 | The @option{-mmfpgpr} option allows GCC to generate the FP move to/from | ||
2254 | general purpose register instructions implemented on the POWER6X | ||
2255 | processor and other processors that support the extended PowerPC V2.05 | ||
2256 | @@ -15592,11 +15597,13 @@ | ||
2257 | @samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740}, | ||
2258 | @samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823}, | ||
2259 | @samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2}, | ||
2260 | -@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{ec603e}, @samp{G3}, | ||
2261 | -@samp{G4}, @samp{G5}, @samp{titan}, @samp{power}, @samp{power2}, @samp{power3}, | ||
2262 | -@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, | ||
2263 | -@samp{power7}, @samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios}, | ||
2264 | -@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}. | ||
2265 | +@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{e5500}, | ||
2266 | +@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, | ||
2267 | +@samp{titan}, @samp{power}, @samp{power2}, @samp{power3}, | ||
2268 | +@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, | ||
2269 | +@samp{power6x}, @samp{power7}, @samp{common}, @samp{powerpc}, | ||
2270 | +@samp{powerpc64}, @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, | ||
2271 | +and @samp{rs64}. | ||
2272 | |||
2273 | @option{-mcpu=common} selects a completely generic processor. Code | ||
2274 | generated under this option will run on any POWER or PowerPC processor. | ||
2275 | @@ -15617,10 +15624,11 @@ | ||
2276 | The @option{-mcpu} options automatically enable or disable the | ||
2277 | following options: | ||
2278 | |||
2279 | -@gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol | ||
2280 | --mnew-mnemonics -mpopcntb -mpopcntd -mpower -mpower2 -mpowerpc64 @gol | ||
2281 | --mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol | ||
2282 | --msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx} | ||
2283 | +@gccoptlist{-maltivec -maltivec2 -mfprnd -mhard-float -mmfcrf | ||
2284 | +-mmultiple @gol -mnew-mnemonics -mpopcntb -mpopcntd -mpower -mpower2 | ||
2285 | +-mpowerpc64 @gol -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float | ||
2286 | +-mdouble-float @gol -msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr | ||
2287 | +-mvsx} | ||
2288 | |||
2289 | The particular options set for any particular CPU will vary between | ||
2290 | compiler versions, depending on what setting seems to produce optimal | ||
2291 | @@ -15671,6 +15679,16 @@ | ||
2292 | @option{-mabi=altivec} to adjust the current ABI with AltiVec ABI | ||
2293 | enhancements. | ||
2294 | |||
2295 | +@item -maltivec2 | ||
2296 | +@itemx -mno-altivec2 | ||
2297 | +@opindex maltivec2 | ||
2298 | +@opindex mno-altivec2 | ||
2299 | +Generate code that uses (does not use) AltiVec2 instructions, and also | ||
2300 | +enable the use of built-in functions that allow more direct access to | ||
2301 | +the AltiVec2 instruction set. You may also need to set | ||
2302 | +@option{-mabi=altivec} to adjust the current ABI with AltiVec ABI | ||
2303 | +enhancements. | ||
2304 | + | ||
2305 | @item -mvrsave | ||
2306 | @itemx -mno-vrsave | ||
2307 | @opindex mvrsave | ||
2308 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-10.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-10.c | ||
2309 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-10.c 1969-12-31 18:00:00.000000000 -0600 | ||
2310 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-10.c 2012-03-06 12:31:05.152039004 -0600 | ||
2311 | @@ -0,0 +1,66 @@ | ||
2312 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2313 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2314 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2315 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2316 | +/* { dg-final { scan-assembler-times "lvtlx" 37 } } */ | ||
2317 | + | ||
2318 | +#include <altivec.h> | ||
2319 | + | ||
2320 | +typedef __vector signed char vsc; | ||
2321 | +typedef __vector signed short vss; | ||
2322 | +typedef __vector signed int vsi; | ||
2323 | +typedef __vector unsigned char vuc; | ||
2324 | +typedef __vector unsigned short vus; | ||
2325 | +typedef __vector unsigned int vui; | ||
2326 | +typedef __vector bool char vbc; | ||
2327 | +typedef __vector bool short vbs; | ||
2328 | +typedef __vector bool int vbi; | ||
2329 | +typedef __vector float vsf; | ||
2330 | +typedef __vector pixel vp; | ||
2331 | +typedef signed char sc; | ||
2332 | +typedef signed short ss; | ||
2333 | +typedef signed int si; | ||
2334 | +typedef signed long sl; | ||
2335 | +typedef unsigned char uc; | ||
2336 | +typedef unsigned short us; | ||
2337 | +typedef unsigned int ui; | ||
2338 | +typedef unsigned long ul; | ||
2339 | +typedef float sf; | ||
2340 | + | ||
2341 | +vsc lc1(long a, void *p) { return __builtin_altivec_lvtlx (a,p); } | ||
2342 | +vsf llx01(long a, vsf *p) { return __builtin_vec_lvtlx (a,p); } | ||
2343 | +vsf llx02(long a, sf *p) { return __builtin_vec_lvtlx (a,p); } | ||
2344 | +vbi llx03(long a, vbi *p) { return __builtin_vec_lvtlx (a,p); } | ||
2345 | +vsi llx04(long a, vsi *p) { return __builtin_vec_lvtlx (a,p); } | ||
2346 | +vsi llx05(long a, si *p) { return __builtin_vec_lvtlx (a,p); } | ||
2347 | +vui llx06(long a, vui *p) { return __builtin_vec_lvtlx (a,p); } | ||
2348 | +vui llx07(long a, ui *p) { return __builtin_vec_lvtlx (a,p); } | ||
2349 | +vbs llx08(long a, vbs *p) { return __builtin_vec_lvtlx (a,p); } | ||
2350 | +vp llx09(long a, vp *p) { return __builtin_vec_lvtlx (a,p); } | ||
2351 | +vss llx10(long a, vss *p) { return __builtin_vec_lvtlx (a,p); } | ||
2352 | +vss llx11(long a, ss *p) { return __builtin_vec_lvtlx (a,p); } | ||
2353 | +vus llx12(long a, vus *p) { return __builtin_vec_lvtlx (a,p); } | ||
2354 | +vus llx13(long a, us *p) { return __builtin_vec_lvtlx (a,p); } | ||
2355 | +vbc llx14(long a, vbc *p) { return __builtin_vec_lvtlx (a,p); } | ||
2356 | +vsc llx15(long a, vsc *p) { return __builtin_vec_lvtlx (a,p); } | ||
2357 | +vsc llx16(long a, sc *p) { return __builtin_vec_lvtlx (a,p); } | ||
2358 | +vuc llx17(long a, vuc *p) { return __builtin_vec_lvtlx (a,p); } | ||
2359 | +vuc llx18(long a, uc *p) { return __builtin_vec_lvtlx (a,p); } | ||
2360 | +vsf Dllx01(long a, vsf *p) { return vec_lvtlx (a,p); } | ||
2361 | +vsf Dllx02(long a, sf *p) { return vec_lvtlx (a,p); } | ||
2362 | +vbi Dllx03(long a, vbi *p) { return vec_lvtlx (a,p); } | ||
2363 | +vsi Dllx04(long a, vsi *p) { return vec_lvtlx (a,p); } | ||
2364 | +vsi Dllx05(long a, si *p) { return vec_lvtlx (a,p); } | ||
2365 | +vui Dllx06(long a, vui *p) { return vec_lvtlx (a,p); } | ||
2366 | +vui Dllx07(long a, ui *p) { return vec_lvtlx (a,p); } | ||
2367 | +vbs Dllx08(long a, vbs *p) { return vec_lvtlx (a,p); } | ||
2368 | +vp Dllx09(long a, vp *p) { return vec_lvtlx (a,p); } | ||
2369 | +vss Dllx10(long a, vss *p) { return vec_lvtlx (a,p); } | ||
2370 | +vss Dllx11(long a, ss *p) { return vec_lvtlx (a,p); } | ||
2371 | +vus Dllx12(long a, vus *p) { return vec_lvtlx (a,p); } | ||
2372 | +vus Dllx13(long a, us *p) { return vec_lvtlx (a,p); } | ||
2373 | +vbc Dllx14(long a, vbc *p) { return vec_lvtlx (a,p); } | ||
2374 | +vsc Dllx15(long a, vsc *p) { return vec_lvtlx (a,p); } | ||
2375 | +vsc Dllx16(long a, sc *p) { return vec_lvtlx (a,p); } | ||
2376 | +vuc Dllx17(long a, vuc *p) { return vec_lvtlx (a,p); } | ||
2377 | +vuc Dllx18(long a, uc *p) { return vec_lvtlx (a,p); } | ||
2378 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-11.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-11.c | ||
2379 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-11.c 1969-12-31 18:00:00.000000000 -0600 | ||
2380 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-11.c 2012-03-06 12:31:05.153039004 -0600 | ||
2381 | @@ -0,0 +1,66 @@ | ||
2382 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2383 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2384 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2385 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2386 | +/* { dg-final { scan-assembler-times "lvtlxl" 37 } } */ | ||
2387 | + | ||
2388 | +#include <altivec.h> | ||
2389 | + | ||
2390 | +typedef __vector signed char vsc; | ||
2391 | +typedef __vector signed short vss; | ||
2392 | +typedef __vector signed int vsi; | ||
2393 | +typedef __vector unsigned char vuc; | ||
2394 | +typedef __vector unsigned short vus; | ||
2395 | +typedef __vector unsigned int vui; | ||
2396 | +typedef __vector bool char vbc; | ||
2397 | +typedef __vector bool short vbs; | ||
2398 | +typedef __vector bool int vbi; | ||
2399 | +typedef __vector float vsf; | ||
2400 | +typedef __vector pixel vp; | ||
2401 | +typedef signed char sc; | ||
2402 | +typedef signed short ss; | ||
2403 | +typedef signed int si; | ||
2404 | +typedef signed long sl; | ||
2405 | +typedef unsigned char uc; | ||
2406 | +typedef unsigned short us; | ||
2407 | +typedef unsigned int ui; | ||
2408 | +typedef unsigned long ul; | ||
2409 | +typedef float sf; | ||
2410 | + | ||
2411 | +vsc lc2(long a, void *p) { return __builtin_altivec_lvtlxl (a,p); } | ||
2412 | +vsf llxl01(long a, vsf *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2413 | +vsf llxl02(long a, sf *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2414 | +vbi llxl03(long a, vbi *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2415 | +vsi llxl04(long a, vsi *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2416 | +vsi llxl05(long a, si *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2417 | +vui llxl06(long a, vui *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2418 | +vui llxl07(long a, ui *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2419 | +vbs llxl08(long a, vbs *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2420 | +vp llxl09(long a, vp *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2421 | +vss llxl10(long a, vss *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2422 | +vss llxl11(long a, ss *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2423 | +vus llxl12(long a, vus *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2424 | +vus llxl13(long a, us *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2425 | +vbc llxl14(long a, vbc *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2426 | +vsc llxl15(long a, vsc *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2427 | +vsc llxl16(long a, sc *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2428 | +vuc llxl17(long a, vuc *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2429 | +vuc llxl18(long a, uc *p) { return __builtin_vec_lvtlxl (a,p); } | ||
2430 | +vsf Dllxl01(long a, vsf *p) { return vec_lvtlxl (a,p); } | ||
2431 | +vsf Dllxl02(long a, sf *p) { return vec_lvtlxl (a,p); } | ||
2432 | +vbi Dllxl03(long a, vbi *p) { return vec_lvtlxl (a,p); } | ||
2433 | +vsi Dllxl04(long a, vsi *p) { return vec_lvtlxl (a,p); } | ||
2434 | +vsi Dllxl05(long a, si *p) { return vec_lvtlxl (a,p); } | ||
2435 | +vui Dllxl06(long a, vui *p) { return vec_lvtlxl (a,p); } | ||
2436 | +vui Dllxl07(long a, ui *p) { return vec_lvtlxl (a,p); } | ||
2437 | +vbs Dllxl08(long a, vbs *p) { return vec_lvtlxl (a,p); } | ||
2438 | +vp Dllxl09(long a, vp *p) { return vec_lvtlxl (a,p); } | ||
2439 | +vss Dllxl10(long a, vss *p) { return vec_lvtlxl (a,p); } | ||
2440 | +vss Dllxl11(long a, ss *p) { return vec_lvtlxl (a,p); } | ||
2441 | +vus Dllxl12(long a, vus *p) { return vec_lvtlxl (a,p); } | ||
2442 | +vus Dllxl13(long a, us *p) { return vec_lvtlxl (a,p); } | ||
2443 | +vbc Dllxl14(long a, vbc *p) { return vec_lvtlxl (a,p); } | ||
2444 | +vsc Dllxl15(long a, vsc *p) { return vec_lvtlxl (a,p); } | ||
2445 | +vsc Dllxl16(long a, sc *p) { return vec_lvtlxl (a,p); } | ||
2446 | +vuc Dllxl17(long a, vuc *p) { return vec_lvtlxl (a,p); } | ||
2447 | +vuc Dllxl18(long a, uc *p) { return vec_lvtlxl (a,p); } | ||
2448 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-12.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-12.c | ||
2449 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-12.c 1969-12-31 18:00:00.000000000 -0600 | ||
2450 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-12.c 2012-03-06 12:31:05.153039004 -0600 | ||
2451 | @@ -0,0 +1,66 @@ | ||
2452 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2453 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2454 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2455 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2456 | +/* { dg-final { scan-assembler-times "lvtrx" 37 } } */ | ||
2457 | + | ||
2458 | +#include <altivec.h> | ||
2459 | + | ||
2460 | +typedef __vector signed char vsc; | ||
2461 | +typedef __vector signed short vss; | ||
2462 | +typedef __vector signed int vsi; | ||
2463 | +typedef __vector unsigned char vuc; | ||
2464 | +typedef __vector unsigned short vus; | ||
2465 | +typedef __vector unsigned int vui; | ||
2466 | +typedef __vector bool char vbc; | ||
2467 | +typedef __vector bool short vbs; | ||
2468 | +typedef __vector bool int vbi; | ||
2469 | +typedef __vector float vsf; | ||
2470 | +typedef __vector pixel vp; | ||
2471 | +typedef signed char sc; | ||
2472 | +typedef signed short ss; | ||
2473 | +typedef signed int si; | ||
2474 | +typedef signed long sl; | ||
2475 | +typedef unsigned char uc; | ||
2476 | +typedef unsigned short us; | ||
2477 | +typedef unsigned int ui; | ||
2478 | +typedef unsigned long ul; | ||
2479 | +typedef float sf; | ||
2480 | + | ||
2481 | +vsc lc3(long a, void *p) { return __builtin_altivec_lvtrx (a,p); } | ||
2482 | +vsf lrx01(long a, vsf *p) { return __builtin_vec_lvtrx (a,p); } | ||
2483 | +vsf lrx02(long a, sf *p) { return __builtin_vec_lvtrx (a,p); } | ||
2484 | +vbi lrx03(long a, vbi *p) { return __builtin_vec_lvtrx (a,p); } | ||
2485 | +vsi lrx04(long a, vsi *p) { return __builtin_vec_lvtrx (a,p); } | ||
2486 | +vsi lrx05(long a, si *p) { return __builtin_vec_lvtrx (a,p); } | ||
2487 | +vui lrx06(long a, vui *p) { return __builtin_vec_lvtrx (a,p); } | ||
2488 | +vui lrx07(long a, ui *p) { return __builtin_vec_lvtrx (a,p); } | ||
2489 | +vbs lrx08(long a, vbs *p) { return __builtin_vec_lvtrx (a,p); } | ||
2490 | +vp lrx09(long a, vp *p) { return __builtin_vec_lvtrx (a,p); } | ||
2491 | +vss lrx10(long a, vss *p) { return __builtin_vec_lvtrx (a,p); } | ||
2492 | +vss lrx11(long a, ss *p) { return __builtin_vec_lvtrx (a,p); } | ||
2493 | +vus lrx12(long a, vus *p) { return __builtin_vec_lvtrx (a,p); } | ||
2494 | +vus lrx13(long a, us *p) { return __builtin_vec_lvtrx (a,p); } | ||
2495 | +vbc lrx14(long a, vbc *p) { return __builtin_vec_lvtrx (a,p); } | ||
2496 | +vsc lrx15(long a, vsc *p) { return __builtin_vec_lvtrx (a,p); } | ||
2497 | +vsc lrx16(long a, sc *p) { return __builtin_vec_lvtrx (a,p); } | ||
2498 | +vuc lrx17(long a, vuc *p) { return __builtin_vec_lvtrx (a,p); } | ||
2499 | +vuc lrx18(long a, uc *p) { return __builtin_vec_lvtrx (a,p); } | ||
2500 | +vsf Dlrx01(long a, vsf *p) { return vec_lvtrx (a,p); } | ||
2501 | +vsf Dlrx02(long a, sf *p) { return vec_lvtrx (a,p); } | ||
2502 | +vbi Dlrx03(long a, vbi *p) { return vec_lvtrx (a,p); } | ||
2503 | +vsi Dlrx04(long a, vsi *p) { return vec_lvtrx (a,p); } | ||
2504 | +vsi Dlrx05(long a, si *p) { return vec_lvtrx (a,p); } | ||
2505 | +vui Dlrx06(long a, vui *p) { return vec_lvtrx (a,p); } | ||
2506 | +vui Dlrx07(long a, ui *p) { return vec_lvtrx (a,p); } | ||
2507 | +vbs Dlrx08(long a, vbs *p) { return vec_lvtrx (a,p); } | ||
2508 | +vp Dlrx09(long a, vp *p) { return vec_lvtrx (a,p); } | ||
2509 | +vss Dlrx10(long a, vss *p) { return vec_lvtrx (a,p); } | ||
2510 | +vss Dlrx11(long a, ss *p) { return vec_lvtrx (a,p); } | ||
2511 | +vus Dlrx12(long a, vus *p) { return vec_lvtrx (a,p); } | ||
2512 | +vus Dlrx13(long a, us *p) { return vec_lvtrx (a,p); } | ||
2513 | +vbc Dlrx14(long a, vbc *p) { return vec_lvtrx (a,p); } | ||
2514 | +vsc Dlrx15(long a, vsc *p) { return vec_lvtrx (a,p); } | ||
2515 | +vsc Dlrx16(long a, sc *p) { return vec_lvtrx (a,p); } | ||
2516 | +vuc Dlrx17(long a, vuc *p) { return vec_lvtrx (a,p); } | ||
2517 | +vuc Dlrx18(long a, uc *p) { return vec_lvtrx (a,p); } | ||
2518 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-13.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-13.c | ||
2519 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-13.c 1969-12-31 18:00:00.000000000 -0600 | ||
2520 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-13.c 2012-03-06 12:31:05.153039004 -0600 | ||
2521 | @@ -0,0 +1,66 @@ | ||
2522 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2523 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2524 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2525 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2526 | +/* { dg-final { scan-assembler-times "lvtrxl" 37 } } */ | ||
2527 | + | ||
2528 | +#include <altivec.h> | ||
2529 | + | ||
2530 | +typedef __vector signed char vsc; | ||
2531 | +typedef __vector signed short vss; | ||
2532 | +typedef __vector signed int vsi; | ||
2533 | +typedef __vector unsigned char vuc; | ||
2534 | +typedef __vector unsigned short vus; | ||
2535 | +typedef __vector unsigned int vui; | ||
2536 | +typedef __vector bool char vbc; | ||
2537 | +typedef __vector bool short vbs; | ||
2538 | +typedef __vector bool int vbi; | ||
2539 | +typedef __vector float vsf; | ||
2540 | +typedef __vector pixel vp; | ||
2541 | +typedef signed char sc; | ||
2542 | +typedef signed short ss; | ||
2543 | +typedef signed int si; | ||
2544 | +typedef signed long sl; | ||
2545 | +typedef unsigned char uc; | ||
2546 | +typedef unsigned short us; | ||
2547 | +typedef unsigned int ui; | ||
2548 | +typedef unsigned long ul; | ||
2549 | +typedef float sf; | ||
2550 | + | ||
2551 | +vsc lc4(long a, void *p) { return __builtin_altivec_lvtrxl (a,p); } | ||
2552 | +vsf lrxl01(long a, vsf *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2553 | +vsf lrxl02(long a, sf *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2554 | +vbi lrxl03(long a, vbi *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2555 | +vsi lrxl04(long a, vsi *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2556 | +vsi lrxl05(long a, si *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2557 | +vui lrxl06(long a, vui *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2558 | +vui lrxl07(long a, ui *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2559 | +vbs lrxl08(long a, vbs *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2560 | +vp lrxl09(long a, vp *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2561 | +vss lrxl10(long a, vss *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2562 | +vss lrxl11(long a, ss *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2563 | +vus lrxl12(long a, vus *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2564 | +vus lrxl13(long a, us *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2565 | +vbc lrxl14(long a, vbc *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2566 | +vsc lrxl15(long a, vsc *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2567 | +vsc lrxl16(long a, sc *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2568 | +vuc lrxl17(long a, vuc *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2569 | +vuc lrxl18(long a, uc *p) { return __builtin_vec_lvtrxl (a,p); } | ||
2570 | +vsf Dlrxl01(long a, vsf *p) { return vec_lvtrxl (a,p); } | ||
2571 | +vsf Dlrxl02(long a, sf *p) { return vec_lvtrxl (a,p); } | ||
2572 | +vbi Dlrxl03(long a, vbi *p) { return vec_lvtrxl (a,p); } | ||
2573 | +vsi Dlrxl04(long a, vsi *p) { return vec_lvtrxl (a,p); } | ||
2574 | +vsi Dlrxl05(long a, si *p) { return vec_lvtrxl (a,p); } | ||
2575 | +vui Dlrxl06(long a, vui *p) { return vec_lvtrxl (a,p); } | ||
2576 | +vui Dlrxl07(long a, ui *p) { return vec_lvtrxl (a,p); } | ||
2577 | +vbs Dlrxl08(long a, vbs *p) { return vec_lvtrxl (a,p); } | ||
2578 | +vp Dlrxl09(long a, vp *p) { return vec_lvtrxl (a,p); } | ||
2579 | +vss Dlrxl10(long a, vss *p) { return vec_lvtrxl (a,p); } | ||
2580 | +vss Dlrxl11(long a, ss *p) { return vec_lvtrxl (a,p); } | ||
2581 | +vus Dlrxl12(long a, vus *p) { return vec_lvtrxl (a,p); } | ||
2582 | +vus Dlrxl13(long a, us *p) { return vec_lvtrxl (a,p); } | ||
2583 | +vbc Dlrxl14(long a, vbc *p) { return vec_lvtrxl (a,p); } | ||
2584 | +vsc Dlrxl15(long a, vsc *p) { return vec_lvtrxl (a,p); } | ||
2585 | +vsc Dlrxl16(long a, sc *p) { return vec_lvtrxl (a,p); } | ||
2586 | +vuc Dlrxl17(long a, vuc *p) { return vec_lvtrxl (a,p); } | ||
2587 | +vuc Dlrxl18(long a, uc *p) { return vec_lvtrxl (a,p); } | ||
2588 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-14.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-14.c | ||
2589 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-14.c 1969-12-31 18:00:00.000000000 -0600 | ||
2590 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-14.c 2012-03-06 12:31:05.154039003 -0600 | ||
2591 | @@ -0,0 +1,66 @@ | ||
2592 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2593 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2594 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2595 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2596 | +/* { dg-final { scan-assembler-times "stvflx" 37 } } */ | ||
2597 | + | ||
2598 | +#include <altivec.h> | ||
2599 | + | ||
2600 | +typedef __vector signed char vsc; | ||
2601 | +typedef __vector signed short vss; | ||
2602 | +typedef __vector signed int vsi; | ||
2603 | +typedef __vector unsigned char vuc; | ||
2604 | +typedef __vector unsigned short vus; | ||
2605 | +typedef __vector unsigned int vui; | ||
2606 | +typedef __vector bool char vbc; | ||
2607 | +typedef __vector bool short vbs; | ||
2608 | +typedef __vector bool int vbi; | ||
2609 | +typedef __vector float vsf; | ||
2610 | +typedef __vector pixel vp; | ||
2611 | +typedef signed char sc; | ||
2612 | +typedef signed short ss; | ||
2613 | +typedef signed int si; | ||
2614 | +typedef signed long sl; | ||
2615 | +typedef unsigned char uc; | ||
2616 | +typedef unsigned short us; | ||
2617 | +typedef unsigned int ui; | ||
2618 | +typedef unsigned long ul; | ||
2619 | +typedef float sf; | ||
2620 | + | ||
2621 | +void sc1(vsc v, long a, void *p) { __builtin_altivec_stvflx (v,a,p); } | ||
2622 | +void slx01(vsf v, long a, vsf *p) { __builtin_vec_stvflx (v,a,p); } | ||
2623 | +void slx02(vsf v, long a, sf *p) { __builtin_vec_stvflx (v,a,p); } | ||
2624 | +void slx03(vbi v, long a, vbi *p) { __builtin_vec_stvflx (v,a,p); } | ||
2625 | +void slx04(vsi v, long a, vsi *p) { __builtin_vec_stvflx (v,a,p); } | ||
2626 | +void slx05(vsi v, long a, si *p) { __builtin_vec_stvflx (v,a,p); } | ||
2627 | +void slx06(vui v, long a, vui *p) { __builtin_vec_stvflx (v,a,p); } | ||
2628 | +void slx07(vui v, long a, ui *p) { __builtin_vec_stvflx (v,a,p); } | ||
2629 | +void slx08(vbs v, long a, vbs *p) { __builtin_vec_stvflx (v,a,p); } | ||
2630 | +void slx09(vp v, long a, vp *p) { __builtin_vec_stvflx (v,a,p); } | ||
2631 | +void slx10(vss v, long a, vss *p) { __builtin_vec_stvflx (v,a,p); } | ||
2632 | +void slx11(vss v, long a, ss *p) { __builtin_vec_stvflx (v,a,p); } | ||
2633 | +void slx12(vus v, long a, vus *p) { __builtin_vec_stvflx (v,a,p); } | ||
2634 | +void slx13(vus v, long a, us *p) { __builtin_vec_stvflx (v,a,p); } | ||
2635 | +void slx14(vbc v, long a, vbc *p) { __builtin_vec_stvflx (v,a,p); } | ||
2636 | +void slx15(vsc v, long a, vsc *p) { __builtin_vec_stvflx (v,a,p); } | ||
2637 | +void slx16(vsc v, long a, sc *p) { __builtin_vec_stvflx (v,a,p); } | ||
2638 | +void slx17(vuc v, long a, vuc *p) { __builtin_vec_stvflx (v,a,p); } | ||
2639 | +void slx18(vuc v, long a, uc *p) { __builtin_vec_stvflx (v,a,p); } | ||
2640 | +void Dslx01(vsf v, long a, vsf *p) { vec_stvflx (v,a,p); } | ||
2641 | +void Dslx02(vsf v, long a, sf *p) { vec_stvflx (v,a,p); } | ||
2642 | +void Dslx03(vbi v, long a, vbi *p) { vec_stvflx (v,a,p); } | ||
2643 | +void Dslx04(vsi v, long a, vsi *p) { vec_stvflx (v,a,p); } | ||
2644 | +void Dslx05(vsi v, long a, si *p) { vec_stvflx (v,a,p); } | ||
2645 | +void Dslx06(vui v, long a, vui *p) { vec_stvflx (v,a,p); } | ||
2646 | +void Dslx07(vui v, long a, ui *p) { vec_stvflx (v,a,p); } | ||
2647 | +void Dslx08(vbs v, long a, vbs *p) { vec_stvflx (v,a,p); } | ||
2648 | +void Dslx09(vp v, long a, vp *p) { vec_stvflx (v,a,p); } | ||
2649 | +void Dslx10(vss v, long a, vss *p) { vec_stvflx (v,a,p); } | ||
2650 | +void Dslx11(vss v, long a, ss *p) { vec_stvflx (v,a,p); } | ||
2651 | +void Dslx12(vus v, long a, vus *p) { vec_stvflx (v,a,p); } | ||
2652 | +void Dslx13(vus v, long a, us *p) { vec_stvflx (v,a,p); } | ||
2653 | +void Dslx14(vbc v, long a, vbc *p) { vec_stvflx (v,a,p); } | ||
2654 | +void Dslx15(vsc v, long a, vsc *p) { vec_stvflx (v,a,p); } | ||
2655 | +void Dslx16(vsc v, long a, sc *p) { vec_stvflx (v,a,p); } | ||
2656 | +void Dslx17(vuc v, long a, vuc *p) { vec_stvflx (v,a,p); } | ||
2657 | +void Dslx18(vuc v, long a, uc *p) { vec_stvflx (v,a,p); } | ||
2658 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-15.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-15.c | ||
2659 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-15.c 1969-12-31 18:00:00.000000000 -0600 | ||
2660 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-15.c 2012-03-06 12:31:05.154039003 -0600 | ||
2661 | @@ -0,0 +1,66 @@ | ||
2662 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2663 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2664 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2665 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2666 | +/* { dg-final { scan-assembler-times "stvflxl" 37 } } */ | ||
2667 | + | ||
2668 | +#include <altivec.h> | ||
2669 | + | ||
2670 | +typedef __vector signed char vsc; | ||
2671 | +typedef __vector signed short vss; | ||
2672 | +typedef __vector signed int vsi; | ||
2673 | +typedef __vector unsigned char vuc; | ||
2674 | +typedef __vector unsigned short vus; | ||
2675 | +typedef __vector unsigned int vui; | ||
2676 | +typedef __vector bool char vbc; | ||
2677 | +typedef __vector bool short vbs; | ||
2678 | +typedef __vector bool int vbi; | ||
2679 | +typedef __vector float vsf; | ||
2680 | +typedef __vector pixel vp; | ||
2681 | +typedef signed char sc; | ||
2682 | +typedef signed short ss; | ||
2683 | +typedef signed int si; | ||
2684 | +typedef signed long sl; | ||
2685 | +typedef unsigned char uc; | ||
2686 | +typedef unsigned short us; | ||
2687 | +typedef unsigned int ui; | ||
2688 | +typedef unsigned long ul; | ||
2689 | +typedef float sf; | ||
2690 | + | ||
2691 | +void sc2(vsc v, long a, void *p) { __builtin_altivec_stvflxl (v,a,p); } | ||
2692 | +void slxl01(vsf v, long a, vsf *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2693 | +void slxl02(vsf v, long a, sf *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2694 | +void slxl03(vbi v, long a, vbi *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2695 | +void slxl04(vsi v, long a, vsi *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2696 | +void slxl05(vsi v, long a, si *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2697 | +void slxl06(vui v, long a, vui *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2698 | +void slxl07(vui v, long a, ui *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2699 | +void slxl08(vbs v, long a, vbs *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2700 | +void slxl09(vp v, long a, vp *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2701 | +void slxl10(vss v, long a, vss *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2702 | +void slxl11(vss v, long a, ss *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2703 | +void slxl12(vus v, long a, vus *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2704 | +void slxl13(vus v, long a, us *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2705 | +void slxl14(vbc v, long a, vbc *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2706 | +void slxl15(vsc v, long a, vsc *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2707 | +void slxl16(vsc v, long a, sc *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2708 | +void slxl17(vuc v, long a, vuc *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2709 | +void slxl18(vuc v, long a, uc *p) { __builtin_vec_stvflxl (v,a,p); } | ||
2710 | +void Dslxl01(vsf v, long a, vsf *p) { vec_stvflxl (v,a,p); } | ||
2711 | +void Dslxl02(vsf v, long a, sf *p) { vec_stvflxl (v,a,p); } | ||
2712 | +void Dslxl03(vbi v, long a, vbi *p) { vec_stvflxl (v,a,p); } | ||
2713 | +void Dslxl04(vsi v, long a, vsi *p) { vec_stvflxl (v,a,p); } | ||
2714 | +void Dslxl05(vsi v, long a, si *p) { vec_stvflxl (v,a,p); } | ||
2715 | +void Dslxl06(vui v, long a, vui *p) { vec_stvflxl (v,a,p); } | ||
2716 | +void Dslxl07(vui v, long a, ui *p) { vec_stvflxl (v,a,p); } | ||
2717 | +void Dslxl08(vbs v, long a, vbs *p) { vec_stvflxl (v,a,p); } | ||
2718 | +void Dslxl09(vp v, long a, vp *p) { vec_stvflxl (v,a,p); } | ||
2719 | +void Dslxl10(vss v, long a, vss *p) { vec_stvflxl (v,a,p); } | ||
2720 | +void Dslxl11(vss v, long a, ss *p) { vec_stvflxl (v,a,p); } | ||
2721 | +void Dslxl12(vus v, long a, vus *p) { vec_stvflxl (v,a,p); } | ||
2722 | +void Dslxl13(vus v, long a, us *p) { vec_stvflxl (v,a,p); } | ||
2723 | +void Dslxl14(vbc v, long a, vbc *p) { vec_stvflxl (v,a,p); } | ||
2724 | +void Dslxl15(vsc v, long a, vsc *p) { vec_stvflxl (v,a,p); } | ||
2725 | +void Dslxl16(vsc v, long a, sc *p) { vec_stvflxl (v,a,p); } | ||
2726 | +void Dslxl17(vuc v, long a, vuc *p) { vec_stvflxl (v,a,p); } | ||
2727 | +void Dslxl18(vuc v, long a, uc *p) { vec_stvflxl (v,a,p); } | ||
2728 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-16.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-16.c | ||
2729 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-16.c 1969-12-31 18:00:00.000000000 -0600 | ||
2730 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-16.c 2012-03-06 12:31:05.154039003 -0600 | ||
2731 | @@ -0,0 +1,66 @@ | ||
2732 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2733 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2734 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2735 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2736 | +/* { dg-final { scan-assembler-times "stvfrx" 37 } } */ | ||
2737 | + | ||
2738 | +#include <altivec.h> | ||
2739 | + | ||
2740 | +typedef __vector signed char vsc; | ||
2741 | +typedef __vector signed short vss; | ||
2742 | +typedef __vector signed int vsi; | ||
2743 | +typedef __vector unsigned char vuc; | ||
2744 | +typedef __vector unsigned short vus; | ||
2745 | +typedef __vector unsigned int vui; | ||
2746 | +typedef __vector bool char vbc; | ||
2747 | +typedef __vector bool short vbs; | ||
2748 | +typedef __vector bool int vbi; | ||
2749 | +typedef __vector float vsf; | ||
2750 | +typedef __vector pixel vp; | ||
2751 | +typedef signed char sc; | ||
2752 | +typedef signed short ss; | ||
2753 | +typedef signed int si; | ||
2754 | +typedef signed long sl; | ||
2755 | +typedef unsigned char uc; | ||
2756 | +typedef unsigned short us; | ||
2757 | +typedef unsigned int ui; | ||
2758 | +typedef unsigned long ul; | ||
2759 | +typedef float sf; | ||
2760 | + | ||
2761 | +void sc3(vsc v, long a, void *p) { __builtin_altivec_stvfrx (v,a,p); } | ||
2762 | +void srx01(vsf v, long a, vsf *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2763 | +void srx02(vsf v, long a, sf *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2764 | +void srx03(vbi v, long a, vbi *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2765 | +void srx04(vsi v, long a, vsi *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2766 | +void srx05(vsi v, long a, si *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2767 | +void srx06(vui v, long a, vui *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2768 | +void srx07(vui v, long a, ui *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2769 | +void srx08(vbs v, long a, vbs *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2770 | +void srx09(vp v, long a, vp *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2771 | +void srx10(vss v, long a, vss *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2772 | +void srx11(vss v, long a, ss *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2773 | +void srx12(vus v, long a, vus *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2774 | +void srx13(vus v, long a, us *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2775 | +void srx14(vbc v, long a, vbc *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2776 | +void srx15(vsc v, long a, vsc *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2777 | +void srx16(vsc v, long a, sc *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2778 | +void srx17(vuc v, long a, vuc *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2779 | +void srx18(vuc v, long a, uc *p) { __builtin_vec_stvfrx (v,a,p); } | ||
2780 | +void Dsrx01(vsf v, long a, vsf *p) { vec_stvfrx (v,a,p); } | ||
2781 | +void Dsrx02(vsf v, long a, sf *p) { vec_stvfrx (v,a,p); } | ||
2782 | +void Dsrx03(vbi v, long a, vbi *p) { vec_stvfrx (v,a,p); } | ||
2783 | +void Dsrx04(vsi v, long a, vsi *p) { vec_stvfrx (v,a,p); } | ||
2784 | +void Dsrx05(vsi v, long a, si *p) { vec_stvfrx (v,a,p); } | ||
2785 | +void Dsrx06(vui v, long a, vui *p) { vec_stvfrx (v,a,p); } | ||
2786 | +void Dsrx07(vui v, long a, ui *p) { vec_stvfrx (v,a,p); } | ||
2787 | +void Dsrx08(vbs v, long a, vbs *p) { vec_stvfrx (v,a,p); } | ||
2788 | +void Dsrx09(vp v, long a, vp *p) { vec_stvfrx (v,a,p); } | ||
2789 | +void Dsrx10(vss v, long a, vss *p) { vec_stvfrx (v,a,p); } | ||
2790 | +void Dsrx11(vss v, long a, ss *p) { vec_stvfrx (v,a,p); } | ||
2791 | +void Dsrx12(vus v, long a, vus *p) { vec_stvfrx (v,a,p); } | ||
2792 | +void Dsrx13(vus v, long a, us *p) { vec_stvfrx (v,a,p); } | ||
2793 | +void Dsrx14(vbc v, long a, vbc *p) { vec_stvfrx (v,a,p); } | ||
2794 | +void Dsrx15(vsc v, long a, vsc *p) { vec_stvfrx (v,a,p); } | ||
2795 | +void Dsrx16(vsc v, long a, sc *p) { vec_stvfrx (v,a,p); } | ||
2796 | +void Dsrx17(vuc v, long a, vuc *p) { vec_stvfrx (v,a,p); } | ||
2797 | +void Dsrx18(vuc v, long a, uc *p) { vec_stvfrx (v,a,p); } | ||
2798 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-17.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-17.c | ||
2799 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-17.c 1969-12-31 18:00:00.000000000 -0600 | ||
2800 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-17.c 2012-03-06 12:31:05.155039001 -0600 | ||
2801 | @@ -0,0 +1,66 @@ | ||
2802 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2803 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2804 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2805 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2806 | +/* { dg-final { scan-assembler-times "stvfrxl" 37 } } */ | ||
2807 | + | ||
2808 | +#include <altivec.h> | ||
2809 | + | ||
2810 | +typedef __vector signed char vsc; | ||
2811 | +typedef __vector signed short vss; | ||
2812 | +typedef __vector signed int vsi; | ||
2813 | +typedef __vector unsigned char vuc; | ||
2814 | +typedef __vector unsigned short vus; | ||
2815 | +typedef __vector unsigned int vui; | ||
2816 | +typedef __vector bool char vbc; | ||
2817 | +typedef __vector bool short vbs; | ||
2818 | +typedef __vector bool int vbi; | ||
2819 | +typedef __vector float vsf; | ||
2820 | +typedef __vector pixel vp; | ||
2821 | +typedef signed char sc; | ||
2822 | +typedef signed short ss; | ||
2823 | +typedef signed int si; | ||
2824 | +typedef signed long sl; | ||
2825 | +typedef unsigned char uc; | ||
2826 | +typedef unsigned short us; | ||
2827 | +typedef unsigned int ui; | ||
2828 | +typedef unsigned long ul; | ||
2829 | +typedef float sf; | ||
2830 | + | ||
2831 | +void sc4(vsc v, long a, void *p) { __builtin_altivec_stvfrxl (v,a,p); } | ||
2832 | +void srxl01(vsf v, long a, vsf *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2833 | +void srxl02(vsf v, long a, sf *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2834 | +void srxl03(vbi v, long a, vbi *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2835 | +void srxl04(vsi v, long a, vsi *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2836 | +void srxl05(vsi v, long a, si *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2837 | +void srxl06(vui v, long a, vui *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2838 | +void srxl07(vui v, long a, ui *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2839 | +void srxl08(vbs v, long a, vbs *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2840 | +void srxl09(vp v, long a, vp *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2841 | +void srxl10(vss v, long a, vss *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2842 | +void srxl11(vss v, long a, ss *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2843 | +void srxl12(vus v, long a, vus *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2844 | +void srxl13(vus v, long a, us *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2845 | +void srxl14(vbc v, long a, vbc *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2846 | +void srxl15(vsc v, long a, vsc *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2847 | +void srxl16(vsc v, long a, sc *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2848 | +void srxl17(vuc v, long a, vuc *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2849 | +void srxl18(vuc v, long a, uc *p) { __builtin_vec_stvfrxl (v,a,p); } | ||
2850 | +void Dsrxl01(vsf v, long a, vsf *p) { vec_stvfrxl (v,a,p); } | ||
2851 | +void Dsrxl02(vsf v, long a, sf *p) { vec_stvfrxl (v,a,p); } | ||
2852 | +void Dsrxl03(vbi v, long a, vbi *p) { vec_stvfrxl (v,a,p); } | ||
2853 | +void Dsrxl04(vsi v, long a, vsi *p) { vec_stvfrxl (v,a,p); } | ||
2854 | +void Dsrxl05(vsi v, long a, si *p) { vec_stvfrxl (v,a,p); } | ||
2855 | +void Dsrxl06(vui v, long a, vui *p) { vec_stvfrxl (v,a,p); } | ||
2856 | +void Dsrxl07(vui v, long a, ui *p) { vec_stvfrxl (v,a,p); } | ||
2857 | +void Dsrxl08(vbs v, long a, vbs *p) { vec_stvfrxl (v,a,p); } | ||
2858 | +void Dsrxl09(vp v, long a, vp *p) { vec_stvfrxl (v,a,p); } | ||
2859 | +void Dsrxl10(vss v, long a, vss *p) { vec_stvfrxl (v,a,p); } | ||
2860 | +void Dsrxl11(vss v, long a, ss *p) { vec_stvfrxl (v,a,p); } | ||
2861 | +void Dsrxl12(vus v, long a, vus *p) { vec_stvfrxl (v,a,p); } | ||
2862 | +void Dsrxl13(vus v, long a, us *p) { vec_stvfrxl (v,a,p); } | ||
2863 | +void Dsrxl14(vbc v, long a, vbc *p) { vec_stvfrxl (v,a,p); } | ||
2864 | +void Dsrxl15(vsc v, long a, vsc *p) { vec_stvfrxl (v,a,p); } | ||
2865 | +void Dsrxl16(vsc v, long a, sc *p) { vec_stvfrxl (v,a,p); } | ||
2866 | +void Dsrxl17(vuc v, long a, vuc *p) { vec_stvfrxl (v,a,p); } | ||
2867 | +void Dsrxl18(vuc v, long a, uc *p) { vec_stvfrxl (v,a,p); } | ||
2868 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-18.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-18.c | ||
2869 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-18.c 1969-12-31 18:00:00.000000000 -0600 | ||
2870 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-18.c 2012-03-06 12:31:05.155039001 -0600 | ||
2871 | @@ -0,0 +1,66 @@ | ||
2872 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2873 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2874 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2875 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2876 | +/* { dg-final { scan-assembler-times "lvswx" 37 } } */ | ||
2877 | + | ||
2878 | +#include <altivec.h> | ||
2879 | + | ||
2880 | +typedef __vector signed char vsc; | ||
2881 | +typedef __vector signed short vss; | ||
2882 | +typedef __vector signed int vsi; | ||
2883 | +typedef __vector unsigned char vuc; | ||
2884 | +typedef __vector unsigned short vus; | ||
2885 | +typedef __vector unsigned int vui; | ||
2886 | +typedef __vector bool char vbc; | ||
2887 | +typedef __vector bool short vbs; | ||
2888 | +typedef __vector bool int vbi; | ||
2889 | +typedef __vector float vsf; | ||
2890 | +typedef __vector pixel vp; | ||
2891 | +typedef signed char sc; | ||
2892 | +typedef signed short ss; | ||
2893 | +typedef signed int si; | ||
2894 | +typedef signed long sl; | ||
2895 | +typedef unsigned char uc; | ||
2896 | +typedef unsigned short us; | ||
2897 | +typedef unsigned int ui; | ||
2898 | +typedef unsigned long ul; | ||
2899 | +typedef float sf; | ||
2900 | + | ||
2901 | +vsc ls1(long a, void *p) { return __builtin_altivec_lvswx (a,p); } | ||
2902 | +vsf ls01(long a, vsf *p) { return __builtin_vec_lvswx (a,p); } | ||
2903 | +vsf ls02(long a, sf *p) { return __builtin_vec_lvswx (a,p); } | ||
2904 | +vbi ls03(long a, vbi *p) { return __builtin_vec_lvswx (a,p); } | ||
2905 | +vsi ls04(long a, vsi *p) { return __builtin_vec_lvswx (a,p); } | ||
2906 | +vsi ls05(long a, si *p) { return __builtin_vec_lvswx (a,p); } | ||
2907 | +vui ls06(long a, vui *p) { return __builtin_vec_lvswx (a,p); } | ||
2908 | +vui ls07(long a, ui *p) { return __builtin_vec_lvswx (a,p); } | ||
2909 | +vbs ls08(long a, vbs *p) { return __builtin_vec_lvswx (a,p); } | ||
2910 | +vp ls09(long a, vp *p) { return __builtin_vec_lvswx (a,p); } | ||
2911 | +vss ls10(long a, vss *p) { return __builtin_vec_lvswx (a,p); } | ||
2912 | +vss ls11(long a, ss *p) { return __builtin_vec_lvswx (a,p); } | ||
2913 | +vus ls12(long a, vus *p) { return __builtin_vec_lvswx (a,p); } | ||
2914 | +vus ls13(long a, us *p) { return __builtin_vec_lvswx (a,p); } | ||
2915 | +vbc ls14(long a, vbc *p) { return __builtin_vec_lvswx (a,p); } | ||
2916 | +vsc ls15(long a, vsc *p) { return __builtin_vec_lvswx (a,p); } | ||
2917 | +vsc ls16(long a, sc *p) { return __builtin_vec_lvswx (a,p); } | ||
2918 | +vuc ls17(long a, vuc *p) { return __builtin_vec_lvswx (a,p); } | ||
2919 | +vuc ls18(long a, uc *p) { return __builtin_vec_lvswx (a,p); } | ||
2920 | +vsf Dls01(long a, vsf *p) { return vec_lvswx (a,p); } | ||
2921 | +vsf Dls02(long a, sf *p) { return vec_lvswx (a,p); } | ||
2922 | +vbi Dls03(long a, vbi *p) { return vec_lvswx (a,p); } | ||
2923 | +vsi Dls04(long a, vsi *p) { return vec_lvswx (a,p); } | ||
2924 | +vsi Dls05(long a, si *p) { return vec_lvswx (a,p); } | ||
2925 | +vui Dls06(long a, vui *p) { return vec_lvswx (a,p); } | ||
2926 | +vui Dls07(long a, ui *p) { return vec_lvswx (a,p); } | ||
2927 | +vbs Dls08(long a, vbs *p) { return vec_lvswx (a,p); } | ||
2928 | +vp Dls09(long a, vp *p) { return vec_lvswx (a,p); } | ||
2929 | +vss Dls10(long a, vss *p) { return vec_lvswx (a,p); } | ||
2930 | +vss Dls11(long a, ss *p) { return vec_lvswx (a,p); } | ||
2931 | +vus Dls12(long a, vus *p) { return vec_lvswx (a,p); } | ||
2932 | +vus Dls13(long a, us *p) { return vec_lvswx (a,p); } | ||
2933 | +vbc Dls14(long a, vbc *p) { return vec_lvswx (a,p); } | ||
2934 | +vsc Dls15(long a, vsc *p) { return vec_lvswx (a,p); } | ||
2935 | +vsc Dls16(long a, sc *p) { return vec_lvswx (a,p); } | ||
2936 | +vuc Dls17(long a, vuc *p) { return vec_lvswx (a,p); } | ||
2937 | +vuc Dls18(long a, uc *p) { return vec_lvswx (a,p); } | ||
2938 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-19.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-19.c | ||
2939 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-19.c 1969-12-31 18:00:00.000000000 -0600 | ||
2940 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-19.c 2012-03-06 12:31:05.155039001 -0600 | ||
2941 | @@ -0,0 +1,66 @@ | ||
2942 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
2943 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
2944 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
2945 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
2946 | +/* { dg-final { scan-assembler-times "lvswxl" 37 } } */ | ||
2947 | + | ||
2948 | +#include <altivec.h> | ||
2949 | + | ||
2950 | +typedef __vector signed char vsc; | ||
2951 | +typedef __vector signed short vss; | ||
2952 | +typedef __vector signed int vsi; | ||
2953 | +typedef __vector unsigned char vuc; | ||
2954 | +typedef __vector unsigned short vus; | ||
2955 | +typedef __vector unsigned int vui; | ||
2956 | +typedef __vector bool char vbc; | ||
2957 | +typedef __vector bool short vbs; | ||
2958 | +typedef __vector bool int vbi; | ||
2959 | +typedef __vector float vsf; | ||
2960 | +typedef __vector pixel vp; | ||
2961 | +typedef signed char sc; | ||
2962 | +typedef signed short ss; | ||
2963 | +typedef signed int si; | ||
2964 | +typedef signed long sl; | ||
2965 | +typedef unsigned char uc; | ||
2966 | +typedef unsigned short us; | ||
2967 | +typedef unsigned int ui; | ||
2968 | +typedef unsigned long ul; | ||
2969 | +typedef float sf; | ||
2970 | + | ||
2971 | +vsc ls2l(long a, void *p) { return __builtin_altivec_lvswxl (a,p); } | ||
2972 | +vsf lsl01(long a, vsf *p) { return __builtin_vec_lvswxl (a,p); } | ||
2973 | +vsf lsl02(long a, sf *p) { return __builtin_vec_lvswxl (a,p); } | ||
2974 | +vbi lsl03(long a, vbi *p) { return __builtin_vec_lvswxl (a,p); } | ||
2975 | +vsi lsl04(long a, vsi *p) { return __builtin_vec_lvswxl (a,p); } | ||
2976 | +vsi lsl05(long a, si *p) { return __builtin_vec_lvswxl (a,p); } | ||
2977 | +vui lsl06(long a, vui *p) { return __builtin_vec_lvswxl (a,p); } | ||
2978 | +vui lsl07(long a, ui *p) { return __builtin_vec_lvswxl (a,p); } | ||
2979 | +vbs lsl08(long a, vbs *p) { return __builtin_vec_lvswxl (a,p); } | ||
2980 | +vp lsl09(long a, vp *p) { return __builtin_vec_lvswxl (a,p); } | ||
2981 | +vss lsl10(long a, vss *p) { return __builtin_vec_lvswxl (a,p); } | ||
2982 | +vss lsl11(long a, ss *p) { return __builtin_vec_lvswxl (a,p); } | ||
2983 | +vus lsl12(long a, vus *p) { return __builtin_vec_lvswxl (a,p); } | ||
2984 | +vus lsl13(long a, us *p) { return __builtin_vec_lvswxl (a,p); } | ||
2985 | +vbc lsl14(long a, vbc *p) { return __builtin_vec_lvswxl (a,p); } | ||
2986 | +vsc lsl15(long a, vsc *p) { return __builtin_vec_lvswxl (a,p); } | ||
2987 | +vsc lsl16(long a, sc *p) { return __builtin_vec_lvswxl (a,p); } | ||
2988 | +vuc lsl17(long a, vuc *p) { return __builtin_vec_lvswxl (a,p); } | ||
2989 | +vuc lsl18(long a, uc *p) { return __builtin_vec_lvswxl (a,p); } | ||
2990 | +vsf Dlsl01(long a, vsf *p) { return vec_lvswxl (a,p); } | ||
2991 | +vsf Dlsl02(long a, sf *p) { return vec_lvswxl (a,p); } | ||
2992 | +vbi Dlsl03(long a, vbi *p) { return vec_lvswxl (a,p); } | ||
2993 | +vsi Dlsl04(long a, vsi *p) { return vec_lvswxl (a,p); } | ||
2994 | +vsi Dlsl05(long a, si *p) { return vec_lvswxl (a,p); } | ||
2995 | +vui Dlsl06(long a, vui *p) { return vec_lvswxl (a,p); } | ||
2996 | +vui Dlsl07(long a, ui *p) { return vec_lvswxl (a,p); } | ||
2997 | +vbs Dlsl08(long a, vbs *p) { return vec_lvswxl (a,p); } | ||
2998 | +vp Dlsl09(long a, vp *p) { return vec_lvswxl (a,p); } | ||
2999 | +vss Dlsl10(long a, vss *p) { return vec_lvswxl (a,p); } | ||
3000 | +vss Dlsl11(long a, ss *p) { return vec_lvswxl (a,p); } | ||
3001 | +vus Dlsl12(long a, vus *p) { return vec_lvswxl (a,p); } | ||
3002 | +vus Dlsl13(long a, us *p) { return vec_lvswxl (a,p); } | ||
3003 | +vbc Dlsl14(long a, vbc *p) { return vec_lvswxl (a,p); } | ||
3004 | +vsc Dlsl15(long a, vsc *p) { return vec_lvswxl (a,p); } | ||
3005 | +vsc Dlsl16(long a, sc *p) { return vec_lvswxl (a,p); } | ||
3006 | +vuc Dlsl17(long a, vuc *p) { return vec_lvswxl (a,p); } | ||
3007 | +vuc Dlsl18(long a, uc *p) { return vec_lvswxl (a,p); } | ||
3008 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-1.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-1.c | ||
3009 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-1.c 1969-12-31 18:00:00.000000000 -0600 | ||
3010 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-1.c 2012-03-06 12:31:05.156039000 -0600 | ||
3011 | @@ -0,0 +1,36 @@ | ||
3012 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3013 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3014 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3015 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3016 | +/* { dg-final { scan-assembler-times "vabsdub" 7 } } */ | ||
3017 | + | ||
3018 | +#include <altivec.h> | ||
3019 | + | ||
3020 | +typedef __vector signed char vsc; | ||
3021 | +typedef __vector signed short vss; | ||
3022 | +typedef __vector signed int vsi; | ||
3023 | +typedef __vector unsigned char vuc; | ||
3024 | +typedef __vector unsigned short vus; | ||
3025 | +typedef __vector unsigned int vui; | ||
3026 | +typedef __vector bool char vbc; | ||
3027 | +typedef __vector bool short vbs; | ||
3028 | +typedef __vector bool int vbi; | ||
3029 | +typedef __vector float vsf; | ||
3030 | +typedef __vector pixel vp; | ||
3031 | +typedef signed char sc; | ||
3032 | +typedef signed short ss; | ||
3033 | +typedef signed int si; | ||
3034 | +typedef signed long sl; | ||
3035 | +typedef unsigned char uc; | ||
3036 | +typedef unsigned short us; | ||
3037 | +typedef unsigned int ui; | ||
3038 | +typedef unsigned long ul; | ||
3039 | +typedef float sf; | ||
3040 | + | ||
3041 | +vuc fa1b(vuc a, vuc b) { return __builtin_altivec_vabsdub (a,b); } | ||
3042 | +vuc ad1(vuc a, vuc b) { return __builtin_vec_absd (a,b); } | ||
3043 | +vuc ad2(vbc a, vuc b) { return __builtin_vec_absd (a,b); } | ||
3044 | +vuc ad3(vuc a, vbc b) { return __builtin_vec_absd (a,b); } | ||
3045 | +vuc Dad1(vuc a, vuc b) { return vec_absd (a,b); } | ||
3046 | +vuc Dad2(vbc a, vuc b) { return vec_absd (a,b); } | ||
3047 | +vuc Dad3(vuc a, vbc b) { return vec_absd (a,b); } | ||
3048 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-20.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-20.c | ||
3049 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-20.c 1969-12-31 18:00:00.000000000 -0600 | ||
3050 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-20.c 2012-03-06 12:31:05.156039000 -0600 | ||
3051 | @@ -0,0 +1,66 @@ | ||
3052 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3053 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3054 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3055 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3056 | +/* { dg-final { scan-assembler-times "stvswx" 37 } } */ | ||
3057 | + | ||
3058 | +#include <altivec.h> | ||
3059 | + | ||
3060 | +typedef __vector signed char vsc; | ||
3061 | +typedef __vector signed short vss; | ||
3062 | +typedef __vector signed int vsi; | ||
3063 | +typedef __vector unsigned char vuc; | ||
3064 | +typedef __vector unsigned short vus; | ||
3065 | +typedef __vector unsigned int vui; | ||
3066 | +typedef __vector bool char vbc; | ||
3067 | +typedef __vector bool short vbs; | ||
3068 | +typedef __vector bool int vbi; | ||
3069 | +typedef __vector float vsf; | ||
3070 | +typedef __vector pixel vp; | ||
3071 | +typedef signed char sc; | ||
3072 | +typedef signed short ss; | ||
3073 | +typedef signed int si; | ||
3074 | +typedef signed long sl; | ||
3075 | +typedef unsigned char uc; | ||
3076 | +typedef unsigned short us; | ||
3077 | +typedef unsigned int ui; | ||
3078 | +typedef unsigned long ul; | ||
3079 | +typedef float sf; | ||
3080 | + | ||
3081 | +void ss1(vsc v, long a, vsc *p) { __builtin_altivec_stvswx (v,a,p); } | ||
3082 | +void ssx01(vsf v, long a, vsf *p) { __builtin_vec_stvswx (v,a,p); } | ||
3083 | +void ssx02(vsf v, long a, sf *p) { __builtin_vec_stvswx (v,a,p); } | ||
3084 | +void ssx03(vbi v, long a, vbi *p) { __builtin_vec_stvswx (v,a,p); } | ||
3085 | +void ssx04(vsi v, long a, vsi *p) { __builtin_vec_stvswx (v,a,p); } | ||
3086 | +void ssx05(vsi v, long a, si *p) { __builtin_vec_stvswx (v,a,p); } | ||
3087 | +void ssx06(vui v, long a, vui *p) { __builtin_vec_stvswx (v,a,p); } | ||
3088 | +void ssx07(vui v, long a, ui *p) { __builtin_vec_stvswx (v,a,p); } | ||
3089 | +void ssx08(vbs v, long a, vbs *p) { __builtin_vec_stvswx (v,a,p); } | ||
3090 | +void ssx09(vp v, long a, vp *p) { __builtin_vec_stvswx (v,a,p); } | ||
3091 | +void ssx10(vss v, long a, vss *p) { __builtin_vec_stvswx (v,a,p); } | ||
3092 | +void ssx11(vss v, long a, ss *p) { __builtin_vec_stvswx (v,a,p); } | ||
3093 | +void ssx12(vus v, long a, vus *p) { __builtin_vec_stvswx (v,a,p); } | ||
3094 | +void ssx13(vus v, long a, us *p) { __builtin_vec_stvswx (v,a,p); } | ||
3095 | +void ssx14(vbc v, long a, vbc *p) { __builtin_vec_stvswx (v,a,p); } | ||
3096 | +void ssx15(vsc v, long a, vsc *p) { __builtin_vec_stvswx (v,a,p); } | ||
3097 | +void ssx16(vsc v, long a, sc *p) { __builtin_vec_stvswx (v,a,p); } | ||
3098 | +void ssx17(vuc v, long a, vuc *p) { __builtin_vec_stvswx (v,a,p); } | ||
3099 | +void ssx18(vuc v, long a, uc *p) { __builtin_vec_stvswx (v,a,p); } | ||
3100 | +void Dssx01(vsf v, long a, vsf *p) { vec_stvswx (v,a,p); } | ||
3101 | +void Dssx02(vsf v, long a, sf *p) { vec_stvswx (v,a,p); } | ||
3102 | +void Dssx03(vbi v, long a, vbi *p) { vec_stvswx (v,a,p); } | ||
3103 | +void Dssx04(vsi v, long a, vsi *p) { vec_stvswx (v,a,p); } | ||
3104 | +void Dssx05(vsi v, long a, si *p) { vec_stvswx (v,a,p); } | ||
3105 | +void Dssx06(vui v, long a, vui *p) { vec_stvswx (v,a,p); } | ||
3106 | +void Dssx07(vui v, long a, ui *p) { vec_stvswx (v,a,p); } | ||
3107 | +void Dssx08(vbs v, long a, vbs *p) { vec_stvswx (v,a,p); } | ||
3108 | +void Dssx09(vp v, long a, vp *p) { vec_stvswx (v,a,p); } | ||
3109 | +void Dssx10(vss v, long a, vss *p) { vec_stvswx (v,a,p); } | ||
3110 | +void Dssx11(vss v, long a, ss *p) { vec_stvswx (v,a,p); } | ||
3111 | +void Dssx12(vus v, long a, vus *p) { vec_stvswx (v,a,p); } | ||
3112 | +void Dssx13(vus v, long a, us *p) { vec_stvswx (v,a,p); } | ||
3113 | +void Dssx14(vbc v, long a, vbc *p) { vec_stvswx (v,a,p); } | ||
3114 | +void Dssx15(vsc v, long a, vsc *p) { vec_stvswx (v,a,p); } | ||
3115 | +void Dssx16(vsc v, long a, sc *p) { vec_stvswx (v,a,p); } | ||
3116 | +void Dssx17(vuc v, long a, vuc *p) { vec_stvswx (v,a,p); } | ||
3117 | +void Dssx18(vuc v, long a, uc *p) { vec_stvswx (v,a,p); } | ||
3118 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-21.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-21.c | ||
3119 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-21.c 1969-12-31 18:00:00.000000000 -0600 | ||
3120 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-21.c 2012-03-06 12:31:05.156039000 -0600 | ||
3121 | @@ -0,0 +1,66 @@ | ||
3122 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3123 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3124 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3125 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3126 | +/* { dg-final { scan-assembler-times "stvswxl" 37 } } */ | ||
3127 | + | ||
3128 | +#include <altivec.h> | ||
3129 | + | ||
3130 | +typedef __vector signed char vsc; | ||
3131 | +typedef __vector signed short vss; | ||
3132 | +typedef __vector signed int vsi; | ||
3133 | +typedef __vector unsigned char vuc; | ||
3134 | +typedef __vector unsigned short vus; | ||
3135 | +typedef __vector unsigned int vui; | ||
3136 | +typedef __vector bool char vbc; | ||
3137 | +typedef __vector bool short vbs; | ||
3138 | +typedef __vector bool int vbi; | ||
3139 | +typedef __vector float vsf; | ||
3140 | +typedef __vector pixel vp; | ||
3141 | +typedef signed char sc; | ||
3142 | +typedef signed short ss; | ||
3143 | +typedef signed int si; | ||
3144 | +typedef signed long sl; | ||
3145 | +typedef unsigned char uc; | ||
3146 | +typedef unsigned short us; | ||
3147 | +typedef unsigned int ui; | ||
3148 | +typedef unsigned long ul; | ||
3149 | +typedef float sf; | ||
3150 | + | ||
3151 | +void ss2l(vsc v, long a, vsc *p) { __builtin_altivec_stvswxl (v,a,p); } | ||
3152 | +void ssxl01(vsf v, long a, vsf *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3153 | +void ssxl02(vsf v, long a, sf *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3154 | +void ssxl03(vbi v, long a, vbi *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3155 | +void ssxl04(vsi v, long a, vsi *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3156 | +void ssxl05(vsi v, long a, si *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3157 | +void ssxl06(vui v, long a, vui *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3158 | +void ssxl07(vui v, long a, ui *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3159 | +void ssxl08(vbs v, long a, vbs *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3160 | +void ssxl09(vp v, long a, vp *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3161 | +void ssxl10(vss v, long a, vss *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3162 | +void ssxl11(vss v, long a, ss *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3163 | +void ssxl12(vus v, long a, vus *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3164 | +void ssxl13(vus v, long a, us *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3165 | +void ssxl14(vbc v, long a, vbc *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3166 | +void ssxl15(vsc v, long a, vsc *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3167 | +void ssxl16(vsc v, long a, sc *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3168 | +void ssxl17(vuc v, long a, vuc *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3169 | +void ssxl18(vuc v, long a, uc *p) { __builtin_vec_stvswxl (v,a,p); } | ||
3170 | +void Dssxl01(vsf v, long a, vsf *p) { vec_stvswxl (v,a,p); } | ||
3171 | +void Dssxl02(vsf v, long a, sf *p) { vec_stvswxl (v,a,p); } | ||
3172 | +void Dssxl03(vbi v, long a, vbi *p) { vec_stvswxl (v,a,p); } | ||
3173 | +void Dssxl04(vsi v, long a, vsi *p) { vec_stvswxl (v,a,p); } | ||
3174 | +void Dssxl05(vsi v, long a, si *p) { vec_stvswxl (v,a,p); } | ||
3175 | +void Dssxl06(vui v, long a, vui *p) { vec_stvswxl (v,a,p); } | ||
3176 | +void Dssxl07(vui v, long a, ui *p) { vec_stvswxl (v,a,p); } | ||
3177 | +void Dssxl08(vbs v, long a, vbs *p) { vec_stvswxl (v,a,p); } | ||
3178 | +void Dssxl09(vp v, long a, vp *p) { vec_stvswxl (v,a,p); } | ||
3179 | +void Dssxl10(vss v, long a, vss *p) { vec_stvswxl (v,a,p); } | ||
3180 | +void Dssxl11(vss v, long a, ss *p) { vec_stvswxl (v,a,p); } | ||
3181 | +void Dssxl12(vus v, long a, vus *p) { vec_stvswxl (v,a,p); } | ||
3182 | +void Dssxl13(vus v, long a, us *p) { vec_stvswxl (v,a,p); } | ||
3183 | +void Dssxl14(vbc v, long a, vbc *p) { vec_stvswxl (v,a,p); } | ||
3184 | +void Dssxl15(vsc v, long a, vsc *p) { vec_stvswxl (v,a,p); } | ||
3185 | +void Dssxl16(vsc v, long a, sc *p) { vec_stvswxl (v,a,p); } | ||
3186 | +void Dssxl17(vuc v, long a, vuc *p) { vec_stvswxl (v,a,p); } | ||
3187 | +void Dssxl18(vuc v, long a, uc *p) { vec_stvswxl (v,a,p); } | ||
3188 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-22.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-22.c | ||
3189 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-22.c 1969-12-31 18:00:00.000000000 -0600 | ||
3190 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-22.c 2012-03-06 12:31:05.157039001 -0600 | ||
3191 | @@ -0,0 +1,66 @@ | ||
3192 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3193 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3194 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3195 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3196 | +/* { dg-final { scan-assembler-times "lvsm" 37 } } */ | ||
3197 | + | ||
3198 | +#include <altivec.h> | ||
3199 | + | ||
3200 | +typedef __vector signed char vsc; | ||
3201 | +typedef __vector signed short vss; | ||
3202 | +typedef __vector signed int vsi; | ||
3203 | +typedef __vector unsigned char vuc; | ||
3204 | +typedef __vector unsigned short vus; | ||
3205 | +typedef __vector unsigned int vui; | ||
3206 | +typedef __vector bool char vbc; | ||
3207 | +typedef __vector bool short vbs; | ||
3208 | +typedef __vector bool int vbi; | ||
3209 | +typedef __vector float vsf; | ||
3210 | +typedef __vector pixel vp; | ||
3211 | +typedef signed char sc; | ||
3212 | +typedef signed short ss; | ||
3213 | +typedef signed int si; | ||
3214 | +typedef signed long sl; | ||
3215 | +typedef unsigned char uc; | ||
3216 | +typedef unsigned short us; | ||
3217 | +typedef unsigned int ui; | ||
3218 | +typedef unsigned long ul; | ||
3219 | +typedef float sf; | ||
3220 | + | ||
3221 | +vsc lsm(long a, void *p) { return __builtin_altivec_lvsm (a,p); } | ||
3222 | +vsf lm01(long a, vsf *p) { return __builtin_vec_lvsm (a,p); } | ||
3223 | +vsf lm02(long a, sf *p) { return __builtin_vec_lvsm (a,p); } | ||
3224 | +vbi lm03(long a, vbi *p) { return __builtin_vec_lvsm (a,p); } | ||
3225 | +vsi lm04(long a, vsi *p) { return __builtin_vec_lvsm (a,p); } | ||
3226 | +vsi lm05(long a, si *p) { return __builtin_vec_lvsm (a,p); } | ||
3227 | +vui lm06(long a, vui *p) { return __builtin_vec_lvsm (a,p); } | ||
3228 | +vui lm07(long a, ui *p) { return __builtin_vec_lvsm (a,p); } | ||
3229 | +vbs lm08(long a, vbs *p) { return __builtin_vec_lvsm (a,p); } | ||
3230 | +vp lm09(long a, vp *p) { return __builtin_vec_lvsm (a,p); } | ||
3231 | +vss lm10(long a, vss *p) { return __builtin_vec_lvsm (a,p); } | ||
3232 | +vss lm11(long a, ss *p) { return __builtin_vec_lvsm (a,p); } | ||
3233 | +vus lm12(long a, vus *p) { return __builtin_vec_lvsm (a,p); } | ||
3234 | +vus lm13(long a, us *p) { return __builtin_vec_lvsm (a,p); } | ||
3235 | +vbc lm14(long a, vbc *p) { return __builtin_vec_lvsm (a,p); } | ||
3236 | +vsc lm15(long a, vsc *p) { return __builtin_vec_lvsm (a,p); } | ||
3237 | +vsc lm16(long a, sc *p) { return __builtin_vec_lvsm (a,p); } | ||
3238 | +vuc lm17(long a, vuc *p) { return __builtin_vec_lvsm (a,p); } | ||
3239 | +vuc lm18(long a, uc *p) { return __builtin_vec_lvsm (a,p); } | ||
3240 | +vsf Dlm01(long a, vsf *p) { return vec_lvsm (a,p); } | ||
3241 | +vsf Dlm02(long a, sf *p) { return vec_lvsm (a,p); } | ||
3242 | +vbi Dlm03(long a, vbi *p) { return vec_lvsm (a,p); } | ||
3243 | +vsi Dlm04(long a, vsi *p) { return vec_lvsm (a,p); } | ||
3244 | +vsi Dlm05(long a, si *p) { return vec_lvsm (a,p); } | ||
3245 | +vui Dlm06(long a, vui *p) { return vec_lvsm (a,p); } | ||
3246 | +vui Dlm07(long a, ui *p) { return vec_lvsm (a,p); } | ||
3247 | +vbs Dlm08(long a, vbs *p) { return vec_lvsm (a,p); } | ||
3248 | +vp Dlm09(long a, vp *p) { return vec_lvsm (a,p); } | ||
3249 | +vss Dlm10(long a, vss *p) { return vec_lvsm (a,p); } | ||
3250 | +vss Dlm11(long a, ss *p) { return vec_lvsm (a,p); } | ||
3251 | +vus Dlm12(long a, vus *p) { return vec_lvsm (a,p); } | ||
3252 | +vus Dlm13(long a, us *p) { return vec_lvsm (a,p); } | ||
3253 | +vbc Dlm14(long a, vbc *p) { return vec_lvsm (a,p); } | ||
3254 | +vsc Dlm15(long a, vsc *p) { return vec_lvsm (a,p); } | ||
3255 | +vsc Dlm16(long a, sc *p) { return vec_lvsm (a,p); } | ||
3256 | +vuc Dlm17(long a, vuc *p) { return vec_lvsm (a,p); } | ||
3257 | +vuc Dlm18(long a, uc *p) { return vec_lvsm (a,p); } | ||
3258 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-2.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-2.c | ||
3259 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-2.c 1969-12-31 18:00:00.000000000 -0600 | ||
3260 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-2.c 2012-03-06 12:31:05.157039001 -0600 | ||
3261 | @@ -0,0 +1,36 @@ | ||
3262 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3263 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3264 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3265 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3266 | +/* { dg-final { scan-assembler-times "vabsduh" 7 } } */ | ||
3267 | + | ||
3268 | +#include <altivec.h> | ||
3269 | + | ||
3270 | +typedef __vector signed char vsc; | ||
3271 | +typedef __vector signed short vss; | ||
3272 | +typedef __vector signed int vsi; | ||
3273 | +typedef __vector unsigned char vuc; | ||
3274 | +typedef __vector unsigned short vus; | ||
3275 | +typedef __vector unsigned int vui; | ||
3276 | +typedef __vector bool char vbc; | ||
3277 | +typedef __vector bool short vbs; | ||
3278 | +typedef __vector bool int vbi; | ||
3279 | +typedef __vector float vsf; | ||
3280 | +typedef __vector pixel vp; | ||
3281 | +typedef signed char sc; | ||
3282 | +typedef signed short ss; | ||
3283 | +typedef signed int si; | ||
3284 | +typedef signed long sl; | ||
3285 | +typedef unsigned char uc; | ||
3286 | +typedef unsigned short us; | ||
3287 | +typedef unsigned int ui; | ||
3288 | +typedef unsigned long ul; | ||
3289 | +typedef float sf; | ||
3290 | + | ||
3291 | +vus fa2h(vus a, vus b) { return __builtin_altivec_vabsduh (a,b); } | ||
3292 | +vus ad4(vus a, vus b) { return __builtin_vec_absd (a,b); } | ||
3293 | +vus ad5(vbs a, vus b) { return __builtin_vec_absd (a,b); } | ||
3294 | +vus ad6(vus a, vbs b) { return __builtin_vec_absd (a,b); } | ||
3295 | +vus Dad4(vus a, vus b) { return vec_absd (a,b); } | ||
3296 | +vus Dad5(vbs a, vus b) { return vec_absd (a,b); } | ||
3297 | +vus Dad6(vus a, vbs b) { return vec_absd (a,b); } | ||
3298 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-3.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-3.c | ||
3299 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-3.c 1969-12-31 18:00:00.000000000 -0600 | ||
3300 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-3.c 2012-03-06 12:31:05.157039001 -0600 | ||
3301 | @@ -0,0 +1,36 @@ | ||
3302 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3303 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3304 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3305 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3306 | +/* { dg-final { scan-assembler-times "vabsduw" 7 } } */ | ||
3307 | + | ||
3308 | +#include <altivec.h> | ||
3309 | + | ||
3310 | +typedef __vector signed char vsc; | ||
3311 | +typedef __vector signed short vss; | ||
3312 | +typedef __vector signed int vsi; | ||
3313 | +typedef __vector unsigned char vuc; | ||
3314 | +typedef __vector unsigned short vus; | ||
3315 | +typedef __vector unsigned int vui; | ||
3316 | +typedef __vector bool char vbc; | ||
3317 | +typedef __vector bool short vbs; | ||
3318 | +typedef __vector bool int vbi; | ||
3319 | +typedef __vector float vsf; | ||
3320 | +typedef __vector pixel vp; | ||
3321 | +typedef signed char sc; | ||
3322 | +typedef signed short ss; | ||
3323 | +typedef signed int si; | ||
3324 | +typedef signed long sl; | ||
3325 | +typedef unsigned char uc; | ||
3326 | +typedef unsigned short us; | ||
3327 | +typedef unsigned int ui; | ||
3328 | +typedef unsigned long ul; | ||
3329 | +typedef float sf; | ||
3330 | + | ||
3331 | +vui fa3w(vui a, vui b) { return __builtin_altivec_vabsduw (a,b); } | ||
3332 | +vui ad7(vui a, vui b) { return __builtin_vec_absd (a,b); } | ||
3333 | +vui ad8(vbi a, vui b) { return __builtin_vec_absd (a,b); } | ||
3334 | +vui ad9(vui a, vbi b) { return __builtin_vec_absd (a,b); } | ||
3335 | +vui Dad7(vui a, vui b) { return vec_absd (a,b); } | ||
3336 | +vui Dad8(vbi a, vui b) { return vec_absd (a,b); } | ||
3337 | +vui Dad9(vui a, vbi b) { return vec_absd (a,b); } | ||
3338 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-4.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-4.c | ||
3339 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-4.c 1969-12-31 18:00:00.000000000 -0600 | ||
3340 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-4.c 2012-03-06 12:31:05.158039002 -0600 | ||
3341 | @@ -0,0 +1,34 @@ | ||
3342 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3343 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3344 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3345 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3346 | +/* { dg-final { scan-assembler-times "lvexbx" 5 } } */ | ||
3347 | + | ||
3348 | +#include <altivec.h> | ||
3349 | + | ||
3350 | +typedef __vector signed char vsc; | ||
3351 | +typedef __vector signed short vss; | ||
3352 | +typedef __vector signed int vsi; | ||
3353 | +typedef __vector unsigned char vuc; | ||
3354 | +typedef __vector unsigned short vus; | ||
3355 | +typedef __vector unsigned int vui; | ||
3356 | +typedef __vector bool char vbc; | ||
3357 | +typedef __vector bool short vbs; | ||
3358 | +typedef __vector bool int vbi; | ||
3359 | +typedef __vector float vsf; | ||
3360 | +typedef __vector pixel vp; | ||
3361 | +typedef signed char sc; | ||
3362 | +typedef signed short ss; | ||
3363 | +typedef signed int si; | ||
3364 | +typedef signed long sl; | ||
3365 | +typedef unsigned char uc; | ||
3366 | +typedef unsigned short us; | ||
3367 | +typedef unsigned int ui; | ||
3368 | +typedef unsigned long ul; | ||
3369 | +typedef float sf; | ||
3370 | + | ||
3371 | +vsc le1b(long a, void *p) { return __builtin_altivec_lvexbx (a,p); } | ||
3372 | +vsc leb1(long a, sc *p) { return __builtin_vec_lvexbx (a,p); } | ||
3373 | +vuc leb2(long a, uc *p) { return __builtin_vec_lvexbx (a,p); } | ||
3374 | +vsc Dleb1(long a, sc *p) { return vec_lvexbx (a,p); } | ||
3375 | +vuc Dleb2(long a, uc *p) { return vec_lvexbx (a,p); } | ||
3376 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-5.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-5.c | ||
3377 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-5.c 1969-12-31 18:00:00.000000000 -0600 | ||
3378 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-5.c 2012-03-06 12:31:05.158039002 -0600 | ||
3379 | @@ -0,0 +1,34 @@ | ||
3380 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3381 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3382 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3383 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3384 | +/* { dg-final { scan-assembler-times "lvexhx" 5 } } */ | ||
3385 | + | ||
3386 | +#include <altivec.h> | ||
3387 | + | ||
3388 | +typedef __vector signed char vsc; | ||
3389 | +typedef __vector signed short vss; | ||
3390 | +typedef __vector signed int vsi; | ||
3391 | +typedef __vector unsigned char vuc; | ||
3392 | +typedef __vector unsigned short vus; | ||
3393 | +typedef __vector unsigned int vui; | ||
3394 | +typedef __vector bool char vbc; | ||
3395 | +typedef __vector bool short vbs; | ||
3396 | +typedef __vector bool int vbi; | ||
3397 | +typedef __vector float vsf; | ||
3398 | +typedef __vector pixel vp; | ||
3399 | +typedef signed char sc; | ||
3400 | +typedef signed short ss; | ||
3401 | +typedef signed int si; | ||
3402 | +typedef signed long sl; | ||
3403 | +typedef unsigned char uc; | ||
3404 | +typedef unsigned short us; | ||
3405 | +typedef unsigned int ui; | ||
3406 | +typedef unsigned long ul; | ||
3407 | +typedef float sf; | ||
3408 | + | ||
3409 | +vss le2h(long a, void *p) { return __builtin_altivec_lvexhx (a,p); } | ||
3410 | +vss leh1(long a, ss *p) { return __builtin_vec_lvexhx (a,p); } | ||
3411 | +vus leh2(long a, us *p) { return __builtin_vec_lvexhx (a,p); } | ||
3412 | +vss Dleh1(long a, ss *p) { return vec_lvexhx (a,p); } | ||
3413 | +vus Dleh2(long a, us *p) { return vec_lvexhx (a,p); } | ||
3414 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-6.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-6.c | ||
3415 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-6.c 1969-12-31 18:00:00.000000000 -0600 | ||
3416 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-6.c 2012-03-06 12:31:05.158039002 -0600 | ||
3417 | @@ -0,0 +1,40 @@ | ||
3418 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3419 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3420 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3421 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3422 | +/* { dg-final { scan-assembler-times "lvexwx" 11 } } */ | ||
3423 | + | ||
3424 | +#include <altivec.h> | ||
3425 | + | ||
3426 | +typedef __vector signed char vsc; | ||
3427 | +typedef __vector signed short vss; | ||
3428 | +typedef __vector signed int vsi; | ||
3429 | +typedef __vector unsigned char vuc; | ||
3430 | +typedef __vector unsigned short vus; | ||
3431 | +typedef __vector unsigned int vui; | ||
3432 | +typedef __vector bool char vbc; | ||
3433 | +typedef __vector bool short vbs; | ||
3434 | +typedef __vector bool int vbi; | ||
3435 | +typedef __vector float vsf; | ||
3436 | +typedef __vector pixel vp; | ||
3437 | +typedef signed char sc; | ||
3438 | +typedef signed short ss; | ||
3439 | +typedef signed int si; | ||
3440 | +typedef signed long sl; | ||
3441 | +typedef unsigned char uc; | ||
3442 | +typedef unsigned short us; | ||
3443 | +typedef unsigned int ui; | ||
3444 | +typedef unsigned long ul; | ||
3445 | +typedef float sf; | ||
3446 | + | ||
3447 | +vsi le3w(long a, void *p) { return __builtin_altivec_lvexwx (a,p); } | ||
3448 | +vsf lew1(long a, sf *p) { return __builtin_vec_lvexwx (a,p); } | ||
3449 | +vsi lew2(long a, si *p) { return __builtin_vec_lvexwx (a,p); } | ||
3450 | +vui lew3(long a, ui *p) { return __builtin_vec_lvexwx (a,p); } | ||
3451 | +vsi lew4(long a, sl *p) { return __builtin_vec_lvexwx (a,p); } | ||
3452 | +vui lew5(long a, ul *p) { return __builtin_vec_lvexwx (a,p); } | ||
3453 | +vsf Dlew1(long a, sf *p) { return vec_lvexwx (a,p); } | ||
3454 | +vsi Dlew2(long a, si *p) { return vec_lvexwx (a,p); } | ||
3455 | +vui Dlew3(long a, ui *p) { return vec_lvexwx (a,p); } | ||
3456 | +vsi Dlew4(long a, sl *p) { return vec_lvexwx (a,p); } | ||
3457 | +vui Dlew5(long a, ul *p) { return vec_lvexwx (a,p); } | ||
3458 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-7.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-7.c | ||
3459 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-7.c 1969-12-31 18:00:00.000000000 -0600 | ||
3460 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-7.c 2012-03-06 12:31:05.159039002 -0600 | ||
3461 | @@ -0,0 +1,42 @@ | ||
3462 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3463 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3464 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3465 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3466 | +/* { dg-final { scan-assembler-times "stvexbx" 13 } } */ | ||
3467 | + | ||
3468 | +#include <altivec.h> | ||
3469 | + | ||
3470 | +typedef __vector signed char vsc; | ||
3471 | +typedef __vector signed short vss; | ||
3472 | +typedef __vector signed int vsi; | ||
3473 | +typedef __vector unsigned char vuc; | ||
3474 | +typedef __vector unsigned short vus; | ||
3475 | +typedef __vector unsigned int vui; | ||
3476 | +typedef __vector bool char vbc; | ||
3477 | +typedef __vector bool short vbs; | ||
3478 | +typedef __vector bool int vbi; | ||
3479 | +typedef __vector float vsf; | ||
3480 | +typedef __vector pixel vp; | ||
3481 | +typedef signed char sc; | ||
3482 | +typedef signed short ss; | ||
3483 | +typedef signed int si; | ||
3484 | +typedef signed long sl; | ||
3485 | +typedef unsigned char uc; | ||
3486 | +typedef unsigned short us; | ||
3487 | +typedef unsigned int ui; | ||
3488 | +typedef unsigned long ul; | ||
3489 | +typedef float sf; | ||
3490 | + | ||
3491 | +void se1b(vsc v, long a, vsc *p) { __builtin_altivec_stvexbx (v,a,p); } | ||
3492 | +void seb1(vsc v, long a, sc *p) { __builtin_vec_stvexbx (v,a,p); } | ||
3493 | +void seb2(vuc v, long a, uc *p) { __builtin_vec_stvexbx (v,a,p); } | ||
3494 | +void seb3(vbc v, long a, sc *p) { __builtin_vec_stvexbx (v,a,p); } | ||
3495 | +void seb4(vbc v, long a, uc *p) { __builtin_vec_stvexbx (v,a,p); } | ||
3496 | +void seb5(vsc v, long a, void *p) { __builtin_vec_stvexbx (v,a,p); } | ||
3497 | +void seb6(vuc v, long a, void *p) { __builtin_vec_stvexbx (v,a,p); } | ||
3498 | +void Dseb1(vsc v, long a, sc *p) { vec_stvexbx (v,a,p); } | ||
3499 | +void Dseb2(vuc v, long a, uc *p) { vec_stvexbx (v,a,p); } | ||
3500 | +void Dseb3(vbc v, long a, sc *p) { vec_stvexbx (v,a,p); } | ||
3501 | +void Dseb4(vbc v, long a, uc *p) { vec_stvexbx (v,a,p); } | ||
3502 | +void Dseb5(vsc v, long a, void *p) { vec_stvexbx (v,a,p); } | ||
3503 | +void Dseb6(vuc v, long a, void *p) { vec_stvexbx (v,a,p); } | ||
3504 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-8.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-8.c | ||
3505 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-8.c 1969-12-31 18:00:00.000000000 -0600 | ||
3506 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-8.c 2012-03-06 12:31:05.159039002 -0600 | ||
3507 | @@ -0,0 +1,42 @@ | ||
3508 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3509 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3510 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3511 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3512 | +/* { dg-final { scan-assembler-times "stvexhx" 13 } } */ | ||
3513 | + | ||
3514 | +#include <altivec.h> | ||
3515 | + | ||
3516 | +typedef __vector signed char vsc; | ||
3517 | +typedef __vector signed short vss; | ||
3518 | +typedef __vector signed int vsi; | ||
3519 | +typedef __vector unsigned char vuc; | ||
3520 | +typedef __vector unsigned short vus; | ||
3521 | +typedef __vector unsigned int vui; | ||
3522 | +typedef __vector bool char vbc; | ||
3523 | +typedef __vector bool short vbs; | ||
3524 | +typedef __vector bool int vbi; | ||
3525 | +typedef __vector float vsf; | ||
3526 | +typedef __vector pixel vp; | ||
3527 | +typedef signed char sc; | ||
3528 | +typedef signed short ss; | ||
3529 | +typedef signed int si; | ||
3530 | +typedef signed long sl; | ||
3531 | +typedef unsigned char uc; | ||
3532 | +typedef unsigned short us; | ||
3533 | +typedef unsigned int ui; | ||
3534 | +typedef unsigned long ul; | ||
3535 | +typedef float sf; | ||
3536 | + | ||
3537 | +void se2h(vss v, long a, vss *p) { __builtin_altivec_stvexhx (v,a,p); } | ||
3538 | +void seh1(vss v, long a, ss *p) { __builtin_vec_stvexhx (v,a,p); } | ||
3539 | +void seh2(vus v, long a, us *p) { __builtin_vec_stvexhx (v,a,p); } | ||
3540 | +void seh3(vbs v, long a, ss *p) { __builtin_vec_stvexhx (v,a,p); } | ||
3541 | +void seh4(vbs v, long a, us *p) { __builtin_vec_stvexhx (v,a,p); } | ||
3542 | +void seh5(vss v, long a, void *p) { __builtin_vec_stvexhx (v,a,p); } | ||
3543 | +void seh6(vus v, long a, void *p) { __builtin_vec_stvexhx (v,a,p); } | ||
3544 | +void Dseh1(vss v, long a, ss *p) { vec_stvexhx (v,a,p); } | ||
3545 | +void Dseh2(vus v, long a, us *p) { vec_stvexhx (v,a,p); } | ||
3546 | +void Dseh3(vbs v, long a, ss *p) { vec_stvexhx (v,a,p); } | ||
3547 | +void Dseh4(vbs v, long a, us *p) { vec_stvexhx (v,a,p); } | ||
3548 | +void Dseh5(vss v, long a, void *p) { vec_stvexhx (v,a,p); } | ||
3549 | +void Dseh6(vus v, long a, void *p) { vec_stvexhx (v,a,p); } | ||
3550 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-9.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-9.c | ||
3551 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-9.c 1969-12-31 18:00:00.000000000 -0600 | ||
3552 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/altivec2_builtin-9.c 2012-03-06 12:31:05.159039002 -0600 | ||
3553 | @@ -0,0 +1,46 @@ | ||
3554 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3555 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3556 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3557 | +/* { dg-options "-O2 -maltivec -maltivec2" } */ | ||
3558 | +/* { dg-final { scan-assembler-times "stvexwx" 17 } } */ | ||
3559 | + | ||
3560 | +#include <altivec.h> | ||
3561 | + | ||
3562 | +typedef __vector signed char vsc; | ||
3563 | +typedef __vector signed short vss; | ||
3564 | +typedef __vector signed int vsi; | ||
3565 | +typedef __vector unsigned char vuc; | ||
3566 | +typedef __vector unsigned short vus; | ||
3567 | +typedef __vector unsigned int vui; | ||
3568 | +typedef __vector bool char vbc; | ||
3569 | +typedef __vector bool short vbs; | ||
3570 | +typedef __vector bool int vbi; | ||
3571 | +typedef __vector float vsf; | ||
3572 | +typedef __vector pixel vp; | ||
3573 | +typedef signed char sc; | ||
3574 | +typedef signed short ss; | ||
3575 | +typedef signed int si; | ||
3576 | +typedef signed long sl; | ||
3577 | +typedef unsigned char uc; | ||
3578 | +typedef unsigned short us; | ||
3579 | +typedef unsigned int ui; | ||
3580 | +typedef unsigned long ul; | ||
3581 | +typedef float sf; | ||
3582 | + | ||
3583 | +void se3w(vsi v, long a, vsi *p) { __builtin_altivec_stvexwx (v,a,p); } | ||
3584 | +void sew1(vsf v, long a, sf *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3585 | +void sew2(vsi v, long a, si *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3586 | +void sew3(vui v, long a, ui *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3587 | +void sew4(vbi v, long a, si *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3588 | +void sew5(vbi v, long a, ui *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3589 | +void sew6(vsf v, long a, void *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3590 | +void sew7(vsi v, long a, void *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3591 | +void sew8(vui v, long a, void *p) { __builtin_vec_stvexwx (v,a,p); } | ||
3592 | +void Dsew1(vsf v, long a, sf *p) { vec_stvexwx (v,a,p); } | ||
3593 | +void Dsew2(vsi v, long a, si *p) { vec_stvexwx (v,a,p); } | ||
3594 | +void Dsew3(vui v, long a, ui *p) { vec_stvexwx (v,a,p); } | ||
3595 | +void Dsew4(vbi v, long a, si *p) { vec_stvexwx (v,a,p); } | ||
3596 | +void Dsew5(vbi v, long a, ui *p) { vec_stvexwx (v,a,p); } | ||
3597 | +void Dsew6(vsf v, long a, void *p) { vec_stvexwx (v,a,p); } | ||
3598 | +void Dsew7(vsi v, long a, void *p) { vec_stvexwx (v,a,p); } | ||
3599 | +void Dsew8(vui v, long a, void *p) { vec_stvexwx (v,a,p); } | ||
3600 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c | ||
3601 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c 1969-12-31 18:00:00.000000000 -0600 | ||
3602 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c 2012-03-06 12:31:15.921038995 -0600 | ||
3603 | @@ -0,0 +1,48 @@ | ||
3604 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3605 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3606 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3607 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3608 | +/* { dg-final { scan-assembler-times "lvlx" 19 } } */ | ||
3609 | + | ||
3610 | +#include <altivec.h> | ||
3611 | + | ||
3612 | +typedef __vector signed char vsc; | ||
3613 | +typedef __vector signed short vss; | ||
3614 | +typedef __vector signed int vsi; | ||
3615 | +typedef __vector unsigned char vuc; | ||
3616 | +typedef __vector unsigned short vus; | ||
3617 | +typedef __vector unsigned int vui; | ||
3618 | +typedef __vector bool char vbc; | ||
3619 | +typedef __vector bool short vbs; | ||
3620 | +typedef __vector bool int vbi; | ||
3621 | +typedef __vector float vsf; | ||
3622 | +typedef __vector pixel vp; | ||
3623 | +typedef signed char sc; | ||
3624 | +typedef signed short ss; | ||
3625 | +typedef signed int si; | ||
3626 | +typedef signed long sl; | ||
3627 | +typedef unsigned char uc; | ||
3628 | +typedef unsigned short us; | ||
3629 | +typedef unsigned int ui; | ||
3630 | +typedef unsigned long ul; | ||
3631 | +typedef float sf; | ||
3632 | + | ||
3633 | +vsc lc1(long a, void *p) { return __builtin_altivec_lvlx (a,p); } | ||
3634 | +vsf llx01(long a, vsf *p) { return __builtin_vec_lvlx (a,p); } | ||
3635 | +vsf llx02(long a, sf *p) { return __builtin_vec_lvlx (a,p); } | ||
3636 | +vbi llx03(long a, vbi *p) { return __builtin_vec_lvlx (a,p); } | ||
3637 | +vsi llx04(long a, vsi *p) { return __builtin_vec_lvlx (a,p); } | ||
3638 | +vsi llx05(long a, si *p) { return __builtin_vec_lvlx (a,p); } | ||
3639 | +vui llx06(long a, vui *p) { return __builtin_vec_lvlx (a,p); } | ||
3640 | +vui llx07(long a, ui *p) { return __builtin_vec_lvlx (a,p); } | ||
3641 | +vbs llx08(long a, vbs *p) { return __builtin_vec_lvlx (a,p); } | ||
3642 | +vp llx09(long a, vp *p) { return __builtin_vec_lvlx (a,p); } | ||
3643 | +vss llx10(long a, vss *p) { return __builtin_vec_lvlx (a,p); } | ||
3644 | +vss llx11(long a, ss *p) { return __builtin_vec_lvlx (a,p); } | ||
3645 | +vus llx12(long a, vus *p) { return __builtin_vec_lvlx (a,p); } | ||
3646 | +vus llx13(long a, us *p) { return __builtin_vec_lvlx (a,p); } | ||
3647 | +vbc llx14(long a, vbc *p) { return __builtin_vec_lvlx (a,p); } | ||
3648 | +vsc llx15(long a, vsc *p) { return __builtin_vec_lvlx (a,p); } | ||
3649 | +vsc llx16(long a, sc *p) { return __builtin_vec_lvlx (a,p); } | ||
3650 | +vuc llx17(long a, vuc *p) { return __builtin_vec_lvlx (a,p); } | ||
3651 | +vuc llx18(long a, uc *p) { return __builtin_vec_lvlx (a,p); } | ||
3652 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c | ||
3653 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c 1969-12-31 18:00:00.000000000 -0600 | ||
3654 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c 2012-03-06 12:31:15.921038995 -0600 | ||
3655 | @@ -0,0 +1,48 @@ | ||
3656 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3657 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3658 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3659 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3660 | +/* { dg-final { scan-assembler-times "lvlxl" 19 } } */ | ||
3661 | + | ||
3662 | +#include <altivec.h> | ||
3663 | + | ||
3664 | +typedef __vector signed char vsc; | ||
3665 | +typedef __vector signed short vss; | ||
3666 | +typedef __vector signed int vsi; | ||
3667 | +typedef __vector unsigned char vuc; | ||
3668 | +typedef __vector unsigned short vus; | ||
3669 | +typedef __vector unsigned int vui; | ||
3670 | +typedef __vector bool char vbc; | ||
3671 | +typedef __vector bool short vbs; | ||
3672 | +typedef __vector bool int vbi; | ||
3673 | +typedef __vector float vsf; | ||
3674 | +typedef __vector pixel vp; | ||
3675 | +typedef signed char sc; | ||
3676 | +typedef signed short ss; | ||
3677 | +typedef signed int si; | ||
3678 | +typedef signed long sl; | ||
3679 | +typedef unsigned char uc; | ||
3680 | +typedef unsigned short us; | ||
3681 | +typedef unsigned int ui; | ||
3682 | +typedef unsigned long ul; | ||
3683 | +typedef float sf; | ||
3684 | + | ||
3685 | +vsc lc2(long a, void *p) { return __builtin_altivec_lvlxl (a,p); } | ||
3686 | +vsf llxl01(long a, vsf *p) { return __builtin_vec_lvlxl (a,p); } | ||
3687 | +vsf llxl02(long a, sf *p) { return __builtin_vec_lvlxl (a,p); } | ||
3688 | +vbi llxl03(long a, vbi *p) { return __builtin_vec_lvlxl (a,p); } | ||
3689 | +vsi llxl04(long a, vsi *p) { return __builtin_vec_lvlxl (a,p); } | ||
3690 | +vsi llxl05(long a, si *p) { return __builtin_vec_lvlxl (a,p); } | ||
3691 | +vui llxl06(long a, vui *p) { return __builtin_vec_lvlxl (a,p); } | ||
3692 | +vui llxl07(long a, ui *p) { return __builtin_vec_lvlxl (a,p); } | ||
3693 | +vbs llxl08(long a, vbs *p) { return __builtin_vec_lvlxl (a,p); } | ||
3694 | +vp llxl09(long a, vp *p) { return __builtin_vec_lvlxl (a,p); } | ||
3695 | +vss llxl10(long a, vss *p) { return __builtin_vec_lvlxl (a,p); } | ||
3696 | +vss llxl11(long a, ss *p) { return __builtin_vec_lvlxl (a,p); } | ||
3697 | +vus llxl12(long a, vus *p) { return __builtin_vec_lvlxl (a,p); } | ||
3698 | +vus llxl13(long a, us *p) { return __builtin_vec_lvlxl (a,p); } | ||
3699 | +vbc llxl14(long a, vbc *p) { return __builtin_vec_lvlxl (a,p); } | ||
3700 | +vsc llxl15(long a, vsc *p) { return __builtin_vec_lvlxl (a,p); } | ||
3701 | +vsc llxl16(long a, sc *p) { return __builtin_vec_lvlxl (a,p); } | ||
3702 | +vuc llxl17(long a, vuc *p) { return __builtin_vec_lvlxl (a,p); } | ||
3703 | +vuc llxl18(long a, uc *p) { return __builtin_vec_lvlxl (a,p); } | ||
3704 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c | ||
3705 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c 1969-12-31 18:00:00.000000000 -0600 | ||
3706 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c 2012-03-06 12:31:15.922038996 -0600 | ||
3707 | @@ -0,0 +1,48 @@ | ||
3708 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3709 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3710 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3711 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3712 | +/* { dg-final { scan-assembler-times "lvrx" 19 } } */ | ||
3713 | + | ||
3714 | +#include <altivec.h> | ||
3715 | + | ||
3716 | +typedef __vector signed char vsc; | ||
3717 | +typedef __vector signed short vss; | ||
3718 | +typedef __vector signed int vsi; | ||
3719 | +typedef __vector unsigned char vuc; | ||
3720 | +typedef __vector unsigned short vus; | ||
3721 | +typedef __vector unsigned int vui; | ||
3722 | +typedef __vector bool char vbc; | ||
3723 | +typedef __vector bool short vbs; | ||
3724 | +typedef __vector bool int vbi; | ||
3725 | +typedef __vector float vsf; | ||
3726 | +typedef __vector pixel vp; | ||
3727 | +typedef signed char sc; | ||
3728 | +typedef signed short ss; | ||
3729 | +typedef signed int si; | ||
3730 | +typedef signed long sl; | ||
3731 | +typedef unsigned char uc; | ||
3732 | +typedef unsigned short us; | ||
3733 | +typedef unsigned int ui; | ||
3734 | +typedef unsigned long ul; | ||
3735 | +typedef float sf; | ||
3736 | + | ||
3737 | +vsc lc3(long a, void *p) { return __builtin_altivec_lvrx (a,p); } | ||
3738 | +vsf lrx01(long a, vsf *p) { return __builtin_vec_lvrx (a,p); } | ||
3739 | +vsf lrx02(long a, sf *p) { return __builtin_vec_lvrx (a,p); } | ||
3740 | +vbi lrx03(long a, vbi *p) { return __builtin_vec_lvrx (a,p); } | ||
3741 | +vsi lrx04(long a, vsi *p) { return __builtin_vec_lvrx (a,p); } | ||
3742 | +vsi lrx05(long a, si *p) { return __builtin_vec_lvrx (a,p); } | ||
3743 | +vui lrx06(long a, vui *p) { return __builtin_vec_lvrx (a,p); } | ||
3744 | +vui lrx07(long a, ui *p) { return __builtin_vec_lvrx (a,p); } | ||
3745 | +vbs lrx08(long a, vbs *p) { return __builtin_vec_lvrx (a,p); } | ||
3746 | +vp lrx09(long a, vp *p) { return __builtin_vec_lvrx (a,p); } | ||
3747 | +vss lrx10(long a, vss *p) { return __builtin_vec_lvrx (a,p); } | ||
3748 | +vss lrx11(long a, ss *p) { return __builtin_vec_lvrx (a,p); } | ||
3749 | +vus lrx12(long a, vus *p) { return __builtin_vec_lvrx (a,p); } | ||
3750 | +vus lrx13(long a, us *p) { return __builtin_vec_lvrx (a,p); } | ||
3751 | +vbc lrx14(long a, vbc *p) { return __builtin_vec_lvrx (a,p); } | ||
3752 | +vsc lrx15(long a, vsc *p) { return __builtin_vec_lvrx (a,p); } | ||
3753 | +vsc lrx16(long a, sc *p) { return __builtin_vec_lvrx (a,p); } | ||
3754 | +vuc lrx17(long a, vuc *p) { return __builtin_vec_lvrx (a,p); } | ||
3755 | +vuc lrx18(long a, uc *p) { return __builtin_vec_lvrx (a,p); } | ||
3756 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c | ||
3757 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c 1969-12-31 18:00:00.000000000 -0600 | ||
3758 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c 2012-03-06 12:31:15.922038996 -0600 | ||
3759 | @@ -0,0 +1,48 @@ | ||
3760 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3761 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3762 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3763 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3764 | +/* { dg-final { scan-assembler-times "lvrxl" 19 } } */ | ||
3765 | + | ||
3766 | +#include <altivec.h> | ||
3767 | + | ||
3768 | +typedef __vector signed char vsc; | ||
3769 | +typedef __vector signed short vss; | ||
3770 | +typedef __vector signed int vsi; | ||
3771 | +typedef __vector unsigned char vuc; | ||
3772 | +typedef __vector unsigned short vus; | ||
3773 | +typedef __vector unsigned int vui; | ||
3774 | +typedef __vector bool char vbc; | ||
3775 | +typedef __vector bool short vbs; | ||
3776 | +typedef __vector bool int vbi; | ||
3777 | +typedef __vector float vsf; | ||
3778 | +typedef __vector pixel vp; | ||
3779 | +typedef signed char sc; | ||
3780 | +typedef signed short ss; | ||
3781 | +typedef signed int si; | ||
3782 | +typedef signed long sl; | ||
3783 | +typedef unsigned char uc; | ||
3784 | +typedef unsigned short us; | ||
3785 | +typedef unsigned int ui; | ||
3786 | +typedef unsigned long ul; | ||
3787 | +typedef float sf; | ||
3788 | + | ||
3789 | +vsc lc4(long a, void *p) { return __builtin_altivec_lvrxl (a,p); } | ||
3790 | +vsf lrxl01(long a, vsf *p) { return __builtin_vec_lvrxl (a,p); } | ||
3791 | +vsf lrxl02(long a, sf *p) { return __builtin_vec_lvrxl (a,p); } | ||
3792 | +vbi lrxl03(long a, vbi *p) { return __builtin_vec_lvrxl (a,p); } | ||
3793 | +vsi lrxl04(long a, vsi *p) { return __builtin_vec_lvrxl (a,p); } | ||
3794 | +vsi lrxl05(long a, si *p) { return __builtin_vec_lvrxl (a,p); } | ||
3795 | +vui lrxl06(long a, vui *p) { return __builtin_vec_lvrxl (a,p); } | ||
3796 | +vui lrxl07(long a, ui *p) { return __builtin_vec_lvrxl (a,p); } | ||
3797 | +vbs lrxl08(long a, vbs *p) { return __builtin_vec_lvrxl (a,p); } | ||
3798 | +vp lrxl09(long a, vp *p) { return __builtin_vec_lvrxl (a,p); } | ||
3799 | +vss lrxl10(long a, vss *p) { return __builtin_vec_lvrxl (a,p); } | ||
3800 | +vss lrxl11(long a, ss *p) { return __builtin_vec_lvrxl (a,p); } | ||
3801 | +vus lrxl12(long a, vus *p) { return __builtin_vec_lvrxl (a,p); } | ||
3802 | +vus lrxl13(long a, us *p) { return __builtin_vec_lvrxl (a,p); } | ||
3803 | +vbc lrxl14(long a, vbc *p) { return __builtin_vec_lvrxl (a,p); } | ||
3804 | +vsc lrxl15(long a, vsc *p) { return __builtin_vec_lvrxl (a,p); } | ||
3805 | +vsc lrxl16(long a, sc *p) { return __builtin_vec_lvrxl (a,p); } | ||
3806 | +vuc lrxl17(long a, vuc *p) { return __builtin_vec_lvrxl (a,p); } | ||
3807 | +vuc lrxl18(long a, uc *p) { return __builtin_vec_lvrxl (a,p); } | ||
3808 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c | ||
3809 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c 1969-12-31 18:00:00.000000000 -0600 | ||
3810 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c 2012-03-06 12:31:15.922038996 -0600 | ||
3811 | @@ -0,0 +1,48 @@ | ||
3812 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3813 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3814 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3815 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3816 | +/* { dg-final { scan-assembler-times "stvlx" 19 } } */ | ||
3817 | + | ||
3818 | +#include <altivec.h> | ||
3819 | + | ||
3820 | +typedef __vector signed char vsc; | ||
3821 | +typedef __vector signed short vss; | ||
3822 | +typedef __vector signed int vsi; | ||
3823 | +typedef __vector unsigned char vuc; | ||
3824 | +typedef __vector unsigned short vus; | ||
3825 | +typedef __vector unsigned int vui; | ||
3826 | +typedef __vector bool char vbc; | ||
3827 | +typedef __vector bool short vbs; | ||
3828 | +typedef __vector bool int vbi; | ||
3829 | +typedef __vector float vsf; | ||
3830 | +typedef __vector pixel vp; | ||
3831 | +typedef signed char sc; | ||
3832 | +typedef signed short ss; | ||
3833 | +typedef signed int si; | ||
3834 | +typedef signed long sl; | ||
3835 | +typedef unsigned char uc; | ||
3836 | +typedef unsigned short us; | ||
3837 | +typedef unsigned int ui; | ||
3838 | +typedef unsigned long ul; | ||
3839 | +typedef float sf; | ||
3840 | + | ||
3841 | +void sc1(vsc v, long a, void *p) { __builtin_altivec_stvlx (v,a,p); } | ||
3842 | +void slx01(vsf v, long a, vsf *p) { __builtin_vec_stvlx (v,a,p); } | ||
3843 | +void slx02(vsf v, long a, sf *p) { __builtin_vec_stvlx (v,a,p); } | ||
3844 | +void slx03(vbi v, long a, vbi *p) { __builtin_vec_stvlx (v,a,p); } | ||
3845 | +void slx04(vsi v, long a, vsi *p) { __builtin_vec_stvlx (v,a,p); } | ||
3846 | +void slx05(vsi v, long a, si *p) { __builtin_vec_stvlx (v,a,p); } | ||
3847 | +void slx06(vui v, long a, vui *p) { __builtin_vec_stvlx (v,a,p); } | ||
3848 | +void slx07(vui v, long a, ui *p) { __builtin_vec_stvlx (v,a,p); } | ||
3849 | +void slx08(vbs v, long a, vbs *p) { __builtin_vec_stvlx (v,a,p); } | ||
3850 | +void slx09(vp v, long a, vp *p) { __builtin_vec_stvlx (v,a,p); } | ||
3851 | +void slx10(vss v, long a, vss *p) { __builtin_vec_stvlx (v,a,p); } | ||
3852 | +void slx11(vss v, long a, ss *p) { __builtin_vec_stvlx (v,a,p); } | ||
3853 | +void slx12(vus v, long a, vus *p) { __builtin_vec_stvlx (v,a,p); } | ||
3854 | +void slx13(vus v, long a, us *p) { __builtin_vec_stvlx (v,a,p); } | ||
3855 | +void slx14(vbc v, long a, vbc *p) { __builtin_vec_stvlx (v,a,p); } | ||
3856 | +void slx15(vsc v, long a, vsc *p) { __builtin_vec_stvlx (v,a,p); } | ||
3857 | +void slx16(vsc v, long a, sc *p) { __builtin_vec_stvlx (v,a,p); } | ||
3858 | +void slx17(vuc v, long a, vuc *p) { __builtin_vec_stvlx (v,a,p); } | ||
3859 | +void slx18(vuc v, long a, uc *p) { __builtin_vec_stvlx (v,a,p); } | ||
3860 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c | ||
3861 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c 1969-12-31 18:00:00.000000000 -0600 | ||
3862 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c 2012-03-06 12:31:15.923039000 -0600 | ||
3863 | @@ -0,0 +1,48 @@ | ||
3864 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3865 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3866 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3867 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3868 | +/* { dg-final { scan-assembler-times "stvlxl" 19 } } */ | ||
3869 | + | ||
3870 | +#include <altivec.h> | ||
3871 | + | ||
3872 | +typedef __vector signed char vsc; | ||
3873 | +typedef __vector signed short vss; | ||
3874 | +typedef __vector signed int vsi; | ||
3875 | +typedef __vector unsigned char vuc; | ||
3876 | +typedef __vector unsigned short vus; | ||
3877 | +typedef __vector unsigned int vui; | ||
3878 | +typedef __vector bool char vbc; | ||
3879 | +typedef __vector bool short vbs; | ||
3880 | +typedef __vector bool int vbi; | ||
3881 | +typedef __vector float vsf; | ||
3882 | +typedef __vector pixel vp; | ||
3883 | +typedef signed char sc; | ||
3884 | +typedef signed short ss; | ||
3885 | +typedef signed int si; | ||
3886 | +typedef signed long sl; | ||
3887 | +typedef unsigned char uc; | ||
3888 | +typedef unsigned short us; | ||
3889 | +typedef unsigned int ui; | ||
3890 | +typedef unsigned long ul; | ||
3891 | +typedef float sf; | ||
3892 | + | ||
3893 | +void sc2(vsc v, long a, void *p) { __builtin_altivec_stvlxl (v,a,p); } | ||
3894 | +void slxl01(vsf v, long a, vsf *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3895 | +void slxl02(vsf v, long a, sf *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3896 | +void slxl03(vbi v, long a, vbi *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3897 | +void slxl04(vsi v, long a, vsi *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3898 | +void slxl05(vsi v, long a, si *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3899 | +void slxl06(vui v, long a, vui *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3900 | +void slxl07(vui v, long a, ui *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3901 | +void slxl08(vbs v, long a, vbs *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3902 | +void slxl09(vp v, long a, vp *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3903 | +void slxl10(vss v, long a, vss *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3904 | +void slxl11(vss v, long a, ss *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3905 | +void slxl12(vus v, long a, vus *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3906 | +void slxl13(vus v, long a, us *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3907 | +void slxl14(vbc v, long a, vbc *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3908 | +void slxl15(vsc v, long a, vsc *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3909 | +void slxl16(vsc v, long a, sc *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3910 | +void slxl17(vuc v, long a, vuc *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3911 | +void slxl18(vuc v, long a, uc *p) { __builtin_vec_stvlxl (v,a,p); } | ||
3912 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c | ||
3913 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c 1969-12-31 18:00:00.000000000 -0600 | ||
3914 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c 2012-03-06 12:31:15.923039000 -0600 | ||
3915 | @@ -0,0 +1,48 @@ | ||
3916 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3917 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3918 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3919 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3920 | +/* { dg-final { scan-assembler-times "stvrx" 19 } } */ | ||
3921 | + | ||
3922 | +#include <altivec.h> | ||
3923 | + | ||
3924 | +typedef __vector signed char vsc; | ||
3925 | +typedef __vector signed short vss; | ||
3926 | +typedef __vector signed int vsi; | ||
3927 | +typedef __vector unsigned char vuc; | ||
3928 | +typedef __vector unsigned short vus; | ||
3929 | +typedef __vector unsigned int vui; | ||
3930 | +typedef __vector bool char vbc; | ||
3931 | +typedef __vector bool short vbs; | ||
3932 | +typedef __vector bool int vbi; | ||
3933 | +typedef __vector float vsf; | ||
3934 | +typedef __vector pixel vp; | ||
3935 | +typedef signed char sc; | ||
3936 | +typedef signed short ss; | ||
3937 | +typedef signed int si; | ||
3938 | +typedef signed long sl; | ||
3939 | +typedef unsigned char uc; | ||
3940 | +typedef unsigned short us; | ||
3941 | +typedef unsigned int ui; | ||
3942 | +typedef unsigned long ul; | ||
3943 | +typedef float sf; | ||
3944 | + | ||
3945 | +void sc3(vsc v, long a, void *p) { __builtin_altivec_stvrx (v,a,p); } | ||
3946 | +void srx01(vsf v, long a, vsf *p) { __builtin_vec_stvrx (v,a,p); } | ||
3947 | +void srx02(vsf v, long a, sf *p) { __builtin_vec_stvrx (v,a,p); } | ||
3948 | +void srx03(vbi v, long a, vbi *p) { __builtin_vec_stvrx (v,a,p); } | ||
3949 | +void srx04(vsi v, long a, vsi *p) { __builtin_vec_stvrx (v,a,p); } | ||
3950 | +void srx05(vsi v, long a, si *p) { __builtin_vec_stvrx (v,a,p); } | ||
3951 | +void srx06(vui v, long a, vui *p) { __builtin_vec_stvrx (v,a,p); } | ||
3952 | +void srx07(vui v, long a, ui *p) { __builtin_vec_stvrx (v,a,p); } | ||
3953 | +void srx08(vbs v, long a, vbs *p) { __builtin_vec_stvrx (v,a,p); } | ||
3954 | +void srx09(vp v, long a, vp *p) { __builtin_vec_stvrx (v,a,p); } | ||
3955 | +void srx10(vss v, long a, vss *p) { __builtin_vec_stvrx (v,a,p); } | ||
3956 | +void srx11(vss v, long a, ss *p) { __builtin_vec_stvrx (v,a,p); } | ||
3957 | +void srx12(vus v, long a, vus *p) { __builtin_vec_stvrx (v,a,p); } | ||
3958 | +void srx13(vus v, long a, us *p) { __builtin_vec_stvrx (v,a,p); } | ||
3959 | +void srx14(vbc v, long a, vbc *p) { __builtin_vec_stvrx (v,a,p); } | ||
3960 | +void srx15(vsc v, long a, vsc *p) { __builtin_vec_stvrx (v,a,p); } | ||
3961 | +void srx16(vsc v, long a, sc *p) { __builtin_vec_stvrx (v,a,p); } | ||
3962 | +void srx17(vuc v, long a, vuc *p) { __builtin_vec_stvrx (v,a,p); } | ||
3963 | +void srx18(vuc v, long a, uc *p) { __builtin_vec_stvrx (v,a,p); } | ||
3964 | diff -ruN gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c | ||
3965 | --- gcc-4.6.2-orig/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c 1969-12-31 18:00:00.000000000 -0600 | ||
3966 | +++ gcc-4.6.2/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c 2012-03-06 12:31:15.923039000 -0600 | ||
3967 | @@ -0,0 +1,48 @@ | ||
3968 | +/* { dg-do compile { target { powerpc*-*-* } } } */ | ||
3969 | +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ | ||
3970 | +/* { dg-require-effective-target powerpc_altivec_ok } */ | ||
3971 | +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ | ||
3972 | +/* { dg-final { scan-assembler-times "stvrxl" 19 } } */ | ||
3973 | + | ||
3974 | +#include <altivec.h> | ||
3975 | + | ||
3976 | +typedef __vector signed char vsc; | ||
3977 | +typedef __vector signed short vss; | ||
3978 | +typedef __vector signed int vsi; | ||
3979 | +typedef __vector unsigned char vuc; | ||
3980 | +typedef __vector unsigned short vus; | ||
3981 | +typedef __vector unsigned int vui; | ||
3982 | +typedef __vector bool char vbc; | ||
3983 | +typedef __vector bool short vbs; | ||
3984 | +typedef __vector bool int vbi; | ||
3985 | +typedef __vector float vsf; | ||
3986 | +typedef __vector pixel vp; | ||
3987 | +typedef signed char sc; | ||
3988 | +typedef signed short ss; | ||
3989 | +typedef signed int si; | ||
3990 | +typedef signed long sl; | ||
3991 | +typedef unsigned char uc; | ||
3992 | +typedef unsigned short us; | ||
3993 | +typedef unsigned int ui; | ||
3994 | +typedef unsigned long ul; | ||
3995 | +typedef float sf; | ||
3996 | + | ||
3997 | +void sc4(vsc v, long a, void *p) { __builtin_altivec_stvrxl (v,a,p); } | ||
3998 | +void srxl01(vsf v, long a, vsf *p) { __builtin_vec_stvrxl (v,a,p); } | ||
3999 | +void srxl02(vsf v, long a, sf *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4000 | +void srxl03(vbi v, long a, vbi *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4001 | +void srxl04(vsi v, long a, vsi *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4002 | +void srxl05(vsi v, long a, si *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4003 | +void srxl06(vui v, long a, vui *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4004 | +void srxl07(vui v, long a, ui *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4005 | +void srxl08(vbs v, long a, vbs *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4006 | +void srxl09(vp v, long a, vp *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4007 | +void srxl10(vss v, long a, vss *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4008 | +void srxl11(vss v, long a, ss *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4009 | +void srxl12(vus v, long a, vus *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4010 | +void srxl13(vus v, long a, us *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4011 | +void srxl14(vbc v, long a, vbc *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4012 | +void srxl15(vsc v, long a, vsc *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4013 | +void srxl16(vsc v, long a, sc *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4014 | +void srxl17(vuc v, long a, vuc *p) { __builtin_vec_stvrxl (v,a,p); } | ||
4015 | +void srxl18(vuc v, long a, uc *p) { __builtin_vec_stvrxl (v,a,p); } | ||
diff --git a/meta/recipes-devtools/gcc/gcc-4.6/gcc.no_power_builtins.patch b/meta/recipes-devtools/gcc/gcc-4.6/gcc.no_power_builtins.patch new file mode 100644 index 0000000000..3f69f29ace --- /dev/null +++ b/meta/recipes-devtools/gcc/gcc-4.6/gcc.no_power_builtins.patch | |||
@@ -0,0 +1,30 @@ | |||
1 | Upstream-Status: Pending | ||
2 | |||
3 | People are working to include this fixes upstream | ||
4 | |||
5 | --- gcc-4.6.3/gcc/config/rs6000/rs6000-c.c-orig 2012-07-10 12:16:59.708254001 -0500 | ||
6 | +++ gcc-4.6.3/gcc/config/rs6000/rs6000-c.c 2012-07-10 12:18:58.625254001 -0500 | ||
7 | @@ -272,19 +272,19 @@ | ||
8 | builtin_define ("_ARCH_PPCGR"); | ||
9 | if (TARGET_POWERPC64) | ||
10 | builtin_define ("_ARCH_PPC64"); | ||
11 | - if (TARGET_MFCRF) | ||
12 | + if (TARGET_MFCRF && rs6000_cpu != PROCESSOR_PPCE6500) | ||
13 | builtin_define ("_ARCH_PWR4"); | ||
14 | - if (TARGET_POPCNTB) | ||
15 | + if (TARGET_POPCNTB && rs6000_cpu != PROCESSOR_PPCE5500 && rs6000_cpu != PROCESSOR_PPCE6500) | ||
16 | builtin_define ("_ARCH_PWR5"); | ||
17 | if (TARGET_FPRND) | ||
18 | builtin_define ("_ARCH_PWR5X"); | ||
19 | - if (TARGET_CMPB) | ||
20 | + if (TARGET_CMPB && rs6000_cpu != PROCESSOR_PPCE5500 && rs6000_cpu != PROCESSOR_PPCE6500) | ||
21 | builtin_define ("_ARCH_PWR6"); | ||
22 | if (TARGET_MFPGPR) | ||
23 | builtin_define ("_ARCH_PWR6X"); | ||
24 | if (! TARGET_POWER && ! TARGET_POWER2 && ! TARGET_POWERPC) | ||
25 | builtin_define ("_ARCH_COM"); | ||
26 | - if (TARGET_POPCNTD) | ||
27 | + if (TARGET_POPCNTD && rs6000_cpu != PROCESSOR_PPCE5500 && rs6000_cpu != PROCESSOR_PPCE6500) | ||
28 | builtin_define ("_ARCH_PWR7"); | ||
29 | if (TARGET_ALTIVEC) | ||
30 | { | ||
diff --git a/meta/recipes-devtools/gcc/gcc-4.6/powerpc-e5500.patch b/meta/recipes-devtools/gcc/gcc-4.6/powerpc-e5500.patch deleted file mode 100644 index 1f478f3ea7..0000000000 --- a/meta/recipes-devtools/gcc/gcc-4.6/powerpc-e5500.patch +++ /dev/null | |||
@@ -1,465 +0,0 @@ | |||
1 | Upstream-Status: Pending | ||
2 | |||
3 | Implements basic e5500 enablement in gcc, with a scheduler, -mcpu | ||
4 | flag, etc... | ||
5 | |||
6 | Also splits the masks for popcntb, popcntd, and cmpb. Originally those | ||
7 | masks would also control other instructions that e5500 does not | ||
8 | support (so, we either get none or all). | ||
9 | |||
10 | For the lack of means to do tests, those instructions were never | ||
11 | enabled until now. The new instructions enabled with this patch are: | ||
12 | popcntb, popcntw, popcntd, bpermd, prtyw, prtyd, cmpb, ldbrx, and | ||
13 | stdbrx. | ||
14 | |||
15 | Signed-off-by: Edmar Wienskoski <edmar@freescale.com> | ||
16 | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> | ||
17 | |||
18 | Index: gcc-4_6-branch/gcc/config.gcc | ||
19 | =================================================================== | ||
20 | --- gcc-4_6-branch.orig/gcc/config.gcc | ||
21 | +++ gcc-4_6-branch/gcc/config.gcc | ||
22 | @@ -395,7 +395,7 @@ powerpc*-*-*) | ||
23 | extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h" | ||
24 | need_64bit_hwint=yes | ||
25 | case x$with_cpu in | ||
26 | - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64) | ||
27 | + xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500) | ||
28 | cpu_is_64bit=yes | ||
29 | ;; | ||
30 | esac | ||
31 | @@ -3493,7 +3493,7 @@ case "${target}" in | ||
32 | | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \ | ||
33 | | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \ | ||
34 | | 604 | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \ | ||
35 | - | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | titan\ | ||
36 | + | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | e5500 | titan\ | ||
37 | | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell) | ||
38 | # OK | ||
39 | ;; | ||
40 | Index: gcc-4_6-branch/gcc/config/rs6000/e5500.md | ||
41 | =================================================================== | ||
42 | --- /dev/null | ||
43 | +++ gcc-4_6-branch/gcc/config/rs6000/e5500.md | ||
44 | @@ -0,0 +1,176 @@ | ||
45 | +;; Pipeline description for Freescale PowerPC e5500 core. | ||
46 | +;; Copyright (C) 2011 Free Software Foundation, Inc. | ||
47 | +;; Contributed by Edmar Wienskoski (edmar@freescale.com) | ||
48 | +;; | ||
49 | +;; This file is part of GCC. | ||
50 | +;; | ||
51 | +;; GCC is free software; you can redistribute it and/or modify it | ||
52 | +;; under the terms of the GNU General Public License as published | ||
53 | +;; by the Free Software Foundation; either version 3, or (at your | ||
54 | +;; option) any later version. | ||
55 | +;; | ||
56 | +;; GCC is distributed in the hope that it will be useful, but WITHOUT | ||
57 | +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
58 | +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | ||
59 | +;; License for more details. | ||
60 | +;; | ||
61 | +;; You should have received a copy of the GNU General Public License | ||
62 | +;; along with GCC; see the file COPYING3. If not see | ||
63 | +;; <http://www.gnu.org/licenses/>. | ||
64 | +;; | ||
65 | +;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU | ||
66 | +;; Max issue 3 insns/clock cycle (includes 1 branch) | ||
67 | + | ||
68 | +(define_automaton "e5500_most,e5500_long") | ||
69 | +(define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most") | ||
70 | + | ||
71 | +;; SFX. | ||
72 | +(define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most") | ||
73 | + | ||
74 | +;; CFX. | ||
75 | +(define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most") | ||
76 | + | ||
77 | +;; Non-pipelined division. | ||
78 | +(define_cpu_unit "e5500_cfx_div" "e5500_long") | ||
79 | + | ||
80 | +;; LSU. | ||
81 | +(define_cpu_unit "e5500_lsu" "e5500_most") | ||
82 | + | ||
83 | +;; FPU. | ||
84 | +(define_cpu_unit "e5500_fpu" "e5500_long") | ||
85 | + | ||
86 | +;; BU. | ||
87 | +(define_cpu_unit "e5500_bu" "e5500_most") | ||
88 | + | ||
89 | +;; The following units are used to make the automata deterministic. | ||
90 | +(define_cpu_unit "present_e5500_decode_0" "e5500_most") | ||
91 | +(define_cpu_unit "present_e5500_sfx_0" "e5500_most") | ||
92 | +(presence_set "present_e5500_decode_0" "e5500_decode_0") | ||
93 | +(presence_set "present_e5500_sfx_0" "e5500_sfx_0") | ||
94 | + | ||
95 | +;; Some useful abbreviations. | ||
96 | +(define_reservation "e5500_decode" | ||
97 | + "e5500_decode_0|e5500_decode_1+present_e5500_decode_0") | ||
98 | +(define_reservation "e5500_sfx" | ||
99 | + "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0") | ||
100 | + | ||
101 | +;; SFX. | ||
102 | +(define_insn_reservation "e5500_sfx" 1 | ||
103 | + (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\ | ||
104 | + shift,cntlz,exts") | ||
105 | + (eq_attr "cpu" "ppce5500")) | ||
106 | + "e5500_decode,e5500_sfx") | ||
107 | + | ||
108 | +(define_insn_reservation "e5500_sfx2" 2 | ||
109 | + (and (eq_attr "type" "cmp,compare,fast_compare,trap") | ||
110 | + (eq_attr "cpu" "ppce5500")) | ||
111 | + "e5500_decode,e5500_sfx") | ||
112 | + | ||
113 | +(define_insn_reservation "e5500_delayed" 2 | ||
114 | + (and (eq_attr "type" "var_shift_rotate,var_delayed_compare,popcnt") | ||
115 | + (eq_attr "cpu" "ppce5500")) | ||
116 | + "e5500_decode,e5500_sfx*2") | ||
117 | + | ||
118 | +(define_insn_reservation "e5500_two" 2 | ||
119 | + (and (eq_attr "type" "two") | ||
120 | + (eq_attr "cpu" "ppce5500")) | ||
121 | + "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx") | ||
122 | + | ||
123 | +(define_insn_reservation "e5500_three" 3 | ||
124 | + (and (eq_attr "type" "three") | ||
125 | + (eq_attr "cpu" "ppce5500")) | ||
126 | + "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx") | ||
127 | + | ||
128 | +;; SFX - Mfcr. | ||
129 | +(define_insn_reservation "e5500_mfcr" 4 | ||
130 | + (and (eq_attr "type" "mfcr") | ||
131 | + (eq_attr "cpu" "ppce5500")) | ||
132 | + "e5500_decode,e5500_sfx_0*4") | ||
133 | + | ||
134 | +;; SFX - Mtcrf. | ||
135 | +(define_insn_reservation "e5500_mtcrf" 1 | ||
136 | + (and (eq_attr "type" "mtcr") | ||
137 | + (eq_attr "cpu" "ppce5500")) | ||
138 | + "e5500_decode,e5500_sfx_0") | ||
139 | + | ||
140 | +;; SFX - Mtjmpr. | ||
141 | +(define_insn_reservation "e5500_mtjmpr" 1 | ||
142 | + (and (eq_attr "type" "mtjmpr,mfjmpr") | ||
143 | + (eq_attr "cpu" "ppce5500")) | ||
144 | + "e5500_decode,e5500_sfx") | ||
145 | + | ||
146 | +;; CFX - Multiply. | ||
147 | +(define_insn_reservation "e5500_multiply" 4 | ||
148 | + (and (eq_attr "type" "imul") | ||
149 | + (eq_attr "cpu" "ppce5500")) | ||
150 | + "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1") | ||
151 | + | ||
152 | +(define_insn_reservation "e5500_multiply_i" 5 | ||
153 | + (and (eq_attr "type" "imul2,imul3,imul_compare") | ||
154 | + (eq_attr "cpu" "ppce5500")) | ||
155 | + "e5500_decode,e5500_cfx_stage0,\ | ||
156 | + e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1") | ||
157 | + | ||
158 | +;; CFX - Divide. | ||
159 | +(define_insn_reservation "e5500_divide" 16 | ||
160 | + (and (eq_attr "type" "idiv") | ||
161 | + (eq_attr "cpu" "ppce5500")) | ||
162 | + "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\ | ||
163 | + e5500_cfx_div*15") | ||
164 | + | ||
165 | +(define_insn_reservation "e5500_divide_d" 26 | ||
166 | + (and (eq_attr "type" "ldiv") | ||
167 | + (eq_attr "cpu" "ppce5500")) | ||
168 | + "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\ | ||
169 | + e5500_cfx_div*25") | ||
170 | + | ||
171 | +;; LSU - Loads. | ||
172 | +(define_insn_reservation "e5500_load" 3 | ||
173 | + (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ | ||
174 | + load_l,sync") | ||
175 | + (eq_attr "cpu" "ppce5500")) | ||
176 | + "e5500_decode,e5500_lsu") | ||
177 | + | ||
178 | +(define_insn_reservation "e5500_fpload" 4 | ||
179 | + (and (eq_attr "type" "fpload,fpload_ux,fpload_u") | ||
180 | + (eq_attr "cpu" "ppce5500")) | ||
181 | + "e5500_decode,e5500_lsu") | ||
182 | + | ||
183 | +;; LSU - Stores. | ||
184 | +(define_insn_reservation "e5500_store" 3 | ||
185 | + (and (eq_attr "type" "store,store_ux,store_u,store_c") | ||
186 | + (eq_attr "cpu" "ppce5500")) | ||
187 | + "e5500_decode,e5500_lsu") | ||
188 | + | ||
189 | +(define_insn_reservation "e5500_fpstore" 3 | ||
190 | + (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") | ||
191 | + (eq_attr "cpu" "ppce5500")) | ||
192 | + "e5500_decode,e5500_lsu") | ||
193 | + | ||
194 | +;; FP. | ||
195 | +(define_insn_reservation "e5500_float" 7 | ||
196 | + (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul") | ||
197 | + (eq_attr "cpu" "ppce5500")) | ||
198 | + "e5500_decode,e5500_fpu") | ||
199 | + | ||
200 | +(define_insn_reservation "e5500_sdiv" 20 | ||
201 | + (and (eq_attr "type" "sdiv") | ||
202 | + (eq_attr "cpu" "ppce5500")) | ||
203 | + "e5500_decode,e5500_fpu*20") | ||
204 | + | ||
205 | +(define_insn_reservation "e5500_ddiv" 35 | ||
206 | + (and (eq_attr "type" "ddiv") | ||
207 | + (eq_attr "cpu" "ppce5500")) | ||
208 | + "e5500_decode,e5500_fpu*35") | ||
209 | + | ||
210 | +;; BU. | ||
211 | +(define_insn_reservation "e5500_branch" 1 | ||
212 | + (and (eq_attr "type" "jmpreg,branch,isync") | ||
213 | + (eq_attr "cpu" "ppce5500")) | ||
214 | + "e5500_decode,e5500_bu") | ||
215 | + | ||
216 | +;; BU - CR logical. | ||
217 | +(define_insn_reservation "e5500_cr_logical" 1 | ||
218 | + (and (eq_attr "type" "cr_logical,delayed_cr") | ||
219 | + (eq_attr "cpu" "ppce5500")) | ||
220 | + "e5500_decode,e5500_bu") | ||
221 | Index: gcc-4_6-branch/gcc/config/rs6000/rs6000-opts.h | ||
222 | =================================================================== | ||
223 | --- gcc-4_6-branch.orig/gcc/config/rs6000/rs6000-opts.h | ||
224 | +++ gcc-4_6-branch/gcc/config/rs6000/rs6000-opts.h | ||
225 | @@ -53,6 +53,7 @@ enum processor_type | ||
226 | PROCESSOR_PPCE300C3, | ||
227 | PROCESSOR_PPCE500MC, | ||
228 | PROCESSOR_PPCE500MC64, | ||
229 | + PROCESSOR_PPCE5500, | ||
230 | PROCESSOR_POWER4, | ||
231 | PROCESSOR_POWER5, | ||
232 | PROCESSOR_POWER6, | ||
233 | Index: gcc-4_6-branch/gcc/config/rs6000/rs6000.c | ||
234 | =================================================================== | ||
235 | --- gcc-4_6-branch.orig/gcc/config/rs6000/rs6000.c | ||
236 | +++ gcc-4_6-branch/gcc/config/rs6000/rs6000.c | ||
237 | @@ -779,6 +779,25 @@ struct processor_costs ppce500mc64_cost | ||
238 | 1, /* prefetch streams /*/ | ||
239 | }; | ||
240 | |||
241 | +/* Instruction costs on PPCE5500 processors. */ | ||
242 | +static const | ||
243 | +struct processor_costs ppce5500_cost = { | ||
244 | + COSTS_N_INSNS (5), /* mulsi */ | ||
245 | + COSTS_N_INSNS (5), /* mulsi_const */ | ||
246 | + COSTS_N_INSNS (5), /* mulsi_const9 */ | ||
247 | + COSTS_N_INSNS (5), /* muldi */ | ||
248 | + COSTS_N_INSNS (14), /* divsi */ | ||
249 | + COSTS_N_INSNS (14), /* divdi */ | ||
250 | + COSTS_N_INSNS (7), /* fp */ | ||
251 | + COSTS_N_INSNS (10), /* dmul */ | ||
252 | + COSTS_N_INSNS (36), /* sdiv */ | ||
253 | + COSTS_N_INSNS (66), /* ddiv */ | ||
254 | + 64, /* cache line size */ | ||
255 | + 32, /* l1 cache */ | ||
256 | + 128, /* l2 cache */ | ||
257 | + 1, /* prefetch streams /*/ | ||
258 | +}; | ||
259 | + | ||
260 | /* Instruction costs on AppliedMicro Titan processors. */ | ||
261 | static const | ||
262 | struct processor_costs titan_cost = { | ||
263 | @@ -1784,6 +1803,9 @@ static struct rs6000_ptt const processor | ||
264 | | MASK_ISEL}, | ||
265 | {"e500mc64", PROCESSOR_PPCE500MC64, POWERPC_BASE_MASK | MASK_POWERPC64 | ||
266 | | MASK_PPC_GFXOPT | MASK_ISEL}, | ||
267 | + {"e5500", PROCESSOR_PPCE5500, POWERPC_BASE_MASK | MASK_POWERPC64 | ||
268 | + | MASK_PPC_GFXOPT | MASK_ISEL | MASK_CMPB | MASK_POPCNTB | ||
269 | + | MASK_POPCNTD}, | ||
270 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | ||
271 | {"970", PROCESSOR_POWER4, | ||
272 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, | ||
273 | @@ -2741,7 +2763,8 @@ rs6000_option_override_internal (bool gl | ||
274 | : PROCESSOR_DEFAULT)); | ||
275 | |||
276 | if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3 | ||
277 | - || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64) | ||
278 | + || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64 | ||
279 | + || rs6000_cpu == PROCESSOR_PPCE5500) | ||
280 | { | ||
281 | if (TARGET_ALTIVEC) | ||
282 | error ("AltiVec not supported in this target"); | ||
283 | @@ -2842,9 +2865,14 @@ rs6000_option_override_internal (bool gl | ||
284 | user's opinion, though. */ | ||
285 | if (rs6000_block_move_inline_limit == 0 | ||
286 | && (rs6000_cpu == PROCESSOR_PPCE500MC | ||
287 | - || rs6000_cpu == PROCESSOR_PPCE500MC64)) | ||
288 | + || rs6000_cpu == PROCESSOR_PPCE500MC64 | ||
289 | + || rs6000_cpu == PROCESSOR_PPCE5500)) | ||
290 | rs6000_block_move_inline_limit = 128; | ||
291 | |||
292 | + /* Those machines does not have fsqrt instruction */ | ||
293 | + if (rs6000_cpu == PROCESSOR_PPCE5500) | ||
294 | + target_flags &= ~MASK_PPC_GPOPT; | ||
295 | + | ||
296 | /* store_one_arg depends on expand_block_move to handle at least the | ||
297 | size of reg_parm_stack_space. */ | ||
298 | if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32)) | ||
299 | @@ -2976,7 +3004,8 @@ rs6000_option_override_internal (bool gl | ||
300 | #endif | ||
301 | |||
302 | if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC | ||
303 | - || rs6000_cpu == PROCESSOR_PPCE500MC64) | ||
304 | + || rs6000_cpu == PROCESSOR_PPCE500MC64 | ||
305 | + || rs6000_cpu == PROCESSOR_PPCE5500) | ||
306 | { | ||
307 | /* The e500 and e500mc do not have string instructions, and we set | ||
308 | MASK_STRING above when optimizing for size. */ | ||
309 | @@ -3023,7 +3052,8 @@ rs6000_option_override_internal (bool gl | ||
310 | || rs6000_cpu == PROCESSOR_POWER6 | ||
311 | || rs6000_cpu == PROCESSOR_POWER7 | ||
312 | || rs6000_cpu == PROCESSOR_PPCE500MC | ||
313 | - || rs6000_cpu == PROCESSOR_PPCE500MC64); | ||
314 | + || rs6000_cpu == PROCESSOR_PPCE500MC64 | ||
315 | + || rs6000_cpu == PROCESSOR_PPCE5500); | ||
316 | |||
317 | /* Allow debug switches to override the above settings. These are set to -1 | ||
318 | in rs6000.opt to indicate the user hasn't directly set the switch. */ | ||
319 | @@ -3245,6 +3275,10 @@ rs6000_option_override_internal (bool gl | ||
320 | rs6000_cost = &ppce500mc64_cost; | ||
321 | break; | ||
322 | |||
323 | + case PROCESSOR_PPCE5500: | ||
324 | + rs6000_cost = &ppce5500_cost; | ||
325 | + break; | ||
326 | + | ||
327 | case PROCESSOR_TITAN: | ||
328 | rs6000_cost = &titan_cost; | ||
329 | break; | ||
330 | @@ -23227,6 +23261,7 @@ rs6000_adjust_cost (rtx insn, rtx link, | ||
331 | || rs6000_cpu_attr == CPU_PPC750 | ||
332 | || rs6000_cpu_attr == CPU_PPC7400 | ||
333 | || rs6000_cpu_attr == CPU_PPC7450 | ||
334 | + || rs6000_cpu_attr == CPU_PPCE5500 | ||
335 | || rs6000_cpu_attr == CPU_POWER4 | ||
336 | || rs6000_cpu_attr == CPU_POWER5 | ||
337 | || rs6000_cpu_attr == CPU_POWER7 | ||
338 | @@ -23771,6 +23806,7 @@ rs6000_issue_rate (void) | ||
339 | case CPU_PPCE300C3: | ||
340 | case CPU_PPCE500MC: | ||
341 | case CPU_PPCE500MC64: | ||
342 | + case CPU_PPCE5500: | ||
343 | case CPU_TITAN: | ||
344 | return 2; | ||
345 | case CPU_RIOS2: | ||
346 | Index: gcc-4_6-branch/gcc/config/rs6000/rs6000.h | ||
347 | =================================================================== | ||
348 | --- gcc-4_6-branch.orig/gcc/config/rs6000/rs6000.h | ||
349 | +++ gcc-4_6-branch/gcc/config/rs6000/rs6000.h | ||
350 | @@ -168,6 +168,7 @@ | ||
351 | %{mcpu=e300c3: -me300} \ | ||
352 | %{mcpu=e500mc: -me500mc} \ | ||
353 | %{mcpu=e500mc64: -me500mc64} \ | ||
354 | +%{mcpu=e5500: -me5500} \ | ||
355 | %{maltivec: -maltivec} \ | ||
356 | %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ | ||
357 | -many" | ||
358 | @@ -477,13 +478,13 @@ extern int rs6000_vector_align[]; | ||
359 | |||
360 | #define TARGET_FCTIDZ TARGET_FCFID | ||
361 | #define TARGET_STFIWX TARGET_PPC_GFXOPT | ||
362 | -#define TARGET_LFIWAX TARGET_CMPB | ||
363 | -#define TARGET_LFIWZX TARGET_POPCNTD | ||
364 | -#define TARGET_FCFIDS TARGET_POPCNTD | ||
365 | -#define TARGET_FCFIDU TARGET_POPCNTD | ||
366 | -#define TARGET_FCFIDUS TARGET_POPCNTD | ||
367 | -#define TARGET_FCTIDUZ TARGET_POPCNTD | ||
368 | -#define TARGET_FCTIWUZ TARGET_POPCNTD | ||
369 | +#define TARGET_LFIWAX (TARGET_CMPB && rs6000_cpu != PROCESSOR_PPCE5500) | ||
370 | +#define TARGET_LFIWZX (TARGET_POPCNTD && rs6000_cpu != PROCESSOR_PPCE5500) | ||
371 | +#define TARGET_FCFIDS TARGET_LFIWZX | ||
372 | +#define TARGET_FCFIDU TARGET_LFIWZX | ||
373 | +#define TARGET_FCFIDUS TARGET_LFIWZX | ||
374 | +#define TARGET_FCTIDUZ TARGET_LFIWZX | ||
375 | +#define TARGET_FCTIWUZ TARGET_LFIWZX | ||
376 | |||
377 | /* E500 processors only support plain "sync", not lwsync. */ | ||
378 | #define TARGET_NO_LWSYNC TARGET_E500 | ||
379 | @@ -494,10 +495,12 @@ extern int rs6000_vector_align[]; | ||
380 | |||
381 | #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \ | ||
382 | && TARGET_DOUBLE_FLOAT \ | ||
383 | - && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) | ||
384 | + && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)) \ | ||
385 | + && rs6000_cpu != PROCESSOR_PPCE5500) | ||
386 | |||
387 | #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ | ||
388 | - && TARGET_FPRS && TARGET_SINGLE_FLOAT) | ||
389 | + && TARGET_FPRS && TARGET_SINGLE_FLOAT \ | ||
390 | + && rs6000_cpu != PROCESSOR_PPCE5500) | ||
391 | |||
392 | #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \ | ||
393 | && TARGET_DOUBLE_FLOAT \ | ||
394 | Index: gcc-4_6-branch/gcc/config/rs6000/rs6000.md | ||
395 | =================================================================== | ||
396 | --- gcc-4_6-branch.orig/gcc/config/rs6000/rs6000.md | ||
397 | +++ gcc-4_6-branch/gcc/config/rs6000/rs6000.md | ||
398 | @@ -126,7 +126,7 @@ | ||
399 | |||
400 | ;; Define an insn type attribute. This is used in function unit delay | ||
401 | ;; computations. | ||
402 | -(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel" | ||
403 | +(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt" | ||
404 | (const_string "integer")) | ||
405 | |||
406 | ;; Define floating point instruction sub-types for use with Xfpu.md | ||
407 | @@ -148,7 +148,7 @@ | ||
408 | ;; Processor type -- this attribute must exactly match the processor_type | ||
409 | ;; enumeration in rs6000.h. | ||
410 | |||
411 | -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan" | ||
412 | +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,power4,power5,power6,power7,cell,ppca2,titan" | ||
413 | (const (symbol_ref "rs6000_cpu_attr"))) | ||
414 | |||
415 | |||
416 | @@ -176,6 +176,7 @@ | ||
417 | (include "e300c2c3.md") | ||
418 | (include "e500mc.md") | ||
419 | (include "e500mc64.md") | ||
420 | +(include "e5500.md") | ||
421 | (include "power4.md") | ||
422 | (include "power5.md") | ||
423 | (include "power6.md") | ||
424 | @@ -2302,13 +2303,17 @@ | ||
425 | (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] | ||
426 | UNSPEC_POPCNTB))] | ||
427 | "TARGET_POPCNTB" | ||
428 | - "popcntb %0,%1") | ||
429 | + "popcntb %0,%1" | ||
430 | + [(set_attr "length" "4") | ||
431 | + (set_attr "type" "popcnt")]) | ||
432 | |||
433 | (define_insn "popcntd<mode>2" | ||
434 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | ||
435 | (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] | ||
436 | "TARGET_POPCNTD" | ||
437 | - "popcnt<wd> %0,%1") | ||
438 | + "popcnt<wd> %0,%1" | ||
439 | + [(set_attr "length" "4") | ||
440 | + (set_attr "type" "popcnt")]) | ||
441 | |||
442 | (define_expand "popcount<mode>2" | ||
443 | [(set (match_operand:GPR 0 "gpc_reg_operand" "") | ||
444 | @@ -5957,10 +5962,10 @@ | ||
445 | && ((TARGET_PPC_GFXOPT | ||
446 | && !HONOR_NANS (<MODE>mode) | ||
447 | && !HONOR_SIGNED_ZEROS (<MODE>mode)) | ||
448 | - || TARGET_CMPB | ||
449 | + || TARGET_LFIWAX | ||
450 | || VECTOR_UNIT_VSX_P (<MODE>mode))" | ||
451 | { | ||
452 | - if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode)) | ||
453 | + if (TARGET_LFIWAX || VECTOR_UNIT_VSX_P (<MODE>mode)) | ||
454 | { | ||
455 | emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1], | ||
456 | operands[2])); | ||
457 | @@ -5979,7 +5984,7 @@ | ||
458 | (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>") | ||
459 | (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")] | ||
460 | UNSPEC_COPYSIGN))] | ||
461 | - "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)" | ||
462 | + "TARGET_LFIWAX && !VECTOR_UNIT_VSX_P (<MODE>mode)" | ||
463 | "fcpsgn %0,%2,%1" | ||
464 | [(set_attr "type" "fp")]) | ||
465 | |||