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-rw-r--r--meta/recipes-devtools/gcc/gcc-4.9.inc24
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.9/0052-Add-target-hook-to-override-DWARF2-frame-register-si.patch138
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.9/0055-PR-rtl-optimization-61801.patch36
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.9/0055-dwarf-reg-processing-helper.patch148
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.9/0056-define-default-cfa-register-mapping.patch75
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.9/0056-top-level-reorder_gcc-bug-61144.patch31
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.9/0060-Only-allow-e500-double-in-SPE_SIMD_REGNO_P-registers.patch55
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.9/0061-target-gcc-includedir.patch (renamed from meta/recipes-devtools/gcc/gcc-4.9/target-gcc-includedir.patch)0
8 files changed, 428 insertions, 79 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.9.inc b/meta/recipes-devtools/gcc/gcc-4.9.inc
index 0f407b7d5d..3af87d1cc6 100644
--- a/meta/recipes-devtools/gcc/gcc-4.9.inc
+++ b/meta/recipes-devtools/gcc/gcc-4.9.inc
@@ -2,11 +2,11 @@ require gcc-common.inc
2 2
3# Third digit in PV should be incremented after a minor release 3# Third digit in PV should be incremented after a minor release
4 4
5PV = "4.9.1" 5PV = "4.9.2"
6 6
7# BINV should be incremented to a revision after a minor gcc release 7# BINV should be incremented to a revision after a minor gcc release
8 8
9BINV = "4.9.1" 9BINV = "4.9.2"
10 10
11FILESEXTRAPATHS =. "${FILE_DIRNAME}/gcc-4.9:" 11FILESEXTRAPATHS =. "${FILE_DIRNAME}/gcc-4.9:"
12 12
@@ -67,17 +67,19 @@ SRC_URI = "\
67 file://0049-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch \ 67 file://0049-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch \
68 file://0050-Revert-Use-dbx_reg_number-for-spanning-registers.patch \ 68 file://0050-Revert-Use-dbx_reg_number-for-spanning-registers.patch \
69 file://0051-eabispe.patch \ 69 file://0051-eabispe.patch \
70 file://0052-Add-target-hook-to-override-DWARF2-frame-register-si.patch \
70 file://0053-gcc-fix-segfault-from-calling-free-on-non-malloc-d-a.patch \ 71 file://0053-gcc-fix-segfault-from-calling-free-on-non-malloc-d-a.patch \
71 file://0054-gcc-Makefile.in-fix-parallel-building-failure.patch \ 72 file://0054-gcc-Makefile.in-fix-parallel-building-failure.patch \
72 file://0055-PR-rtl-optimization-61801.patch \ 73 file://0055-dwarf-reg-processing-helper.patch \
73 file://0056-top-level-reorder_gcc-bug-61144.patch \ 74 file://0056-define-default-cfa-register-mapping.patch \
74 file://0057-aarch64-config.patch \ 75 file://0057-aarch64-config.patch \
75 file://0058-gcc-r212171.patch \ 76 file://0058-gcc-r212171.patch \
76 file://0059-gcc-PR-rtl-optimization-63348.patch \ 77 file://0059-gcc-PR-rtl-optimization-63348.patch \
77 file://target-gcc-includedir.patch \ 78 file://0060-Only-allow-e500-double-in-SPE_SIMD_REGNO_P-registers.patch \
79 file://0061-target-gcc-includedir.patch \
78" 80"
79SRC_URI[md5sum] = "fddf71348546af523353bd43d34919c1" 81SRC_URI[md5sum] = "4df8ee253b7f3863ad0b86359cd39c43"
80SRC_URI[sha256sum] = "d334781a124ada6f38e63b545e2a3b8c2183049515a1abab6d513f109f1d717e" 82SRC_URI[sha256sum] = "2020c98295856aa13fda0f2f3a4794490757fc24bcca918d52cc8b4917b972dd"
81 83
82S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/gcc-${PV}" 84S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/gcc-${PV}"
83B = "${WORKDIR}/gcc-${PV}/build.${HOST_SYS}.${TARGET_SYS}" 85B = "${WORKDIR}/gcc-${PV}/build.${HOST_SYS}.${TARGET_SYS}"
@@ -125,10 +127,8 @@ EXTRA_OECONF_INTERMEDIATE = "\
125 127
126EXTRA_OECONF_append_libc-uclibc = " --disable-decimal-float " 128EXTRA_OECONF_append_libc-uclibc = " --disable-decimal-float "
127 129
128EXTRA_OECONF_PATHS = "\ 130EXTRA_OECONF_PATHS = "\
129 --with-gxx-include-dir=/not/exist{target_includedir}/c++/${BINV} \ 131 --with-gxx-include-dir=/not/exist{target_includedir}/c++/${BINV} \
130 --with-sysroot=/not/exist \ 132 --with-sysroot=/not/exist \
131 --with-build-sysroot=${STAGING_DIR_TARGET} \ 133 --with-build-sysroot=${STAGING_DIR_TARGET} \
132" 134"
133
134
diff --git a/meta/recipes-devtools/gcc/gcc-4.9/0052-Add-target-hook-to-override-DWARF2-frame-register-si.patch b/meta/recipes-devtools/gcc/gcc-4.9/0052-Add-target-hook-to-override-DWARF2-frame-register-si.patch
new file mode 100644
index 0000000000..f6958b32c9
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.9/0052-Add-target-hook-to-override-DWARF2-frame-register-si.patch
@@ -0,0 +1,138 @@
1From d626297e87e19251a284ea1e9360e831b48999ca Mon Sep 17 00:00:00 2001
2From: mpf <mpf@138bc75d-0d04-0410-961f-82ee72b054a4>
3Date: Thu, 4 Sep 2014 08:32:05 +0000
4Subject: [PATCH] Add target hook to override DWARF2 frame register size
5
6gcc/
7
8 * target.def (TARGET_DWARF_FRAME_REG_MODE): New target hook.
9 * targhooks.c (default_dwarf_frame_reg_mode): New function.
10 * targhooks.h (default_dwarf_frame_reg_mode): New prototype.
11 * doc/tm.texi.in (TARGET_DWARF_FRAME_REG_MODE): Document.
12 * doc/tm.texi: Regenerate.
13 * dwarf2cfi.c (expand_builtin_init_dwarf_reg_sizes): Abstract mode
14 selection logic to default_dwarf_frame_reg_mode.
15
16
17
18git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@214898 138bc75d-0d04-0410-961f-82ee72b054a4
19
20Signed-off-by: Khem Raj <raj.khem@gmail.com>
21Upstream-Status: Backport [gcc 5.0]
22
23---
24 gcc/ChangeLog | 10 ++++++++++
25 gcc/doc/tm.texi | 7 +++++++
26 gcc/doc/tm.texi.in | 2 ++
27 gcc/dwarf2cfi.c | 4 +---
28 gcc/target.def | 11 +++++++++++
29 gcc/targhooks.c | 13 +++++++++++++
30 gcc/targhooks.h | 1 +
31 7 files changed, 45 insertions(+), 3 deletions(-)
32
33Index: gcc-4.9.2/gcc/doc/tm.texi
34===================================================================
35--- gcc-4.9.2.orig/gcc/doc/tm.texi
36+++ gcc-4.9.2/gcc/doc/tm.texi
37@@ -9017,6 +9017,13 @@ register in Dwarf. Otherwise, this hook
38 If not defined, the default is to return @code{NULL_RTX}.
39 @end deftypefn
40
41+@deftypefn {Target Hook} {enum machine_mode} TARGET_DWARF_FRAME_REG_MODE (int @var{regno})
42+Given a register, this hook should return the mode which the
43+corresponding Dwarf frame register should have. This is normally
44+used to return a smaller mode than the raw mode to prevent call
45+clobbered parts of a register altering the frame register size
46+@end deftypefn
47+
48 @deftypefn {Target Hook} void TARGET_INIT_DWARF_REG_SIZES_EXTRA (tree @var{address})
49 If some registers are represented in Dwarf-2 unwind information in
50 multiple pieces, define this hook to fill in information about the
51Index: gcc-4.9.2/gcc/doc/tm.texi.in
52===================================================================
53--- gcc-4.9.2.orig/gcc/doc/tm.texi.in
54+++ gcc-4.9.2/gcc/doc/tm.texi.in
55@@ -6745,6 +6745,8 @@ the target supports DWARF 2 frame unwind
56
57 @hook TARGET_DWARF_REGISTER_SPAN
58
59+@hook TARGET_DWARF_FRAME_REG_MODE
60+
61 @hook TARGET_INIT_DWARF_REG_SIZES_EXTRA
62
63 @hook TARGET_ASM_TTYPE
64Index: gcc-4.9.2/gcc/dwarf2cfi.c
65===================================================================
66--- gcc-4.9.2.orig/gcc/dwarf2cfi.c
67+++ gcc-4.9.2/gcc/dwarf2cfi.c
68@@ -271,11 +271,9 @@ expand_builtin_init_dwarf_reg_sizes (tre
69 if (rnum < DWARF_FRAME_REGISTERS)
70 {
71 HOST_WIDE_INT offset = rnum * GET_MODE_SIZE (mode);
72- enum machine_mode save_mode = reg_raw_mode[i];
73 HOST_WIDE_INT size;
74+ enum machine_mode save_mode = targetm.dwarf_frame_reg_mode (i);
75
76- if (HARD_REGNO_CALL_PART_CLOBBERED (i, save_mode))
77- save_mode = choose_hard_reg_mode (i, 1, true);
78 if (dnum == DWARF_FRAME_RETURN_COLUMN)
79 {
80 if (save_mode == VOIDmode)
81Index: gcc-4.9.2/gcc/target.def
82===================================================================
83--- gcc-4.9.2.orig/gcc/target.def
84+++ gcc-4.9.2/gcc/target.def
85@@ -3218,6 +3218,17 @@ If not defined, the default is to return
86 rtx, (rtx reg),
87 hook_rtx_rtx_null)
88
89+/* Given a register return the mode of the corresponding DWARF frame
90+ register. */
91+DEFHOOK
92+(dwarf_frame_reg_mode,
93+ "Given a register, this hook should return the mode which the\n\
94+corresponding Dwarf frame register should have. This is normally\n\
95+used to return a smaller mode than the raw mode to prevent call\n\
96+clobbered parts of a register altering the frame register size",
97+ enum machine_mode, (int regno),
98+ default_dwarf_frame_reg_mode)
99+
100 /* If expand_builtin_init_dwarf_reg_sizes needs to fill in table
101 entries not corresponding directly to registers below
102 FIRST_PSEUDO_REGISTER, this hook should generate the necessary
103Index: gcc-4.9.2/gcc/targhooks.c
104===================================================================
105--- gcc-4.9.2.orig/gcc/targhooks.c
106+++ gcc-4.9.2/gcc/targhooks.c
107@@ -1438,6 +1438,19 @@ default_debug_unwind_info (void)
108 return UI_NONE;
109 }
110
111+/* Determine the correct mode for a Dwarf frame register that represents
112+ register REGNO. */
113+
114+enum machine_mode
115+default_dwarf_frame_reg_mode (int regno)
116+{
117+ enum machine_mode save_mode = reg_raw_mode[regno];
118+
119+ if (HARD_REGNO_CALL_PART_CLOBBERED (regno, save_mode))
120+ save_mode = choose_hard_reg_mode (regno, 1, true);
121+ return save_mode;
122+}
123+
124 /* To be used by targets where reg_raw_mode doesn't return the right
125 mode for registers used in apply_builtin_return and apply_builtin_arg. */
126
127Index: gcc-4.9.2/gcc/targhooks.h
128===================================================================
129--- gcc-4.9.2.orig/gcc/targhooks.h
130+++ gcc-4.9.2/gcc/targhooks.h
131@@ -194,6 +194,7 @@ extern int default_label_align_max_skip
132 extern int default_jump_align_max_skip (rtx);
133 extern section * default_function_section(tree decl, enum node_frequency freq,
134 bool startup, bool exit);
135+extern enum machine_mode default_dwarf_frame_reg_mode (int);
136 extern enum machine_mode default_get_reg_raw_mode (int);
137
138 extern void *default_get_pch_validity (size_t *);
diff --git a/meta/recipes-devtools/gcc/gcc-4.9/0055-PR-rtl-optimization-61801.patch b/meta/recipes-devtools/gcc/gcc-4.9/0055-PR-rtl-optimization-61801.patch
deleted file mode 100644
index b27abdef38..0000000000
--- a/meta/recipes-devtools/gcc/gcc-4.9/0055-PR-rtl-optimization-61801.patch
+++ /dev/null
@@ -1,36 +0,0 @@
1From 556537c4ad0df4cbebb74197bb2bdea75cf5dd35 Mon Sep 17 00:00:00 2001
2From: rguenth <rguenth@138bc75d-0d04-0410-961f-82ee72b054a4>
3Date: Thu, 17 Jul 2014 07:48:49 +0000
4Subject: [PATCH] 2014-07-17 Richard Biener <rguenther@suse.de>
5
6 PR rtl-optimization/61801
7 * sched-deps.c (sched_analyze_2): For ASM_OPERANDS and
8 ASM_INPUT don't set reg_pending_barrier if it appears in a
9 debug-insn.
10
11
12git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@212739 138bc75d-0d04-0410-961f-82ee72b054a4
13
14Upstream-Status: Backport [https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61801]
15Signed-off-by: Peter A. Bigot <pab@pabigot.com>
16
17---
18 gcc/sched-deps.c | 3 ++-
19
20diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c
21index efc4223..df29bd3 100644
22--- a/gcc/sched-deps.c
23+++ b/gcc/sched-deps.c
24@@ -2750,7 +2750,8 @@ sched_analyze_2 (struct deps_desc *deps, rtx x, rtx insn)
25 Consider for instance a volatile asm that changes the fpu rounding
26 mode. An insn should not be moved across this even if it only uses
27 pseudo-regs because it might give an incorrectly rounded result. */
28- if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
29+ if ((code != ASM_OPERANDS || MEM_VOLATILE_P (x))
30+ && !DEBUG_INSN_P (insn))
31 reg_pending_barrier = TRUE_BARRIER;
32
33 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
34--
351.8.5.5
36
diff --git a/meta/recipes-devtools/gcc/gcc-4.9/0055-dwarf-reg-processing-helper.patch b/meta/recipes-devtools/gcc/gcc-4.9/0055-dwarf-reg-processing-helper.patch
new file mode 100644
index 0000000000..557dab0f31
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.9/0055-dwarf-reg-processing-helper.patch
@@ -0,0 +1,148 @@
1From 4fd39f1329379e00f958394adde6be96f0caf21f Mon Sep 17 00:00:00 2001
2From: hainque <hainque@138bc75d-0d04-0410-961f-82ee72b054a4>
3Date: Fri, 5 Dec 2014 16:53:22 +0000
4Subject: [PATCH] 2014-12-05 Olivier Hainque <hainque@adacore.com>
5
6 * dwarf2cfi.c (init_one_dwarf_reg_size): New helper, processing
7 one particular reg for expand_builtin_init_dwarf_reg_sizes.
8 (expand_builtin_init_dwarf_reg_sizes): Rework to use helper and
9 account for dwarf register spans.
10
11
12
13git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218428 138bc75d-0d04-0410-961f-82ee72b054a4
14
15Signed-off-by: Khem Raj <raj.khem@gmail.com>
16Upstream-Status: Backport [gcc 5.0]
17
18---
19 gcc/ChangeLog | 7 +++++
20 gcc/dwarf2cfi.c | 98 +++++++++++++++++++++++++++++++++++++++++++++------------
21 2 files changed, 85 insertions(+), 20 deletions(-)
22
23Index: gcc-4.9.2/gcc/dwarf2cfi.c
24===================================================================
25--- gcc-4.9.2.orig/gcc/dwarf2cfi.c
26+++ gcc-4.9.2/gcc/dwarf2cfi.c
27@@ -252,7 +252,59 @@ init_return_column_size (enum machine_mo
28 gen_int_mode (size, mode));
29 }
30
31-/* Generate code to initialize the register size table. */
32+/* Datastructure used by expand_builtin_init_dwarf_reg_sizes and
33+ init_one_dwarf_reg_size to communicate on what has been done by the
34+ latter. */
35+
36+typedef struct
37+{
38+ /* Whether the dwarf return column was initialized. */
39+ bool wrote_return_column;
40+
41+ /* For each hard register REGNO, whether init_one_dwarf_reg_size
42+ was given REGNO to process already. */
43+ bool processed_regno [FIRST_PSEUDO_REGISTER];
44+
45+} init_one_dwarf_reg_state;
46+
47+/* Helper for expand_builtin_init_dwarf_reg_sizes. Generate code to
48+ initialize the dwarf register size table entry corresponding to register
49+ REGNO in REGMODE. TABLE is the table base address, SLOTMODE is the mode to
50+ use for the size entry to initialize, and INIT_STATE is the communication
51+ datastructure conveying what we're doing to our caller. */
52+
53+static
54+void init_one_dwarf_reg_size (int regno, machine_mode regmode,
55+ rtx table, machine_mode slotmode,
56+ init_one_dwarf_reg_state *init_state)
57+{
58+ const unsigned int dnum = DWARF_FRAME_REGNUM (regno);
59+ const unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1);
60+
61+ const HOST_WIDE_INT slotoffset = rnum * GET_MODE_SIZE (slotmode);
62+ const HOST_WIDE_INT regsize = GET_MODE_SIZE (regmode);
63+
64+ init_state->processed_regno[regno] = true;
65+
66+ if (rnum >= DWARF_FRAME_REGISTERS)
67+ return;
68+
69+ if (dnum == DWARF_FRAME_RETURN_COLUMN)
70+ {
71+ if (regmode == VOIDmode)
72+ return;
73+ init_state->wrote_return_column = true;
74+ }
75+
76+ if (slotoffset < 0)
77+ return;
78+
79+ emit_move_insn (adjust_address (table, slotmode, slotoffset),
80+ gen_int_mode (regsize, slotmode));
81+}
82+
83+/* Generate code to initialize the dwarf register size table located
84+ at the provided ADDRESS. */
85
86 void
87 expand_builtin_init_dwarf_reg_sizes (tree address)
88@@ -261,35 +313,40 @@ expand_builtin_init_dwarf_reg_sizes (tre
89 enum machine_mode mode = TYPE_MODE (char_type_node);
90 rtx addr = expand_normal (address);
91 rtx mem = gen_rtx_MEM (BLKmode, addr);
92- bool wrote_return_column = false;
93+
94+ init_one_dwarf_reg_state init_state;
95+
96+ memset ((char *)&init_state, 0, sizeof (init_state));
97
98 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
99 {
100- unsigned int dnum = DWARF_FRAME_REGNUM (i);
101- unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1);
102-
103- if (rnum < DWARF_FRAME_REGISTERS)
104- {
105- HOST_WIDE_INT offset = rnum * GET_MODE_SIZE (mode);
106- HOST_WIDE_INT size;
107- enum machine_mode save_mode = targetm.dwarf_frame_reg_mode (i);
108+ machine_mode save_mode;
109+ rtx span;
110
111- if (dnum == DWARF_FRAME_RETURN_COLUMN)
112+ /* No point in processing a register multiple times. This could happen
113+ with register spans, e.g. when a reg is first processed as a piece of
114+ a span, then as a register on its own later on. */
115+
116+ if (init_state.processed_regno[i])
117+ continue;
118+
119+ save_mode = targetm.dwarf_frame_reg_mode (i);
120+ span = targetm.dwarf_register_span (gen_rtx_REG (save_mode, i));
121+ if (!span)
122+ init_one_dwarf_reg_size (i, save_mode, mem, mode, &init_state);
123+ else
124+ {
125+ for (int si = 0; si < XVECLEN (span, 0); si++)
126 {
127- if (save_mode == VOIDmode)
128- continue;
129- wrote_return_column = true;
130- }
131- size = GET_MODE_SIZE (save_mode);
132- if (offset < 0)
133- continue;
134+ rtx reg = XVECEXP (span, 0, si);
135+ init_one_dwarf_reg_size
136+ (REGNO (reg), GET_MODE (reg), mem, mode, &init_state);
137+ }
138
139- emit_move_insn (adjust_address (mem, mode, offset),
140- gen_int_mode (size, mode));
141 }
142 }
143
144- if (!wrote_return_column)
145+ if (!init_state.wrote_return_column)
146 init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN);
147
148 #ifdef DWARF_ALT_FRAME_RETURN_COLUMN
diff --git a/meta/recipes-devtools/gcc/gcc-4.9/0056-define-default-cfa-register-mapping.patch b/meta/recipes-devtools/gcc/gcc-4.9/0056-define-default-cfa-register-mapping.patch
new file mode 100644
index 0000000000..3b6c94c492
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.9/0056-define-default-cfa-register-mapping.patch
@@ -0,0 +1,75 @@
1From c0235a33de8c4f78cce35b2a8c2035c83fe1bd14 Mon Sep 17 00:00:00 2001
2From: hainque <hainque@138bc75d-0d04-0410-961f-82ee72b054a4>
3Date: Fri, 5 Dec 2014 17:01:42 +0000
4Subject: [PATCH] 2014-12-05 Olivier Hainque <hainque@adacore.com>
5
6 gcc/
7 * defaults.h: (DWARF_REG_TO_UNWIND_COLUMN): Define default.
8 * dwarf2cfi.c (init_one_dwarf_reg_size): Honor
9 DWARF_REG_TO_UNWIND_COLUMN.
10
11 libgcc/
12 * unwind-dw2.c (DWARF_REG_TO_UNWIND_COLUMN): Remove default def,
13 now provided by defaults.h.
14
15
16
17git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218429 138bc75d-0d04-0410-961f-82ee72b054a4
18
19Signed-off-by: Khem Raj <raj.khem@gmail.com>
20Upstream-Status: Backport [gcc 5.0]
21
22---
23 gcc/ChangeLog | 6 ++++++
24 gcc/defaults.h | 5 +++++
25 gcc/dwarf2cfi.c | 3 ++-
26 libgcc/ChangeLog | 5 +++++
27 libgcc/unwind-dw2.c | 4 ----
28 5 files changed, 18 insertions(+), 5 deletions(-)
29
30Index: gcc-4.9.2/gcc/defaults.h
31===================================================================
32--- gcc-4.9.2.orig/gcc/defaults.h
33+++ gcc-4.9.2/gcc/defaults.h
34@@ -438,6 +438,11 @@ see the files COPYING3 and COPYING.RUNTI
35 #define DWARF_FRAME_REGNUM(REG) DBX_REGISTER_NUMBER (REG)
36 #endif
37
38+/* The mapping from dwarf CFA reg number to internal dwarf reg numbers. */
39+#ifndef DWARF_REG_TO_UNWIND_COLUMN
40+#define DWARF_REG_TO_UNWIND_COLUMN(REGNO) (REGNO)
41+#endif
42+
43 /* Map register numbers held in the call frame info that gcc has
44 collected using DWARF_FRAME_REGNUM to those that should be output in
45 .debug_frame and .eh_frame. */
46Index: gcc-4.9.2/gcc/dwarf2cfi.c
47===================================================================
48--- gcc-4.9.2.orig/gcc/dwarf2cfi.c
49+++ gcc-4.9.2/gcc/dwarf2cfi.c
50@@ -280,8 +280,9 @@ void init_one_dwarf_reg_size (int regno,
51 {
52 const unsigned int dnum = DWARF_FRAME_REGNUM (regno);
53 const unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1);
54+ const unsigned int dcol = DWARF_REG_TO_UNWIND_COLUMN (rnum);
55
56- const HOST_WIDE_INT slotoffset = rnum * GET_MODE_SIZE (slotmode);
57+ const HOST_WIDE_INT slotoffset = dcol * GET_MODE_SIZE (slotmode);
58 const HOST_WIDE_INT regsize = GET_MODE_SIZE (regmode);
59
60 init_state->processed_regno[regno] = true;
61Index: gcc-4.9.2/libgcc/unwind-dw2.c
62===================================================================
63--- gcc-4.9.2.orig/libgcc/unwind-dw2.c
64+++ gcc-4.9.2/libgcc/unwind-dw2.c
65@@ -55,10 +55,6 @@
66 #define PRE_GCC3_DWARF_FRAME_REGISTERS DWARF_FRAME_REGISTERS
67 #endif
68
69-#ifndef DWARF_REG_TO_UNWIND_COLUMN
70-#define DWARF_REG_TO_UNWIND_COLUMN(REGNO) (REGNO)
71-#endif
72-
73 /* ??? For the public function interfaces, we tend to gcc_assert that the
74 column numbers are in range. For the dwarf2 unwind info this does happen,
75 although so far in a case that doesn't actually matter.
diff --git a/meta/recipes-devtools/gcc/gcc-4.9/0056-top-level-reorder_gcc-bug-61144.patch b/meta/recipes-devtools/gcc/gcc-4.9/0056-top-level-reorder_gcc-bug-61144.patch
deleted file mode 100644
index f44893251c..0000000000
--- a/meta/recipes-devtools/gcc/gcc-4.9/0056-top-level-reorder_gcc-bug-61144.patch
+++ /dev/null
@@ -1,31 +0,0 @@
1
2Upstream-Status: Backport
3
4Originally-submitted-by: Peter Urbanec <openembedded-devel@urbanec.net>
5Signed-off-by: Saul Wold <sgw@linux.intel.com>
6
7--- /dev/null
8+++ b/meta/recipes-devtools/gcc/gcc-4.9/0056-top-level-reorder_gcc-bug-61144.patch
9@@ -0,0 +1,21 @@
10+--- a/gcc/varpool.c 2014/10/05 02:50:01 215895
11++++ b/gcc/varpool.c 2014/10/05 04:52:19 215896
12+@@ -329,8 +329,16 @@
13+
14+ /* Variables declared 'const' without an initializer
15+ have zero as the initializer if they may not be
16+- overridden at link or run time. */
17+- if (!DECL_INITIAL (real_decl)
18++ overridden at link or run time.
19++
20++ It is actually requirement for C++ compiler to optimize const variables
21++ consistently. As a GNU extension, do not enfore this rule for user defined
22++ weak variables, so we support interposition on:
23++ static const int dummy = 0;
24++ extern const int foo __attribute__((__weak__, __alias__("dummy")));
25++ */
26++ if ((!DECL_INITIAL (real_decl)
27++ || (DECL_WEAK (decl) && !DECL_COMDAT (decl)))
28+ && (DECL_EXTERNAL (decl) || decl_replaceable_p (decl)))
29+ return error_mark_node;
30+
31
diff --git a/meta/recipes-devtools/gcc/gcc-4.9/0060-Only-allow-e500-double-in-SPE_SIMD_REGNO_P-registers.patch b/meta/recipes-devtools/gcc/gcc-4.9/0060-Only-allow-e500-double-in-SPE_SIMD_REGNO_P-registers.patch
new file mode 100644
index 0000000000..75a9fdd441
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.9/0060-Only-allow-e500-double-in-SPE_SIMD_REGNO_P-registers.patch
@@ -0,0 +1,55 @@
1From 5c0092070253113cf0d9c45eacc884b3ecc34d81 Mon Sep 17 00:00:00 2001
2From: jsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4>
3Date: Sat, 25 Oct 2014 00:23:17 +0000
4Subject: [PATCH] Only allow e500 double in SPE_SIMD_REGNO_P registers.
5
6rs6000_hard_regno_nregs_internal allows SPE vectors in single
7registers satisfying SPE_SIMD_REGNO_P (i.e. register numbers 0 to
831). However, the corresponding test for e500 double treats all
9registers as being able to store a 64-bit value, rather than just
10those GPRs.
11
12Logically this inconsistency is wrong; in addition, it causes problems
13unwinding from signal handlers. linux-unwind.h uses
14ARG_POINTER_REGNUM as a place to store the return address from a
15signal handler, but this logic in rs6000_hard_regno_nregs_internal
16results in that being considered an 8-byte register, resulting in
17assertion failures.
18(<https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02625.html> first
19needs to be applied for unwinding to work in general on e500.) This
20patch makes rs6000_hard_regno_nregs_internal handle the e500 double
21case consistently with SPE vectors.
22
23Tested with no regressions with cross to powerpc-linux-gnuspe (given
24the aforementioned patch applied). Failures of signal handling
25unwinding tests such as gcc.dg/cleanup-{8,9,10,11}.c are fixed by this
26patch.
27
28 * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Do
29 not allow e500 double in registers not satisyfing
30 SPE_SIMD_REGNO_P.
31
32
33git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@216688 138bc75d-0d04-0410-961f-82ee72b054a4
34
35Signed-off-by: Khem Raj <raj.khem@gmail.com>
36Upstream-Status: Backport [gcc 5.0]
37
38---
39 gcc/ChangeLog | 6 ++++++
40 gcc/config/rs6000/rs6000.c | 2 +-
41 2 files changed, 7 insertions(+), 1 deletion(-)
42
43Index: gcc-4.9.2/gcc/config/rs6000/rs6000.c
44===================================================================
45--- gcc-4.9.2.orig/gcc/config/rs6000/rs6000.c
46+++ gcc-4.9.2/gcc/config/rs6000/rs6000.c
47@@ -1703,7 +1703,7 @@ rs6000_hard_regno_nregs_internal (int re
48 SCmode so as to pass the value correctly in a pair of
49 registers. */
50 else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
51- && !DECIMAL_FLOAT_MODE_P (mode))
52+ && !DECIMAL_FLOAT_MODE_P (mode) && SPE_SIMD_REGNO_P (regno))
53 reg_size = UNITS_PER_FP_WORD;
54
55 else
diff --git a/meta/recipes-devtools/gcc/gcc-4.9/target-gcc-includedir.patch b/meta/recipes-devtools/gcc/gcc-4.9/0061-target-gcc-includedir.patch
index f48c66dcac..f48c66dcac 100644
--- a/meta/recipes-devtools/gcc/gcc-4.9/target-gcc-includedir.patch
+++ b/meta/recipes-devtools/gcc/gcc-4.9/0061-target-gcc-includedir.patch
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-17 06:54:25 +0000