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-rw-r--r--meta/recipes-devtools/gcc/gcc-4.7/ppce5500-e6500-support.patch713
1 files changed, 0 insertions, 713 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.7/ppce5500-e6500-support.patch b/meta/recipes-devtools/gcc/gcc-4.7/ppce5500-e6500-support.patch
deleted file mode 100644
index e3341fc0a6..0000000000
--- a/meta/recipes-devtools/gcc/gcc-4.7/ppce5500-e6500-support.patch
+++ /dev/null
@@ -1,713 +0,0 @@
1Upstream-Status: Backport
2Signed-off-by: Khem Raj <raj.khem@gmail.com>
3
4From b770074cee13445eba1bf4e99649c5ceac9a4b5a Mon Sep 17 00:00:00 2001
5From: edmarwjr <edmarwjr@138bc75d-0d04-0410-961f-82ee72b054a4>
6Date: Tue, 5 Jun 2012 16:05:16 +0000
7Subject: [PATCH] 2012-06-01 Edmar Wienskoski <edmar@freescale.com>
8
9 * config/rs6000/e5500.md: New file.
10 * config/rs6000/e6500.md: New file.
11 * config/rs6000/rs6000.c (processor_costs): Add new costs for
12 e5500 and e6500.
13 (rs6000_option_override_internal): Altivec and Spe options not
14 allowed with e5500. Spe options not allowed with e6500. Increase
15 move inline limit for e5500 and e6500. Disable string instructions
16 for e5500 and e6500. Enable branch targets alignment for e5500 and
17 e6500. Initialize rs6000_cost for e5500 and e6500.
18 (rs6000_adjust_cost): Add extra scheduling cycles between compare
19 and brnach for e5500 and e6500.
20 (rs6000_issue_rate): Set issue rate for e5500 and e6500.
21 * config/rs6000/rs6000-cpus.def: Add cpu definitions for e5500 and
22 e6500.
23 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add e5500 and e6500.
24 * config/rs6000/rs6000.md (define_attr "cpu"): Add ppce5500 and
25 ppce6500.
26 Include e5500.md and e6500.md.
27 * config/rs6000/rs6000-opt.h (processor_type): Add
28 PROCESSOR_PPCE5500 and PROCESSOR_PPCE6500.
29 * config.gcc (cpu_is_64bit): Add new cores e5500, e6500.
30 (powerpc*-*-*): Add new cores e5500, e6500.
31 * doc/invoke.texi: (item -mcpu): Add e5500 and e6500 to list of cpus.
32
33gcc/testsuite
342012-06-01 Edmar Wienskoski <edmar@freescale.com>
35
36 * gcc.dg/tree-ssa/vector-3.c: Adjust regular expression.
37
38
39
40git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@188244 138bc75d-0d04-0410-961f-82ee72b054a4
41---
42 gcc/ChangeLog | 26 ++++
43 gcc/config.gcc | 6 +-
44 gcc/config/rs6000/e5500.md | 176 ++++++++++++++++++++++++
45 gcc/config/rs6000/e6500.md | 213 ++++++++++++++++++++++++++++++
46 gcc/config/rs6000/rs6000-cpus.def | 4 +
47 gcc/config/rs6000/rs6000-opts.h | 2 +
48 gcc/config/rs6000/rs6000.c | 68 +++++++++-
49 gcc/config/rs6000/rs6000.h | 2 +
50 gcc/config/rs6000/rs6000.md | 4 +-
51 gcc/doc/invoke.texi | 12 +-
52 gcc/testsuite/ChangeLog | 4 +
53 gcc/testsuite/gcc.dg/tree-ssa/vector-3.c | 2 +-
54 12 files changed, 506 insertions(+), 13 deletions(-)
55 create mode 100644 gcc/config/rs6000/e5500.md
56 create mode 100644 gcc/config/rs6000/e6500.md
57
58Index: gcc-4_7-branch/gcc/config.gcc
59===================================================================
60--- gcc-4_7-branch.orig/gcc/config.gcc 2012-07-06 19:52:30.000000000 -0700
61+++ gcc-4_7-branch/gcc/config.gcc 2012-07-06 19:53:26.350779999 -0700
62@@ -413,7 +413,7 @@
63 extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h"
64 need_64bit_hwint=yes
65 case x$with_cpu in
66- xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64)
67+ xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500)
68 cpu_is_64bit=yes
69 ;;
70 esac
71@@ -3361,8 +3361,8 @@
72 | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
73 | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \
74 | 604 | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
75- | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | titan\
76- | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
77+ | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | e5500 | e6500 \
78+ | titan | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
79 # OK
80 ;;
81 *)
82Index: gcc-4_7-branch/gcc/config/rs6000/e5500.md
83===================================================================
84--- /dev/null 1970-01-01 00:00:00.000000000 +0000
85+++ gcc-4_7-branch/gcc/config/rs6000/e5500.md 2012-07-06 19:53:26.350779999 -0700
86@@ -0,0 +1,176 @@
87+;; Pipeline description for Freescale PowerPC e5500 core.
88+;; Copyright (C) 2012 Free Software Foundation, Inc.
89+;; Contributed by Edmar Wienskoski (edmar@freescale.com)
90+;;
91+;; This file is part of GCC.
92+;;
93+;; GCC is free software; you can redistribute it and/or modify it
94+;; under the terms of the GNU General Public License as published
95+;; by the Free Software Foundation; either version 3, or (at your
96+;; option) any later version.
97+;;
98+;; GCC is distributed in the hope that it will be useful, but WITHOUT
99+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
100+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
101+;; License for more details.
102+;;
103+;; You should have received a copy of the GNU General Public License
104+;; along with GCC; see the file COPYING3. If not see
105+;; <http://www.gnu.org/licenses/>.
106+;;
107+;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
108+;; Max issue 3 insns/clock cycle (includes 1 branch)
109+
110+(define_automaton "e5500_most,e5500_long")
111+(define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most")
112+
113+;; SFX.
114+(define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most")
115+
116+;; CFX.
117+(define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most")
118+
119+;; Non-pipelined division.
120+(define_cpu_unit "e5500_cfx_div" "e5500_long")
121+
122+;; LSU.
123+(define_cpu_unit "e5500_lsu" "e5500_most")
124+
125+;; FPU.
126+(define_cpu_unit "e5500_fpu" "e5500_long")
127+
128+;; BU.
129+(define_cpu_unit "e5500_bu" "e5500_most")
130+
131+;; The following units are used to make the automata deterministic.
132+(define_cpu_unit "present_e5500_decode_0" "e5500_most")
133+(define_cpu_unit "present_e5500_sfx_0" "e5500_most")
134+(presence_set "present_e5500_decode_0" "e5500_decode_0")
135+(presence_set "present_e5500_sfx_0" "e5500_sfx_0")
136+
137+;; Some useful abbreviations.
138+(define_reservation "e5500_decode"
139+ "e5500_decode_0|e5500_decode_1+present_e5500_decode_0")
140+(define_reservation "e5500_sfx"
141+ "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0")
142+
143+;; SFX.
144+(define_insn_reservation "e5500_sfx" 1
145+ (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
146+ shift,cntlz,exts")
147+ (eq_attr "cpu" "ppce5500"))
148+ "e5500_decode,e5500_sfx")
149+
150+(define_insn_reservation "e5500_sfx2" 2
151+ (and (eq_attr "type" "cmp,compare,fast_compare,trap")
152+ (eq_attr "cpu" "ppce5500"))
153+ "e5500_decode,e5500_sfx")
154+
155+(define_insn_reservation "e5500_delayed" 2
156+ (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
157+ (eq_attr "cpu" "ppce5500"))
158+ "e5500_decode,e5500_sfx*2")
159+
160+(define_insn_reservation "e5500_two" 2
161+ (and (eq_attr "type" "two")
162+ (eq_attr "cpu" "ppce5500"))
163+ "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx")
164+
165+(define_insn_reservation "e5500_three" 3
166+ (and (eq_attr "type" "three")
167+ (eq_attr "cpu" "ppce5500"))
168+ "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx")
169+
170+;; SFX - Mfcr.
171+(define_insn_reservation "e5500_mfcr" 4
172+ (and (eq_attr "type" "mfcr")
173+ (eq_attr "cpu" "ppce5500"))
174+ "e5500_decode,e5500_sfx_0*4")
175+
176+;; SFX - Mtcrf.
177+(define_insn_reservation "e5500_mtcrf" 1
178+ (and (eq_attr "type" "mtcr")
179+ (eq_attr "cpu" "ppce5500"))
180+ "e5500_decode,e5500_sfx_0")
181+
182+;; SFX - Mtjmpr.
183+(define_insn_reservation "e5500_mtjmpr" 1
184+ (and (eq_attr "type" "mtjmpr,mfjmpr")
185+ (eq_attr "cpu" "ppce5500"))
186+ "e5500_decode,e5500_sfx")
187+
188+;; CFX - Multiply.
189+(define_insn_reservation "e5500_multiply" 4
190+ (and (eq_attr "type" "imul")
191+ (eq_attr "cpu" "ppce5500"))
192+ "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
193+
194+(define_insn_reservation "e5500_multiply_i" 5
195+ (and (eq_attr "type" "imul2,imul3,imul_compare")
196+ (eq_attr "cpu" "ppce5500"))
197+ "e5500_decode,e5500_cfx_stage0,\
198+ e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
199+
200+;; CFX - Divide.
201+(define_insn_reservation "e5500_divide" 16
202+ (and (eq_attr "type" "idiv")
203+ (eq_attr "cpu" "ppce5500"))
204+ "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
205+ e5500_cfx_div*15")
206+
207+(define_insn_reservation "e5500_divide_d" 26
208+ (and (eq_attr "type" "ldiv")
209+ (eq_attr "cpu" "ppce5500"))
210+ "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
211+ e5500_cfx_div*25")
212+
213+;; LSU - Loads.
214+(define_insn_reservation "e5500_load" 3
215+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
216+ load_l,sync")
217+ (eq_attr "cpu" "ppce5500"))
218+ "e5500_decode,e5500_lsu")
219+
220+(define_insn_reservation "e5500_fpload" 4
221+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
222+ (eq_attr "cpu" "ppce5500"))
223+ "e5500_decode,e5500_lsu")
224+
225+;; LSU - Stores.
226+(define_insn_reservation "e5500_store" 3
227+ (and (eq_attr "type" "store,store_ux,store_u,store_c")
228+ (eq_attr "cpu" "ppce5500"))
229+ "e5500_decode,e5500_lsu")
230+
231+(define_insn_reservation "e5500_fpstore" 3
232+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
233+ (eq_attr "cpu" "ppce5500"))
234+ "e5500_decode,e5500_lsu")
235+
236+;; FP.
237+(define_insn_reservation "e5500_float" 7
238+ (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
239+ (eq_attr "cpu" "ppce5500"))
240+ "e5500_decode,e5500_fpu")
241+
242+(define_insn_reservation "e5500_sdiv" 20
243+ (and (eq_attr "type" "sdiv")
244+ (eq_attr "cpu" "ppce5500"))
245+ "e5500_decode,e5500_fpu*20")
246+
247+(define_insn_reservation "e5500_ddiv" 35
248+ (and (eq_attr "type" "ddiv")
249+ (eq_attr "cpu" "ppce5500"))
250+ "e5500_decode,e5500_fpu*35")
251+
252+;; BU.
253+(define_insn_reservation "e5500_branch" 1
254+ (and (eq_attr "type" "jmpreg,branch,isync")
255+ (eq_attr "cpu" "ppce5500"))
256+ "e5500_decode,e5500_bu")
257+
258+;; BU - CR logical.
259+(define_insn_reservation "e5500_cr_logical" 1
260+ (and (eq_attr "type" "cr_logical,delayed_cr")
261+ (eq_attr "cpu" "ppce5500"))
262+ "e5500_decode,e5500_bu")
263Index: gcc-4_7-branch/gcc/config/rs6000/e6500.md
264===================================================================
265--- /dev/null 1970-01-01 00:00:00.000000000 +0000
266+++ gcc-4_7-branch/gcc/config/rs6000/e6500.md 2012-07-06 19:53:26.354779999 -0700
267@@ -0,0 +1,213 @@
268+;; Pipeline description for Freescale PowerPC e6500 core.
269+;; Copyright (C) 2012 Free Software Foundation, Inc.
270+;; Contributed by Edmar Wienskoski (edmar@freescale.com)
271+;;
272+;; This file is part of GCC.
273+;;
274+;; GCC is free software; you can redistribute it and/or modify it
275+;; under the terms of the GNU General Public License as published
276+;; by the Free Software Foundation; either version 3, or (at your
277+;; option) any later version.
278+;;
279+;; GCC is distributed in the hope that it will be useful, but WITHOUT
280+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
281+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
282+;; License for more details.
283+;;
284+;; You should have received a copy of the GNU General Public License
285+;; along with GCC; see the file COPYING3. If not see
286+;; <http://www.gnu.org/licenses/>.
287+;;
288+;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM
289+;; Max issue 3 insns/clock cycle (includes 1 branch)
290+
291+(define_automaton "e6500_most,e6500_long,e6500_vec")
292+(define_cpu_unit "e6500_decode_0,e6500_decode_1" "e6500_most")
293+
294+;; SFX.
295+(define_cpu_unit "e6500_sfx_0,e6500_sfx_1" "e6500_most")
296+
297+;; CFX.
298+(define_cpu_unit "e6500_cfx_stage0,e6500_cfx_stage1" "e6500_most")
299+
300+;; Non-pipelined division.
301+(define_cpu_unit "e6500_cfx_div" "e6500_long")
302+
303+;; LSU.
304+(define_cpu_unit "e6500_lsu" "e6500_most")
305+
306+;; FPU.
307+(define_cpu_unit "e6500_fpu" "e6500_long")
308+
309+;; BU.
310+(define_cpu_unit "e6500_bu" "e6500_most")
311+
312+;; Altivec unit
313+(define_cpu_unit "e6500_vec,e6500_vecperm" "e6500_vec")
314+
315+;; The following units are used to make the automata deterministic.
316+(define_cpu_unit "present_e6500_decode_0" "e6500_most")
317+(define_cpu_unit "present_e6500_sfx_0" "e6500_most")
318+(presence_set "present_e6500_decode_0" "e6500_decode_0")
319+(presence_set "present_e6500_sfx_0" "e6500_sfx_0")
320+
321+;; Some useful abbreviations.
322+(define_reservation "e6500_decode"
323+ "e6500_decode_0|e6500_decode_1+present_e6500_decode_0")
324+(define_reservation "e6500_sfx"
325+ "e6500_sfx_0|e6500_sfx_1+present_e6500_sfx_0")
326+
327+;; SFX.
328+(define_insn_reservation "e6500_sfx" 1
329+ (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
330+ shift,cntlz,exts")
331+ (eq_attr "cpu" "ppce6500"))
332+ "e6500_decode,e6500_sfx")
333+
334+(define_insn_reservation "e6500_sfx2" 2
335+ (and (eq_attr "type" "cmp,compare,fast_compare,trap")
336+ (eq_attr "cpu" "ppce6500"))
337+ "e6500_decode,e6500_sfx")
338+
339+(define_insn_reservation "e6500_delayed" 2
340+ (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
341+ (eq_attr "cpu" "ppce6500"))
342+ "e6500_decode,e6500_sfx*2")
343+
344+(define_insn_reservation "e6500_two" 2
345+ (and (eq_attr "type" "two")
346+ (eq_attr "cpu" "ppce6500"))
347+ "e6500_decode,e6500_decode+e6500_sfx,e6500_sfx")
348+
349+(define_insn_reservation "e6500_three" 3
350+ (and (eq_attr "type" "three")
351+ (eq_attr "cpu" "ppce6500"))
352+ "e6500_decode,(e6500_decode+e6500_sfx)*2,e6500_sfx")
353+
354+;; SFX - Mfcr.
355+(define_insn_reservation "e6500_mfcr" 4
356+ (and (eq_attr "type" "mfcr")
357+ (eq_attr "cpu" "ppce6500"))
358+ "e6500_decode,e6500_sfx_0*4")
359+
360+;; SFX - Mtcrf.
361+(define_insn_reservation "e6500_mtcrf" 1
362+ (and (eq_attr "type" "mtcr")
363+ (eq_attr "cpu" "ppce6500"))
364+ "e6500_decode,e6500_sfx_0")
365+
366+;; SFX - Mtjmpr.
367+(define_insn_reservation "e6500_mtjmpr" 1
368+ (and (eq_attr "type" "mtjmpr,mfjmpr")
369+ (eq_attr "cpu" "ppce6500"))
370+ "e6500_decode,e6500_sfx")
371+
372+;; CFX - Multiply.
373+(define_insn_reservation "e6500_multiply" 4
374+ (and (eq_attr "type" "imul")
375+ (eq_attr "cpu" "ppce6500"))
376+ "e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1")
377+
378+(define_insn_reservation "e6500_multiply_i" 5
379+ (and (eq_attr "type" "imul2,imul3,imul_compare")
380+ (eq_attr "cpu" "ppce6500"))
381+ "e6500_decode,e6500_cfx_stage0,\
382+ e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1")
383+
384+;; CFX - Divide.
385+(define_insn_reservation "e6500_divide" 16
386+ (and (eq_attr "type" "idiv")
387+ (eq_attr "cpu" "ppce6500"))
388+ "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
389+ e6500_cfx_div*15")
390+
391+(define_insn_reservation "e6500_divide_d" 26
392+ (and (eq_attr "type" "ldiv")
393+ (eq_attr "cpu" "ppce6500"))
394+ "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
395+ e6500_cfx_div*25")
396+
397+;; LSU - Loads.
398+(define_insn_reservation "e6500_load" 3
399+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
400+ load_l,sync")
401+ (eq_attr "cpu" "ppce6500"))
402+ "e6500_decode,e6500_lsu")
403+
404+(define_insn_reservation "e6500_fpload" 4
405+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
406+ (eq_attr "cpu" "ppce6500"))
407+ "e6500_decode,e6500_lsu")
408+
409+(define_insn_reservation "e6500_vecload" 4
410+ (and (eq_attr "type" "vecload")
411+ (eq_attr "cpu" "ppce6500"))
412+ "e6500_decode,e6500_lsu")
413+
414+;; LSU - Stores.
415+(define_insn_reservation "e6500_store" 3
416+ (and (eq_attr "type" "store,store_ux,store_u,store_c")
417+ (eq_attr "cpu" "ppce6500"))
418+ "e6500_decode,e6500_lsu")
419+
420+(define_insn_reservation "e6500_fpstore" 3
421+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
422+ (eq_attr "cpu" "ppce6500"))
423+ "e6500_decode,e6500_lsu")
424+
425+(define_insn_reservation "e6500_vecstore" 4
426+ (and (eq_attr "type" "vecstore")
427+ (eq_attr "cpu" "ppce6500"))
428+ "e6500_decode,e6500_lsu")
429+
430+;; FP.
431+(define_insn_reservation "e6500_float" 7
432+ (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
433+ (eq_attr "cpu" "ppce6500"))
434+ "e6500_decode,e6500_fpu")
435+
436+(define_insn_reservation "e6500_sdiv" 20
437+ (and (eq_attr "type" "sdiv")
438+ (eq_attr "cpu" "ppce6500"))
439+ "e6500_decode,e6500_fpu*20")
440+
441+(define_insn_reservation "e6500_ddiv" 35
442+ (and (eq_attr "type" "ddiv")
443+ (eq_attr "cpu" "ppce6500"))
444+ "e6500_decode,e6500_fpu*35")
445+
446+;; BU.
447+(define_insn_reservation "e6500_branch" 1
448+ (and (eq_attr "type" "jmpreg,branch,isync")
449+ (eq_attr "cpu" "ppce6500"))
450+ "e6500_decode,e6500_bu")
451+
452+;; BU - CR logical.
453+(define_insn_reservation "e6500_cr_logical" 1
454+ (and (eq_attr "type" "cr_logical,delayed_cr")
455+ (eq_attr "cpu" "ppce6500"))
456+ "e6500_decode,e6500_bu")
457+
458+;; VSFX.
459+(define_insn_reservation "e6500_vecsimple" 1
460+ (and (eq_attr "type" "vecsimple,veccmp")
461+ (eq_attr "cpu" "ppce6500"))
462+ "e6500_decode,e6500_vec")
463+
464+;; VCFX.
465+(define_insn_reservation "e6500_veccomplex" 4
466+ (and (eq_attr "type" "veccomplex")
467+ (eq_attr "cpu" "ppce6500"))
468+ "e6500_decode,e6500_vec")
469+
470+;; VFPU.
471+(define_insn_reservation "e6500_vecfloat" 6
472+ (and (eq_attr "type" "vecfloat")
473+ (eq_attr "cpu" "ppce6500"))
474+ "e6500_decode,e6500_vec")
475+
476+;; VPERM.
477+(define_insn_reservation "e6500_vecperm" 2
478+ (and (eq_attr "type" "vecperm")
479+ (eq_attr "cpu" "ppce6500"))
480+ "e6500_decode,e6500_vecperm")
481Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def
482===================================================================
483--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-cpus.def 2012-07-06 19:52:30.000000000 -0700
484+++ gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def 2012-07-06 19:53:26.354779999 -0700
485@@ -87,6 +87,10 @@
486 | MASK_ISEL)
487 RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
488 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
489+RS6000_CPU ("e5500", PROCESSOR_PPCE5500, POWERPC_BASE_MASK | MASK_POWERPC64
490+ | MASK_PPC_GFXOPT | MASK_ISEL)
491+RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
492+ | MASK_MFCRF | MASK_ISEL)
493 RS6000_CPU ("860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
494 RS6000_CPU ("970", PROCESSOR_POWER4,
495 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
496Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h
497===================================================================
498--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-opts.h 2012-07-06 19:52:30.000000000 -0700
499+++ gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h 2012-07-06 19:53:26.354779999 -0700
500@@ -54,6 +54,8 @@
501 PROCESSOR_PPCE300C3,
502 PROCESSOR_PPCE500MC,
503 PROCESSOR_PPCE500MC64,
504+ PROCESSOR_PPCE5500,
505+ PROCESSOR_PPCE6500,
506 PROCESSOR_POWER4,
507 PROCESSOR_POWER5,
508 PROCESSOR_POWER6,
509Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.c
510===================================================================
511--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.c 2012-07-06 19:52:30.000000000 -0700
512+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.c 2012-07-06 19:53:26.354779999 -0700
513@@ -755,6 +755,44 @@
514 1, /* prefetch streams /*/
515 };
516
517+/* Instruction costs on PPCE5500 processors. */
518+static const
519+struct processor_costs ppce5500_cost = {
520+ COSTS_N_INSNS (5), /* mulsi */
521+ COSTS_N_INSNS (5), /* mulsi_const */
522+ COSTS_N_INSNS (4), /* mulsi_const9 */
523+ COSTS_N_INSNS (5), /* muldi */
524+ COSTS_N_INSNS (14), /* divsi */
525+ COSTS_N_INSNS (14), /* divdi */
526+ COSTS_N_INSNS (7), /* fp */
527+ COSTS_N_INSNS (10), /* dmul */
528+ COSTS_N_INSNS (36), /* sdiv */
529+ COSTS_N_INSNS (66), /* ddiv */
530+ 64, /* cache line size */
531+ 32, /* l1 cache */
532+ 128, /* l2 cache */
533+ 1, /* prefetch streams /*/
534+};
535+
536+/* Instruction costs on PPCE6500 processors. */
537+static const
538+struct processor_costs ppce6500_cost = {
539+ COSTS_N_INSNS (5), /* mulsi */
540+ COSTS_N_INSNS (5), /* mulsi_const */
541+ COSTS_N_INSNS (4), /* mulsi_const9 */
542+ COSTS_N_INSNS (5), /* muldi */
543+ COSTS_N_INSNS (14), /* divsi */
544+ COSTS_N_INSNS (14), /* divdi */
545+ COSTS_N_INSNS (7), /* fp */
546+ COSTS_N_INSNS (10), /* dmul */
547+ COSTS_N_INSNS (36), /* sdiv */
548+ COSTS_N_INSNS (66), /* ddiv */
549+ 64, /* cache line size */
550+ 32, /* l1 cache */
551+ 128, /* l2 cache */
552+ 1, /* prefetch streams /*/
553+};
554+
555 /* Instruction costs on AppliedMicro Titan processors. */
556 static const
557 struct processor_costs titan_cost = {
558@@ -2741,13 +2779,19 @@
559 error ("target attribute or pragma changes SPE ABI");
560
561 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
562- || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
563+ || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
564+ || rs6000_cpu == PROCESSOR_PPCE5500)
565 {
566 if (TARGET_ALTIVEC)
567 error ("AltiVec not supported in this target");
568 if (TARGET_SPE)
569 error ("SPE not supported in this target");
570 }
571+ if (rs6000_cpu == PROCESSOR_PPCE6500)
572+ {
573+ if (TARGET_SPE)
574+ error ("SPE not supported in this target");
575+ }
576
577 /* Disable Cell microcode if we are optimizing for the Cell
578 and not optimizing for size. */
579@@ -2842,7 +2886,9 @@
580 user's opinion, though. */
581 if (rs6000_block_move_inline_limit == 0
582 && (rs6000_cpu == PROCESSOR_PPCE500MC
583- || rs6000_cpu == PROCESSOR_PPCE500MC64))
584+ || rs6000_cpu == PROCESSOR_PPCE500MC64
585+ || rs6000_cpu == PROCESSOR_PPCE5500
586+ || rs6000_cpu == PROCESSOR_PPCE6500))
587 rs6000_block_move_inline_limit = 128;
588
589 /* store_one_arg depends on expand_block_move to handle at least the
590@@ -2989,6 +3035,8 @@
591 case PROCESSOR_PPC8548:
592 case PROCESSOR_PPCE500MC:
593 case PROCESSOR_PPCE500MC64:
594+ case PROCESSOR_PPCE5500:
595+ case PROCESSOR_PPCE6500:
596
597 rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
598 rs6000_double_float = TARGET_E500_DOUBLE;
599@@ -3033,7 +3081,9 @@
600 || rs6000_cpu == PROCESSOR_POWER6
601 || rs6000_cpu == PROCESSOR_POWER7
602 || rs6000_cpu == PROCESSOR_PPCE500MC
603- || rs6000_cpu == PROCESSOR_PPCE500MC64);
604+ || rs6000_cpu == PROCESSOR_PPCE500MC64
605+ || rs6000_cpu == PROCESSOR_PPCE5500
606+ || rs6000_cpu == PROCESSOR_PPCE6500);
607
608 /* Allow debug switches to override the above settings. These are set to -1
609 in rs6000.opt to indicate the user hasn't directly set the switch. */
610@@ -3256,6 +3306,14 @@
611 rs6000_cost = &ppce500mc64_cost;
612 break;
613
614+ case PROCESSOR_PPCE5500:
615+ rs6000_cost = &ppce5500_cost;
616+ break;
617+
618+ case PROCESSOR_PPCE6500:
619+ rs6000_cost = &ppce6500_cost;
620+ break;
621+
622 case PROCESSOR_TITAN:
623 rs6000_cost = &titan_cost;
624 break;
625@@ -22304,6 +22362,8 @@
626 || rs6000_cpu_attr == CPU_PPC750
627 || rs6000_cpu_attr == CPU_PPC7400
628 || rs6000_cpu_attr == CPU_PPC7450
629+ || rs6000_cpu_attr == CPU_PPCE5500
630+ || rs6000_cpu_attr == CPU_PPCE6500
631 || rs6000_cpu_attr == CPU_POWER4
632 || rs6000_cpu_attr == CPU_POWER5
633 || rs6000_cpu_attr == CPU_POWER7
634@@ -22849,6 +22909,8 @@
635 case CPU_PPCE300C3:
636 case CPU_PPCE500MC:
637 case CPU_PPCE500MC64:
638+ case CPU_PPCE5500:
639+ case CPU_PPCE6500:
640 case CPU_TITAN:
641 return 2;
642 case CPU_RIOS2:
643Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.h
644===================================================================
645--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.h 2012-07-06 19:52:30.000000000 -0700
646+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.h 2012-07-06 19:53:26.358779999 -0700
647@@ -168,6 +168,8 @@
648 %{mcpu=e300c3: -me300} \
649 %{mcpu=e500mc: -me500mc} \
650 %{mcpu=e500mc64: -me500mc64} \
651+%{mcpu=e5500: -me5500} \
652+%{mcpu=e6500: -me6500} \
653 %{maltivec: -maltivec} \
654 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
655 -many"
656Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.md
657===================================================================
658--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.md 2012-07-06 19:52:32.000000000 -0700
659+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.md 2012-07-06 19:53:26.358779999 -0700
660@@ -166,7 +166,7 @@
661 ;; Processor type -- this attribute must exactly match the processor_type
662 ;; enumeration in rs6000.h.
663
664-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
665+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"
666 (const (symbol_ref "rs6000_cpu_attr")))
667
668
669@@ -194,6 +194,8 @@
670 (include "e300c2c3.md")
671 (include "e500mc.md")
672 (include "e500mc64.md")
673+(include "e5500.md")
674+(include "e6500.md")
675 (include "power4.md")
676 (include "power5.md")
677 (include "power6.md")
678Index: gcc-4_7-branch/gcc/doc/invoke.texi
679===================================================================
680--- gcc-4_7-branch.orig/gcc/doc/invoke.texi 2012-07-06 19:43:53.000000000 -0700
681+++ gcc-4_7-branch/gcc/doc/invoke.texi 2012-07-06 19:53:26.362779999 -0700
682@@ -16565,11 +16565,13 @@
683 @samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740},
684 @samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
685 @samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2},
686-@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{ec603e}, @samp{G3},
687-@samp{G4}, @samp{G5}, @samp{titan}, @samp{power}, @samp{power2}, @samp{power3},
688-@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x},
689-@samp{power7}, @samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios},
690-@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
691+@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{e5500},
692+@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
693+@samp{titan}, @samp{power}, @samp{power2}, @samp{power3},
694+@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6},
695+@samp{power6x}, @samp{power7}, @samp{common}, @samp{powerpc},
696+@samp{powerpc64}, @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc},
697+and @samp{rs64}.
698
699 @option{-mcpu=common} selects a completely generic processor. Code
700 generated under this option will run on any POWER or PowerPC processor.
701Index: gcc-4_7-branch/gcc/testsuite/gcc.dg/tree-ssa/vector-3.c
702===================================================================
703--- gcc-4_7-branch.orig/gcc/testsuite/gcc.dg/tree-ssa/vector-3.c 2012-07-06 19:43:53.000000000 -0700
704+++ gcc-4_7-branch/gcc/testsuite/gcc.dg/tree-ssa/vector-3.c 2012-07-06 19:53:26.362779999 -0700
705@@ -14,7 +14,7 @@
706
707 /* We should be able to optimize this to just "return 0.0;" */
708 /* { dg-final { scan-tree-dump-times "BIT_FIELD_REF" 0 "optimized"} } */
709-/* { dg-final { scan-tree-dump-times "0.0" 1 "optimized"} } */
710+/* { dg-final { scan-tree-dump-times "0\\\.0" 1 "optimized"} } */
711
712 /* { dg-final { cleanup-tree-dump "optimized" } } */
713
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